coreboot August 2012

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New patch to review for coreboot: 7ab20fa Synchronize rdtsc instructions
by Stefan Reinauer 08 Aug '12

08 Aug '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1422 -gerrit commit 7ab20fad6bcad3f4ec86462c05a58a0aae1f6673 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Aug 7 14:44:51 2012 -0700 Synchronize rdtsc instructions The CPU can arbitrarily reorder calls to rdtsc, significantly reducing the precision of timing using the CPUs time stamp counter. Unfortunately the method of synchronizing rdtsc is different on AMD and Intel CPUs. There is a generic method, using the cpuid instruction, but that uses up a lot of registers, and is very slow. Hence, use the correct lfence/mfence instructions (for CPUs that we know support it) Change-Id: I17ecb48d283f38f23148c13159aceda704c64ea5 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/amd/agesa/Kconfig | 1 + src/cpu/amd/model_10xxx/Kconfig | 1 + src/cpu/amd/model_fxx/Kconfig | 1 + src/cpu/intel/model_1067x/Kconfig | 1 + src/cpu/intel/model_106cx/Kconfig | 2 +- src/cpu/intel/model_206ax/Kconfig | 1 + src/cpu/intel/model_6ex/Kconfig | 1 + src/cpu/intel/model_6fx/Kconfig | 1 + src/cpu/x86/Kconfig | 16 ++++++++++++++++ src/include/cpu/x86/tsc.h | 21 ++++++++++++++++++--- 10 files changed, 42 insertions(+), 4 deletions(-) diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 5ec5ce8..b7e69e0 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -25,6 +25,7 @@ config CPU_AMD_AGESA default y if CPU_AMD_AGESA_FAMILY15 default y if CPU_AMD_AGESA_FAMILY15_TN default n + select TSC_SYNC_LFENCE if CPU_AMD_AGESA diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig index 221d044..0890771 100644 --- a/src/cpu/amd/model_10xxx/Kconfig +++ b/src/cpu/amd/model_10xxx/Kconfig @@ -3,6 +3,7 @@ config CPU_AMD_MODEL_10XXX select SSE select SSE2 select MMCONF_SUPPORT_DEFAULT + select TSC_SYNC_LFENCE if CPU_AMD_MODEL_10XXX config CPU_ADDR_BITS diff --git a/src/cpu/amd/model_fxx/Kconfig b/src/cpu/amd/model_fxx/Kconfig index e04605b..0afc4b0 100644 --- a/src/cpu/amd/model_fxx/Kconfig +++ b/src/cpu/amd/model_fxx/Kconfig @@ -3,6 +3,7 @@ config CPU_AMD_MODEL_FXX select MMX select SSE select SSE2 + select TSC_SYNC_LFENCE if CPU_AMD_MODEL_FXX config UDELAY_IO diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig index b079922..852c9cd 100644 --- a/src/cpu/intel/model_1067x/Kconfig +++ b/src/cpu/intel/model_1067x/Kconfig @@ -2,3 +2,4 @@ config CPU_INTEL_MODEL_1067X bool select SMP select SSE2 + select TSC_SYNC_MFENCE diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index 103ed50..7a75ec1 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -4,9 +4,9 @@ config CPU_INTEL_MODEL_106CX select SSE2 select UDELAY_LAPIC select AP_IN_SIPI_WAIT + select TSC_SYNC_MFENCE config CPU_ADDR_BITS int default 32 - diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 9cc6edd..6635868 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -14,6 +14,7 @@ config CPU_SPECIFIC_OPTIONS select SMM_TSEG select MICROCODE_IN_CBFS #select AP_IN_SIPI_WAIT + select TSC_SYNC_MFENCE config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/model_6ex/Kconfig b/src/cpu/intel/model_6ex/Kconfig index 31d24bd..e2b1986 100644 --- a/src/cpu/intel/model_6ex/Kconfig +++ b/src/cpu/intel/model_6ex/Kconfig @@ -4,3 +4,4 @@ config CPU_INTEL_MODEL_6EX select SSE2 select UDELAY_LAPIC select AP_IN_SIPI_WAIT + select TSC_SYNC_MFENCE diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig index 851685c..4517f17 100644 --- a/src/cpu/intel/model_6fx/Kconfig +++ b/src/cpu/intel/model_6fx/Kconfig @@ -4,3 +4,4 @@ config CPU_INTEL_MODEL_6FX select SSE2 select UDELAY_LAPIC select AP_IN_SIPI_WAIT + select TSC_SYNC_MFENCE diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 07e9d9e..9a96aea 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -23,6 +23,22 @@ config TSC_CALIBRATE_WITH_IO bool default n +config TSC_SYNC_LFENCE + bool + default n + help + The CPU driver should select this if the CPU needs + to execute an lfence instruction in order to synchronize + rdtsc. This is true for all modern AMD CPUs. + +config TSC_SYNC_MFENCE + bool + default n + help + The CPU driver should select this if the CPU needs + to execute an mfence instruction in order to synchronize + rdtsc. This is true for all modern Intel CPUs. + config XIP_ROM_SIZE hex default ROM_SIZE if ROMCC diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h index c573627..615aa1c 100644 --- a/src/include/cpu/x86/tsc.h +++ b/src/include/cpu/x86/tsc.h @@ -10,10 +10,16 @@ typedef struct tsc_struct tsc_t; static inline tsc_t rdtsc(void) { tsc_t res; - __asm__ __volatile__ ( + asm volatile ( +#if CONFIG_TSC_SYNC_MFENCE + "mfence\n" +#endif +#if CONFIG_TSC_SYNC_LFENCE + "lfence\n" +#endif "rdtsc" : "=a" (res.lo), "=d"(res.hi) /* outputs */ - ); + ); return res; } @@ -22,7 +28,16 @@ static inline tsc_t rdtsc(void) static inline unsigned long long rdtscll(void) { unsigned long long val; - asm volatile ("rdtsc" : "=A" (val)); + asm volatile ( +#if CONFIG_TSC_SYNC_MFENCE + "mfence\n" +#endif +#if CONFIG_TSC_SYNC_LFENCE + "lfence\n" +#endif + "rdtsc" + : "=A" (val) + ); return val; } #endif

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Patch set updated for coreboot: b3f75cd VIA Nano: Add support for VIA Nano CPUs
by Alexandru Gagniuc 08 Aug '12

08 Aug '12

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1257 -gerrit commit b3f75cda920ecc056099f640a0339d380e6b4bea Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jul 20 18:17:01 2012 -0500 VIA Nano: Add support for VIA Nano CPUs Add code to do the following for the VIA Nano CPUs - Update microcode - Set maximum frequency - Initialize power states - Set up cache Attempting to change the voltage or frequency of the CPU without applying the microcode update will hang the CPU, so we only do transitions if we can verify the microcode has been updated. The microcode is updated directly from CBFS. No microcode is included in ramstage. The microcode is not included in this commit. To get the microcode, run bios_extract on the manufacturer supplied BIOS, and look for the file marked "P6 Microcode". Include this file in CBFS. You can have the build system include this file automatically by selecting Expert Mode, then look under 'Chipset' -> 'Include CPU microcode in CBFS' -> Include external microcode file (check) 'Path and filename of CPU microcode' should contain the location of the microcode file previously extracted. Change-Id: I586aaca5715e047b42ef901d66772ace0e6b655e Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/via/Kconfig | 1 + src/cpu/via/Makefile.inc | 6 +- src/cpu/via/nano/Kconfig | 41 ++++++++ src/cpu/via/nano/Makefile.inc | 33 ++++++ src/cpu/via/nano/nano_init.c | 204 +++++++++++++++++++++++++++++++++++++++ src/cpu/via/nano/update_ucode.c | 150 ++++++++++++++++++++++++++++ src/cpu/via/nano/update_ucode.h | 73 ++++++++++++++ 7 files changed, 505 insertions(+), 3 deletions(-) diff --git a/src/cpu/via/Kconfig b/src/cpu/via/Kconfig index 570d408..5c38c91 100644 --- a/src/cpu/via/Kconfig +++ b/src/cpu/via/Kconfig @@ -1,2 +1,3 @@ source src/cpu/via/c3/Kconfig source src/cpu/via/c7/Kconfig +source src/cpu/via/nano/Kconfig diff --git a/src/cpu/via/Makefile.inc b/src/cpu/via/Makefile.inc index 2616111..f1e198d 100644 --- a/src/cpu/via/Makefile.inc +++ b/src/cpu/via/Makefile.inc @@ -1,3 +1,3 @@ -subdirs-$(CONFIG_CPU_VIA_C7) += c7 -subdirs-$(CONFIG_CPU_VIA_C3) += c3 - +subdirs-$(CONFIG_CPU_VIA_C7) += c7 +subdirs-$(CONFIG_CPU_VIA_C3) += c3 +subdirs-$(CONFIG_CPU_VIA_NANO) += nano diff --git a/src/cpu/via/nano/Kconfig b/src/cpu/via/nano/Kconfig new file mode 100644 index 0000000..3b1c213 --- /dev/null +++ b/src/cpu/via/nano/Kconfig @@ -0,0 +1,41 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see <http://www.gnu.org/licenses/>. +## + +config CPU_VIA_NANO + bool + +if CPU_VIA_NANO + +config CPU_SPECIFIC_OPTIONS + def_bool y + select UDELAY_TSC + select MMX + select SSE2 + select CACHE_AS_RAM + select CPU_MICROCODE_IN_CBFS + +config DCACHE_RAM_BASE + hex + default 0xffe00000 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + +endif # CPU_VIA_NANO diff --git a/src/cpu/via/nano/Makefile.inc b/src/cpu/via/nano/Makefile.inc new file mode 100644 index 0000000..6b0c1e9 --- /dev/null +++ b/src/cpu/via/nano/Makefile.inc @@ -0,0 +1,33 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see <http://www.gnu.org/licenses/>. +## + +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm + +driver-y += nano_init.c +ramstage-y += update_ucode.c + +# We need to hear from VIA to get permission to include this file in the +# official coreboot repository. Until then, we leave this commented out +# cpu-microcode-y += nano_ucode_blob.c + +cpu_incs += $(src)/cpu/via/car/cache_as_ram.inc diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c new file mode 100644 index 0000000..417119f --- /dev/null +++ b/src/cpu/via/nano/nano_init.c @@ -0,0 +1,204 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "update_ucode.h" +#include <console/console.h> +#include <device/device.h> +#include <cpu/cpu.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/cache.h> +#include <delay.h> + +#define MODEL_NANO 0x2 +#define MODEL_NANO_3000_B0 0x8 +#define MODEL_NANO_3000_B2 0xa + +#define MSR_IA32_PERF_STATUS 0x00000198 +#define MSR_IA32_PERF_CTL 0x00000199 +#define MSR_IA32_MISC_ENABLE 0x000001a0 +#define NANO_MYSTERIOUS_MSR 0x120e + +static void nano_finish_fid_vid_transition(void) +{ + + msr_t msr; + /* Wait until the power transition ends */ + int cnt = 0; + do { + udelay(16); + msr = rdmsr(MSR_IA32_PERF_STATUS); + cnt++; + if (cnt > 128) { + printk(BIOS_WARNING, + "Error while updating multiplier and voltage\n"); + break; + } + } while (msr.lo & ((1 << 16) | (1 << 17))); + + /* Print the new FID and Voltage */ + u8 cur_vid = (msr.lo >> 0) & 0xff; + u8 cur_fid = (msr.lo >> 8) & 0xff; + printk(BIOS_INFO, "New CPU multiplier: %dx\n", cur_fid); + printk(BIOS_INFO, "New Voltage ID : %dx\n", cur_vid); +} + +static void nano_set_max_fid_vid(void) +{ + msr_t msr; + /* Get voltage and frequency info */ + msr = rdmsr(MSR_IA32_PERF_STATUS); + u8 min_fid = (msr.hi >> 24); + u8 max_fid = (msr.hi >> 8) & 0xff; + u8 min_vid = (msr.hi >> 16) & 0xff; + u8 max_vid = (msr.hi >> 0) & 0xff; + u8 cur_vid = (msr.lo >> 0) & 0xff; + u8 cur_fid = (msr.lo >> 8) & 0xff; + + printk(BIOS_INFO, "CPU multiplier: %dx (min %dx; max %dx)\n", + cur_fid, min_fid, max_fid); + printk(BIOS_INFO, "Voltage ID : %dx (min %dx; max %dx)\n", + cur_vid, min_vid, max_vid); + + if( (cur_fid != max_fid) || (cur_vid != max_vid) ) { + /* Set highest frequency and VID */ + msr.lo = msr.hi; + msr.hi = 0; + wrmsr(MSR_IA32_PERF_CTL, msr); + /* Wait for the transition to complete, otherwise, the CPU + * might reset itself repeatedly */ + nano_finish_fid_vid_transition(); + } + /* As a side note, if we didn't update the microcode by this point, the + * second PLL will not lock correctly. The clock will still be provided + * by the first PLL, and execution will continue normally, ___until___ + * the CPU switches PLL. Once that happens we will no longer have a + * working clock source, and the CPU will hang + * Moral of the story: update the microcode, or don't change FID + * This check is handled before calling nano_power() */ +} + +static void nano_power(void) +{ + msr_t msr; + /* Enable Powersaver */ + msr = rdmsr(MSR_IA32_MISC_ENABLE); + msr.lo |= (1 << 16); + wrmsr(MSR_IA32_MISC_ENABLE, msr); + + /* Enable 6 bit or 7-bit VRM support + * This MSR is not documented by VIA docs, other than setting these + * bits */ + msr = rdmsr(NANO_MYSTERIOUS_MSR); + msr.lo |= ( (1<<7) | (1<<4) ); + /* FIXME: Do we have a 6-bit or 7-bit VRM? + * set bit [5] for 7-bit, or don't set it for 6 bit VRM + * This will probably require a Kconfig option + * My board has a 7-bit VRM, so I can't test the 6-bit VRM stuff */ + msr.lo |= (1<<5); + wrmsr(NANO_MYSTERIOUS_MSR, msr); + + /* Set the maximum frequency and voltage */ + nano_set_max_fid_vid(); + + /* Enable TM3 */ + msr = rdmsr(MSR_IA32_MISC_ENABLE); + msr.lo |= ( (1<<3) | (1<<13) ); + wrmsr(MSR_IA32_MISC_ENABLE, msr); + + u8 stepping = ( cpuid_eax(0x1) ) &0xf; + if(stepping >= MODEL_NANO_3000_B0) { + /* Hello Nano 3000. The Terminator needs a CPU upgrade */ + /* Enable C1e, C2e, C3e, and C4e states */ + msr = rdmsr(MSR_IA32_MISC_ENABLE); + msr.lo |= ( (1<<25) | (1<<26) | (1<<31)); /* C1e, C2e, C3e */ + msr.hi |= (1<<0); /* C4e */ + wrmsr(MSR_IA32_MISC_ENABLE, msr); + } + + /* Lock on Powersaver */ + msr = rdmsr(MSR_IA32_MISC_ENABLE); + msr.lo |= (1<<20); + wrmsr(MSR_IA32_MISC_ENABLE, msr); +} + +static void nano_init(device_t dev) +{ + struct cpuinfo_x86 c; + + get_fms(&c, dev->device); + + /* We didn't test this on the Nano 1000/2000 series, so warn the user */ + if(c.x86_mask < MODEL_NANO_3000_B0) { + printk(BIOS_EMERG, "WARNING: This CPU has not been tested. " + "Please report any issues encountered. \n"); + } + switch (c.x86_mask) { + case MODEL_NANO: + printk(BIOS_INFO, "VIA Nano"); + break; + case MODEL_NANO_3000_B0: + printk(BIOS_INFO, "VIA Nano 3000 rev B0"); + break; + case MODEL_NANO_3000_B2: + printk(BIOS_INFO, "VIA Nano 3000 rev B2"); + break; + default: + printk(BIOS_EMERG, "Stepping not recognized: %x\n", c.x86_mask); + } + printk(BIOS_INFO, "\n"); + + /* We only read microcode from CBFS. If we don't have any microcode in + * CBFS, we'll just get back with 0 updates. User choice FTW. */ + unsigned int n_updates = nano_update_ucode(); + + if(n_updates != 0){ + nano_power(); + } else { + /* Changing the frequency or voltage without first updating the + * microcode will hang the CPU, so just don't do it */ + printk(BIOS_EMERG, "WARNING: CPU Microcode not updated.\n" + " Will not change frequency, as this may hang the CPU.\n"); + } + + /* Turn on cache */ + x86_enable_cache(); + /* Set up Memory Type Range Registers */ + x86_setup_mtrrs(); + x86_mtrr_check(); + /* Enable the local cpu apics */ + setup_lapic(); +} + +static struct device_operations cpu_dev_ops = { + .init = nano_init, +}; + +static struct cpu_device_id cpu_table[] = { + {X86_VENDOR_CENTAUR, 0x06f2}, // VIA NANO 1000/2000 Series + {X86_VENDOR_CENTAUR, 0x06f8}, // VIA NANO 3000 rev B0 + {X86_VENDOR_CENTAUR, 0x06fa}, // VIA NANO 3000 rev B2 + {0, 0}, +}; + +static const struct cpu_driver driver __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; diff --git a/src/cpu/via/nano/update_ucode.c b/src/cpu/via/nano/update_ucode.c new file mode 100644 index 0000000..8f7ee22 --- /dev/null +++ b/src/cpu/via/nano/update_ucode.c @@ -0,0 +1,150 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "update_ucode.h" +#include <cpu/x86/msr.h> +#include <console/console.h> +#include <stddef.h> +#include <cpu/cpu.h> +#include <arch/cpu.h> +#include <cbfs.h> + +static ucode_update_status nano_apply_ucode(const nano_ucode_header *ucode) +{ + printk(BIOS_SPEW, "Attempting to apply microcode update\n"); + + msr_t msr; + /* Address of ucode block goes in msr.lo for 32-bit mode + * Now remember, we need to pass the address of the actual microcode, + * not the header. The header is just there to help us. */ + msr.lo = (unsigned int)(&(ucode->ucode_start)); + msr.hi = 0; + wrmsr(MSR_IA32_BIOS_UPDT_TRIG, msr); + + /* Let's see if we updated succesfully */ + msr = rdmsr(MSR_UCODE_UPDATE_STATUS); + + return msr.lo & 0x07; +} + +static void nano_print_ucode_info(const nano_ucode_header *ucode) +{ + printk(BIOS_SPEW, "Microcode update information:\n"); + printk(BIOS_SPEW, "Name: %8s\n", ucode->name ); + printk(BIOS_SPEW, "Date: %u/%u/%u\n", ucode->month, + ucode->day, ucode->year ); +} + +static ucode_validity nano_ucode_is_valid(const nano_ucode_header *ucode) +{ + /* We must have a valid signature */ + if(ucode->signature != NANO_UCODE_SIGNATURE) + return NANO_UCODE_SIGNATURE_ERROR; + /* The size of the head must be exactly 12 double words */ + if( (ucode->total_size - ucode->payload_size) != NANO_UCODE_HEADER_SIZE) + return NANO_UCODE_WRONG_SIZE; + + /* How about a checksum ? Checksum must be 0 + * Two's complement done over the entire file, including the header */ + int i; + u32 check = 0; + u32 *raw = (void*) ucode; + for(i = 0 ; i < ((ucode->total_size) >> 2); i++) { + check += raw[i]; + } + if(check != 0) + return NANO_UCODE_CHECKSUM_FAIL; + /* Made it here huh? Then it looks valid to us. + * If there's anything else wrong, the CPU will reject the update */ + return NANO_UCODE_VALID; +} + +static void nano_print_ucode_status(ucode_update_status stat) +{ + switch(stat) + { + case UCODE_UPDATE_SUCCESS: + printk(BIOS_INFO, "Microcode update succesful.\n"); + break; + case UCODE_UPDATE_FAIL: + printk(BIOS_ALERT, "Microcode update failed, bad environment." + "Update was not applied.\n"); + break; + case UCODE_UPDATE_WRONG_CPU: + printk(BIOS_ALERT, "Update not applicable to this CPU.\n"); + break; + case UCODE_INVALID_UPDATE_BLOCK: + printk(BIOS_ALERT, "Microcode block invalid." + "Update was not applied.\n"); + break; + default: + printk(BIOS_ALERT, "Unknown status. No update applied.\n"); + } +} + +unsigned int nano_update_ucode(void) +{ + size_t i; + unsigned int n_updates = 0; + const struct cbfs_file *cbfs_ucode; + u32 fms = cpuid_eax(0x1); + + cbfs_ucode = cbfs_find("cpu_microcode_blob.bin"); + /* Oops, did you forget to include the microcode ? */ + if(cbfs_ucode == NULL) { + printk(BIOS_ALERT, "WARNING: No microcode file found in CBFS. " + "Aborting microcode updates\n"); + return 0; + } + + /* Considering we are running with eXecute-In-Place (XIP), there's no + * need to worry that accessing data from ROM will slow us down. + * Microcode data should be aligned to a 4-byte boundary, but CBFS + * already does that for us (Do you, CBFS?) */ + const u32 *ucode_data = CBFS_SUBHEADER(cbfs_ucode); + const u32 ucode_len = ntohl(cbfs_ucode->len); + + /* We might do a lot of loops searching for the microcode updates, but + * keep in mind, nano_ucode_is_valid searches for the signature before + * doing anything else. */ + for( i = 0; i < (ucode_len >> 2); /* don't increment i here */ ) + { + ucode_update_status stat; + const nano_ucode_header * ucode = (void *)(&ucode_data[i]); + if(nano_ucode_is_valid(ucode) != NANO_UCODE_VALID) { + i++; + continue; + } + /* Since we have a valid microcode, there's no need to search + * in this region, so we restart our search at the end of this + * microcode */ + i += (ucode->total_size >> 2); + /* Is the microcode compatible with our CPU? */ + if(ucode->applicable_fms != fms) continue; + /* For our most curious users */ + nano_print_ucode_info(ucode); + /* The meat of the pie */ + stat = nano_apply_ucode(ucode); + /* The user might want to know how the update went */ + nano_print_ucode_status(stat); + if(stat == UCODE_UPDATE_SUCCESS) n_updates++; + } + + return n_updates; +} diff --git a/src/cpu/via/nano/update_ucode.h b/src/cpu/via/nano/update_ucode.h new file mode 100644 index 0000000..14063fa --- /dev/null +++ b/src/cpu/via/nano/update_ucode.h @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ +#ifndef __UPDATE_UCODE_H +#define __UPDATE_UCODE_H + +#include <console/console.h> +#include <cpu/cpu.h> + +#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079 +#define MSR_IA32_BIOS_SIGN_ID 0x0000008b +#define MSR_UCODE_UPDATE_STATUS 0x00001205 + +#define NANO_UCODE_SIGNATURE 0x53415252 +#define NANO_UCODE_HEADER_SIZE 0x30 + +/* These are values returned by the CPU after we attempt microcode updates. + * We care what these values are exactly, so we define them to be sure */ +typedef enum { + UCODE_UPDATE_NOT_ATTEMPTED = 0x0, + UCODE_UPDATE_SUCCESS = 0x1, + UCODE_UPDATE_FAIL = 0x2, + UCODE_UPDATE_WRONG_CPU = 0x3, + UCODE_INVALID_UPDATE_BLOCK = 0x4, +} ucode_update_status; + + +typedef enum ucode_validity_enum { + NANO_UCODE_VALID = 0, /* We only care that valid == 0 */ + NANO_UCODE_SIGNATURE_ERROR, + NANO_UCODE_WRONG_SIZE, + NANO_UCODE_CHECKSUM_FAIL, +} ucode_validity; + +typedef struct { + u32 signature; /* NANO_UCODE_SIGNATURE */ + u32 update_revision; /* Revision of the update header */ + u16 year; /* Year of patch release */ + u8 day; /* Day of patch release */ + u8 month; /* Month of patch release */ + u32 applicable_fms; /* Fam/model/stepping to which ucode applies */ + u32 checksum; /* Two's complement checksum of ucode+header */ + u32 loader_revision; /* Revision of hardware ucode update loader*/ + u32 rfu_1; /* Reservod for future use */ + u32 payload_size; /* Size of the ucode payload only */ + u32 total_size; /* Size of the ucode, including header */ + char name[8]; /* ASCII string of ucode filename */ + u32 rfu_2; /* Reservod for future use */ + /* First double-word of the ucode payload + * Its address represents the beginning of the ucode update we need to + * send to the CPU */ + u32 ucode_start; + +} nano_ucode_header; + +unsigned int nano_update_ucode(void); + +#endif /* __UPDATE_UCODE_H */

1 0

Patch set updated for coreboot: f473298 NOTFORMERGE: VX900 early init, Nano CPU init, and EPIA M850 board
by Alexandru Gagniuc 08 Aug '12

08 Aug '12

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1228 -gerrit commit f473298a4c34744036802c00194b0bb4fcbc90a5 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Wed Jul 25 13:16:39 2012 -0500 NOTFORMERGE: VX900 early init, Nano CPU init, and EPIA M850 board Early initialization for VIA VX900: MMCONF: Works from very early ramstage. I am curently keeping MMCONF disabled during development, because I want to timestamp romstage, and compare the with and without MMCONF results. SMBUS is functional. RAMINIT: Raminit works with 1 rank, but untested with several ranks. DRAM calibration when more than one DIMM is present is not fully implemented. Correct MRS command mapping not implemented for DIMMS which swap address pins. The delay calibration strategy is to put some predefined delays for the DQ input delays, and run hardware calibration on the other three delays (DQS input, DQ/DQS output). For the future, we could change this strategy to one that uses the hardware calibration of DQ input. Unfortunately, according to my testing, the DQ input delay calibration does not work reliably. Memtest runs through the serial console, and does not whine about any memory errors (longest test was about 6 hours). VX900 in ramstage: LPC: Added LPC driver struct in VX800 code. The LPCs seem to be similar enough that the VX800 LPC code works on the VX900 (not fully tested) VGA still displays garbage. The VGA driver for VX800 could work with the VX900, provided UMA memory is initialized during romstage. I have decided to initialize the VGA in ramstage for two reasons: 1. bugs in the initializing of the VGA can make the memory checks fail, and 2. ramstage is compressed, so we save a bit of ROM space. The VX800 VGA code can thus not be used for the VX900. VIA EPIA M850 board: Minimum infrastructure to compile a coreboot image for this board is added; most PCI devices are switched off in devicetree.cb The VIA Nano patch: http://review.coreboot.org/#/c/1257/ will be updated once the new CBFS microcode system is merged and fixed. Change-Id: I7624944dbc05fbf3019897a116954d71dfda0031 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- .gitignore | 7 + src/arch/x86/Makefile.inc | 7 - src/arch/x86/include/arch/romcc_io.h | 28 + src/cpu/amd/model_10xxx/Kconfig | 33 +- src/cpu/via/nano/nano_ucode_blob.c | 900 +++++++++++++++++++++++++ src/cpu/via/nano/update_ucode.h | 2 +- src/devices/dram/dram.h | 154 +++++ src/devices/dram/dram_util.c | 297 ++++++++ src/devices/smbus/early_smbus.c | 141 ++++ src/devices/smbus/smbus.h | 99 +++ src/include/device/pci_ids.h | 22 + src/include/lib.h | 1 + src/lib/ramtest.c | 35 + src/mainboard/via/Kconfig | 3 + src/mainboard/via/epia-m850/Kconfig | 46 ++ src/mainboard/via/epia-m850/Makefile.inc | 21 + src/mainboard/via/epia-m850/devicetree.cb | 89 +++ src/mainboard/via/epia-m850/mainboard.c | 24 + src/mainboard/via/epia-m850/romstage.c | 79 +++ src/northbridge/via/Kconfig | 1 + src/northbridge/via/Makefile.inc | 1 + src/northbridge/via/vx800/lpc.c | 6 + src/northbridge/via/vx800/vga.c | 48 +-- src/northbridge/via/vx900/Kconfig | 38 + src/northbridge/via/vx900/Makefile.inc | 44 ++ src/northbridge/via/vx900/chip.h | 23 + src/northbridge/via/vx900/chrome9hd.c | 364 ++++++++++ src/northbridge/via/vx900/early_smbus.c | 191 ++++++ src/northbridge/via/vx900/early_uma_ram.c | 135 ++++ src/northbridge/via/vx900/early_vx900.c | 59 ++ src/northbridge/via/vx900/early_vx900.h | 46 ++ src/northbridge/via/vx900/forgotten.c | 32 + src/northbridge/via/vx900/forgotten.h | 78 +++ src/northbridge/via/vx900/northbridge.c | 136 ++++ src/northbridge/via/vx900/raminit.h | 72 ++ src/northbridge/via/vx900/raminit_ddr3.c | 1046 +++++++++++++++++++++++++++++ src/northbridge/via/vx900/romstrap.inc | 50 ++ src/northbridge/via/vx900/romstrap.lds | 27 + src/northbridge/via/vx900/traf_ctrl.c | 35 + src/northbridge/via/vx900/vx900.h | 74 ++ 40 files changed, 4446 insertions(+), 48 deletions(-) diff --git a/.gitignore b/.gitignore index 8e259c7..40c3f79 100644 --- a/.gitignore +++ b/.gitignore @@ -1,3 +1,4 @@ +.gitignore .config .config.old .xcompile @@ -47,3 +48,9 @@ util/superiotool/superiotool util/romcc/romcc util/romcc/tests/*.S-O2-mmmx util/romcc/tests/fail_test*.S +*~ +*.patch +*.rom + util/ +coreboot.kdev4 +memtest diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index d08f66a..3b27fe3 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -51,9 +51,6 @@ endif ifeq ($(CONFIG_AP_CODE_IN_CAR),y) COREBOOT_ROM_DEPENDENCIES+=$(objcbfs)/coreboot_ap.elf endif -ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL),y) -COREBOOT_ROM_DEPENDENCIES+=$(CONFIG_CPU_MICROCODE_FILE) -endif extract_nth=$(word $(1), $(subst |, ,$(2))) @@ -105,10 +102,6 @@ ifeq ($(CONFIG_INCLUDE_CONFIG_FILE),y) sed -e '/^#/d' -e '/^ *$$/d' $(DOTCONFIG) >> $(obj)/config.tmp ; \ $(CBFSTOOL) $@.tmp add $(obj)/config.tmp config raw; rm -f $(obj)/config.tmp ; fi endif -ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL),y) - @printf " CPU uCode cpu_microcode\n" - $(CBFSTOOL) $@.tmp add $(CONFIG_CPU_MICROCODE_FILE) cpu_microcode microcode -endif mv $@.tmp $@ @printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n" $(CBFSTOOL) $@ print diff --git a/src/arch/x86/include/arch/romcc_io.h b/src/arch/x86/include/arch/romcc_io.h index 37fb7ab..8876b28 100644 --- a/src/arch/x86/include/arch/romcc_io.h +++ b/src/arch/x86/include/arch/romcc_io.h @@ -244,6 +244,34 @@ static inline __attribute__((always_inline)) void pci_write_config32(device_t de #endif } +static inline __attribute__((always_inline)) +void pci_mod_config8(device_t dev, unsigned int where, + uint8_t clr_mask, uint8_t set_mask) +{ + uint8_t reg8 = pci_read_config8(dev, where); + reg8 &= ~clr_mask; + reg8 |= set_mask; + pci_write_config8(dev, where, reg8); +} +static inline __attribute__((always_inline)) +void pci_mod_config16(device_t dev, unsigned int where, + uint16_t clr_mask, uint16_t set_mask) +{ + uint16_t reg16 = pci_read_config16(dev, where); + reg16 &= ~clr_mask; + reg16 |= set_mask; + pci_write_config16(dev, where, reg16); +} +static inline __attribute__((always_inline)) +void pci_mod_config32(device_t dev, unsigned int where, + uint32_t clr_mask, uint32_t set_mask) +{ + uint32_t reg32 = pci_read_config32(dev, where); + reg32 &= ~clr_mask; + reg32 |= set_mask; + pci_write_config32(dev, where, reg32); +} + #define PCI_DEV_INVALID (0xffffffffU) static inline device_t pci_io_locate_device(unsigned pci_id, device_t dev) { diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig index 64ac850..221d044 100644 --- a/src/cpu/amd/model_10xxx/Kconfig +++ b/src/cpu/amd/model_10xxx/Kconfig @@ -3,7 +3,6 @@ config CPU_AMD_MODEL_10XXX select SSE select SSE2 select MMCONF_SUPPORT_DEFAULT - select RESPECTS_UPDATE_CPU_MICROCODE_OPTION if CPU_AMD_MODEL_10XXX config CPU_ADDR_BITS @@ -52,4 +51,36 @@ config SET_FIDVID_CORE_RANGE endif # SET_FIDVID +config UPDATE_CPU_MICROCODE + bool + default y + +config UPDATE_CPU_MICROCODE + bool "Update CPU microcode" + default y + depends on EXPERT && CPU_AMD_MODEL_10XXX + help + Select this to apply patches to the CPU microcode provided by + AMD without source, and distributed with coreboot, to address + issues in the CPU post production. + + Microcode updates distributed with coreboot are not necessarily + the latest version available from AMD. Updates are only applied + if they are newer than the microcode already in your CPU. + + Unselect this to let Fam10h CPUs run with microcode as shipped + from factory. No binary microcode patches will be included in the + coreboot image in that case, which can help with creating an image + for which complete source code is available, which in turn might + simplify license compliance. + + Microcode updates intend to solve issues that have been discovered + after CPU production. The common case is that systems work as + intended with updated microcode, but we have also seen cases where + issues were solved by not applying the microcode updates. + + Note that some operating system include these same microcode + patches, so you may need to also disable microcode updates in + your operating system in order for this option to matter. + endif # CPU_AMD_MODEL_10XXX diff --git a/src/cpu/via/nano/nano_ucode_blob.c b/src/cpu/via/nano/nano_ucode_blob.c new file mode 100644 index 0000000..6fc04db --- /dev/null +++ b/src/cpu/via/nano/nano_ucode_blob.c @@ -0,0 +1,900 @@ +unsigned array[3588] = +{ + 0x53415252, 0x00000000, 0x010f07d9, 0x000006f2, + 0x04bb1af1, 0x00000001, 0xffffffff, 0x00000ca0, + 0x00000cd0, 0x46363030, 0x45325032, 0x00000000, + 0xcb93e3bb, 0x191b8d4a, 0x1863851e, 0x5073b90e, + 0x637e23a3, 0xfb2b5429, 0x04714c6c, 0xc15656b7, + 0x1a338d28, 0x1b182ec1, 0x3c52af0a, 0x6d370976, + 0x969bc177, 0x64487a31, 0xcc081129, 0x5e1eab09, + 0x60510c3c, 0x8a8056df, 0xd63b03a9, 0xa44b1274, + 0x0debc269, 0x8b0345ed, 0x4970a2f6, 0x207d49ea, + 0x204d200f, 0x382f15c8, 0xa036eb02, 0xb4a7bc00, + 0xdb71ba56, 0x94b7c995, 0x9a62daf2, 0x1121f430, + 0x3e4a5be0, 0x3c7161fc, 0x871cf176, 0x401b4152, + 0x7666d9e6, 0xa7d0a300, 0xba2badc0, 0xb76c09d7, + 0x20188e4c, 0x790a4683, 0xc9e67da8, 0x0e06ac83, + 0x61a20460, 0xff613e2b, 0x75987149, 0x1f377798, + 0x0d2d0a03, 0x80770351, 0xfdd1521a, 0x9e0c3559, + 0x615cff3f, 0x4b52bf4f, 0x7f147ef1, 0x8710413d, + 0xa1f56c83, 0x82b4e353, 0x41059fd8, 0x0ba3cee2, + 0xec086b55, 0x30884385, 0x8de9db16, 0x5b43fe34, + 0x181d9769, 0xaf85ba70, 0xc1e0339d, 0x57543307, + 0x6a9f4dae, 0xc311f618, 0xb517af2e, 0xf1dee71b, + 0x055b82d4, 0x2c87f018, 0x855e566e, 0x62902b91, + 0x81add936, 0x369c1e10, 0x580b5188, 0x72884066, + 0x60451175, 0x33f8c435, 0xeb7a0000, 0x403bb343, + 0xa7af4cee, 0x52dc1a70, 0x0f14769b, 0xc3322154, + 0xbe2d133c, 0x18631717, 0x4dd84315, 0x004885c0, + 0xeb301a26, 0xff84832c, 0xcba0da4a, 0xa62d6358, + 0x63f014e7, 0xfd11a7cd, 0xe4caac35, 0xee8eac91, + 0xf46f29e6, 0x98b09104, 0xf3e95a8d, 0x66b0a414, + 0xd8fc6cd4, 0x5ffd91e9, 0x59df2432, 0x5a76aba5, + 0x39564d85, 0x05743921, 0x0f8c6cc2, 0xc75205b0, + 0x69ebf3a1, 0xbd742cf5, 0x75b4904f, 0xb6757441, + 0x0019eb84, 0x65186919, 0x5cda5257, 0x9abec161, + 0x2703a74d, 0xb8e17040, 0xcee1b384, 0x13e81aed, + 0x5f1accea, 0x61593e03, 0x1e3a816e, 0xddd02632, + 0x489c55c3, 0x999ee852, 0x6f1fc127, 0xb8a3dda1, + 0x88218af7, 0xafd4a7c1, 0x8a9cd570, 0x525b63d8, + 0x39ca4752, 0x18cda626, 0xc6871457, 0x53606f5f, + 0x57e6bc19, 0xe7fca134, 0x5b554854, 0xa92ca963, + 0x9fefd3ff, 0x208c2169, 0x585520fa, 0x1661b36e, + 0x47ab65ee, 0xdfebfbf9, 0x9c66a187, 0x17dad804, + 0x2c78cadc, 0xd5e76482, 0xc5325e9f, 0x75f4e6a3, + 0x5bf89d31, 0xe3b8343b, 0x66ae81c0, 0xb08e79bd, + 0x7c14f7d3, 0x77c55a1c, 0xb9564471, 0x7fbf729a, + 0x80b59bd8, 0xa11c09fd, 0x07e3ca4c, 0xbab01bcd, + 0x3789f6bc, 0x9818d37d, 0xe6d32289, 0x0f6a4bf6, + 0xcd25812f, 0xb77d2cdb, 0xfc2d2824, 0xb86998dd, + 0x66de552c, 0x063f6eba, 0xd65591a3, 0x59ade6b7, + 0x5dfa16eb, 0x8c5b0b17, 0xc5b92112, 0x2f5a48b8, + 0x81ad574a, 0x42259f3e, 0x79403f4b, 0x0924fc75, + 0x108fe221, 0xa251e85f, 0x4e8c16ec, 0x365c9527, + 0x2abbb52f, 0x118c79a7, 0xb05ba6c0, 0x0eb2b3ed, + 0x8b011c88, 0x79175adb, 0xcbafe02c, 0x9307c24f, + 0xd15209ca, 0x23e569fd, 0x26815346, 0x425bd748, + 0x504217c2, 0x64e9d2c0, 0x400ba29a, 0x632e3858, + 0x7ab4e2d5, 0x6e868452, 0x85bd8005, 0x189cd3c0, + 0xd3cbe3f7, 0x820a90aa, 0x4f68b900, 0x65c53860, + 0x9a86de7f, 0x4c836b6b, 0x73841092, 0x78590b4a, + 0xcd4afc02, 0x73e79113, 0xafefe0f9, 0x30bec385, + 0x1fc9252f, 0x6ee8ce4d, 0x3cfa91bb, 0xf493ad13, + 0xf02593e0, 0xa63b96da, 0xa7a9c5cb, 0xdcf34661, + 0xdabcc8c9, 0x1f330aa8, 0x288df4de, 0xffc2462a, + 0xba825a78, 0x6a12478b, 0xda32e0a9, 0xb832887e, + 0x5fe63cc3, 0x26cc1f1b, 0x4c7015be, 0x52b54080, + 0xb025f5f1, 0x8f8d5ede, 0xbfd6ce2f, 0x924891c3, + 0xbe57187d, 0x46e5774f, 0x60a835a3, 0x55a976d3, + 0xe30f0595, 0xca07e54a, 0x8231e320, 0x8f977146, + 0x475d7c82, 0x10d413c6, 0xc052b913, 0x4c837bc3, + 0xbb18ba72, 0x504e64d8, 0x6981f723, 0xda361a85, + 0x93443179, 0x74ee16a6, 0xe69a40a5, 0xc117916c, + 0xef2f94ac, 0xa06b1e43, 0xdc6e01f9, 0x738e45d0, + 0x6b691cca, 0xd3aee7a7, 0x4fe6ee6c, 0xaf2c3419, + 0x936e5354, 0xaa757d6d, 0xd01d94fc, 0x47472d81, + 0x59489f6d, 0x05cc8f75, 0xeaf2c914, 0xde038603, + 0x421e1d5d, 0x45130e4f, 0x8567c50a, 0x240a6fe6, + 0x2d270151, 0xeebc219e, 0x0c144950, 0x7d720b18, + 0xe6fcf50f, 0x0cda08b2, 0x9241fad6, 0x93152f2d, + 0x168b85b9, 0x6eeaeacd, 0xd260c66e, 0x98722b57, + 0xe7fcce71, 0x8cf65088, 0x7c218a64, 0x9e957b44, + 0xb2f65850, 0x077e049f, 0x2e53ea65, 0x7bf3cb90, + 0xca9a4364, 0xddacedc2, 0x1d14f350, 0x3bde8346, + 0xf7e5d1ee, 0x7328349d, 0xd665e46f, 0xeffc771b, + 0xb8e40217, 0xaf1ffddb, 0xacef49f0, 0x7a4767e1, + 0x29659ac1, 0x8fdfee86, 0x2652e871, 0x32ef6440, + 0x23981fef, 0xd6956341, 0x44996531, 0xc6dac529, + 0xdb49a5c1, 0xb49e0268, 0x03b9a628, 0x859a9cb5, + 0x2324f6de, 0x8e09a640, 0x73111b32, 0x209d2265, + 0xf8ce7adf, 0x1fee2336, 0x91be0cc2, 0xa6231b34, + 0x2ee23a48, 0x1f9f0f02, 0xcef888d5, 0x54928d45, + 0x84a864f8, 0xdffdc2ac, 0xedead650, 0x895781ca, + 0x2c1ae5c7, 0x7cd560f0, 0xf346ad96, 0x2a919ca3, + 0xe845fb6a, 0x5d571861, 0xa28f98f7, 0x0625128f, + 0xb3032eea, 0x5e737938, 0xab4e2758, 0x30da5a1a, + 0x0700091c, 0x49e24af7, 0xb8739db8, 0x7071cb8d, + 0xe8b664cf, 0x5fd996ac, 0x69949200, 0x7e8e89ed, + 0xb534a7bc, 0x79fcab56, 0xf7c922c0, 0x260db9df, + 0x044a7415, 0x771bf7c6, 0x43c80438, 0xa68f9d6e, + 0x26866efd, 0x069dbef7, 0x5ec95f89, 0x118a6f4e, + 0x04f307c8, 0xd2442831, 0xc3a4055d, 0x38dd57bb, + 0x5a2bf99e, 0x943c8216, 0x8a8a8d67, 0x06d8933d, + 0x36d8c238, 0x52892351, 0x233fca34, 0x8f37f14a, + 0x03da33bb, 0x5403344c, 0x89abc6db, 0x0c615ee4, + 0x841c70f6, 0x2eb7465a, 0xbe04d7f2, 0x58d30b98, + 0x684f579c, 0x04968042, 0xa1288066, 0xa02d7561, + 0xef31130a, 0x7af7c497, 0xd06ac0f2, 0xd7d213f3, + 0xc7151981, 0x6f62d944, 0xfa29cd6e, 0xcc39d1c6, + 0x1ac2747b, 0x3c15dd86, 0x9c0c31eb, 0x81297dc2, + 0x1da797fc, 0x7eede51d, 0xb7acaba4, 0x3fe2d1af, + 0x72255af0, 0x99649635, 0x993f7868, 0x400d58f5, + 0x6d606432, 0xb3a02790, 0xbc8b9346, 0x001c3213, + 0xf0521676, 0x8fed58a2, 0x91a13447, 0x2a2e3fe3, + 0x3d961ac1, 0xee9f3e1a, 0xdb1e5cc0, 0x91170710, + 0x3bb17cd9, 0xa87cc42a, 0x29fb31dd, 0x540fa9c9, + 0xe74c97ef, 0x08e2ac05, 0xee5255cb, 0x8ccb8dad, + 0x14508794, 0x75702112, 0x05ecb30b, 0x5b68f36f, + 0xdd90f0f0, 0x4c60e9fe, 0x1152b8b2, 0x1598fe5e, + 0x10f1a26d, 0x95b63950, 0x4360fd96, 0x65c82329, + 0x2a4b6080, 0x9ff2d6aa, 0x8ff3c3af, 0x2ebdbdec, + 0xc42c46d9, 0x1af653ee, 0x5fbf4d3a, 0xa9936322, + 0xdc317ab0, 0x7671bdbd, 0xc971f3aa, 0x07978288, + 0x7c47615b, 0x0db52c1b, 0x3d0eda0b, 0xe63c6102, + 0xd56ef998, 0xaa755081, 0x0a749833, 0xcf4ec8ed, + 0x34a92cff, 0xee1bf9a1, 0xb59b0b64, 0x96354086, + 0x9d7d5a3c, 0x8144a9ad, 0x96830ca9, 0x90703b77, + 0x44db18c2, 0x0932960c, 0xc89dbf7b, 0x3ca76c1c, + 0xe6cc836b, 0x368eede3, 0x55c18caf, 0x00cbafd5, + 0xc3078024, 0x7d15441c, 0xd23ad62c, 0xf7661a68, + 0x98847057, 0xd6767a16, 0x196501b6, 0x68396b86, + 0xef4af71b, 0xa81367c2, 0xa4d13e7d, 0xbb8eebeb, + 0x4db5f47a, 0x731be642, 0xc2a15f27, 0x3324a7ea, + 0x0db10f7b, 0xaba8fe35, 0x225eb533, 0x9f188e3d, + 0xa5da4ad3, 0x3464c397, 0xc7572bc2, 0x43bc38e5, + 0x3a79ff7f, 0x3021c8f4, 0x822d257e, 0x295f9ee3, + 0xa62aa886, 0xeedfdbd0, 0x10ba9b9b, 0x6304cbca, + 0x03bbb766, 0x5fccc253, 0x6434c05e, 0xabd80cac, + 0x036ea64a, 0xc7babe5a, 0xde7b2fbe, 0xbcd2d22a, + 0x5f8219a6, 0xfc75fedf, 0x4f17ce1c, 0x6e670ca9, + 0x625b6ae6, 0xee8e9f95, 0x3b3eaae1, 0x9b3ca894, + 0x0b0ba78b, 0xfad8065d, 0xa1006779, 0xad9dc956, + 0x9f1d8e3d, 0x92f57a18, 0x9bc9e111, 0xc318ae8f, + 0xb6862269, 0x3d06fb0d, 0x861c740b, 0xb95e8053, + 0x419e7fd2, 0xc360dc82, 0x26d99c21, 0x4336524b, + 0x8a9414e5, 0xef9e020e, 0x57e81247, 0xa32a3cab, + 0x568e0a11, 0x4daf23bd, 0x1b5d7277, 0x212b7332, + 0xdb34afb5, 0xf3d0c01d, 0x5ca627df, 0xaa39c230, + 0x4192aa29, 0xed166fa9, 0x071922a6, 0x61074f39, + 0xfa700b5a, 0x4a60ed83, 0x1d1d9850, 0x5fe6c671, + 0x17730867, 0x6b2c5bfc, 0x0e0dd897, 0xa5c82db3, + 0xffcd57cb, 0x962ec9fb, 0x1ac2bdfc, 0x8b85b190, + 0x7a4b5a35, 0xd1224522, 0x900462c7, 0x32805daa, + 0xa1a8b29b, 0x4720559b, 0x1d846a68, 0x08edd510, + 0x02ca010f, 0xeadce4c4, 0x038cde06, 0xbdbfadac, + 0x9144d599, 0x670e6072, 0xc14d3857, 0x61f2de60, + 0x003d684f, 0xc1ddece7, 0x66c453b6, 0xaf66d81a, + 0xe15a2f94, 0xbb3c1f59, 0xab6f1f7d, 0x3b24d812, + 0xd629cd94, 0x09d51c81, 0x45cc0259, 0x8eaa8b98, + 0xbd945c62, 0x4e74d9ba, 0x449372d0, 0x59bbc106, + 0xaa2e4bda, 0xeb24fd0b, 0xc461db59, 0x89fb5031, + 0xd51d68bd, 0xe43f615f, 0x0cda1656, 0xe5d77e7a, + 0x8136b5c1, 0x13b0c9fd, 0x424adc1c, 0x62797556, + 0x450ac473, 0x7f1a6b9d, 0xf678b474, 0x56bd0f0e, + 0xe0d75f60, 0x29fc1192, 0xed79a7de, 0x331ffd62, + 0xacdac9e9, 0x59de2860, 0x81765718, 0x288c9049, + 0x5aa21365, 0x1d8c1119, 0x1f69f6aa, 0x9d5fecc7, + 0xccab7d03, 0x611dd66d, 0x88cff2c3, 0xa32df329, + 0xfb79f49c, 0xa5673b94, 0x01ca3e4a, 0x4a3c4a3a, + 0x79e381ee, 0xfdccd33a, 0xdfffe03c, 0x71785391, + 0xd35dc0a3, 0x90c514d7, 0x7f272154, 0x2fbade0b, + 0x7e7a40f7, 0x81225389, 0xbc7959fe, 0xfc11b819, + 0xb35a6494, 0xf2536a6f, 0x08797aa8, 0x448cd990, + 0x9444e16e, 0x03e145ae, 0xd5df6c1b, 0xbf11e6bf, + 0xa4cfa985, 0xa22bfbfe, 0x0a51c5c8, 0xdc037e99, + 0x22433d50, 0x734d2ba1, 0x8462dcd9, 0x93c0eaca, + 0xef87a4bd, 0x7ddfcd1e, 0x73e7d2c6, 0x55c6a86c, + 0xc1d99aae, 0xe88fa687, 0xbeadd303, 0x91af28c0, + 0x38e178a0, 0x903911b9, 0x804982e8, 0x4e28b42c, + 0x50d16e74, 0x5cf89c55, 0xa5e4a723, 0x69647877, + 0xb9e426a6, 0x5f0b5419, 0x4c810a84, 0x99c0bc0b, + 0x1c66db66, 0x9d664e5c, 0x97c517f4, 0xcd7bf742, + 0x284a6299, 0x29a414f6, 0x266b30bf, 0x341a3c0f, + 0x03649f3c, 0x3baaff4f, 0x150626e4, 0xcc705cac, + 0x97f93343, 0x5c667935, 0x796e0213, 0x87339a47, + 0xb67e7c0b, 0x19d36387, 0xfdebd50f, 0x2ccbb93a, + 0x53418f96, 0xb9913750, 0x474e557d, 0x39066bfe, + 0xc132ed2f, 0x969eef68, 0xeea46a2b, 0xf38d3ac8, + 0x94fa4b4a, 0x0f3d5a39, 0x663681bb, 0x052d913d, + 0x0ed760d8, 0x6a86a5e6, 0x3b4f8215, 0x45e1703e, + 0x7b6da797, 0x2f417ce8, 0x370805fb, 0x10d71f7d, + 0x939e57b1, 0x660658bf, 0xb0578eff, 0x83c92004, + 0x82d2e830, 0x6a069ede, 0x37bff328, 0xcfc11964, + 0xc1551e3b, 0x43f5f81d, 0x993a4c70, 0xb5368f5c, + 0xcdfd6ab1, 0x33fb820b, 0x8982c211, 0x658c9d3d, + 0x03d94fea, 0x9d14461e, 0xf6054c0b, 0x23505ea9, + 0x767bc220, 0x2ae3ca31, 0xf3994369, 0x60c3f27e, + 0x4b9b0489, 0x44cc2326, 0x8c6f6753, 0x92905384, + 0x4aa90362, 0x5fb075a6, 0x2e61e8bb, 0x46cd1270, + 0xe72c6c9d, 0x83111ee4, 0xccd8f5c5, 0x5103ec2f, + 0x6e851815, 0x947f246e, 0xde86ad18, 0x9760a987, + 0x059e48e2, 0x58a79e93, 0x6aa5b31a, 0x35aabcd5, + 0x71f4d3e7, 0x1ae1f425, 0xecce2950, 0x6253dc95, + 0xd91f8ddc, 0x214a4a07, 0xb4d299ad, 0x13ef8d8e, + 0xbed7b47f, 0x4a12a7eb, 0xeb0963ab, 0xdf0f3b8f, + 0x2aa6845d, 0x80881430, 0xd615c63d, 0x4d244696, + 0xf627cc27, 0xe03210af, 0x2bc55248, 0xf16867e9, + 0x1e065d75, 0xc2b362cd, 0xd9751d64, 0xc2949adf, + 0x53415252, 0x00000000, 0x061a07d9, 0x000006f3, + 0x08074e5a, 0x00000001, 0xffffffff, 0x00000390, + 0x000003c0, 0x46363030, 0x32315033, 0x00000000, + 0xb07f7392, 0x535a690e, 0xb60295df, 0xfaff25b9, + 0x4f4609e6, 0x9fe6ac72, 0x879663b0, 0xab25c96a, + 0x65e5e671, 0x5cd611f8, 0xf39e82bd, 0x931d23de, + 0x4504a04c, 0x2ba455fb, 0x2fc1034c, 0xbd47d87e, + 0xdeb4d91c, 0x33e88111, 0xf1521b6d, 0xa0f8cb0f, + 0x013166c3, 0xa784e786, 0xb564c335, 0x826dca49, + 0xda84b5e5, 0x63b0da88, 0xd15fd3b3, 0x501590bf, + 0x9efa91a7, 0x5f8b7591, 0x97710227, 0xf162ab61, + 0x76ec62b9, 0xa8bbba48, 0x5be51483, 0xb84fdb38, + 0x933f9758, 0x8616b6b7, 0xc0b405c4, 0xcdbd4e00, + 0x254c6488, 0x907dc541, 0x90edf61d, 0x5beef31e, + 0x782de3cf, 0x158500d4, 0x9cee8612, 0xdebe1f64, + 0xce9d7aa3, 0x0b968a79, 0x520ae716, 0x3dc74a69, + 0xb2393da8, 0x6a9f4ec0, 0x7e609890, 0x07121f6b, + 0xb318c3f8, 0x52db78bd, 0x2530e9fe, 0xae1a1b72, + 0xef55426d, 0x462b9823, 0x9b5fcc9f, 0x46b525ee, + 0x5284a388, 0xc1ce0d78, 0xf9e86226, 0xaad31a00, + 0xb183aeb0, 0xa75f6593, 0xffa6705a, 0x1d43b713, + 0x644424eb, 0x1f9cc20e, 0xa096550f, 0x3497cebd, + 0x1941af1f, 0xcf205da8, 0xb3996a90, 0xa08cd793, + 0xe1021d21, 0xaa80086e, 0x30e29788, 0xd35458e5, + 0x6d5b50cf, 0xc5aaa0f0, 0xd8dceac7, 0x096d6e2a, + 0x10b245dc, 0xba5c77c1, 0x2970e03b, 0x4b742ff2, + 0x6a2ffbf5, 0x42d4cdbc, 0xeb2744c1, 0xf49eb6f5, + 0x806e288c, 0x608e6ad8, 0x9fa0d47f, 0xb40e1ae4, + 0x0e63b495, 0x6b1b1fbd, 0x8f1dcda5, 0xff0f7888, + 0xeb425a16, 0x1eee7e0a, 0x69c202bc, 0x04020726, + 0xbbc62de3, 0x6ebbd54b, 0x22be95c7, 0xe37298e9, + 0x309bd861, 0xb04b8d33, 0x63b1e9dd, 0xa27459a1, + 0x1f7f69eb, 0xb4cfda0b, 0x226d81a3, 0xaef54cc2, + 0xfdb2af55, 0x8f40bd55, 0x7c75fc1b, 0x1ea27f79, + 0x7d4775a3, 0x49b65d08, 0xbd9afb11, 0x9c54c786, + 0x01fe71ea, 0x9bfc7e9a, 0xe8dca094, 0x416dd13c, + 0xc160dfe5, 0x737538f7, 0x6e4a1a3b, 0x3e6dafc7, + 0x6d72e2ce, 0x12e54b8a, 0x7035f549, 0xb072e1d4, + 0x3b38588f, 0xe026e230, 0xeb224bf0, 0xe37f21c9, + 0x9a36fef9, 0x5d82682d, 0x11e5edc2, 0x3442a202, + 0x5072abc3, 0xe544eb7e, 0x578bde22, 0x295f8584, + 0x02c23076, 0x35476376, 0x9f135eb8, 0x0613fe0f, + 0x5ff04afc, 0xd3e1053f, 0x23b58392, 0xc4a0f77a, + 0xb87814d6, 0x3a8c17f4, 0xb5efab44, 0x3fe2c21e, + 0xcbe0efb6, 0x12997b25, 0x5b18b44e, 0x6b849d21, + 0x580f84e4, 0x99a964d0, 0x3fa892a9, 0xd4b01144, + 0x6d54c83b, 0x31659593, 0xd7596e21, 0x642c0e11, + 0x7403ea9c, 0x47719512, 0x33a86634, 0x8ae60597, + 0xb94e5df6, 0x5cf4e917, 0xe438f361, 0x8f5d4d13, + 0x00f3d7b7, 0xb9b15305, 0x8e9e1537, 0x350c32f9, + 0x31d5f77f, 0xdb7ae793, 0x70094efd, 0xca83ff65, + 0xa7f487dc, 0xb15ddccc, 0x99609635, 0xf06787f3, + 0x8bc4b4e1, 0x6ebc77e2, 0xf55f780b, 0x4a3b9c96, + 0x91860f8a, 0x75827196, 0xb5948530, 0xc7152cb7, + 0xec776fea, 0x55c73d21, 0xc4b036c5, 0x69af8697, + 0x1d80bc77, 0x91eea8a8, 0xd1ba9808, 0x5a0a812f, + 0xc2a14b33, 0x351a2801, 0xc0b41870, 0x3241a4f9, + 0xa09fe4b5, 0x407aae2b, 0x394b6e00, 0x323a0b88, + 0xa01681d5, 0xda56a382, 0x216d8f3d, 0x7b8e0b61, + 0xfb4aa26e, 0x6e5c4623, 0xdc082e4c, 0xe9ea397c, + 0x53415252, 0x00000000, 0x061907da, 0x000006f8, + 0xd4f1b587, 0x00000001, 0xffffffff, 0x00000220, + 0x00000250, 0x46363030, 0x46325438, 0x00000000, + 0x3299b452, 0x689711fa, 0xee4c84d4, 0xba1598f3, + 0x1b403653, 0x2798a70b, 0x224e13ad, 0xc328665d, + 0x19f33bc3, 0x54e1be26, 0xe8128c3f, 0x06f9f27f, + 0x6fb344ff, 0x36bd410e, 0x229793f2, 0x4d5bc18d, + 0xc4f03970, 0xfc7234d0, 0x1856eb5d, 0xcb3a0ed7, + 0x524e9de9, 0x1f6cde76, 0x1affdd49, 0xadd2bab5, + 0x9c472670, 0x84553d4e, 0x7c8124e1, 0xaddd4ac0, + 0xf3588d7c, 0x4642a4be, 0xb1eaa4e5, 0x9069602a, + 0x44118af3, 0x3c4c0dbc, 0xacfafeca, 0xa6c708be, + 0x4610f501, 0x91f4aabe, 0x0fa3cddf, 0xc64761a7, + 0x22022ece, 0xa4d589bc, 0x237de460, 0x60067a6c, + 0xf4cff750, 0xd7f5f8c5, 0x9ce2a52a, 0x5653e820, + 0x139344a8, 0xc1203a30, 0x4e7f9226, 0xf562836d, + 0x0280a4f9, 0x6f23eb5e, 0x3a0e7684, 0x23281e3e, + 0xb3c7c258, 0x216d2392, 0xba5f0c35, 0x4e82b0fc, + 0xf4e4b3ab, 0x1cd124b7, 0xe1a3261c, 0x5972c999, + 0x9575d310, 0x58c81253, 0xc24d1f17, 0xd224c5f7, + 0x1205ac8a, 0x2a0fccee, 0x3017b59b, 0x8caf9c22, + 0x9e2a470c, 0x3a217bfb, 0xafc9c401, 0x8f278be9, + 0xedcc7fce, 0x293cfb52, 0x2fbcf8f5, 0x2470a1df, + 0xc8fa046e, 0x58315fcb, 0xfc7c7834, 0xcab53bdd, + 0xf3615edf, 0x65f5df91, 0xb145ec86, 0x246bb495, + 0x6a71f1e8, 0xc01d50cf, 0x6768cb06, 0x835912be, + 0x884a8f0b, 0xafa8c8c0, 0xfa37d361, 0x8026f64e, + 0x8c755c89, 0x4c412800, 0x94f8c215, 0xcee50ecd, + 0xe4098f72, 0xe932bccd, 0xf0d2a3b0, 0xe3cbfd25, + 0xecc7ce41, 0x501b9db9, 0x160ef756, 0x35e97342, + 0xc1de34a6, 0xb9f30ca2, 0x1e5018a7, 0xcc6ed6c3, + 0x84698919, 0x8e1337e2, 0x299b3d65, 0x401339a2, + 0x437d0911, 0xa0baf2cc, 0xe23713b1, 0x814cde1a, + 0x18977d01, 0x22a6a5fd, 0x75eba689, 0x586ecb90, + 0x9a5b37e3, 0x3d3da0f1, 0xed63599a, 0x40dba6cc, + 0xa8a920a7, 0x9b548faf, 0x7562d2ca, 0xd69ac4e0, + 0x59ef1bfc, 0x08787853, 0x82844a28, 0x2cd823e5, + 0x53415252, 0x00000000, 0x051a07da, 0x000006f8, + 0x5d1a2de5, 0x00000001, 0xffffffff, 0x00000c20, + 0x00000c50, 0x46363030, 0x64325038, 0x00000000, + 0x1239d07e, 0x691e32e0, 0xd205e5c0, 0xdfc570de, + 0x278e4479, 0x4bca3390, 0x6e7e9b71, 0xd4a85a32, + 0x99af2c5e, 0xb452d0a5, 0x4bec4f39, 0x045a8308, + 0x09639159, 0xe5ee7bd3, 0x1f49d8ef, 0x3a72c6ce, + 0x9a299074, 0xf7a294c2, 0xf88ad4e9, 0x99a46faf, + 0xd106a8e9, 0x1c1c978b, 0x22c43cc1, 0x4af01738, + 0x1f0d51e1, 0x43976497, 0xd59b7f7c, 0x77879a05, + 0xe8e89fed, 0x93e1b538, 0x9d3855ef, 0x7ea23c17, + 0xe550e1f6, 0x17613f73, 0x0783fc18, 0x81980e9d, + 0x107dc8df, 0xe620b143, 0x48236b44, 0xabf1efb9, + 0x7100c5c7, 0xd2245ace, 0x8c859d0b, 0x563a71b7, + 0x697dc982, 0xc34a7399, 0x84fea92f, 0xfe6fae64, + 0x5e053930, 0xf3de4ab5, 0xc9924782, 0xa4509166, + 0x96780cbb, 0xf9008bb1, 0x4d9f7e1b, 0x0e117f75, + 0x01c28c4a, 0xe4321ae6, 0xfb340eab, 0x666247a1, + 0xa8a5a4a8, 0xe47a3486, 0x94b71bff, 0xeb6d4841, + 0x51b7dbbf, 0xcf6bdc3e, 0xae0c68a0, 0xd28c8e55, + 0x170435d7, 0x9ee8dcb5, 0xcd2de33e, 0xd13ac2de, + 0xa15478d6, 0x226485e7, 0xff7ab105, 0xa0c4ae78, + 0x4a8c6cd6, 0xbe4008ab, 0x1037e1e5, 0x5eeb7789, + 0x9811fe9c, 0xde44c9ed, 0xa2ffd6d1, 0xecc9f0da, + 0x00a460e2, 0x44767b1a, 0xe854e585, 0xc70d0131, + 0x3f519a63, 0x468d4386, 0xbbd9c826, 0xa8de428a, + 0x0015b96d, 0x17221e10, 0x514e719e, 0x62398cee, + 0xb67bb642, 0x0b552de8, 0xe2b2d2f6, 0x22be5083, + 0x5ab773ae, 0x46cf2603, 0x86d62320, 0xa0748945, + 0x5493221a, 0xa783c1ba, 0x622660e8, 0xb6dc2449, + 0xc1897743, 0xfd20c8b4, 0xe14c135f, 0x4e811706, + 0xdfdd2b7d, 0x3c16ffa5, 0xd0905f28, 0xc823bef5, + 0xd862aa3b, 0x31365fb9, 0x7bd9c7ab, 0xbcf2d6c4, + 0xbfc18909, 0xe26312ca, 0x5a68d937, 0x6d250f9b, + 0x0781914d, 0xabe54ba9, 0x85d894e6, 0x8c825963, + 0xc6e50f72, 0x538ea5a1, 0x861a4623, 0x2bffc2de, + 0xe28ae4a2, 0x397d6007, 0xa861f13d, 0xdba785be, + 0xc11c37e5, 0xc41a74d7, 0x0f1485c5, 0x1e477a67, + 0x8c3d8f46, 0xf7ed4dc8, 0xe99bc25a, 0x1900b0b0, + 0xe5cb1b0e, 0x86d18bbf, 0x06ce255c, 0xa762a311, + 0x721137c7, 0x26770edd, 0x41839b2c, 0x4bd33366, + 0x53836b63, 0xfdc9ed92, 0x5a5145cd, 0xb389fb44, + 0x2314ff6d, 0x3b6f0c95, 0x3b201e62, 0xbc5c0994, + 0xc620809b, 0x2d9cfacb, 0xe7ed2028, 0x43ecd1c1, + 0x13586475, 0x4a720fd7, 0x402f351d, 0xb9781bf9, + 0x730e46b4, 0x6810e052, 0xf1dd1b73, 0x8c93e152, + 0xb668f9a8, 0x387ee173, 0x41b84b1a, 0xfccfcd68, + 0x6047f011, 0xaec6155a, 0x29e0273b, 0x3c9d935e, + 0xcb98f03e, 0x4fb51e6f, 0x3ad9b929, 0x6569a278, + 0x09b3f6a5, 0x722e9d27, 0x3d4e7da7, 0x11eb3728, + 0x076d703d, 0xdca1cf88, 0x2bfad541, 0xcb82293b, + 0x99c39f16, 0x6bcb6cbb, 0x1ed41582, 0xcc9be6f0, + 0x11f00eb4, 0x1ba055d1, 0xe9a43853, 0x5c055bbe, + 0x1ba8500c, 0x70430fd4, 0x45583d82, 0xfc41ef87, + 0x3e513205, 0xfd65386c, 0x8a814402, 0x14117437, + 0x8a486978, 0xb49cc14d, 0x9c22a9e9, 0x746c15ae, + 0xcab3486f, 0x3989de53, 0xd7e237cb, 0x5feb4d98, + 0x5c56cbc2, 0x841b5e44, 0x09c9a118, 0xf1f2d529, + 0x4fb098fc, 0x1cb3e1ea, 0x9f25bb78, 0xd56f9469, + 0x38b08d7a, 0x19b0e914, 0x86311f65, 0x7069459d, + 0x711daf17, 0x09738673, 0x53e9bedb, 0x043032e5, + 0x32058bd4, 0x22b1a50f, 0xc66b2642, 0x2a7c553c, + 0xe7da476d, 0xdfbcc19a, 0x538b5822, 0x3bca007f, + 0x082d45fc, 0x78bfcdcb, 0x98e554c4, 0x9ec8e392, + 0xebf5ed7c, 0x3b154db7, 0xacf59ef8, 0x8443d4a5, + 0xd90a6e4d, 0x486d9807, 0xfd4bab17, 0x76628450, + 0xc73b007e, 0x9397abc5, 0x63f035c8, 0x92c4603b, + 0xe5807fd2, 0xd305a2ae, 0x65d2c231, 0xdf35bd23, + 0xaae754fe, 0x46b9de20, 0x699fd249, 0xa38ddaf0, + 0xb3dbf2df, 0x151c7094, 0x7bf864b9, 0x65aff002, + 0x7d8d621b, 0xce073aa8, 0x6086f5b5, 0xfd4d8243, + 0x791482c3, 0x0df0d01d, 0x6ad8e4ba, 0x6ad0d3f7, + 0x2b77d92b, 0x6d68d02d, 0x4a43d822, 0xfef3b1a1, + 0x54e96282, 0xdb7ab5b3, 0x72aac1d9, 0xfb4f83ad, + 0x1e51747c, 0x36fea058, 0x1e715a12, 0xf3aa6639, + 0xfd1a3a64, 0xf173bee2, 0x6a382ad0, 0x48435821, + 0x31b90284, 0x3b9ba0c1, 0xf2329444, 0x323f7d8d, + 0x8c72dc74, 0xce9301e1, 0x8cb5cd91, 0x124f7dcd, + 0xcac6a0f6, 0xe487f261, 0x88e05297, 0x49074df2, + 0x1c4c72ea, 0xbf37e900, 0x09103656, 0x723f13f7, + 0x454b06c2, 0xe35eaf5f, 0x8879aaa4, 0x78c5ef10, + 0xe5895238, 0x749df405, 0x0ce57fec, 0x6da90247, + 0xea013e94, 0x6c907d03, 0x1b2f69b5, 0xb2744c73, + 0xad1fa97c, 0xca641bb7, 0x10af012e, 0x0c922243, + 0xa35519c2, 0xcc3067e7, 0x1064d47d, 0x087e9aa6, + 0x803b5642, 0x9936d3c1, 0x3336db24, 0x2c3ccdec, + 0xe5b6be8a, 0xe69dea99, 0x4a6f9632, 0xa9a945ca, + 0xe7ba26df, 0xb2dae8a0, 0xde770e47, 0x91138e00, + 0x3895be22, 0xd0b5f9b5, 0x834c3f69, 0xf75d5f75, + 0x90468761, 0x009f6475, 0x73fe55e6, 0x73a00e1c, + 0xddaaa0c5, 0xeb3ab712, 0x15d4c070, 0x1cdafd9f, + 0x67831b13, 0xef666e8c, 0xc28c36a6, 0x42e5e1f4, + 0xd5eb66b7, 0x388f50b3, 0x048c56ed, 0x2f4f9415, + 0x435785a6, 0x9d42dc6f, 0x4273b34e, 0x3c3595e8, + 0x15f938b4, 0xe2dd91ca, 0x83336b59, 0x4fd6fb7c, + 0xbb696bdf, 0x27ce9bd3, 0xdbb85616, 0xf9d9fb6a, + 0xb2f0eff5, 0x9216697f, 0x8f51ff6c, 0x99aa370b, + 0x2acda31f, 0xd6a36d34, 0xd8475f8d, 0x00c6db0e, + 0xfb5db914, 0xeccd35a5, 0x9de84e78, 0x11c242a3, + 0xae3788e1, 0xc3f11ed6, 0xdb7da54d, 0xf9c24298, + 0x2d1ddec5, 0x180df86c, 0x32fd5b37, 0x82e762ba, + 0x19c464f9, 0x0b746141, 0x7069dd69, 0xd509970c, + 0xdd325119, 0xe6195b0d, 0xf56796e7, 0xa0d7b2c9, + 0xe392698d, 0x3d72adeb, 0x40e9eff3, 0xdf27aa62, + 0xfbe9b1bb, 0x3eaf1333, 0x32d9cba9, 0xa90704aa, + 0x2de9b422, 0x50f4c07c, 0xb63b4b7e, 0xa34313ca, + 0x981dedfd, 0xeab79e01, 0x8900d971, 0x54ecd36d, + 0x09146d31, 0x232c3d8b, 0x724b0f3f, 0x27beaf1b, + 0x6380dce1, 0xf345f0c1, 0xa6cd4fb7, 0x5412699f, + 0x0ebceac3, 0x92a5d843, 0x6c47d876, 0x34db9582, + 0xf0159db3, 0x1e08b349, 0x8858102d, 0x24109519, + 0xbcb7cae4, 0x84cf5852, 0x9e052e13, 0xb81c27bf, + 0xd2750406, 0x5a35b818, 0xfb2c4908, 0xa4972bf0, + 0x89296d16, 0xa7d13b99, 0xd74fa892, 0x1a9de940, + 0xf2f439d9, 0x81eae6cd, 0x964f0918, 0x20c1f8bc, + 0x415977f4, 0x85a775dd, 0xac52244e, 0x8fcc423c, + 0x2d29104d, 0xbc61c01a, 0xf9675ac5, 0x90b773d2, + 0x54d53eea, 0x1a9f081c, 0xa052d353, 0x9813df28, + 0x3b2f5310, 0x0e771c09, 0xf4fedb01, 0x3e8efd60, + 0x278d845d, 0xde7f42ba, 0x2345f3ac, 0xbebef98c, + 0xe8adcba5, 0xdcd1e4ad, 0xf83bc609, 0x9a2fa38f, + 0x2ac6482f, 0xa20cf438, 0x1a56ccc9, 0x79f1ed26, + 0xd16c090c, 0x3c4d43ba, 0x3b2face9, 0x8f2a121a, + 0x23bff2f3, 0xc05f634e, 0x7abcaff3, 0x8f640674, + 0x91c1718a, 0xafed69e8, 0x5045ac4a, 0x1305672c, + 0x50d9e2e3, 0xcc009820, 0xcf623411, 0x383811a7, + 0xc1803f0f, 0x20cee852, 0xa5954ac9, 0x930e486f, + 0xb6381088, 0x8c5f599b, 0x7c36f62d, 0x603132d6, + 0xe79e0289, 0x23e6bbcb, 0xf36d61c5, 0xa188ccb4, + 0x8138aea8, 0xa93c9f62, 0x68450a57, 0xedf82eca, + 0x7e930a05, 0xc368bf51, 0xb92feb10, 0x17f95ccf, + 0x6f15cfea, 0x0c6734c4, 0x7c86850d, 0x01ed6dbd, + 0x1db961a7, 0x50d369c2, 0x81fe1af0, 0x598b6b2a, + 0x42a3a9cf, 0x6e05e662, 0xf5b6a456, 0x2748aeb0, + 0xc4645796, 0x5d9c489b, 0xbd6c830e, 0x1c161f9c, + 0x476deedd, 0x269b3eec, 0xc602402d, 0x4b6fc409, + 0x9f068add, 0xda7e60b9, 0xd8348fcb, 0x73d2b0d1, + 0xa5959497, 0xeef9eca7, 0x4e32cb40, 0xec36b3ec, + 0x4f1b132a, 0x662d5a69, 0xa6a019d6, 0x5c463ceb, + 0x7d41e303, 0x59014126, 0x00fa882c, 0x4b1364b2, + 0xcf0fabda, 0x2b1c9268, 0xb43c1b3f, 0xa684737b, + 0x47f06aac, 0xcb04b166, 0x2af950ee, 0x216d324e, + 0x9a9fbbbe, 0x33a47d17, 0x76f86457, 0xd93c3cd2, + 0x20db26d9, 0xd49946dc, 0x6d95f662, 0x937c535a, + 0x096e0a00, 0x62c05258, 0xe21c3f63, 0xbd267ef9, + 0xc8c98b92, 0xb3e7880a, 0x528d53d3, 0x1d33fd8a, + 0xf94c986f, 0xa8e57165, 0xac413d88, 0x34f19e3b, + 0x50a3d8b7, 0x58fb8676, 0x54769514, 0xbde066cb, + 0x2f764378, 0xea725550, 0x0a8da2f2, 0xca2eb43e, + 0xdb390910, 0x99912ba4, 0x684a13a0, 0xf9dfce0c, + 0x892a9f9a, 0xae224458, 0x18711cf0, 0x65c356ec, + 0x381439ef, 0xd464bd27, 0x35de3dff, 0xaaa4df24, + 0x10d24190, 0x3928a9cc, 0x0c825daa, 0x478c90a3, + 0x5e6e78ca, 0x74f376d9, 0xd956af27, 0x063de8ca, + 0x2f01ee2a, 0x6bc4cf28, 0x3e34901c, 0xd32a57ee, + 0x213685b6, 0x75d5440a, 0x10695179, 0xded4b2b0, + 0x7061436d, 0xbf4ea54e, 0xbd2ddcd5, 0xcfcc7995, + 0xbc811e36, 0xcf6b17a3, 0x2bb295b6, 0xd3c0e8f2, + 0xf8d0f7d6, 0x185a221b, 0x25006d43, 0xffbb6a42, + 0x519c1a07, 0xe1e1024e, 0x5061c863, 0x4b0ba1ea, + 0x5f86a8cb, 0x9a141d40, 0x65ed1bbb, 0x59aaccdc, + 0xc301f198, 0xfc80d362, 0x5a837e5a, 0xe0cfb2e5, + 0xc260a4dd, 0x31eff844, 0xfa7a0250, 0xff916b6a, + 0x532e7112, 0xec3d9fb3, 0x67eadd71, 0x5d035008, + 0x1031f03e, 0x10bc1eb0, 0xa4ffda78, 0x3fc90618, + 0x069d00fd, 0x55e1a1a2, 0x0a989734, 0x5e710bde, + 0x014971ee, 0x4da810b6, 0x81bc117d, 0x4c1ef7ce, + 0x3b1700d3, 0x71384ebd, 0xdd61e7e8, 0x289950f1, + 0xd07180c8, 0xb2e515cc, 0x997acc95, 0x5be0c088, + 0x1d8158dc, 0xf0a69511, 0xb956f917, 0x9b5d5862, + 0x0d6465b6, 0xce06697f, 0xfe1c0e62, 0xa4580f33, + 0x2eeb88b5, 0x681dac6a, 0x9cfc3e9b, 0xa6ac8962, + 0xf3881c23, 0x20e2f490, 0xc2537859, 0xed893623, + 0xf425531f, 0x318333b7, 0x3256ae11, 0xd7a21e7a, + 0x878f5dea, 0x863f99d8, 0x6a0aff4b, 0xad9ef05f, + 0x2e0b2622, 0x328ee279, 0x9d78deba, 0x098fb6b4, + 0xfd55c005, 0x09f38311, 0xaf043a10, 0x5beef91b, + 0x49003cd2, 0x9131085f, 0x6fa720d9, 0x478eba08, + 0x1ebd8a6c, 0x70a5de24, 0xf3381bd1, 0x0cd7e36e, + 0xb8a700a0, 0x2e9c5742, 0x9b09100e, 0x57c7e936, + 0xf9505650, 0x3e0aeb75, 0x48bb9648, 0xdafe191a, + 0x0dcfc0eb, 0x99959593, 0x23215288, 0xd094cb50, + 0xd5e7fbb2, 0xc891856d, 0x9e5939fd, 0xd394ea44, + 0xf9657de6, 0xa2a2775b, 0x9926805d, 0xd8ac5f16, + 0x5c86f714, 0x00d46245, 0x1303e8ea, 0xc98bb0e2, + 0x3417f3ee, 0xe75bfce0, 0xeadd8c71, 0xc17a4930, + 0x5f29da29, 0xe807c6d0, 0xbed5247f, 0xbf731759, + 0xf9787556, 0x3a476c20, 0xd85972b5, 0x1ec03708, + 0xa0690f12, 0x2fc6ed76, 0x014aa07c, 0x3725e608, + 0x31adaeb9, 0x2d1a12bf, 0xc97eed8c, 0xe55bb6f0, + 0xc6e2c259, 0xa09811a2, 0x8dae432c, 0x969602b5, + 0xf389d691, 0x32d9dc61, 0x43758e7b, 0x7c4b2cf6, + 0x97945f6c, 0x59c54e8a, 0x6262fbb0, 0x677b4c79, + 0x7a1f6899, 0x17298ee9, 0x6b0cd48f, 0xe38037cc, + 0x3c210d43, 0xe5239986, 0x15140d7f, 0x6be997b4, + 0x34e54608, 0x896736ef, 0x6f719086, 0x1c946889, + 0x8c02a0a5, 0x530d2d15, 0x76afe26b, 0xbec240c8, + 0x53415252, 0x00000000, 0x0a0507da, 0x000006fa, + 0xc28eb1c2, 0x00000001, 0xffffffff, 0x00000300, + 0x00000330, 0x46363030, 0x37335441, 0x00000000, + 0x0d31346a, 0xeb2ca8ec, 0xc65a3981, 0x28ddcdcc, + 0xf3a8fae5, 0x19d731f5, 0xdf863966, 0x7635b5f2, + 0x36d4f0b2, 0xbe24024e, 0x51f57cda, 0x9241c870, + 0x68895578, 0x74f59766, 0x5fbda11c, 0xb818f7d7, + 0xf35d31b8, 0xe4e576ee, 0xbe1a8a54, 0xe6c59c9c, + 0x54d5b539, 0xdca35f5b, 0x19eba0ec, 0x4fba2f04, + 0x0df76dfc, 0x05d5b057, 0x36784885, 0x5b43e337, + 0x14285276, 0x4561194e, 0x103a82ae, 0x9c7b625a, + 0x9d96b6f3, 0xa4fd5883, 0x20585c48, 0x94c67d0d, + 0x9ce050d2, 0xd0b5165e, 0x63a0bd8e, 0xf9cd1ece, + 0x1584115a, 0x5a662320, 0x63e96e07, 0x7818aac2, + 0x6e71233d, 0x1fd178d4, 0x79f16ec9, 0x82f84202, + 0x39d8be98, 0x15723245, 0x48ce0075, 0x801ead46, + 0x69e8dd35, 0xe5d94c2a, 0x6abb1b97, 0x20762ad6, + 0x5e0df657, 0xf7f9a887, 0x20ffb759, 0xbb52002c, + 0xa488ebeb, 0xac4eb608, 0x2dd6fc64, 0x67763775, + 0x31961884, 0xcd2edeb2, 0x275aed6f, 0x90d87287, + 0x2e0f651a, 0xf14b5cac, 0x6bc86e79, 0xcd5ea86c, + 0x322ae237, 0x7ece1ef2, 0x45abb79e, 0x5a1b6a68, + 0xe3aa633f, 0x9f471388, 0x73ac0258, 0x32ef97ee, + 0xe7a98b7a, 0x3feb205f, 0x5466aca4, 0xbf65921c, + 0x977da54a, 0xeb27e06f, 0x44bd2376, 0x78e9dd9b, + 0x0c426ef0, 0x6ba253ff, 0x1ea0144d, 0x6099a85b, + 0x1f0de3db, 0x15e925f7, 0x1e172b91, 0x8a9d83ab, + 0x0948df11, 0xc4338ceb, 0x3d13d77b, 0xc4ba859e, + 0x601c45a4, 0x2b7a4cfd, 0xd6f42cb0, 0x03827c56, + 0xcbe180ef, 0x8ac33028, 0xdd3a5aea, 0x772c2d5d, + 0x44884fa7, 0xb37de9c0, 0x9e7fba9d, 0x761f99f1, + 0x118f7fcc, 0x7bd6346d, 0xa5c85359, 0xe09d8dae, + 0x6034a867, 0x4af20a35, 0xe213d5b5, 0x83678e65, + 0x7fa12f26, 0x881bf834, 0xd7a898f9, 0x2e00d34d, + 0xadfd0f9f, 0x64f62e57, 0xeb94a4e6, 0x2741735d, + 0xfdd7bf3d, 0x0bb5d428, 0x04c6cf8e, 0x7c91f2e2, + 0x862dafe0, 0xe2bc5ef5, 0x1cf8983f, 0x48fb28fb, + 0xf3725287, 0xfceacf3c, 0x9c97d1b6, 0x244aa0f2, + 0x74cd0c3d, 0x62def4c1, 0x5389a927, 0x9213a193, + 0xfbccaf62, 0xe0c52a28, 0x2f960d1e, 0x261fdc3a, + 0xa4011e50, 0x8cba98a3, 0xc1ee67fd, 0x8bdc9bd1, + 0xd2ba1d9a, 0x2ff19168, 0x2c893f34, 0x465b9763, + 0xac4a2241, 0xdabab40a, 0x848d8ed7, 0x32e0c7db, + 0xe037749b, 0xa806fe6d, 0xfd392283, 0x54c23f8b, + 0xddff2a30, 0xbc3cf4b2, 0xfa60ba33, 0xa9bba869, + 0x0ab138e4, 0xd0a75765, 0x83a03739, 0xed1e0b96, + 0x7b2a9c07, 0x21d68bd2, 0x1c74b719, 0x63eaac88, + 0xea824a44, 0x3f1e946d, 0xaa660153, 0x30d73746, + 0x25019ec8, 0x93a60137, 0xebd12222, 0x2a97f7a8, + 0xca0d18f0, 0x60a7b913, 0xe208502f, 0xf7f99b2e, + 0xa111ffab, 0x17977781, 0xa1d5ac7b, 0xdeb44610, + 0x53415252, 0x00000000, 0x091807da, 0x000006fa, + 0x0bd03d37, 0x00000001, 0xffffffff, 0x00000c10, + 0x00000c40, 0x46363030, 0x36335041, 0x00000000, + 0xa8502cf0, 0x6b8ae36f, 0xcc201a00, 0xf99bd698, + 0xbaa54ce5, 0xd26c6c64, 0x6586a335, 0xdf114ce6, + 0x65768732, 0x0c9fff59, 0xf0c87c99, 0x3cb93d44, + 0x776f6f6a, 0x4cd46553, 0x3b5548de, 0xba94bd6d, + 0xacfdae04, 0x01d0ed9a, 0x2b51dcbb, 0x0e88b2c0, + 0x0a87b9bd, 0x7fdafd01, 0x2b2114a4, 0x094f0a66, + 0xa19ef4ff, 0xf00fc22f, 0x0a791589, 0x14b0605b, + 0x65c880ce, 0x98a25bd3, 0xc46bcf0f, 0x23b28754, + 0x9d5b0d0a, 0xc7b95ff1, 0x4b559af5, 0x2c972fb7, + 0x24c7393a, 0x50953092, 0xcdfbb400, 0xd8b74e66, + 0x167c8540, 0xe5f33cf3, 0x6f06bece, 0x67853c91, + 0xec256024, 0x4321a8d7, 0xdf8db159, 0xb3c4ea19, + 0x49c55dbb, 0x6cd0893f, 0x24926b88, 0x8b6d8c1e, + 0xcbc1ca74, 0x0d97abf7, 0xbd0683e5, 0xfbd070ae, + 0x2d86f2ba, 0xdf2d5df1, 0x1c94ac1d, 0xce105cc6, + 0x707d966a, 0x425adf11, 0xd5437db4, 0x9439e46c, + 0xf491c327, 0xa264301e, 0x74f59c4c, 0x4fd8cd7d, + 0x4d2ee13b, 0xeedc9b07, 0xb48c496e, 0x0a9a158b, + 0xe2aa1f80, 0xe56e1be4, 0x601147a5, 0x9e8e1a67, + 0xe311dea5, 0x0e787f57, 0xe6d48d91, 0xfc5efa36, + 0x8d740ced, 0x626aa6ec, 0xfa47f6c6, 0x78236dbc, + 0xac414eda, 0xbe9b7c3f, 0x922aa24c, 0xe824c36b, + 0x4bf0a6ea, 0x4650f510, 0xe14ea433, 0x8a863587, + 0x99f2e00c, 0xace2241e, 0x673a6a21, 0xeacd0611, + 0x1d5d9f26, 0x63542bdc, 0x19769443, 0x83fb04f6, + 0xd2dba174, 0x41fc8e8e, 0xb753a248, 0xbe7f5d53, + 0x97bd16c8, 0xb6e3ea74, 0x10a04714, 0x678ba0fe, + 0x41903bb6, 0xdc3f69f5, 0x69c0e20e, 0xa3857a0e, + 0xa66aec62, 0x4f1129d4, 0x39bf5e5c, 0x6566814d, + 0x6ebc5d8d, 0x74fab02e, 0x6ce9ff42, 0x20dd4b0d, + 0x89a915bc, 0xdb86b288, 0xe6a2f5c0, 0xd26fa8d8, + 0x8ce2b6ef, 0xb38cb16c, 0x7e187321, 0xe9057cf7, + 0xfeff6963, 0xafcbd93d, 0x1ac7600e, 0xf953ad97, + 0xdd8daaa5, 0x24ffd3a3, 0x6a87f2e0, 0xa5a876ae, + 0xbe7ec94d, 0x630e9bdd, 0x14cf97ff, 0x0ad023f8, + 0xafc7d6b6, 0x01d9c914, 0xcaa89ce8, 0xb87471ee, + 0xf7a6722f, 0x37e1c449, 0x16efc69c, 0x6b5fd873, + 0x0cb4dbf5, 0xd7e3e2fc, 0x1b980086, 0x3fcc2b9b, + 0xef724017, 0x6ab5078a, 0x9c469135, 0xda49a6d8, + 0x94bd4cd4, 0x5ee98e66, 0x4bb9cd31, 0x96bb17de, + 0x3796eef6, 0x0a0cdc6f, 0x5855dd79, 0x21f4df2a, + 0x70fcf480, 0x1e408673, 0x2c9a1e7c, 0xd8281ab2, + 0xd2251523, 0xc207118f, 0xb520e691, 0xf7be5cd0, + 0xae7af3ad, 0xd8bd2853, 0xed06f5e7, 0x70e4318d, + 0xd949fff5, 0x84a7dca6, 0x54116bcb, 0xe38fab7c, + 0x41f88f1a, 0x148f2a61, 0x6598203c, 0xf3df679c, + 0xa47d2d48, 0x6ebd84aa, 0xca409338, 0x5ea735c7, + 0x8f5902a3, 0x486b9a72, 0x2a6c9f7a, 0x4f58af16, + 0x8e589cbd, 0x847b026e, 0xeb883553, 0x9bd04361, + 0xdf75294b, 0x5701b848, 0x8e4c290e, 0x84ae09a2, + 0x7c2e5310, 0x1f1e3351, 0x57464eba, 0x2f2bd882, + 0x55312151, 0xd699d4a8, 0x86c0cb2a, 0xc18625d5, + 0x01e34f5f, 0xdd71a9b5, 0x00d1404c, 0x478a8fdd, + 0xaca315cd, 0x08c2bb61, 0xe1e95f74, 0x5c0f2e74, + 0xc5b86ecd, 0x5efba52e, 0x27162c32, 0x2cd364e0, + 0x7c2ff4dd, 0x20afee39, 0x01f06c32, 0x5705321c, + 0x721e9a19, 0x0406919f, 0x793ddfdb, 0x34ad2684, + 0xb870a1c0, 0x12723655, 0x8f3a0553, 0x1eb77d55, + 0x31777ded, 0x80d06c75, 0x9e0f8431, 0x289bd541, + 0x742e6c03, 0xd9d32028, 0xb7891977, 0xaddc8f96, + 0x1815c705, 0x7c50fb3f, 0x72e1a6d5, 0x58a49102, + 0x94734a5a, 0xf1431853, 0xcb403be0, 0x80ff034c, + 0x1cca1d4c, 0xa451b20a, 0xcfff97a1, 0x6897d11a, + 0x153fe0f9, 0x6747b5df, 0x3a88bcef, 0x6648176b, + 0x7986c1d7, 0x3f2d7a08, 0x8ea0db0e, 0xf0f57877, + 0x0ed1edbf, 0x95158803, 0x0425f867, 0x79237bc3, + 0x28ce7bcc, 0x60f311a5, 0xc7ba09fb, 0x55596285, + 0xc724ebe4, 0xeac78d31, 0x3e6c778e, 0x05252503, + 0x3dcdcb51, 0x78c59d5c, 0xa3dee354, 0x52b19d1a, + 0xfca398b0, 0x63f65f9d, 0xc9fc4fa4, 0xd35ebec9, + 0xa3698241, 0x05d0e962, 0xf7526d10, 0x7777b4e4, + 0x72482300, 0x96d42113, 0xce18adb9, 0x0f6fae9b, + 0xbd737b23, 0x2f327586, 0x456e2db2, 0xe8bacf5c, + 0xa3333916, 0xb1045776, 0xe831b66b, 0x28c002f1, + 0x6907e87b, 0xd44c8009, 0xb8bfbd22, 0x5f11a712, + 0xb99ed38c, 0xf14ef1bf, 0xa50cffec, 0x3ac7cc61, + 0x967864d6, 0x0f4dd3f2, 0x9a52c6e0, 0x4622af4c, + 0x8c5fe79d, 0x1f5aaf51, 0xb379d3fc, 0x06f5485c, + 0xb46f53fc, 0xfb7b867e, 0x4fd79268, 0xb426ba21, + 0x3bd32579, 0xeccf15e1, 0xdbf2585f, 0x38dc054a, + 0xf66e29ce, 0x93d218ef, 0x38a61bee, 0x5d764b3b, + 0x698c1bee, 0xd1f1dcca, 0xcb4d774f, 0x7ae6113e, + 0xbc46ab5d, 0x7cea59f7, 0xef726f3c, 0x86e552c8, + 0x54b5c263, 0xbb9f213c, 0xb0ec7aee, 0xae412550, + 0x7d672e4c, 0x479482d1, 0xbe984fd4, 0xbb40b4e9, + 0xce460f5b, 0xc25d2d8e, 0x14d43871, 0xc622459e, + 0xd25cdf24, 0x4cfc08fe, 0x6e66c76d, 0x6163f5e5, + 0x590ef352, 0x38dd5eee, 0x5b56b3c0, 0xbf7a708f, + 0xd11ce5b9, 0x46fe1639, 0x87e53fae, 0x52b6d358, + 0x32d6eb0b, 0x2c8d0693, 0x7b823fba, 0x1743a83d, + 0x89ec17f7, 0x74679c91, 0x14768344, 0xf27ab26f, + 0xcafbebd7, 0xb996128f, 0xef5940d8, 0xf3d2817c, + 0xbfa77515, 0x223a22a1, 0xc301ff17, 0xfb63edb7, + 0x4d0b235a, 0x9dbd7318, 0xf165ef57, 0x872805e4, + 0x78fbcb1b, 0x8715e546, 0x909b519b, 0x073ebe68, + 0x520c18f5, 0x75d543ef, 0xfffd247f, 0xc51faa72, + 0xc3ff9c28, 0x05d95767, 0xf8a8ce29, 0x6c3100df, + 0x9602b7b5, 0xf1df9514, 0xdfbde49a, 0x63f347c3, + 0xa3fedee4, 0x5ab74220, 0x9e3ab0fb, 0x6024aa18, + 0x941b54f2, 0xaf740c6b, 0x07278738, 0xdc9f9f70, + 0x528d7eb4, 0xb78b4da4, 0x7e0859ca, 0x4d7f2f34, + 0x4cce084c, 0x1e1eaa38, 0xe237324d, 0x096f11bc, + 0x8b040823, 0x2a1c921a, 0x13df560f, 0x8d6f9621, + 0x34ed0c9c, 0x8f52c968, 0x8c079396, 0x5c2d78c5, + 0xba61f0ba, 0x0d6737a7, 0xc7ac90b5, 0x40711497, + 0xc610777e, 0x1baf3ab6, 0x2a509778, 0xb64267ae, + 0xf0292472, 0x316c99d9, 0x2773d52f, 0x31de412b, + 0x7d7c33d9, 0x5418cbd7, 0x779a60f5, 0x2b6635a1, + 0x4a7480ad, 0xa91700ed, 0xdd719d72, 0xf4ef7bfa, + 0xf292f4a7, 0xe20a154c, 0x6980673e, 0xd087d272, + 0x3f62947c, 0xcf82e629, 0x998f72d1, 0x181537ec, + 0xec99111e, 0x9ff94a7e, 0x5838ed56, 0x652e00ad, + 0x63d2e127, 0x291b39ed, 0xe8874f1f, 0x9fcea857, + 0x4b44e4d7, 0x79facf6b, 0xfa97248d, 0xabf1b436, + 0x44bf8ca3, 0xa2342483, 0x27b39aae, 0x54ad61e8, + 0x62aaf9c8, 0xcf1f0e5f, 0x57727cb9, 0x2bbe1a27, + 0xad813e18, 0xade7e54a, 0x6d9ae354, 0x7dda6e41, + 0x6b503615, 0xe539a489, 0xacd4cf0c, 0x50b5ee9b, + 0xe12cd634, 0xdaa2358a, 0xf3ed5c3c, 0xd7bf1749, + 0xc8953072, 0x8e5cebe6, 0xa89070ea, 0xb8978ab1, + 0x9bb10556, 0x14552e00, 0x5e3254e6, 0x3749eeca, + 0xdafe140d, 0xe7ed3e04, 0x5bed7ee9, 0xf9f2b6d0, + 0x78958f75, 0xe5e5677a, 0x6bd77819, 0x802ca29a, + 0x90bbda35, 0x1ed94bcc, 0x04d5fd91, 0xb23898df, + 0xef508485, 0xc2db56db, 0x335a3555, 0xafd667b7, + 0x2e41b466, 0xd17eb896, 0x98ba5a85, 0x7205a0cd, + 0xa89f5fe5, 0xbc8082bf, 0x0ea9336d, 0xd5f7695f, + 0x3df7ae79, 0x0c16a95b, 0x872eca3f, 0x6565c3c6, + 0xa7c70d84, 0x5a9cfc9d, 0xf9d365e1, 0x83b41c41, + 0xa361972f, 0xcedd50d9, 0x0dd0ffaf, 0x33beb660, + 0x6e5f8aae, 0x39d89272, 0x59a2dd37, 0x46b32dd6, + 0x23d1b438, 0xaed8f126, 0xf56c2494, 0x1be3e72a, + 0x49559bde, 0x651f3b68, 0xa77ee774, 0xf6ee86d2, + 0xd6958a8b, 0x12ba080f, 0xce76bd3b, 0xafad53b0, + 0xe5fb067a, 0x4f4b6149, 0x54215017, 0xad0378e2, + 0x482d9f3f, 0xfb953d72, 0xd078f21d, 0x8b91bcd0, + 0xd5eff898, 0x2d47c13a, 0xfc918304, 0x6569bbdd, + 0xdfccdc07, 0x3f6c1171, 0x0aa3e691, 0x22b945c6, + 0x123c08b9, 0x3c61ad47, 0xf3684a46, 0x6ddf05df, + 0x45587657, 0x65d93c69, 0x3028c52a, 0x0f0bc6f9, + 0x9686fdc6, 0x50c758fe, 0x4fb30ed1, 0xfbc1e704, + 0xfdb31f63, 0x593a7512, 0x316393b2, 0xc9f4832b, + 0x4f1a5a37, 0xb1b47d4d, 0x5fcc8ccd, 0xe8069867, + 0x0e3709c9, 0x09e4cb6d, 0x7a5db9a9, 0x64a714d4, + 0xbec5c79a, 0x16bea0a5, 0x81666c3d, 0x35f96dea, + 0x9b6405f0, 0x3ad8a387, 0x8672e95e, 0xf6b43b37, + 0x8c2a03e8, 0x454073e1, 0x2dcec42d, 0xf78c7e73, + 0x082676e2, 0x0350e3fb, 0xd8221bde, 0x825a4d19, + 0xb9fa4b07, 0xb107ffac, 0x2a4b6eea, 0x3e642e4b, + 0xa7585a91, 0x84610e89, 0x63238347, 0xbbc51fd3, + 0xfe022393, 0x5ca78d29, 0x817b9406, 0x4e56ceb6, + 0x41675640, 0x2e7ce351, 0x97409f25, 0xf723c6ec, + 0x0392c2de, 0xd6a28f3a, 0x78de0130, 0xae0a3790, + 0xee61980d, 0x7f1bb7b8, 0x1e09abde, 0x978c8936, + 0x3f389b96, 0xec790b39, 0xf822a35b, 0x8a1d3592, + 0xdebdb41d, 0x133b9d1a, 0x5883447b, 0xbcf8bb09, + 0x8fe79675, 0xaa8f1d7b, 0xd017c7b7, 0xcd06e94f, + 0x8755fc1a, 0xffaa89fa, 0x29be8e81, 0x6fcf52a5, + 0x55725694, 0x02573e0b, 0x233e87cc, 0x4ef6c107, + 0x6f903aec, 0xe71d60d1, 0xa043f83c, 0xe5899344, + 0x40d5ea27, 0xde3a6bd4, 0x22cffa9b, 0xb70a3a9d, + 0xee1e1fc1, 0x9f304bcf, 0x9a00125e, 0x4fdce973, + 0x81cfc376, 0xba14685c, 0x1307212d, 0x9d3cb67c, + 0xcf5174a2, 0xce2df038, 0x3d98a9bb, 0x1e4e0289, + 0x70370e7a, 0xab7f5a12, 0xd9a73509, 0x84073ecd, + 0x1640aed1, 0xb129a7e9, 0xfd8d50b7, 0xaa97ef05, + 0xa398d289, 0x3d0445b0, 0x2a063516, 0x0ac49d0e, + 0x273b8e5e, 0xad1c3b0a, 0x59c61b56, 0xdf16f4b2, + 0x55710d7c, 0x4f8a9a78, 0xe9a3e9cc, 0x96c33642, + 0xc1711c0b, 0x453e85a7, 0x36cb0791, 0xd052b65f, + 0xd9745f46, 0x720f96c6, 0x112e753a, 0x8e487589, + 0x040c3d65, 0x1c642c49, 0x59cebaef, 0x3c44c71d, + 0x416fe930, 0xa2092f52, 0x8b89f343, 0xf44f9656, + 0x2fe20f9e, 0xbc5acf24, 0x43238ee6, 0x247a5997, + 0x2f0e3771, 0xc03e76d9, 0xdef328ee, 0xed802543, + 0x2a32c194, 0x4cd92940, 0x3d9eccbc, 0x9fb7ac0e, + 0x23e4acff, 0x0f6ef7cd, 0xdfb588d0, 0x2aa0b794, + 0x7a5d022a, 0x4356c9b3, 0x97281179, 0x41337e53, + 0x76790819, 0xb9a5ca77, 0xaf1a9b2a, 0x1a655dfb, + 0x6b106bc8, 0xee6fcab5, 0xe16c7aac, 0x45cb5be6, + 0x280d9a95, 0xf2ddc81b, 0x9e1f01e0, 0x1148cf1d, + 0xf483fc39, 0x3a66021c, 0x1057a22c, 0xa0685244, + 0x1e8a55bc, 0x0390fe02, 0x76c29392, 0x53c53e08, + 0xa733d7a2, 0xcb877f82, 0x4fd82ea5, 0x53cb96f3, + 0x4547075d, 0x41c477e8, 0xb0912c69, 0x57ed6e48, + 0x3e743d6c, 0x882451c7, 0xc868cedd, 0xb3fae605, + 0xd81848cb, 0xf3b16ab0, 0x5f3c7494, 0x4fca84d3, + 0x621cafcb, 0xa7225d72, 0x83596120, 0xc8f57258, + 0x5b443741, 0x0858ebb9, 0xa7392619, 0x26c71263, + 0xdfac85c7, 0x95929d75, 0x2a082fe4, 0xb91c4054, + 0x2b1a13b2, 0x717e3a2c, 0xfe2165ed, 0x1c5b1653, + 0x9ab498cd, 0x3b3d437a, 0xe9c737d3, 0xfd071595, + 0x638c4625, 0x997ec96b, 0xa4b0d070, 0xe459568c, + 0x53415252, 0x00000000, 0x091807da, 0x000006fa, + 0xd43a9824, 0x00000001, 0xffffffff, 0x00000940, + 0x00000970, 0x46363030, 0x36335041, 0x00000000, + 0x302b7fb9, 0x51c322f3, 0x1481e6b5, 0x9950f1a5, + 0x27048310, 0xb3895c51, 0x5a93c4a9, 0xeb6c4601, + 0x95b0f2ff, 0x99ff6dc9, 0x83843695, 0xb687e255, + 0xa3efa9f1, 0x23d98810, 0x846ac2d3, 0x1c9d6010, + 0x6715bfdc, 0xa789fab9, 0xe56a1d09, 0x0eeb0427, + 0x9ed0a3a7, 0x45ec7559, 0x0c2eb033, 0x17f146dc, + 0x30c35795, 0x37a56765, 0x66b11205, 0x5471a208, + 0x5a0049b8, 0xc008aca5, 0x29ee84fb, 0x66e3303d, + 0x101656d6, 0x2e7de920, 0x673cabfd, 0xf05d1c06, + 0x64c507f6, 0xd823cbe0, 0x7e7f4183, 0x04cad122, + 0x747e3ba9, 0x3226c602, 0x7dc01760, 0xce634320, + 0x84f55355, 0x1c411f23, 0x6972e335, 0x06f74042, + 0xa8006f71, 0xfeed7d7e, 0x3f09abbf, 0x6a1a8c7f, + 0x0d1b730c, 0x5c73a586, 0x9d73ed26, 0xe43c786a, + 0x1da597e3, 0x34c8f323, 0x447d5fb3, 0x9976957d, + 0x2c5df47b, 0xf19a1bc3, 0xe53b3cbe, 0xf0a8e170, + 0x11f0f112, 0x60e00900, 0xc4014477, 0xcbbda9cf, + 0x478c7d43, 0x0c76da66, 0x54f59535, 0x3a310af5, + 0x81a2e87b, 0xae577790, 0xc610b904, 0xaa7afec7, + 0x0ba491df, 0xc44ac7ea, 0x055551b0, 0x967834ff, + 0x46075ceb, 0x3f0d8a90, 0x6336f1f4, 0x638e85be, + 0xdbc8df61, 0x0112c46c, 0x94aa12ed, 0xe1814406, + 0xcb48defa, 0x4c5543ca, 0x756f2306, 0xd7a66dd7, + 0x48262543, 0xece84d6d, 0x6addde77, 0x8e5045a5, + 0x94761706, 0x2a8f98ff, 0x14898b09, 0xc5111544, + 0x60c93fc7, 0x6bea5ad2, 0x81282ca0, 0xe34f2730, + 0x9013ce09, 0xebe061d9, 0x975eb536, 0xadcd9034, + 0x257fc5a9, 0xffc3bd52, 0x1eadf9ba, 0x0bd81a5c, + 0xea0c52f9, 0x8347a620, 0x78663976, 0xccaa6aec, + 0x2bd641d4, 0xc3dcc4dc, 0x55e5296d, 0x9e94bfe1, + 0x746c3a01, 0x99f0dcea, 0xf52657aa, 0x3622ceb3, + 0xa95f8c65, 0x8eaaee04, 0xd71aea04, 0xfcfd6e78, + 0x7984686c, 0xe40a8dbf, 0xf50ee2e9, 0x93eb96c1, + 0xe834ee5b, 0x5d05b60b, 0x20c10cea, 0x0a8c2645, + 0x155a6187, 0xde1aedae, 0x7204cf15, 0xe85373e4, + 0xe9f93d4a, 0xc7531d3a, 0x5c535875, 0x46ec1ae6, + 0x6aeea9bd, 0x871bb354, 0x1ab2be63, 0xf8dad26c, + 0x7b04e772, 0x48564a81, 0x742d28ba, 0x6e698de4, + 0xa0779db3, 0x1ce0c3d7, 0x237cb6b0, 0xf286fe37, + 0x781af9aa, 0xf4d61b0b, 0xe26b7572, 0x51f38cb3, + 0x604873cb, 0x693a158f, 0xb2a0b427, 0xa6cf762b, + 0xe91831d4, 0x0376bf4b, 0x0ea5b667, 0x830b103e, + 0x25a8dd84, 0x21e82db9, 0x6d4c0e5e, 0xfb767d16, + 0x4b883e4b, 0x3de33b14, 0xc9490454, 0x33d61eb4, + 0xd0197448, 0x940e34a4, 0x8c48a3b1, 0x3456c76f, + 0x92535ef7, 0x95328e66, 0x8882cce2, 0xce2b761b, + 0x729cf0e7, 0xa892dd65, 0x804de33d, 0x1549715e, + 0x8c819f7a, 0x982d9d26, 0x05314c31, 0x2ea19906, + 0xf48db2da, 0xd1b20b93, 0x2bbaea99, 0x4289b538, + 0x1352afb3, 0x15aa3a0a, 0x3b80f3f5, 0xc1a1719c, + 0x132c9711, 0x46fd6ca8, 0x771b91c5, 0x09414702, + 0x9a9fb8d6, 0xff2bc606, 0xb6214f8a, 0x74dacacf, + 0x513c4dd5, 0x137fa66c, 0x503d5d37, 0xe024c0da, + 0x793e186f, 0x31c2bf95, 0x320c616a, 0x83719c1d, + 0xde0d6e00, 0x9409b2a0, 0xe213fae2, 0x21731821, + 0x83f51eb3, 0x3cb2eab5, 0xd9c401d3, 0x8d5379ac, + 0x624189bb, 0x5233e883, 0x1f3d0c02, 0x3b46edc3, + 0xb47d4661, 0xff867384, 0xf4daa252, 0xfc55fa25, + 0xb465352e, 0xe1ff2a20, 0x438427df, 0x8cd561f1, + 0x8c2debb1, 0xf89d5e68, 0x74015f75, 0xa5ea69fa, + 0x0197a406, 0xbc60439a, 0x32244a3c, 0x4c0b5007, + 0x61d1138d, 0x024a59f1, 0x305fe9cc, 0x724833dc, + 0xcbae0bea, 0x8de58519, 0x62968adc, 0xadd0011c, + 0xc5b23595, 0x5b3990c9, 0xd3c64ecc, 0xb5d33759, + 0x054c797b, 0xc172220c, 0xda29fe07, 0x7f450ebf, + 0xec12a33e, 0x86d9bbb3, 0x78bffba7, 0x6a183c16, + 0x3cdb717b, 0x601e0c7f, 0xcf945c26, 0x073e7331, + 0xdebd7ad0, 0x62879d5c, 0xe0273347, 0xa2ff18e4, + 0x78a14f44, 0x20728f07, 0x25cfa3d5, 0xd699e2a7, + 0xc729bf4e, 0x9250bd92, 0xbabf3a88, 0xf69d91ac, + 0x0de005b2, 0xee6c6551, 0xf3ec51af, 0x0d4ab84f, + 0x85b7f548, 0xa0dcf7ae, 0x55efb6a5, 0xbcc9fdb5, + 0xe789546e, 0x8a209948, 0xb49fc3dd, 0x945fd8f7, + 0x9c2ab04e, 0x17625832, 0x18253aab, 0x26e3b5fe, + 0xd03ebf0d, 0xe5f8b8e4, 0xcdf3ef2f, 0x4024ca62, + 0xd3436616, 0xd19b1010, 0x7e53746c, 0xbaea2597, + 0xdd72726c, 0xb5a6a4c4, 0x348efd94, 0xba4d3a94, + 0x3d736b7c, 0xd32fd9e8, 0x98624886, 0xeaab1e7d, + 0xeec8edc6, 0x51dacdff, 0xf7359960, 0x221caa31, + 0x34fb3350, 0x794d034c, 0x6aef3d76, 0xc925c505, + 0xf752c1ad, 0x04b61fde, 0x7b42ef68, 0x1a119091, + 0xe21077a2, 0xc0c21dfb, 0x480cee09, 0x70144e31, + 0x49d345b9, 0xb3fe6f47, 0x11d12867, 0xe99898c6, + 0x6e54b4fd, 0x5f8d169c, 0x93e707b9, 0x1a90974c, + 0xd6a685e4, 0x6c20c321, 0x29f12f73, 0x12e54190, + 0x04de2470, 0x6dbb24bb, 0x7f0fd71c, 0xd5e2c954, + 0x7d93c73a, 0xd2a2c48d, 0x61e2db8d, 0x1a192d47, + 0xc2d8d438, 0x5e779066, 0xc4bcc619, 0x06f872ef, + 0xf3401439, 0x573ebd1b, 0x61896e22, 0xde431aef, + 0xbad386d8, 0xf54ca23b, 0x57d8016f, 0xd98e33ac, + 0xc5f29f61, 0x85217cb1, 0x250a23ef, 0x16c2d7ce, + 0x8b8b0207, 0xaeaf1661, 0x8c645ab3, 0x10692f9a, + 0x84845cb2, 0x3809ed87, 0x958b72cf, 0xfdc465f9, + 0x167924f4, 0x79b72fd3, 0xd53e01b8, 0x878c0bc7, + 0x444d821d, 0xb2329171, 0x68dae31b, 0x6dd25eb0, + 0x876262cc, 0x600fcaf3, 0xa26397e5, 0xab3b5cd5, + 0x11f6df26, 0x3b503f54, 0xfd28517b, 0xac2c6723, + 0xf189feec, 0x6c0eabe7, 0xc3b57dd3, 0x9383ffbc, + 0xaff39d18, 0x4dae936e, 0x8806e540, 0xd956dfe9, + 0x7726c523, 0xe20d141f, 0x75249f0c, 0x641c7ecf, + 0x4d75cad2, 0x5e2097c6, 0xffdba551, 0xf97adab1, + 0x8d86a099, 0x4ce7dafa, 0xc4bf244c, 0xbd5ab78b, + 0x9060c834, 0x4f0533da, 0xeee0c724, 0x39963d31, + 0xcde4a77c, 0xf2222170, 0x00675c98, 0x72b6807a, + 0xfceec299, 0xb4bfd75f, 0x82385beb, 0x8a4fa5e6, + 0x1f4d790b, 0x8cb998f6, 0x5e41077c, 0xbdb77edc, + 0x5b885781, 0xdcd539a0, 0x50f70de2, 0xf72c206e, + 0xd47a8c39, 0xc8c84742, 0x4f5e1cde, 0x8ec26342, + 0x45add698, 0xc0bd2b6d, 0x10096f65, 0xc7e30310, + 0x1c951782, 0x37b5edea, 0xe10aea7f, 0xf40d763c, + 0x01a93a40, 0x197d0a4b, 0x3d41eed5, 0xe9beb9d6, + 0x1d9247a4, 0xeafe224c, 0x2f2578d5, 0x45eb10a4, + 0xb6b22e2b, 0xef55f252, 0xb4e224e4, 0x067dcb26, + 0xb6d0b2a3, 0xfd8a0221, 0x049bbf33, 0x70752994, + 0xf75fd79b, 0x34fcb9d9, 0x90ca2832, 0xf1c767ca, + 0x387d06cd, 0x9d5bfdfc, 0x45fb1391, 0xffbf1a8f, + 0xa7713b73, 0x04b45260, 0x41f7aadf, 0x4e9ab87d, + 0x26cfd8fc, 0x4ae2842a, 0x00b21491, 0x8e41fff9, + 0x931d987b, 0x1780ad94, 0x74d9d450, 0x6b4e7b86, + 0xd290203b, 0x2677caa9, 0x962f8e81, 0x2ed26089, + 0x14e26f42, 0xeb70b144, 0xa095d8c1, 0x6b572c29, + 0x78fbacf2, 0x5cdc5cfb, 0xfae86706, 0xddda5706, + 0xaa767744, 0x7493a4a2, 0x0e9f6b3f, 0x9806a4df, + 0x10e4c5d5, 0x9b49682a, 0xcb1d045c, 0x0b93aa0f, + 0x9204696b, 0x82d18f87, 0x1551957c, 0x5410f2ed, + 0xb937ab2e, 0xaaf40b54, 0x2b9d4857, 0x50231070, + 0x49ee3994, 0xceaa9dbb, 0x9bd8c899, 0xe9605a77, + 0xfd88758b, 0x6464201d, 0xa0605f2c, 0xc54d1473, + 0x30f678bd, 0xe07ade92, 0x315e83b4, 0x9f0e9866, + 0x6861b81f, 0xe3dbc8c2, 0xd67d8c2d, 0x27ffa228, + 0x25727f2b, 0xc6637d9b, 0x455637b4, 0x5aabdb00, + 0xb74a792c, 0x5bc1a7a8, 0xcbb106d8, 0xd7088b31, + 0xefec63ed, 0x5fcb7619, 0x79b5006e, 0x46de8644, + 0xdc61db98, 0x7701dca1, 0x1a9622f6, 0x6d192615, + 0xc380d47a, 0x10685fa3, 0x1f7fc304, 0x06d3796a, + 0x345013f3, 0x4c2db462, 0xddab6807, 0xf2525b65, + 0x086d312b, 0x62df52a6, 0x0903ce35, 0xf526c030, + 0x58ad7ac0, 0xf188c61f, 0x09869aa0, 0x76ae266b, + 0xe352afc2, 0xa5f2f582, 0x5ec4d829, 0x78fbae90, + 0xfb64e6ea, 0x96f43d96, 0x735098d0, 0x45006937, + 0xb8c64d9d, 0xdc1eacc8, 0x48674e13, 0x809f1e57, + 0x3481a112, 0xe97aa223, 0xd9609801, 0x120265b2, + 0x12211b6f, 0x7a930f99, 0x10d1fa9b, 0x69413983, + 0x72c88496, 0xf6bd37de, 0x397c05bf, 0x69cf3d17, + 0x2472b3e5, 0x6534bde0, 0x175c0e03, 0xfd31a289, + 0xe4d5d467, 0x933c0637, 0x14547ff0, 0x63dddc17, + 0x734f0426, 0x1b7d4414, 0x1d61e181, 0xa9bb645b, + 0xe33daddd, 0x0f3fd487, 0xb36f4aef, 0x042e3609 +}; diff --git a/src/cpu/via/nano/update_ucode.h b/src/cpu/via/nano/update_ucode.h index 14063fa..6a22d18 100644 --- a/src/cpu/via/nano/update_ucode.h +++ b/src/cpu/via/nano/update_ucode.h @@ -40,7 +40,7 @@ typedef enum { } ucode_update_status; -typedef enum ucode_validity_enum { +typedef enum { NANO_UCODE_VALID = 0, /* We only care that valid == 0 */ NANO_UCODE_SIGNATURE_ERROR, NANO_UCODE_WRONG_SIZE, diff --git a/src/devices/dram/dram.h b/src/devices/dram/dram.h new file mode 100644 index 0000000..d79cc52 --- /dev/null +++ b/src/devices/dram/dram.h @@ -0,0 +1,154 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef DRAM_H +#define DRAM_H + +#include <stdint.h> + +/* DRAM type, byte 2 of spd */ +#define DRAM_TYPE_UNDEFINED 0x00 +#define DRAM_TYPE_FPM_DRAM 0x01 +#define DRAM_TYPE_EDO 0x02 +#define DRAM_TYPE_PIPELINED_NIBBLE 0x03 +#define DRAM_TYPE_SDRAM 0x04 +#define DRAM_TYPE_ROM 0x05 +#define DRAM_TYPE_DDR_SGRAM 0x06 +#define DRAM_TYPE_DDR 0x07 +#define DRAM_TYPE_DDR2 0x08 +#define DRAM_TYPE_DDR2_FBDIMM 0x09 +#define DRAM_TYPE_DDR2_FB_PROBE 0x0a +#define DRAM_TYPE_DDR3 0x0b + +/* Module type (byte 3, bits 3:0) of SPD */ +#define DIMM_TYPE_UNDEFINED 0 +#define DIMM_TYPE_RDIMM 1 +#define DIMM_TYPE_UDIMM 2 +#define DIMM_TYPE_SO_DIMM 3 +#define DIMM_TYPE_MICRO_DIMM 4 +#define DIMM_TYPE_MINI_RDIMM 5 +#define DIMM_TYPE_MINI_UDIMM 6 +#define DIMM_TYPE_MINI_CDIMM 7 +#define DIMM_TYPE_72B_SO_UDIMM 8 +#define DIMM_TYPE_72B_SO_RDIMM 9 +#define DIMM_TYPE_72B_SO_CDIMM 10 + +#if defined(CONFIG_DEBUG_RAM_SETUP) && (CONFIG_DEBUG_RAM_SETUP) +#define printram(x, ...) printk(BIOS_DEBUG, x, ##__VA_ARGS__) +#else +#define printram(x, ...) +#endif + +/* Different values for tCK, representing standard DDR3 frequencies + * As always, these values are in 1/256 ns units */ +#define TCK_1066MHZ 240 +#define TCK_800MHZ 320 +#define TCK_666MHZ 384 +#define TCK_533MHZ 480 +#define TCK_400MHZ 640 +#define TCK_333MHZ 768 +#define TCK_266MHZ 960 +#define TCK_200MHZ 1280 + +#define RAM_UNIT (1<<24) + +#include <stdint.h> + +/** + *\brief DIMM characteristics + * + * The characteristics of each DIMM, as presented by the SPD + */ +typedef struct dimm_attr_st { + u8 dram_type; + u16 cas_supported; + /* Number of ranks */ + u8 ranks; + /* Number or row address bits */ + u8 row_bits; + /* Number or column address bits */ + u8 col_bits; + /* Size of module in (1 << 24) bytes (16MB) */ + u16 size; + /* Latencies are in units of ns, scaled by x256 */ + u32 tCK; + u32 tAA; + u32 tWR; + u32 tRCD; + u32 tRRD; + u32 tRP; + u32 tRAS; + u32 tRC; + u32 tRFC; + u32 tWTR; + u32 tRTP; + u32 tFAW; + +} dimm_attr; + +typedef struct ramctr_timing_st { + u8 dram_type; + u16 cas_supported; + /* tLatencies are in units of ns, scaled by x256 */ + u32 tCK; + u32 tAA; + u32 tWR; + u32 tRCD; + u32 tRRD; + u32 tRP; + u32 tRAS; + u32 tRC; + u32 tRFC; + u32 tWTR; + u32 tRTP; + u32 tFAW; + /* Latencies in terms of clock cycles + * They are saved separately as they are needed for DRAM MRS commands*/ + u8 CAS; /* CAS read latency */ + u8 CWL; /* CAS write latency */ + u8 WR; /* write recovery time */ + +} ramctr_timing; + + +typedef u8 spd_raw_data[256]; + +/** + * \brief Decode the raw spd data + */ +void spd_decode_ddr3(dimm_attr *dimm, spd_raw_data spd_data); + +/** + * \brief Checks if the DIMM is Registered based on byte[3] of the spd + */ +int dimm_is_registered(u8 spd_byte3); + +/** + * \brief Print the info in dimm + */ +void dram_print_spd_ddr3(const dimm_attr *dimm); + +/** + * \brief Read double word from specified address + * + * Should be useful when doing an MRS to the DIMM + */ +u32 volatile_read(u32 addr); + +#endif /* DRAM_H */ diff --git a/src/devices/dram/dram_util.c b/src/devices/dram/dram_util.c new file mode 100644 index 0000000..75913e4 --- /dev/null +++ b/src/devices/dram/dram_util.c @@ -0,0 +1,297 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "dram.h" +#include <console/console.h> +#include <device/device.h> + +u32 volatile_read(volatile u32 addr) +{ + volatile u32 result; + result = *(volatile u32*)addr; + return result; +} + +int dimm_is_registered(u8 spd_byte3) +{ + spd_byte3 &= 0x0f; + if( (spd_byte3 == DIMM_TYPE_RDIMM) + | (spd_byte3 == DIMM_TYPE_MINI_RDIMM) + | (spd_byte3 == DIMM_TYPE_72B_SO_RDIMM) ) + return 1; + + return 0; +} + +void spd_decode_ddr3(dimm_attr *dimm, spd_raw_data spd) +{ + int nCRC, i; + u16 crc, spd_crc; + u8 * ptr = spd; + u8 ftb_divisor; + u8 ftb_dividend; + u8 capacity_shift, bus_width, sdram_width; + u32 mtb; /* medium time base */ + /* Make sure that the spd dump is indeed from a DDR3 module */ + if(spd[2] != DRAM_TYPE_DDR3) + { + printram("Not a DDR3 SPD!\n"); + dimm->dram_type = DRAM_TYPE_UNDEFINED; + return; + } + dimm->dram_type = DRAM_TYPE_DDR3; + + /* Find the number of bytes covered by CRC */ + if(spd[0] & 0x80) { + nCRC = 117; + } else { + nCRC =126; + } + + /* Compute the CRC */ + crc = 0; + while (--nCRC >= 0) { + crc = crc ^ (int)*ptr++ << 8; + for (i = 0; i < 8; ++i) + if (crc & 0x8000) { + crc = crc << 1 ^ 0x1021; + } else { + crc = crc << 1; + } + } + /* Compare with the CRC in the SPD */ + spd_crc = (spd[127] << 8) + spd[126]; + /* Verify the CRC is correct */ + if(crc != spd_crc) + printram("SPD CRC failed!!!"); + + + unsigned int reg, val, param; + printram(" Revision: %x \n", spd[1] ); + printram(" Type : %x \n", spd[2] ); + printram(" Key : %x \n", spd[3] ); + + reg = spd[4]; + /* Number of memory banks */ + val = (reg >> 4) & 0x07; + if (val > 0x03) printram(" Invalid number of memory banks\n"); + param = 1 << (val + 3); + printram(" Banks : %u \n", param ); + /* SDRAM capacity */ + capacity_shift = reg & 0x0f; + if (capacity_shift > 0x06) printram(" Invalid module capacity\n"); + if (capacity_shift < 0x02) { + printram(" Capacity: %u Mb\n", 256 << capacity_shift); + } else { + printram(" Capacity: %u Gb\n", 1 << (capacity_shift - 2)); + } + + reg = spd[5]; + /* Row address bits */ + val = (reg >> 4) & 0x07; + if(val > 0x04) printram(" Invalid row address bits\n"); + dimm->row_bits = val + 12; + /* Column address bits */ + val = reg & 0x07; + if(val > 0x03) printram(" Invalid column address bits\n"); + dimm->col_bits = val + 9; + + /* Module nominal voltage */ + reg = spd[6]; + print_debug(" Supported voltages: "); + if(reg & (1<<2) ) print_debug("1.2V "); + if(reg & (1<<1) ) print_debug("1.35V "); + if( !(reg & (1<<0)) ) print_debug("1.5V "); + print_debug("\n"); + + /* Module organization */ + reg = spd[7]; + /* Number of ranks*/ + val = (reg >> 3) & 0x07; + if(val > 3) printram(" Invalid number of ranks\n"); + dimm->ranks = val + 1; + /* SDRAM device width */ + val = (reg & 0x07); + if(val > 3) printram(" Invalid SDRAM width\n"); + sdram_width = (4 << val); + printram(" SDRAM width : %u \n", sdram_width); + + /* Memory bus width */ + reg = spd[8]; + /* Bus extension */ + val = (reg >> 3) & 0x03; + if(val > 1) printram(" Invalid bus extension\n"); + printram(" Bus extension : %u bits\n", val?8:0); + /* Bus width */ + val = reg & 0x07; + if(val > 3) printram(" Invalid bus width\n"); + bus_width = 8 << val; + printram(" Bus width : %u \n", bus_width); + + /* We have all the info we need to compute the dimm size */ + /* Capacity is 256Mbit multiplied by the power of 2 specified in + * capacity_shift + * The rest is the JEDEC formula */ + /* I am certain it will fit in 16 bits + * Remember, It's in units of 2^24 bytes*/ + dimm->size = ( (1 << (capacity_shift + (25-24)) ) * bus_width + * dimm->ranks ) / sdram_width; + + /* Fine Timebase (FTB) Dividend/Divisor */ + /* Dividend */ + ftb_dividend = (spd[9] >> 4) & 0x0f; + /* Divisor */ + ftb_divisor = spd[9] & 0x0f; + + /* Medium Timebase = + * Medium Timebase (MTB) Dividend / + * Medium Timebase (MTB) Divisor */ + mtb = (((u32)spd[10]) << 8) / spd [11]; + + /* SDRAM Minimum Cycle Time (tCKmin) */ + dimm->tCK = spd[12] * mtb; + + /* CAS Latencies Supported */ + dimm->cas_supported = (spd[15] << 8) + spd[14]; + + /* Minimum CAS Latency Time (tAAmin) */ + dimm->tAA = spd[16] * mtb; + + /* Minimum Write Recovery Time (tWRmin) */ + dimm->tWR = spd[17] * mtb; + + /* Minimum RAS# to CAS# Delay Time (tRCDmin) */ + dimm->tRCD = spd[18] * mtb; + + /* Minimum Row Active to Row Active Delay Time (tRRDmin) */ + dimm->tRRD = spd[19] * mtb; + + /* Minimum Row Precharge Delay Time (tRPmin)*/ + dimm->tRP = spd[20] * mtb; + + /* Minimum Active to Precharge Delay Time (tRASmin) */ + dimm->tRAS = (((spd[21] & 0x0f) << 8) + spd[22]) * mtb; + + /* Minimum Active to Active/Refresh Delay Time (tRCmin) */ + dimm->tRC = (((spd[21] & 0xf0) << 4) + spd[23]) * mtb; + + /* Minimum Refresh Recovery Delay Time (tRFCmin) */ + dimm->tRFC = ((spd[25] << 8) + spd[24]) * mtb; + + /* Minimum Internal Write to Read Command Delay Time (tWTRmin) */ + dimm->tWTR = spd[26] * mtb; + + /* Minimum Internal Read to Precharge Command Delay Time (tRTPmin) */ + dimm->tRTP = spd[27] * mtb; + + /* Minimum Four Activate Window Delay Time (tFAWmin) */ + dimm->tFAW = (((spd[28] & 0x0f) << 8) + spd[29]) * mtb; + + /* SDRAM Optional Features */ + reg = spd[30]; + print_debug(" Optional features :"); + if(reg & 0x80) print_debug(" DLL-Off_mode"); + if(reg & 0x02) print_debug(" RZQ/7"); + if(reg & 0x01) print_debug(" RZQ/6"); + print_debug("\n"); + + /* SDRAM Thermal and Refresh Options */ + reg = spd[31]; + print_debug(" Thermal features :"); + if(reg & 0x80) print_debug(" PASR"); + if(reg & 0x08) print_debug(" ODTS"); + if(reg & 0x04) print_debug(" ASR"); + if(reg & 0x02) print_debug(" ext_temp_refresh"); + if(reg & 0x01) print_debug(" ext_temp_range"); + print_debug("\n"); + + /* Module Thermal Sensor */ + reg = spd[32]; + print_debug(" Thermal sensor : "); + if(reg & 0x80) print_debug("yes"); + else print_debug("no"); + print_debug("\n"); + + /* SDRAM Device Type */ + reg = spd[33]; + print_debug(" Standard SDRAM : "); + if(reg & 0x80) print_debug("no"); + else print_debug("yes"); + print_debug("\n"); + + /* Fine Offset for SDRAM Minimum Cycle Time (tCKmin) */ + //printram(" tCKmin FTB : %i \n", spd[34]); + /* Fine Offset for Minimum CAS Latency Time (tAAmin) */ + //printram(" tAAmin FTB : %i \n", spd[35]); + /* Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) */ + //printram(" tRCDmin FTB : %i \n", spd[36]); + /* Fine Offset for Minimum Row Precharge Delay Time (tRPmin) */ + //printram(" tRPmin FTB : %i \n", spd[37]); + /* Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin) */ + //printram(" tRCmin FTB : %i \n", spd[38]); + + if(spd[60] & 0x01) + printram(" DIMM Address bits mirrorred!!!\n"); + +} + +static void print_ns(const char * msg, u32 val) +{ + u32 mant, fp; + mant = val/256; + fp = (val % 256) * 1000/256; + + printram("%s%3u.%.3u ns\n", msg, mant, fp); +} + +void dram_print_spd_ddr3(const dimm_attr *dimm) +{ + u16 val16; + int i; + + printram(" Row addr bits : %u \n", dimm->row_bits); + printram(" Column addr bits : %u \n", dimm->col_bits); + printram(" Number of ranks : %u \n", dimm->ranks); + printram(" DIMM Capacity : %u MB\n", dimm->size << 4); + + /* CAS Latencies Supported */ + val16 = dimm->cas_supported; + print_debug(" CAS latencies :"); + i = 0; + do{ + if(val16 & 1) printram(" %u", i + 4); + i++; + val16 >>= 1; + } while(val16); + print_debug("\n"); + + print_ns(" tCKmin : ", dimm->tCK); + print_ns(" tAAmin : ", dimm->tAA); + print_ns(" tWRmin : ", dimm->tWR); + print_ns(" tRCDmin : ", dimm->tRCD); + print_ns(" tRRDmin : ", dimm->tRRD); + print_ns(" tRPmin : ", dimm->tRP); + print_ns(" tRASmin : ", dimm->tRAS); + print_ns(" tRCmin : ", dimm->tRC); + print_ns(" tRFCmin : ", dimm->tRFC); + print_ns(" tWTRmin : ", dimm->tWTR); + print_ns(" tRTPmin : ", dimm->tRTP); + print_ns(" tFAWmin : ", dimm->tFAW); + +} diff --git a/src/devices/smbus/early_smbus.c b/src/devices/smbus/early_smbus.c new file mode 100644 index 0000000..4583aca --- /dev/null +++ b/src/devices/smbus/early_smbus.c @@ -0,0 +1,141 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ +/** + * @file post_codes.h + * + * This file defines the implementations for the functions defined in smbus.h + * These are a generic SMBUS implementation, which should work with a majority + * of chipsets. + * They are marked weak so that they can be overridden by the chipset code if + * necessary. + */ + +#include "smbus.h" + +/** + * \brief Brief delay for SMBUS transactions + */ +__attribute__((weak)) +void __smbus_delay(void) +{ + inb(0x80); +} + +/** + * \brief Clear the SMBUS host status register + */ +__attribute__((weak)) +void __smbus_reset(u16 __smbus_io_base) +{ + outb(0xdf, SMBHSTSTAT); +} + +/** + * \brief Print an error, should it occur. If no error, just exit. + * + * @param host_status The data returned on the host status register after + * a transaction is processed. + * @param loops The number of times a transaction was attempted. + * @return 0 if no error occurred + * 1 if an error was detected + */ +__attribute__((weak)) +int __smbus_print_error(u8 host_status, int loops, u16 __smbus_io_base) +{ + /* Check if there actually was an error. */ + if ((host_status == 0x00 || host_status == 0x40 || + host_status == 0x42) && (loops < SMBUS_TIMEOUT)) + return 0; + + if (loops >= SMBUS_TIMEOUT) + printsmbus("SMBus timeout\n"); + if (host_status & (1 << 4)) + printsmbus("Interrupt/SMI# was Failed Bus Transaction\n"); + if (host_status & (1 << 3)) + printsmbus("Bus error\n"); + if (host_status & (1 << 2)) + printsmbus("Device error\n"); + if (host_status & (1 << 1)) + printsmbus("Interrupt/SMI# completed successfully\n"); + if (host_status & (1 << 0)) + printsmbus("Host busy\n"); + return 1; +} + +/** + * \brief Checks if the SMBUS is currently busy with a transaction + */ +__attribute__((weak)) +int __smbus_is_busy(u16 __smbus_io_base) +{ + /* Check if bit 0 of the status register is 1 (busy) or 0 (ready) */ + return ( (inb(SMBHSTSTAT) & (1 << 0)) == 1); +} + +/** + * \brief Wait for the SMBUS to become ready to process a new transaction. + */ +__attribute__((weak)) +int __smbus_wait_until_ready(u16 __smbus_io_base) +{ + int loops; + + printsmbus("Waiting until SMBus ready\n"); + + /* Loop up to SMBUS_TIMEOUT times, waiting for bit 0 of the + * SMBus Host Status register to go to 0, indicating the operation + * was completed successfully. I don't remember why I did it this way, + * but I think it was because ROMCC was running low on registers */ + loops = 0; + while (__smbus_is_busy(__smbus_io_base) && loops < SMBUS_TIMEOUT) + ++loops; + + return __smbus_print_error(inb(SMBHSTSTAT), loops, __smbus_io_base); +} + +/** + * \brief Read a byte from the SMBUS. + * + * @param dimm The address location of the DIMM on the SMBus. + * @param offset The offset the data is located at. + */ +__attribute__((weak)) +u8 __smbus_read_byte(u8 dimm, u8 offset, u16 __smbus_io_base) +{ + u8 val; + + /* Initialize SMBUS sequence */ + __smbus_reset(__smbus_io_base); + /* Clear host data port. */ + outb(0x00, SMBHSTDAT0); + + __smbus_wait_until_ready(__smbus_io_base); + + /* Actual addr to reg format. */ + dimm = (dimm << 1); + dimm |= 1; /* read command */ + outb(dimm, SMBXMITADD); + outb(offset, SMBHSTCMD); + /* Start transaction, byte data read. */ + outb(0x48, SMBHSTCTL); + __smbus_wait_until_ready(__smbus_io_base); + + val = inb(SMBHSTDAT0); + return val; +} \ No newline at end of file diff --git a/src/devices/smbus/smbus.h b/src/devices/smbus/smbus.h new file mode 100644 index 0000000..820a0dd --- /dev/null +++ b/src/devices/smbus/smbus.h @@ -0,0 +1,99 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/** + * @file post_codes.h + * + * This file defines the prototypes for several common SMBUS functions + * These functions are prefixed with __smbus_ so that they do not conflict with + * the dozens of similar (duplicated) implementations in many southbridges. + * + * As a last parameter, the SMBUS functions take a u16 value __smbus_io_base, + * which represents the base IO port for smbus transactions + */ + +#include <arch/io.h> + +/** + * \brief SMBUS IO ports in relation to the base IO port + */ +#define SMBHSTSTAT __smbus_io_base + 0x0 +#define SMBSLVSTAT __smbus_io_base + 0x1 +#define SMBHSTCTL __smbus_io_base + 0x2 +#define SMBHSTCMD __smbus_io_base + 0x3 +#define SMBXMITADD __smbus_io_base + 0x4 +#define SMBHSTDAT0 __smbus_io_base + 0x5 +#define SMBHSTDAT1 __smbus_io_base + 0x6 +#define SMBBLKDAT __smbus_io_base + 0x7 +#define SMBSLVCTL __smbus_io_base + 0x8 +#define SMBTRNSADD __smbus_io_base + 0x9 +#define SMBSLVDATA __smbus_io_base + 0xa + +#define SMBUS_TIMEOUT (100*1000*10) + +/** + * \brief printk macro for SMBUS debugging + */ +#if defined(CONFIG_DEBUG_SMBUS_SETUP) && (CONFIG_DEBUG_SMBUS_SETUP) +#define printsmbus(x, ...) printk(BIOS_DEBUG, x, ##__VA_ARGS__) +#else +#define printsmbus(x, ...) +#endif + +void __smbus_reset(u16 __smbus_io_base); +int __smbus_print_error(u8 host_status, int loops, u16 __smbus_io_base); +int __smbus_is_busy(u16 __smbus_io_base); +int __smbus_wait_until_ready(u16 __smbus_io_base); +u8 __smbus_read_byte(u8 dimm, u8 offset, u16 __smbus_io_base); + +void __smbus_delay(void); + +#if defined(SMBUS_IO_BASE) && (SMBUS_IO_BASE != 0) + +__attribute__((always_inline, unused)) +static void smbus_reset(void) +{ + __smbus_reset(SMBUS_IO_BASE); +} + +__attribute__((always_inline, unused)) +static int smbus_is_busy(void) +{ + return __smbus_is_busy(SMBUS_IO_BASE); +} + +__attribute__((always_inline, unused)) +static int smbus_wait_until_ready(void) +{ + return __smbus_wait_until_ready(SMBUS_IO_BASE); +} + +__attribute__((always_inline, unused)) +static int smbus_print_error(u8 host_status, int loops) +{ + return __smbus_print_error(host_status, loops, SMBUS_IO_BASE); +} + +__attribute__((always_inline, unused)) +static u8 smbus_read_byte(u8 dimm, u8 offset) +{ + return __smbus_read_byte(dimm, offset, SMBUS_IO_BASE); +} + +#endif \ No newline at end of file diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 7aac1f7..4f2556c 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -1337,6 +1337,28 @@ #define PCI_DEVICE_ID_VIA_VX855_VGA 0x5122 #define PCI_DEVICE_ID_VIA_VX855_VLINK 0x7409 #define PCI_DEVICE_ID_VIA_VX855_MEMCTRL 0x3409 +/* VIA VX900 PCI IDs */ +#define PCI_DEVICE_ID_VIA_VX900_HOST_BR 0x0410 +#define PCI_DEVICE_ID_VIA_VX900_ERR 0x1410 +#define PCI_DEVICE_ID_VIA_VX900_CPU_CTR 0x2410 +#define PCI_DEVICE_ID_VIA_VX900_MEMCTRL 0x3410 +#define PCI_DEVICE_ID_VIA_VX900_PM 0x4410 +#define PCI_DEVICE_ID_VIA_VX900_TRAF 0x5410 +#define PCI_DEVICE_ID_VIA_VX900_SCRATCH 0x6410 +#define PCI_DEVICE_ID_VIA_VX900_NBRIDGE 0x7410 +#define PCI_DEVICE_ID_VIA_VX900_LPC 0x8410 +#define PCI_DEVICE_ID_VIA_VX900_PEX1 0xa410 +#define PCI_DEVICE_ID_VIA_VX900_PEX2 0xb410 +#define PCI_DEVICE_ID_VIA_VX900_PEX3 0xc410 +#define PCI_DEVICE_ID_VIA_VX900_PEX4 0xd410 +#define PCI_DEVICE_ID_VIA_VX900_PEX_CTR 0xe410 +#define PCI_DEVICE_ID_VIA_VX900_SBRIDGE 0xa535 +#define PCI_DEVICE_ID_VIA_VX900_PCI_BR 0xb535 +#define PCI_DEVICE_ID_VIA_VX900_VGA 0x7122 +#define PCI_DEVICE_ID_VIA_VX900_VID_DEC 0x9170 +#define PCI_DEVICE_ID_VIA_VX900_HDAC 0x3288 +#define PCI_DEVICE_ID_VIA_VX900_ETH 0x3119 +/* VIA CN700 */ #define PCI_DEVICE_ID_VIA_CN700_AGP 0x0314 #define PCI_DEVICE_ID_VIA_CN700_ERR 0x1314 #define PCI_DEVICE_ID_VIA_CN700_HOST 0x2314 diff --git a/src/include/lib.h b/src/include/lib.h index b2f38a8..b51911a 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -38,6 +38,7 @@ void move_gdt(void); /* Defined in src/lib/ramtest.c */ void ram_check(unsigned long start, unsigned long stop); int ram_check_nodie(unsigned long start, unsigned long stop); +int ram_check_noprint_nodie(unsigned long start, unsigned long stop); void quick_ram_check(void); /* Defined in src/lib/stack.c */ diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c index 3457210..192d573 100644 --- a/src/lib/ramtest.c +++ b/src/lib/ramtest.c @@ -223,6 +223,41 @@ int ram_check_nodie(unsigned long start, unsigned long stop) return ret; } +int ram_check_noprint_nodie(unsigned long start, unsigned long stop) +{ + unsigned long addr, value, value2; + unsigned short int idx; + unsigned char failed, failures; + uint8_t verbose = 0; + + for (idx=0; idx<0x400; idx+=4) { + test_pattern(idx, &addr, &value); + write_phys(start + addr, value); + } + + /* Make sure we don't read before we wrote */ + phys_memory_barrier(); + + failures = 0; + for (idx=0; idx<0x400; idx+=4) { + test_pattern(idx, &addr, &value); + value2 = read_phys(start + addr); + + failed = (value2 != value); + failures |= failed; + if (failed && !verbose) { + } + if (verbose) { + } + } + if (failures) { + return 1; + } + else { + } + return 0; +} + void quick_ram_check(void) { int fail = 0; diff --git a/src/mainboard/via/Kconfig b/src/mainboard/via/Kconfig index 6980548..48f4055 100644 --- a/src/mainboard/via/Kconfig +++ b/src/mainboard/via/Kconfig @@ -9,6 +9,8 @@ config BOARD_VIA_EPIA_CN bool "EPIA-CN" config BOARD_VIA_EPIA_M700 bool "EPIA-M700" +config BOARD_VIA_EPIA_M850 + bool "EPIA-M850" config BOARD_VIA_EPIA_M bool "EPIA-M" config BOARD_VIA_EPIA_N @@ -23,6 +25,7 @@ endchoice source "src/mainboard/via/epia/Kconfig" source "src/mainboard/via/epia-cn/Kconfig" source "src/mainboard/via/epia-m700/Kconfig" +source "src/mainboard/via/epia-m850/Kconfig" source "src/mainboard/via/epia-m/Kconfig" source "src/mainboard/via/epia-n/Kconfig" source "src/mainboard/via/pc2500e/Kconfig" diff --git a/src/mainboard/via/epia-m850/Kconfig b/src/mainboard/via/epia-m850/Kconfig new file mode 100644 index 0000000..44c1cf1 --- /dev/null +++ b/src/mainboard/via/epia-m850/Kconfig @@ -0,0 +1,46 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011-2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see <http://www.gnu.org/licenses/>. +## + +if BOARD_VIA_EPIA_M850 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_VIA_NANO + select NORTHBRIDGE_VIA_VX900 + select SUPERIO_FINTEK_F81865F + #select BOARD_HAS_FADT + #select HAVE_PIRQ_TABLE + #select HAVE_ACPI_TABLES + #select HAVE_OPTION_TABLE + select BOARD_ROMSIZE_KB_512 + +config MAINBOARD_DIR + string + default via/epia-m850 + +config MAINBOARD_PART_NUMBER + string + default "EPIA-M850" + +config IRQ_SLOT_COUNT + int + default 13 + +endif # BOARD_VIA_EPIA_M850 diff --git a/src/mainboard/via/epia-m850/Makefile.inc b/src/mainboard/via/epia-m850/Makefile.inc new file mode 100644 index 0000000..9c6d31f --- /dev/null +++ b/src/mainboard/via/epia-m850/Makefile.inc @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see <http://www.gnu.org/licenses/>. +## + +#romstage-y += ./../../../superio/fintek/f81865f/f81865f_early_serial.c + diff --git a/src/mainboard/via/epia-m850/devicetree.cb b/src/mainboard/via/epia-m850/devicetree.cb new file mode 100644 index 0000000..0b2f28e --- /dev/null +++ b/src/mainboard/via/epia-m850/devicetree.cb @@ -0,0 +1,89 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see <http://www.gnu.org/licenses/>. +## + +chip northbridge/via/vx900 # Northbridge + device lapic_cluster 0 on # APIC cluster + chip cpu/via/nano # VIA NANO + device lapic 0 on end # APIC + end + end + device pci_domain 0 on + device pci 0.0 off end # [0410] Host controller + device pci 0.1 off end # [1410] Error Reporting + device pci 0.2 off end # [2410] CPU Bus Control + device pci 0.3 off end # [3410] DRAM Bus Control + device pci 0.4 off end # [4410] Power Management + device pci 0.5 on end # [5410] APIC+Traffic Control + device pci 0.6 off end # [6410] Scratch Registers + device pci 0.7 on end # [7410] V4 Link Control + device pci 1.0 on end # [7122] VGA Chrome9 HD + device pci 1.1 off end # [9170] Audio Device + device pci 3.0 off end # [a410] PEX1 + device pci 3.1 off end # [b410] PEX2 + device pci 3.2 off end # [c410] PEX3 + device pci 3.3 off end # [d410] PEX4 + device pci 3.4 off end # [e410] PCIE bridge + device pci c.0 off end # [95d0] SDIO Host Controller + device pci d.0 off end # [9530] Memory Card controller + device pci f.0 off end # [9001] SATA Controller + device pci 10.0 off end # [3038] USB 1.1 + device pci 10.1 off end # [3038] USB 1.1 + device pci 10.2 off end # [3038] USB 1.1 + device pci 10.3 off end # [3038] USB 1.1 + device pci 10.4 off end # [3104] USB 2.0 + device pci 11.0 on # [8410] LPC Bus Control + #chip drivers/generic/generic # DIMM 0 channel 1 + # device i2c 50 on end + #end + #chip drivers/generic/generic # DIMM 1 channel 1 + # device i2c 51 on end + #end + chip superio/fintek/f81865f # Super duper IO + device pnp 4e.0 off end # Floppy + device pnp 4e.3 off end # Parallel Port + device pnp 4e.4 off end # Hardware Monitor + device pnp 4e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 4e.6 off end # GPIO + device pnp 4e.a off end # PME + device pnp 4e.10 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.11 off # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 4e.12 off # COM3 + io 0x60 = 0x3e8 + irq 0x70 = 10 + end + device pnp 4e.13 off # COM4 + io 0x60 = 0x2e8 + irq 0x70 = 11 + end + end # superio/fintek/f81865f + end # LPC + device pci 11.7 off end # [a353] North-South control + device pci 14.0 off end # [3288] Azalia HDAC + end +end diff --git a/src/mainboard/via/epia-m850/mainboard.c b/src/mainboard/via/epia-m850/mainboard.c new file mode 100644 index 0000000..57b12e1 --- /dev/null +++ b/src/mainboard/via/epia-m850/mainboard.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <device/device.h> + +struct chip_operations mainboard_ops = { + CHIP_NAME("VIA EPIA-M850 Mainboard") +}; diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c new file mode 100644 index 0000000..dbc2121 --- /dev/null +++ b/src/mainboard/via/epia-m850/romstage.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/* + * Inspired from the EPIA-M700 + */ + +#include <stdint.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <arch/hlt.h> +#include <console/console.h> +#include <lib.h> +#include "cpu/x86/bist.h" +#include <string.h> + +#include "northbridge/via/vx900/early_vx900.h" +#include "northbridge/via/vx900/raminit.h" +#include "superio/fintek/f81865f/f81865f_early_serial.c" + +#define SERIAL_DEV PNP_DEV(0x4e, 0x10) + +/* cache_as_ram.inc jumps to here. */ +void main(unsigned long bist) +{ + /* First thing we need to do on the VX900, before anything else */ + vx900_enable_pci_config_space(); + + f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + print_debug("Console initialized. \n"); + + /* Halt if there was a built-in self test failure. */ + report_bist_failure(bist); + + /* Oh, almighty, give us the SMBUS */ + enable_smbus(); + + /* If this works, then SMBUS is up and running */ + /* dump_spd_data(); */ + + /* Now we can worry about raminit. + * This board only has DDR3, so no need to worry about which DRAM type + * to use */ + dimm_layout dimms = {{0x50, 0x51, SPD_END_LIST}}; + vx900_init_dram_ddr3(&dimms); + + //ram_check(0, 0x80); + //ram_check(512<<10, 0x80); + ram_check(1024<<10, 0x80); + ram_check((1<<20), 0x80); + ram_check((1<<24), 0x80); + ram_check((512 + 256 -1)<<20, 0x80); + //ram_check(988*1024*1024, 0x80); + + print_debug("We passed RAM verify\n"); + + return; + +} diff --git a/src/northbridge/via/Kconfig b/src/northbridge/via/Kconfig index 2c38acf..8a747b9 100644 --- a/src/northbridge/via/Kconfig +++ b/src/northbridge/via/Kconfig @@ -4,3 +4,4 @@ source src/northbridge/via/cn400/Kconfig source src/northbridge/via/vt8601/Kconfig source src/northbridge/via/vt8623/Kconfig source src/northbridge/via/vx800/Kconfig +source src/northbridge/via/vx900/Kconfig diff --git a/src/northbridge/via/Makefile.inc b/src/northbridge/via/Makefile.inc index 75cb15b..2e74b61 100644 --- a/src/northbridge/via/Makefile.inc +++ b/src/northbridge/via/Makefile.inc @@ -4,4 +4,5 @@ subdirs-$(CONFIG_NORTHBRIDGE_VIA_CN700) += cn700 subdirs-$(CONFIG_NORTHBRIDGE_VIA_CX700) += cx700 subdirs-$(CONFIG_NORTHBRIDGE_VIA_CN400) += cn400 subdirs-$(CONFIG_NORTHBRIDGE_VIA_VX800) += vx800 +subdirs-$(CONFIG_NORTHBRIDGE_VIA_VX900) += vx900 diff --git a/src/northbridge/via/vx800/lpc.c b/src/northbridge/via/vx800/lpc.c index b9941d1..144ede0 100644 --- a/src/northbridge/via/vx800/lpc.c +++ b/src/northbridge/via/vx800/lpc.c @@ -375,3 +375,9 @@ static const struct pci_driver lpc_driver __pci_driver = { .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_VX855_LPC, }; + +static const struct pci_driver lpc_driver_900 __pci_driver = { + .ops = &vx800_lpc_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_VX900_LPC, +}; \ No newline at end of file diff --git a/src/northbridge/via/vx800/vga.c b/src/northbridge/via/vx800/vga.c index e438012..0bedde0 100644 --- a/src/northbridge/via/vx800/vga.c +++ b/src/northbridge/via/vx800/vga.c @@ -126,24 +126,6 @@ static int via_vx800_int15_handler(struct eregs *regs) return res; } -#ifdef UNUSED_CODE -static void write_protect_vgabios(void) -{ - device_t dev; - - printk(BIOS_INFO, "write_protect_vgabios\n"); - /* there are two possible devices. Just do both. */ - dev = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VX855_MEMCTRL, 0); - if (dev) - pci_write_config8(dev, 0x80, 0xff); - /*vx855 no th 0x61 reg */ - /*dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_VLINK, 0); - //if(dev) - // pci_write_config8(dev, 0x61, 0xff); */ -} -#endif - static void vga_enable_console(void) { /* Call VGA BIOS int10 function 0x4f14 to enable main console @@ -152,7 +134,7 @@ static void vga_enable_console(void) */ /* int#, EAX, EBX, ECX, EDX, ESI, EDI */ - realmode_interrupt(0x10, 0x4f14, 0x8003, 0x0001, 0x0000, 0x0000, 0x0000); + //realmode_interrupt(0x10, 0x4f14, 0x8003, 0x0001, 0x0000, 0x0000, 0x0000); } extern u8 acpi_sleep_type; @@ -173,7 +155,7 @@ static void vga_init(device_t dev) //pci_write_config32(dev,0x14, 0xdd000000); pci_write_config32(dev, 0x10, VIACONFIG_VGA_PCI_10); pci_write_config32(dev, 0x14, VIACONFIG_VGA_PCI_14); - pci_write_config8(dev, 0x3c, 0x0a); //same with vx855_lpc.c + pci_write_config8(dev, PCI_INTERRUPT_LINE, 0x0a);//same with vx855_lpc.c //*/ printk(BIOS_DEBUG, "Initializing VGA...\n"); @@ -182,27 +164,9 @@ static void vga_init(device_t dev) printk(BIOS_DEBUG, "Enable VGA console\n"); vga_enable_console(); - - if ((acpi_sleep_type == 3)/* || (PAYLOAD_IS_SEABIOS == 0)*/) { - /* It's not clear if these need to be programmed before or after - * the VGA bios runs. Try both, clean up later */ - /* Set memory rate to 200MHz */ - outb(0x3d, CRTM_INDEX); - reg8 = inb(CRTM_DATA); - reg8 &= 0x0f; - reg8 |= (0x3 << 4); - outb(0x3d, CRTM_INDEX); - outb(reg8, CRTM_DATA); - -#if 0 - /* Set framebuffer size to CONFIG_VIDEO_MB mb */ - reg8 = (CONFIG_VIDEO_MB/4); - outb(0x39, SR_INDEX); - outb(reg8, SR_DATA); -#endif - } } + static struct device_operations vga_operations = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, @@ -216,3 +180,9 @@ static const struct pci_driver vga_driver __pci_driver = { .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_VX855_VGA, }; + +static const struct pci_driver vga_driver_900 __pci_driver = { + .ops = &vga_operations, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_VX900_VGA, +}; diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig new file mode 100644 index 0000000..7d3e0dc --- /dev/null +++ b/src/northbridge/via/vx900/Kconfig @@ -0,0 +1,38 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see <http://www.gnu.org/licenses/>. +## + +config NORTHBRIDGE_VIA_VX900 + bool + select IOAPIC + select HAVE_DEBUG_RAM_SETUP + select HAVE_DEBUG_SMBUS + # Don't do MMCONF until we have at least some usable hardware working + # Yes, MMCONF works, and it works nicely, but it also adds some + # complications that are better dealt once the code is running well + #select MMCONF_SUPPORT + #select MMCONF_SUPPORT_DEFAULT + select GFXUMA + +config MMCONF_BASE_ADDRESS + hex + default 0xc0000000 + +config VGA_BIOS_ID + string + default "1106,7122" \ No newline at end of file diff --git a/src/northbridge/via/vx900/Makefile.inc b/src/northbridge/via/vx900/Makefile.inc new file mode 100644 index 0000000..efe6092 --- /dev/null +++ b/src/northbridge/via/vx900/Makefile.inc @@ -0,0 +1,44 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011-2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see <http://www.gnu.org/licenses/>. +## + +romstage-y += early_smbus.c +romstage-y += early_vx900.c +romstage-y += early_uma_ram.c +romstage-y += raminit_ddr3.c +romstage-y += ./../../../devices/dram/dram_util.c +romstage-y += ./../../../devices/smbus/early_smbus.c +#romstage-y += $(src)/drivers/pc80/udelay_io.c +romstage-y += ./../../../drivers/pc80/udelay_io.c + +driver-y += northbridge.c +driver-y += chrome9hd.c +driver-y += traf_ctrl.c + +# The buildsystem only includes this file if CONFIG_VGA is selected. +# We need to do some VGA I/O before the VGA can be initialized. We can make good +# use of some of the functions there, so include them unconditionally +ramstage-y += ./../../../drivers/pc80/vga/vga_io.c + +# It seems that using the LPC driver from VX800 works. The differences in +# register layout are minimal. +# TODO: Is this really a good idea? +driver-y += ./../vx800/lpc.c + +chipset_bootblock_inc += $(src)/northbridge/via/vx900/romstrap.inc +chipset_bootblock_lds += $(src)/northbridge/via/vx900/romstrap.lds diff --git a/src/northbridge/via/vx900/chip.h b/src/northbridge/via/vx900/chip.h new file mode 100644 index 0000000..15c9744 --- /dev/null +++ b/src/northbridge/via/vx900/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +struct northbridge_via_vx900_config { +}; + +extern struct chip_operations northbridge_via_vx900_ops; diff --git a/src/northbridge/via/vx900/chrome9hd.c b/src/northbridge/via/vx900/chrome9hd.c new file mode 100644 index 0000000..beafb51 --- /dev/null +++ b/src/northbridge/via/vx900/chrome9hd.c @@ -0,0 +1,364 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <pc80/vga_io.h> + +#include "vx900.h" + +#define CHROME_9_HD_MIN_FB_SIZE 8 +#define CHROME_9_HD_MAX_FB_SIZE 512 + +/* Helper to determine the framebuffer size */ +u32 chrome9hd_fb_size(void) +{ + static u32 fb_size = 0; + /* We do some PCI and CMOS IO to find our value, so if we've already + * found it, save some time */ + if(fb_size != 0) + return fb_size; + /* FIXME: read fb_size from CMOS, but until that is implemented, start + * from 512MB */ + u32 sizem = 512; + + /* The minimum framebuffer size is 8MB. */ + sizem = max(sizem, CHROME_9_HD_MIN_FB_SIZE); + + const device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0); + /* We have two limitations on the maximum framebuffer size: + * 1) (Sanity) No more that 1/4 of system RAM + * 2) (Hardware limitation) No larger than DRAM in last rank + * Check both of these limitations and apply them to our framebuffer */ + u32 tomm = (pci_read_config16(mcu, 0x88) & 0x07ff) << (24-20); + u32 max_sizem = tomm >> 2; + if(sizem > max_sizem) { + printk(BIOS_ALERT, "The framebuffer size of of %dMB is larger" + " than 1/4 of available memory.\n" + " Limiting framebuffer to %dMB\n", sizem, max_sizem); + sizem = max_sizem; + } + + /* Now handle limitation #2 + * Look at the ending address of the memory ranks, from last to first, + * until we find one that is not zero. That is our last rank, and its + * size is the limit of our framebuffer. */ + int i; + for(i = VX900_MAX_MEM_RANKS - 1; i > -1; i--) { + u8 reg8 = pci_read_config8(mcu, 0x40 + 1); + if(reg8 == 0) + continue; + /* We've reached the last populated rank */ + u8 ranksize = reg8 - pci_read_config8(mcu, 0x48 + i); + max_sizem = ranksize >> 6; + }; + if(sizem > max_sizem) { + printk(BIOS_ALERT, "The framebuffer size of of %dMB is larger" + " than size of the last DRAM rank.\n" + " Limiting framebuffer to %dMB\n", sizem, max_sizem); + sizem = max_sizem; + } + + /* Now round the framebuffer size to the closest power of 2 */ + u8 fb_pow = 0; + while(sizem >> fb_pow) fb_pow ++; + fb_pow --; + sizem = (1 << fb_pow); + /* We store the framebuffer size in bytes, for simplicity */ + fb_size = sizem << 20; + return fb_size; +} + +#if 0 && CONFIG_OPTION_ROM_RUN_YABEL +#include <x86emu/x86emu.h> +static int vx900_int15_handler_yabel(void) +{ + int res=-1; + printk(BIOS_DEBUG, "%s %0x\n", __func__, M.x86.R_AX & 0xffff); + switch(M.x86.R_AX & 0xffff) { + case 0x5f19: + M.x86.R_AX=0x5f; + M.x86.R_CX=0x03; + res=0; + break; + case 0x5f18: + { + /* + * BL Bit[7:4] + * Memory Data Rate + * 0000: 66MHz + * 0001: 100MHz + * 0010: 133MHz + * 0011: 200MHz ( DDR200 ) + * 0100: 266MHz ( DDR266 ) + * 0101: 333MHz ( DDR333 ) + * 0110: 400MHz ( DDR400 ) + * 0111: 533MHz ( DDR I/II 533 + * 1000: 667MHz ( DDR I/II 667) + * Bit[3:0] + * N: Frame Buffer Size 2^N MB + */ + u8 i; + device_t dev; + dev = dev_find_slot(0, PCI_DEVFN(0, 3)); + i = pci_read_config8(dev, 0xa1); + i = (i & 0x70); + i = i >> 4; + if (i == 0) { + M.x86.R_AX = 0x00; //not support 5f18 + break; + } + i = i + 2; + M.x86.R_BX = (u32) i; + i = pci_read_config8(dev, 0x90); + i = (i & 0x07); + i = i + 3; + i = i << 4; + M.x86.R_BX = M.x86.R_BX + ((u32) i); + M.x86.R_AX = 0x5f; + res = 0; + break; + } + case 0x5f00: + M.x86.R_AX = 0x005f; + res = 0; + break; + case 0x5f01: + M.x86.R_AX = 0x5f; + M.x86.R_CX = (M.x86.R_CX & 0xffffff00 ) | 2; // panel type = 2 = 1024 * 768 + res = 0; + break; + case 0x5f02: + M.x86.R_AX=0x5f; + M.x86.R_BX= (M.x86.R_BX & 0xffff0000) | 2; + M.x86.R_CX= (M.x86.R_CX & 0xffff0000) | 0x401; // PAL + crt only + M.x86.R_DX= (M.x86.R_DX & 0xffff0000) | 0; // TV Layout - default + res=0; + break; + case 0x5f0f: + M.x86.R_AX = 0x005f; + res = 0; + break; + default: + printk(BIOS_DEBUG, "Unsupported INT15 call %04x!\n", + M.x86.R_AX & 0xffff); + M.x86.R_AX = 0; + break; + } + return res; +} + +static void vx900_vga_set_int15_handler(void) +{ + printk(BIOS_DEBUG, "Our int15 handler is at %p\n", + &vx900_int15_handler_yabel); + typedef int (* yabel_handleIntFunc)(void); + extern yabel_handleIntFunc yabel_intFuncArray[256]; + yabel_intFuncArray[0x15] = vx900_int15_handler_yabel; +} +#endif + +static void chrome9hd_set_sid_vid(u16 vendor, u16 device) +{ + vga_sr_write(0x36, vendor >> 8); /* SVID high byte */ + vga_sr_write(0x35, vendor & 0xff); /* SVID low byte */ + vga_sr_write(0x38, device >> 8); /* SID high byte */ + vga_sr_write(0x37, device & 0xff); /* SID low byte */ +} + +static void chrome9hd_biosguide_init_seq(device_t dev) +{ + device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0); + device_t host = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VX900_HOST_BR, 0); + print_debug("1\n"); + /* Step 1 - Enable VGA controller */ + /* FIXME: This is the VGA hole @ 640k-768k, and the vga port io + * We need the port IO, but can we disable the memory hole? */ + print_debug("1.a\n"); + pci_mod_config8(mcu, 0xa4, 0, 0x80); /* VGA memory hole */ + + print_debug("2\n"); + /* Step 2 - Forward MDA cycles to GFX */ + pci_mod_config8(host, 0x4e, 1<<1, 0); /* FIXME */ + + print_debug("3\n"); + /* Step 3 - Enable GFX I/O space */ + pci_mod_config8(dev, PCI_COMMAND, 0, PCI_COMMAND_IO); + + print_debug("4\n"); + /* Step 4 - Enable video subsystem */ + vga_enable_mask(1<<0, 1<<0); + + print_debug("5\n"); + /* Step 5 - Unlock accessing of IO space */ + vga_sr_write(0x10, 0x01); + + /* Step 8 - Enable memory base register on the GFX */ + if(uma_memory_base == 0) + die("uma_memory_base not set. Abandon ship!\n"); + printk(BIOS_DEBUG, "UMA base @0x%.10llx\n", uma_memory_base); + vga_sr_write(0x6d, (uma_memory_base >> 21) & 0xff); /* base 28:21 */ + vga_sr_write(0x6e, (uma_memory_base >> 29) & 0xff); /* base 36:29 */ + vga_sr_write(0x6f, 0x00); /* base what what in the butt ?? */ + + /* Step 9 - Set SID/VID */ + chrome9hd_set_sid_vid(0x1106, 0x7122); + + /* Prime PLL FIXME: bad comment */ + //vga_sr_mask(0x3c, 1<<2, 1<<2); + + //VGA IO Address Select. 3B5 or 3D5? + //vga_misc_mask(1<<0, 1<<0); + + //enable Base VGA 16 Bits Decode + //pci_mod_config8(host, 0x4e, 0, 1<<4); +} + +static void chrome9hd_init(device_t dev) +{ + print_debug("======================================================\n"); + print_debug("== Chrome9 HD INIT\n"); + print_debug("======================================================\n"); + + chrome9hd_biosguide_init_seq(dev); + + //vx900_vga_set_int15_handler(); + + u32 fb_address = pci_read_config32(dev, PCI_BASE_ADDRESS_2); + fb_address &= ~0x0F; + if (!fb_address) { + printk(BIOS_WARNING, "Chrome: No FB BAR assigned!\n"); + return; + } + + printk(BIOS_INFO, "Chrome: Using %dMB Framebuffer at 0x%08X.\n", + 256, fb_address); + + /* Poison the framebuffer */ +// size_t i, j; +// for(i = 0; i < 256; i++) { +// u32 * fb = (u32*) (u32)(fb_address + i * (1<<20)); +// for(j = 0; j < (1<<20)>>2; j++) { +// fb[j] = 0xdeadbeef; +// } +// } + + pci_write_config8(dev, PCI_INTERRUPT_LINE, 0x0a);//same with vx855_lpc.c + + printk(BIOS_DEBUG, "Initializing VGA...\n"); + + pci_dev_init(dev); + + printk(BIOS_DEBUG, "Enable VGA console\n"); + //vga_enable_console(); +} + +static void chrome9hd_enable(device_t dev) +{ + print_debug("======================================================\n"); + print_debug("== Chrome9 HD ENABLE\n"); + print_debug("======================================================\n"); + + device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0); + /* FIXME: here? -=- ACLK 250Mhz */ + pci_mod_config8(mcu, 0xbb, 0, 0x01); +} + +static void chrome9hd_disable(device_t dev) +{ + print_debug("======================================================\n"); + print_debug("== Chrome9 HD DISABLE\n"); + print_debug("======================================================\n"); + + device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0); + /* Disable GFX - This step effectively renders the GFX inert + * It won't even show up as a PCI device during enumeration */ + pci_mod_config8(mcu, 0xa1, 1<<7, 0); +} + +static void chrome9hd_read_resources(device_t dev) +{ + print_debug("======================================================\n"); + print_debug("== Chrome9 HD READ RESOURCES\n"); + print_debug("======================================================\n"); + + /* Mirror mirror, shiny glass, tell me that is not my ass */ + u32 fb_size = chrome9hd_fb_size() >> 20; + + uma_resource(dev, 0x18, uma_memory_base>>10, uma_memory_size>>10); + + u8 fb_pow = 0; + while(fb_size >> fb_pow) fb_pow ++; + fb_pow --; + + /* Step 6 - Let MCU know the framebuffer size */ + device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0); + pci_mod_config8(mcu, 0xa1, 7<<4, (fb_pow - 2) <<4); + + /* Step 7 - Let GFX know the framebuffer size (through PCI and IOCTL) + * The size we set here affects the behavior of BAR2, and the amount of + * MMIO space it requests. The default is 512MB, so if we don't set this + * before reading the resources, we could waste space below 4G */ + pci_write_config8(dev, 0xb2, ((0xff << (fb_pow - 2)) & ~(1<<7)) ); + vga_sr_write(0x68, (0xff << (fb_pow - 1)) ); + + pci_dev_read_resources(dev); +} + +static void chrome9hd_set_resources(device_t dev) +{ + print_debug("======================================================\n"); + print_debug("== Chrome9 HD SET RESOURCES\n"); + print_debug("======================================================\n"); + + pci_dev_set_resources(dev); +} + +static void chrome9hd_enable_resources(device_t dev) +{ + print_debug("======================================================\n"); + print_debug("== Chrome9 HD ENABLE RESOURCES\n"); + print_debug("======================================================\n"); + + pci_dev_enable_resources(dev); +} + +static struct device_operations chrome9hd_operations = { + .read_resources = chrome9hd_read_resources, + .set_resources = chrome9hd_set_resources, + .enable_resources = chrome9hd_enable_resources, + .init = chrome9hd_init, + .disable = chrome9hd_disable, + .enable = chrome9hd_enable, + .ops_pci = 0, +}; + +static const struct pci_driver chrome9hd_driver __pci_driver = { + .ops = &chrome9hd_operations, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_VX900_VGA, +}; \ No newline at end of file diff --git a/src/northbridge/via/vx900/early_smbus.c b/src/northbridge/via/vx900/early_smbus.c new file mode 100644 index 0000000..aa6cec0 --- /dev/null +++ b/src/northbridge/via/vx900/early_smbus.c @@ -0,0 +1,191 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <device/pci_ids.h> +#include "early_vx900.h" + +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <console/console.h> +#include <devices/dram/dram.h> + +__attribute__((unused)) +static void smbus_delays(int delays) +{ + while(delays--) __smbus_delay(); +} + + +/** + * Read a byte from the SMBus. + * + * @param dimm The address location of the DIMM on the SMBus. + * @param offset The offset the data is located at. + */ +u8 __smbus_read_byte(u8 dimm, u8 offset, u16 __smbus_io_base) +{ + u8 val; + + /* Initialize SMBUS sequence */ + smbus_reset(); + /* Clear host data port. */ + outb(0x00, SMBHSTDAT0); + + smbus_wait_until_ready(); + smbus_delays(50); + + /* Actual addr to reg format. */ + dimm = (dimm << 1); + dimm |= 1; /* read command */ + outb(dimm, SMBXMITADD); + outb(offset, SMBHSTCMD); + /* Start transaction, byte data read. */ + outb(0x48, SMBHSTCTL); + smbus_wait_until_ready(); + + val = inb(SMBHSTDAT0); + return val; +} + +void enable_smbus(void) +{ + device_t dev; + u8 reg8; + u16 __smbus_io_base = SMBUS_IO_BASE; + + /* Locate the Power Management control */ + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VX900_LPC), 0); + + if (dev == PCI_DEV_INVALID) { + die("Power Managment Controller not found\n"); + } + + /* + * To use SMBus to manage devices on the system board, it is a must to + * enable SMBus function by setting + * PMU_RXD2[0] (SMBus Controller Enable) to 1. + * And set PMU_RXD0 and PMU_RXD1 (SMBus I/O Base) to an appropriate + * I/O port address, so that all registers in SMBus I/O port can be + * accessed. + */ + + reg8 = pci_read_config8(dev, 0xd2); + /* Enable SMBus controller */ + reg8 |= 1; + /* Set SMBUS clock from 128k source */ + reg8 |= 1<<2; + pci_write_config8(dev, 0xd2, reg8); + + reg8 = pci_read_config8(dev, 0x94); + /* SMBUS clock from divider of 14.318 MHz */ + reg8 &= ~(1<<7); + pci_write_config8(dev, 0x94, reg8); + + /* Set SMBus IO base */ + pci_write_config16(dev, 0xd0, SMBUS_IO_BASE); + + /* + * Initialize the SMBus sequence: + */ + /* Clear SMBus host status register */ + smbus_reset(); + /* Clear SMBus host data 0 register */ + outb(0x00, SMBHSTDAT0); + + /* Wait for SMBUS */ + smbus_wait_until_ready(); + +} + +void spd_read(u8 addr, spd_raw_data spd) +{ + u8 reg; + int i, regs; + reg = smbus_read_byte(addr, 2); + if(reg != 0x0b) + { + printk(BIOS_DEBUG, "SMBUS device %x not a DDR3 module\n", addr); + spd[2] = 0; + return; + } + + reg = smbus_read_byte(addr, 0); + reg &= 0xf; + if (reg == 0x3) { + regs = 256; + } else if (reg == 0x2) { + regs = 176; + } else if (reg == 0x1) { + regs = 128; + } else { + printk(BIOS_INFO, "No DIMM present at %x\n", addr); + spd[2] = 0; + return; + } + printk(BIOS_DEBUG, "SPD Data for DIMM %x \n", addr); + for (i = 0; i < regs; i++) { + reg = smbus_read_byte(addr, i); + //printk(BIOS_DEBUG, " Offset %u = 0x%x \n", i, reg ); + spd[i] = reg; + } +} + +void dump_spd_data(void) +{ + int dimm, offset, regs; + unsigned int reg; + spd_raw_data spd; + dimm_attr dimmx; + + for (dimm = 0x50; dimm < 0x52; dimm++) { + reg = smbus_read_byte(dimm, 2); + if(reg != 0x0b) + { + printk(BIOS_DEBUG, + "SMBUS device %x not a DDR3 module\n", dimm); + continue; + } + + reg = smbus_read_byte(dimm, 0); + reg &= 0xf; + if (reg == 0x3) { + regs = 256; + } else if (reg == 0x2) { + regs = 176; + } else if (reg == 0x1) { + regs = 128; + } else { + printk(BIOS_INFO, "No DIMM present at %x\n", dimm); + regs = 0; + continue; + } + printk(BIOS_DEBUG, "SPD Data for DIMM %x \n", dimm); + for (offset = 0; offset < regs; offset++) { + reg = smbus_read_byte(dimm, offset); + //printk(BIOS_DEBUG, " Offset %u = 0x%x \n", offset, reg ); + spd[offset] = reg; + } + + spd_decode_ddr3(&dimmx, spd); + dram_print_spd_ddr3(&dimmx); + + } +} + diff --git a/src/northbridge/via/vx900/early_uma_ram.c b/src/northbridge/via/vx900/early_uma_ram.c new file mode 100644 index 0000000..d19d062 --- /dev/null +++ b/src/northbridge/via/vx900/early_uma_ram.c @@ -0,0 +1,135 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +# include "early_vx900.h" + +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <console/console.h> +#include <cbfs.h> +#include <device/pci_def.h> +#include <stddef.h> + +/* These are mainly arbitration values for the MCU to arbitrate bandwidth + * between CPU requests and GFX requests. They are set such that the GFX will + * get more bandwidth when needed (i.e. 3D graphics) + * If the GFX is idle, the CPU will still be able to use all available memory + * bandwidth. */ +static pci_reg8 mcu_vga_arbiter_config[] = { + {0xa2, 0xb4}, /* Arbitration - GFX */ + {0xa6, 0x01}, /* Enable 8QW request merging from GFX*/ + {0xb0, 0xb8}, /* Arbitration - Video decoder */ + {0xb1, 0x22}, /* Enable 8QW request merging from Video decoder */ + {0xb8, 0x11}, /* Priority adjustemnt for Video Decoder */ + {0xb9, 0x11}, /* Arbitration - Video Decoder Queue - I */ + {0xba, 0x11}, /* Arbitration - Video Decoder Queue - II */ +}; + +static void vx900_gfx_dram_arbitration(void) +{ + size_t i; + for(i = 0; i < (sizeof(mcu_vga_arbiter_config)/sizeof(pci_reg8)); i++) + { + pci_write_config8(MCU, mcu_vga_arbiter_config[i].addr, + mcu_vga_arbiter_config[i].val); + } +} + +void vx900_dram_set_gfx_resources(void) +{ + printk(BIOS_SPEW, "Setting up GFX mem area \n"); + /* FIXME: enable VGA or not? */ + /* u32 fbuff_size = vga_decide_framebuffer_size(); + * if(fbuff_size == 0) { + * Do not initialize the IGP + * return; + * } */ + + + /* Step 1 - Enable VGA controller */ +// pci_mod_config8(MCU, 0xa1, 0, 0x80); + /* FIXME: This is the VGA hole @ 640k-768k, and the vga port io + * We need the port IO, but can we disable the memory hole? */ +// pci_mod_config8(MCU, 0xa4, 0, 0x80); /* VGA memory hole */ + + //device_t d0f0 = PCI_DEV(0,0,0); + /* Step 2 - Forward MDA to GFX */ +// pci_mod_config8(d0f0, 0x4e, 1<<1, 0); /* FIXME */ + + /* Step 3 - Enable GFX I/O space */ +// pci_mod_config8(GFX, PCI_COMMAND, 0, PCI_COMMAND_IO); + + /* Step 4 - Enable video subsystem */ +// u8 io8 = inb(0x3c3); +// io8 |= 1<<0; +// outb(io8, 0x3c3); + //3410-20-KKL-04 +S + + /* Step 5 - Unlock accessing of IO space */ +// vx900_gfx_write8(0x10, 0x01); + + /* Prime PLL FIXME: bad comment */ + //vx900_gfx_mod8(0x3c, 0, 1<<2); + //vx900_gfx_mod8(0x3c, 0, 0); + + //VGA IO Address Select. 3B5 or 3D5? + u8 io8 = inb(0x03cc); + io8 |= 0x01; + outb(io8, 0x3c2); + //3410-20-KKL-04 +E + + /* Bandwidth, bandwidth, bandwidth */ + vx900_gfx_dram_arbitration(); + + /* FIXME: here? -=- ACLK 250Mhz */ + pci_mod_config8(MCU, 0xbb, 0, 0x01); + + /* Step 6 - Let MCU know the framebuffer size */ +// pci_mod_config8(MCU, 0xa1, 7<<4, (fb_pow - 2) <<4); + /* Step 7 - Let GFX know the framebuffer size (through PCI and IOCTL) */ +// pci_write_config8(GFX, 0xb2, ((0xff << (fb_pow - 2)) & ~(1<<7)) ); +// vx900_gfx_write8(0x68, (0xff << (fb_pow - 1)) ); + + /* Step 8 - Enable memory base register on the GFX */ +// const u64 tom = ( pci_read_config16(MCU, 0x88) & 0x07ff ) << 24; +// const u64 fb_base = tom - (fb_size << 20); +// vx900_gfx_write8(0x6d, (fb_base >> 21) & 0xff); /* base 28:21 */ +// vx900_gfx_write8(0x6e, (fb_base >> 29) & 0xff); /* base 36:29 */ +// vx900_gfx_write8(0x6f, 0x00); /* base what what in the butt ?? */ + + /* Step 9 - Set SID/VID */ +// vx900_gfx_set_sid_vid(0x1106, 0x7122); + + /* VGA framebuffer is system-local (in system RAM) */ +// pci_write_config8(GFX, 0xb0, 0x01); + + //enable Base VGA 16 Bits Decode + //pci_mod_config8(HOST_CTR, 0x4e, 0, 1<<4); + + /* That was it for the BIOS guide steps */ + /* FIXME: Do we need these canucking IO bars? */ + //pci_write_config32(GFX, PCI_BASE_ADDRESS_0, 0xf8000008); + //pci_write_config32(GFX, PCI_BASE_ADDRESS_1, 0xfc000000); + //pci_write_config32(GFX, PCI_BASE_ADDRESS_2, fb_base | 0x08); + + /* Direct framebuffer access + * FIXME: framebuffer base should be decided based on TOM and size */ + /* Let the MCU know of the frambuffer base, for direct access by CPU */ + //(MCU, 0xa0, 0x0ffe, 0x0200); +} \ No newline at end of file diff --git a/src/northbridge/via/vx900/early_vx900.c b/src/northbridge/via/vx900/early_vx900.c new file mode 100644 index 0000000..535ecd9 --- /dev/null +++ b/src/northbridge/via/vx900/early_vx900.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "early_vx900.h" +#include <arch/romcc_io.h> +#include <console/console.h> + +void vx900_enable_pci_config_space(void) +{ + /* MMCONF is not yet enabled, so we'll need to specify we want to do + * pci_io. We don't want to do pci_mmio until we enable it */ + /* Enable multifunction bit for northbridge. + * This enables the PCI configuration spaces of D0F1 to D0F7 to be + * accessed */ + pci_io_write_config8(HOST_CTR, 0x4f, 0x01); + +#if CONFIG_MMCONF_SUPPORT + /* COOL, now enable MMCONF */ + u8 reg8 = pci_io_read_config8(TRAF_CTR, 0x60); + reg8 |= 3; + pci_io_write_config8(PCI_DEV(TRAF_CTR, 0x60, reg8); + reg8 = CONFIG_MMCONF_BASE_ADDRESS >> 28; + pci_io_write_config8(TRAF_CTR, 0x61, reg8); +#endif +} + +void vx900_disable_legacy_rom_shadow(void) +{ + /* Disable shitty 8086 legacy shadows + * This frees the entire 640k-1M range for DRAM + * VGA may still use 640k-768k if enabled later */ + pci_write_config8(MCU, 0x80, 0xff); /* ROM 768k - 832k */ + pci_write_config8(MCU, 0x81, 0xff); /* ROM 832k - 896k */ + pci_write_config8(MCU, 0x82, 0xff); /* ROM 896k - 960k */ + /* ROM 960k - 1M * SMRAM: 640k - 768k */ + pci_write_config8(MCU, 0x83, 0x31); +} + +void vx900_disable_gfx(void) +{ + /* Disable GFX */ + pci_mod_config8(MCU, 0xa1, 1<<7, 0); +} diff --git a/src/northbridge/via/vx900/early_vx900.h b/src/northbridge/via/vx900/early_vx900.h new file mode 100644 index 0000000..5704686 --- /dev/null +++ b/src/northbridge/via/vx900/early_vx900.h @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef EARLY_VX900_H +#define EARLY_VX900_H + +#include "raminit.h" +#include "vx900.h" + +#include <arch/io.h> +#include <devices/smbus/smbus.h> +#include <stdint.h> + +#define HOST_CTR PCI_DEV(0, 0, 0) +#define TRAF_CTR PCI_DEV(0, 0, 5) +#define MCU PCI_DEV(0, 0, 3) +#define GFX PCI_DEV(0, 1, 0) +#define LPC PCI_DEV(0, 0x11, 0) + +void enable_smbus(void); +void dump_spd_data(void); +void spd_read(u8 addr, spd_raw_data spd); + +void vx900_enable_pci_config_space(void); +void vx900_disable_legacy_rom_shadow(void); + +void vx900_dram_set_gfx_resources(void); +void vx900_disable_gfx(void); + +#endif /* EARLY_VX900_H */ diff --git a/src/northbridge/via/vx900/forgotten.c b/src/northbridge/via/vx900/forgotten.c new file mode 100644 index 0000000..1b79e4e --- /dev/null +++ b/src/northbridge/via/vx900/forgotten.c @@ -0,0 +1,32 @@ +#include "forgotten.h" +#include <../../dram/dram.h> + +u16 ddr3_get_mr3(char dataflow_from_mpr) +{ + u32 cmd = 0; + if(dataflow_from_mpr) cmd |= (1<<2); + return cmd; +} + +/* + * Translate the MRS command into the memory address corresponding to the + * command. This is based on the CPU address to memory address mapping described + * by the initial values of registers 0x52 and 0x53, so do not fuck with them + * until after the MRS commands have been sent to all ranks + */ + +u32 vx900_get_mrs_addr(u8 mrs_type, u16 cmd); + +u32 vx900_get_mrs_addr(u8 mrs_type, u16 cmd) +{ + u32 addr = 0; + /* A3 <-> MA0, A4 <-> MA1, ... A12 <-> MA9 */ + addr |= ((cmd &0x3ff)<< 3); + /* A20 <-> MA10 */ + addr |= (((cmd >> 10) & 0x1) << 20); + /* A13 <-> MA11, A14 <-> MA12 */ + addr |= (((cmd >> 11) & 0x3) << 13); + /* A17 <-> BA0, A18 <-> BA1, A19 <-> BA2 */ + addr |= ((mrs_type & 0x7) << 17); + return addr; +} diff --git a/src/northbridge/via/vx900/forgotten.h b/src/northbridge/via/vx900/forgotten.h new file mode 100644 index 0000000..43641f7 --- /dev/null +++ b/src/northbridge/via/vx900/forgotten.h @@ -0,0 +1,78 @@ +#ifndef REDUNDANT_H +#define REDUNDANT_H + +#define DDR3_MR0_PRECHARGE_SLOW 0 +#define DDR3_MR0_PRECHARGE_FAST 1 +#define DDR3_MR0_MODE_NORMAL 0 +#define DDR3_MR0_MODE_TEST 1 +#define DDR3_MR0_DLL_RESET_NO 0 +#define DDR3_MR0_DLL_RESET_YES 1 +#define DDR3_MR0_BURST_TYPE_SEQUENTIAL 0 +#define DDR3_MR0_BURST_TYPE_INTERLEAVED 1 +#define DDR3_MR0_BURST_LENGTH_FIXED_8 0 +#define DDR3_MR0_BURST_LENGTH_CHOP 1 +#define DDR3_MR0_BURST_LENGTH_FIXED_4 2 +/** + * \brief Get command address for a DDR3 MR0 command + */ +u16 ddr3_get_mr0( + char precharge_pd, + u8 write_recovery, + char dll_reset, + char mode, + u8 cas, + char interleaved_burst, + u8 burst_lenght +); + +#define DDR3_MR1_TQDS_DISABLE 0 +#define DDR3_MR1_TQDS_ENABLE 1 +#define DDR3_MR1_QOFF_ENABLE 0 +#define DDR3_MR1_QOFF_DISABLE 1 +#define DDR3_MR1_WRITE_LEVELING_DISABLE 0 +#define DDR3_MR1_WRITE_LEVELING_ENABLE 1 +#define DDR3_MR1_RTT_NOM_OFF 0 +#define DDR3_MR1_RTT_NOM_RZQ4 1 +#define DDR3_MR1_RTT_NOM_RZQ2 2 +#define DDR3_MR1_RTT_NOM_RZQ6 3 +#define DDR3_MR1_RTT_NOM_RZQ12 4 +#define DDR3_MR1_RTT_NOM_RZQ8 5 +#define DDR3_MR1_AL_DISABLE 0 +#define DDR3_MR1_AL_CL_MINUS_1 1 +#define DDR3_MR1_AL_CL_MINUS_2 2 +#define DDR3_MR1_ODS_RZQ6 0 +#define DDR3_MR1_ODS_RZQ7 1 +#define DDR3_MR1_DLL_ENABLE 0 +#define DDR3_MR1_DLL_DISABLE 1 +/** + * \brief Get command address for a DDR3 MR1 command + */ +u16 ddr3_get_mr1( + char q_off, + char tdqs, + u8 rtt_nom, + char write_leveling, + u8 output_drive_strenght, + u8 additive_latency, + u8 dll_disable +); + +#define DDR3_MR2_RTT_WR_OFF 0 +#define DDR3_MR2_RTT_WR_RZQ4 1 +#define DDR3_MR2_RTT_WR_RZQ2 2 +/** + * \brief Get command address for a DDR3 MR2 command + */ +u16 ddr3_get_mr2( + u8 rtt_wr, + char extended_temp, + char auto_self_refresh, + u8 cas_write +); + +/** + * \brief Get command address for a DDR3 MR3 command + */ +u16 ddr3_get_mr3(char dataflow_from_mpr); + +#endif /* REDUNDANT_H */ \ No newline at end of file diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c new file mode 100644 index 0000000..8c4c935 --- /dev/null +++ b/src/northbridge/via/vx900/northbridge.c @@ -0,0 +1,136 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "vx900.h" +#include "chip.h" + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/cpu.h> +#include <cbmem.h> + +static void vx900_set_resources(device_t dev) +{ + print_debug("========================================" + "========================================\n" ); + print_debug("============= VX900 memory sizing & Co. " + "========================================\n" ); + print_debug("========================================" + "========================================\n" ); + + + int idx = 0; + const device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0); + if(!mcu) { + die("Something is terribly wrong.\n" + " We tried locating the MCU on the PCI bus, " + "but couldn't find it. Halting.\n"); + } + + u32 pci_tolm = find_pci_tolm(dev->link_list); + printk(BIOS_SPEW, "Found PCI tolm at %.8x\n", pci_tolm); + printk(BIOS_SPEW, "Found PCI tolm at %dMB\n", pci_tolm>>20); + + /* The last valid DRAM address is computed by the MCU + * One issue might be if we have a hole in the rank mappings, so that + * virtual ranks are not mapped successively in the linear address space + * (Ex: rank 0 mapped 0-1G, rank 1 mapped 2G-3G) + * We don't do this awkward mapping in RAM init, so we don't worry about + * it here, but it is something to keep in mind if having RAM issues */ + u32 vx900_tom = pci_read_config16(mcu, 0x88) & 0x07ff; + const u32 tomk = vx900_tom << (24-10); + printk(BIOS_SPEW, "Found top of memory at %dMB\n", tomk>>10); + + /* Do the same for top of low RAM */ + u32 vx900_tolm = (pci_read_config16(mcu, 0x84) & 0xfff0) >> 4; + const u32 full_tolmk = vx900_tolm << (20-10); + printk(BIOS_SPEW, "Found top of low memory at %dMB\n", full_tolmk>>10); + + /* What about the framebuffer for the integrated GPU? */ + u32 fbufk = chrome9hd_fb_size() >> 10; + printk(BIOS_SPEW, "Integrated graphics buffer: %dMB\n", fbufk>>10); + + /* Can't use the framebuffer as system RAM, sorry */ + u32 tolmk = full_tolmk - fbufk; + ram_resource(dev, idx++, 0, 640); + printk(BIOS_SPEW, "System ram left: %dMB\n", tolmk>>10); + /* FIXME: how can we avoid leaving this hole? + * Leave a hole for VGA, 0xa0000 - 0xc0000 ?? */ + ram_resource(dev, idx++, 768, (tolmk - 768)); + uma_memory_size = fbufk << 10; + uma_memory_base = tolmk << 10; + + #if CONFIG_WRITE_HIGH_TABLES + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (tolmk<<10) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; + printk(BIOS_DEBUG, "high_tables_base: %08llx, size %lld\n", + high_tables_base, high_tables_size); + #endif + print_debug("======================================================\n"); + assign_resources(dev->link_list); +} + +static void cpu_bus_init(device_t dev) +{ + initialize_cpus(dev->link_list); +} + +static void cpu_bus_noop(device_t dev) +{ +} +static struct device_operations cpu_bus_ops = { + .read_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, + .enable_resources = cpu_bus_noop, + .init = cpu_bus_init, + .scan_bus = 0, +}; + +static struct device_operations pci_domain_ops = { + .read_resources = pci_domain_read_resources, + .set_resources = vx900_set_resources, + .enable_resources = NULL, + .init = NULL, + .scan_bus = pci_domain_scan_bus, +#if CONFIG_MMCONF_SUPPORT_DEFAULT + .ops_pci_bus = &pci_ops_mmconf, +#else + .ops_pci_bus = &pci_cf8_conf1, +#endif +}; + +static void enable_dev(device_t dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { + dev->ops = &pci_domain_ops; + } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { + dev->ops = &cpu_bus_ops; + } +} + +struct chip_operations northbridge_via_vx900_ops = { + CHIP_NAME("VIA VX900 Chipset") + .enable_dev = enable_dev, +}; + diff --git a/src/northbridge/via/vx900/raminit.h b/src/northbridge/via/vx900/raminit.h new file mode 100644 index 0000000..a1b8710 --- /dev/null +++ b/src/northbridge/via/vx900/raminit.h @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef RAMINIT_VX900_H +#define RAMINIT_VX900_H + +#include <devices/dram/dram.h> +#include "vx900.h" + +#define SPD_END_LIST 0xff + +typedef struct dimm_layout_st +{ + /* The address of the DIMM on the SMBUS * + * 0xFF to terminate the array*/ + u8 spd_addr[VX900_MAX_DIMM_SLOTS + 1]; +} dimm_layout; + +typedef struct dimm_info_st +{ + dimm_attr dimm[VX900_MAX_DIMM_SLOTS]; +} dimm_info; + +typedef struct mem_rank_st { + u16 start_addr; + u16 end_addr; +}mem_rank; + +typedef struct rank_layout_st { + u32 phys_rank_size[VX900_MAX_MEM_RANKS]; + mem_rank virt[VX900_MAX_MEM_RANKS]; +} rank_layout; + +typedef struct pci_reg8_st { + u8 addr; + u8 val; +} pci_reg8; + +typedef u8 timing_dly[8]; + +typedef struct delay_range_st { + timing_dly low; + timing_dly avg; + timing_dly high; +} delay_range; + +typedef struct vx900_delay_calib_st { + delay_range rx_dq_cr; + delay_range rx_dqs; + delay_range tx_dq; + delay_range tx_dqs; +} vx900_delay_calib; + +void vx900_init_dram_ddr3(const dimm_layout *dimms); + +#endif /* RAMINIT_VX900_H */ diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c new file mode 100644 index 0000000..290add7 --- /dev/null +++ b/src/northbridge/via/vx900/raminit_ddr3.c @@ -0,0 +1,1046 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "early_vx900.h" +#include "raminit.h" +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <console/console.h> +#include <device/pci_ids.h> +#include <delay.h> +#include <lib.h> +#include <string.h> + +/* Map BA0 to A17, BA1 to A18 */ +/* Map BA2 to A19, RA0/RA1 must not overlap BA[0:2] */ +#define VX900_MRS_MA_MAP 0x4b33 /* MA Pin Mapping for MRS commands */ +#define VX900_CALIB_MA_MAP 0x5911 /* MA Pin mapping for calibrations */ + +/* Registers 0x78 -> 0x7f contain calibration the settings for DRAM IO timing + * The dataset in these registers is selected from 0x70. + * Once the correct dataset is selected the delays can be altered. + * delay_type refers to TxDQS, TxDQ, RxDQS, or RxCR + * bound refers to either manual, average, upper bound, or lower bound + */ +#define VX900_CALIB_TxDQS 0 +#define VX900_CALIB_TxDQ 1 +#define VX900_CALIB_RxDQS 2 +#define VX900_CALIB_RxDQ_CR 3 + +#define VX900_CALIB_AVERAGE 0 +#define VX900_CALIB_LOWER 1 +#define VX900_CALIB_UPPER 2 +#define VX900_CALIB_MANUAL 4 + +static void vx900_delay_calib_mode_select(u8 delay_type, u8 bound) +{ + /* Which calibration setting */ + u8 reg8 = (delay_type & 0x03) << 2; + /* Upper, lower, average, or manual setting */ + reg8 |= (bound & 0x03); + pci_write_config8(MCU, 0x70, reg8); +} + +static void vx900_read_0x78_0x7f(timing_dly dly) +{ + *((u32*) (&(dly[0]))) = pci_read_config32(MCU, 0x78); + *((u32*) (&(dly[4]))) = pci_read_config32(MCU, 0x7c); +} + +static void vx900_write_0x78_0x7f(const timing_dly dly) +{ + pci_write_config32(MCU, 0x78, *((u32*) (&(dly[0]))) ); + pci_write_config32(MCU, 0x7c, *((u32*) (&(dly[4]))) ); +} + +static void vx900_read_delay_range(delay_range *d_range, u8 mode) +{ + vx900_delay_calib_mode_select(mode, VX900_CALIB_LOWER); + vx900_read_0x78_0x7f(d_range->low); + vx900_delay_calib_mode_select(mode, VX900_CALIB_AVERAGE); + vx900_read_0x78_0x7f(d_range->avg); + vx900_delay_calib_mode_select(mode, VX900_CALIB_UPPER); + vx900_read_0x78_0x7f(d_range->high); +} + +static void dump_delay(const timing_dly dly) +{ + u8 i; + for(i = 0; i < 8; i ++) + { + printram(" %.2x", dly[i]); + } + printram("\n"); +} + +static void dump_delay_range(const delay_range d_range) +{ + printram("Lower limit: "); + dump_delay(d_range.low); + printram("Average: "); + dump_delay(d_range.avg); + printram("Upper limit: "); + dump_delay(d_range.high); +} + +/* These are some "safe" values that can be used for memory initialization. + * Some will stay untouched, and others will be overwritten later on + * YOU REALLY NEED THE DATASHEET TO UNDERSTAND THESE !!! */ +static pci_reg8 mcu_init_config[] = { + {0x40, 0x01}, /* Virtual rank 0 ending address = 64M - 1 */ + {0x41, 0x00}, {0x42, 0x00}, {0x43, 0x00}, /* Virtual Ranks ending */ + {0x48, 0x00}, /* Virtual rank 0 starting address = 0 */ + {0x49, 0x00}, {0x4a, 0x00}, {0x4b, 0x00}, /* Virtual Ranks beginning */ + {0x50, 0xd8}, /* Set ranks 0-3 to 11 col bits, 16 row bits */ + /* Disable all virtual ranks */ + {0x54, 0x00}, {0x55, 0x00}, {0x56, 0x00}, {0x57, 0x00}, + /* Disable rank interleaving in ranks 0-3 */ + {0x58, 0x00}, {0x59, 0x00}, {0x5a, 0x00}, {0x5b, 0x00}, + {0x6c, 0xA0}, /* Memory type: DDR3, VDIMM: 1.5V, 64-bit DRAM */ + {0xc4, 0x80}, /* Enable 8 memory banks */ + {0xc6, 0x80}, /* Minimum latency from self-refresh. Bit [7] must be 1 */ + /* FIXME: do it here or in Final config? */ + {0xc8, 0x80}, /* Enable automatic triggering of short ZQ calibration */ + {0x99, 0xf0}, /* Power Management and Bypass Reorder Queue */ + /* Enable differential DQS; MODT assertion values suggested in DS */ + {0x9e, 0xa1}, {0x9f, 0x51}, + /* DQ/DQM Duty Control - Do not put any extra delays*/ + {0xe9, 0x00}, {0xea, 0x00}, {0xeb, 0x00}, {0xec, 0x00}, + {0xed, 0x00}, {0xee, 0x00}, {0xef, 0x00}, + {0xfc, 0x00}, {0xfd, 0x00}, {0xfe, 0x00}, {0xff, 0x00}, + /* The following parameters we may or may not change */ + {0x61, 0x2e}, /* DRAMC Pipeline Control */ + {0x77, 0x10}, /* MDQS Output Control */ + + /* The following are parameters we'll most likely never change again */ + {0x60, 0xf4}, /* DRAM Pipeline Turn-Around Setting */ + {0x65, 0x49}, /* DRAM Arbitration Bandwidth Timer - I */ + {0x66, 0x80}, /* DRAM Queue / Arbitration */ + {0x69, 0xc6}, /* Bank Control: 8 banks, high priority refresh */ + {0x6a, 0xfc}, /* DRAMC Request Reorder Control */ + {0x6e, 0x38}, /* Burst lenght: 8, burst-chop: enable */ + {0x73, 0x04}, /* Close All Pages Threshold */ + + /* The following need to be dynamically asserted */ + /* See: check_special_registers.c */ + {0x74, 0xa0}, /* Yes, same 0x74; add one more T */ + {0x76, 0x60}, /* Write Data Phase Control */ + +}; + +/* This table keeps the driving strength control setting that we can safely use + * doring initialization. */ +static pci_reg8 mcu_drv_ctrl_config[] = { + {0xd3, 0x03}, /* Enable auto-compensation circuit for ODT strength */ + {0xd4, 0x80}, /* Set internal ODT to dynamically turn on or off */ + {0xd6, 0x20}, /* Enable strong driving for MA and DRAM commands*/ + {0xd0, 0x88}, /* (ODT) Strength ?has effect? */ + {0xe0, 0x88}, /* DRAM Driving – Group DQS (MDQS) */ + {0xe1, 0x00}, /* Disable offset mode for driving strength control */ + {0xe2, 0x88}, /* DRAM Driving – Group DQ (MD, MDQM) */ + {0xe4, 0xcc}, /* DRAM Driving – Group CSA (MCS, MCKE, MODT) */ + {0xe8, 0x88}, /* DRAM Driving – Group MA (MA, MBA, MSRAS, MSCAS, MSWE)*/ + {0xe6, 0xff}, /* DRAM Driving – Group DCLK0 (DCLK[2:0] for DIMM0) */ + {0xe7, 0xff}, /* DRAM Driving – Group DCLK1 (DCLK[5:3] for DIMM1) */ + {0xe4, 0xcc}, /* DRAM Driving – Group CSA (MCS, MCKE, MODT)*/ + {0x91, 0x08}, /* MCLKO Output Phase Delay - I */ + {0x92, 0x08}, /* MCLKO Output Phase Delay - II */ + {0x93, 0x16}, /* CS/CKE Output Phase Delay */ + {0x95, 0x16}, /* SCMD/MA Output Phase Delay */ + {0x9b, 0x3f}, /* Memory Clock Output Enable */ +}; + +static void vx900_dram_set_ma_map(u16 map) +{ + pci_write_config16(MCU, 0x52, map); +} + +static void vx900_dram_write_init_config(void) +{ + /* Keep our RAM space free of legacy stuff */ + vx900_disable_legacy_rom_shadow(); + + /* Now worry about the real RAM init */ + size_t i; + for(i = 0; i < (sizeof(mcu_init_config)/sizeof(pci_reg8)); i++) + { + pci_write_config8(MCU, mcu_init_config[i].addr, + mcu_init_config[i].val); + } + vx900_dram_set_ma_map(VX900_CALIB_MA_MAP); +} + +static void dram_find_spds_ddr3(const dimm_layout *addr, dimm_info *dimm) +{ + size_t i = 0; + int dimms = 0; + do { + spd_raw_data spd; + spd_read(addr->spd_addr[i], spd); + spd_decode_ddr3(&dimm->dimm[i], spd); + if(dimm->dimm[i].dram_type != DRAM_TYPE_DDR3) continue; + dimms++; + dram_print_spd_ddr3(&dimm->dimm[i]); + } while(addr->spd_addr[++i] != SPD_END_LIST + && i < VX900_MAX_DIMM_SLOTS); + + if(!dimms) + die("No DIMMs were found"); +} + +static void dram_find_common_params(const dimm_info *dimms, ramctr_timing *ctrl) +{ + size_t i, valid_dimms; + memset(ctrl, 0, sizeof(ramctr_timing)); + ctrl->cas_supported = 0xff; + valid_dimms = 0; + for(i = 0; i < VX900_MAX_DIMM_SLOTS; i++) + { + const dimm_attr *dimm = &dimms->dimm[i]; + if(dimm->dram_type == DRAM_TYPE_UNDEFINED) continue; + valid_dimms++; + + if(valid_dimms == 1) { + /* First DIMM defines the type of DIMM */ + ctrl->dram_type = dimm->dram_type; + } else { + /* Check if we have mismatched DIMMs */ + if(ctrl->dram_type != dimm->dram_type) + die("Mismatched DIMM Types"); + } + /* Find all possible CAS combinations */ + ctrl->cas_supported &= dimm->cas_supported; + + /* Find the smallest common latencies supported by all DIMMs */ + ctrl->tCK = max(ctrl->tCK, dimm->tCK ); + ctrl->tAA = max(ctrl->tAA, dimm->tAA ); + ctrl->tWR = max(ctrl->tWR, dimm->tWR ); + ctrl->tRCD = max(ctrl->tRCD, dimm->tRCD); + ctrl->tRRD = max(ctrl->tRRD, dimm->tRRD); + ctrl->tRP = max(ctrl->tRP, dimm->tRP ); + ctrl->tRAS = max(ctrl->tRAS, dimm->tRAS); + ctrl->tRC = max(ctrl->tRC, dimm->tRC ); + ctrl->tRFC = max(ctrl->tRFC, dimm->tRFC); + ctrl->tWTR = max(ctrl->tWTR, dimm->tWTR); + ctrl->tRTP = max(ctrl->tRTP, dimm->tRTP); + ctrl->tFAW = max(ctrl->tFAW, dimm->tFAW); + + } + + if(!ctrl->cas_supported) die("Unsupported DIMM combination. " + "DIMMS do not support common CAS latency"); + if(!valid_dimms) die("No valid DIMMs found"); +} + +static void vx900_dram_phys_bank_range(const dimm_info *dimms, + rank_layout *ranks) +{ + size_t i; + for(i = 0; i < VX900_MAX_DIMM_SLOTS; i ++) + { + if(dimms->dimm[i].dram_type == DRAM_TYPE_UNDEFINED) + continue; + u8 nranks = dimms->dimm[i].ranks; + if(nranks > 2) + die("Found DIMM with more than two ranks, which is not " + "supported by this chipset"); + u32 size = dimms->dimm[i].size; + if(nranks == 2) { + /* Each rank holds half the capacity of the DIMM */ + size >>= 1; + ranks->phys_rank_size[i<<1] = size; + ranks->phys_rank_size[(i<<1) | 1] = size; + } else { + /* Otherwise, everything is held in the first bank */ + ranks->phys_rank_size[i<<1] = size; + ranks->phys_rank_size[(i<<1) | 1] = 0;; + } + } +} + +static void vx900_dram_driving_ctrl(const dimm_info *dimm) +{ + size_t i, ndimms; + u8 val; + + /* For ODT range selection, datasheet recommends + * when 1 DIMM present: 60 Ohm + * when 2 DIMMs present: 120 Ohm */ + ndimms = 0; + for(i = 0; i < VX900_MAX_DIMM_SLOTS; i++) { + if(dimm->dimm[i].dram_type == DRAM_TYPE_DDR3) ndimms++; + } + val = (ndimms > 1) ? 0x0 : 0x1; + pci_write_config8(MCU, 0xd5, val << 2); + + + /* FIXME: Assert dynamically based on dimm config */ + /* DRAM ODT Lookup Table*/ + pci_write_config8(MCU, 0x9c, 0xe4); + + for(i = 0; i < (sizeof(mcu_drv_ctrl_config)/sizeof(pci_reg8)); i++) + { + pci_write_config8(MCU, mcu_drv_ctrl_config[i].addr, + mcu_drv_ctrl_config[i].val); + } +} + +static void vx900_pr_map_all_vr3(void) +{ + /* Enable all ranks and set them to VR3 */ + pci_write_config16(MCU, 0x54, 0xbbbb); +} +/* Map physical rank pr to virtual rank vr */ +static void vx900_map_pr_vr(u8 pr, u8 vr) +{ + pr &= 0x3; vr &= 0x3; + /* Enable rank (bit [3], and set the VR number bits [1:0] */ + u16 val = 0x8 | vr; + /* Now move the value to the appropriate PR */ + val <<= (pr * 4); + pci_mod_config16(MCU, 0x54, 0xf << (pr * 4), val); + printram("Mapping PR %u to VR %u\n", pr, vr); +} + +static u8 vx900_get_CWL(u8 CAS) +{ + /* Get CWL based on CAS using the following rule: + * _________________________________________ + * CAS: | 4T | 5T | 6T | 7T | 8T | 9T | 10T | 11T | + * CWL: | 5T | 5T | 5T | 6T | 6T | 7T | 7T | 8T | + */ + static const u8 cas_cwl_map[] = {5, 5, 5, 6, 6, 7, 7, 8}; + if(CAS > 11) return 8; + return cas_cwl_map[CAS - 4]; +} + +static void vx900_dram_timing(ramctr_timing *ctrl) +{ + /* Here we are calculating latencies, and writing them to the appropiate + * registers. Some registers do not take latencies from 0T, for example: + * CAS: 000 = 4T, 001 = 5T, 010 = 6T, etc + * In this example we subtract 4T from the result for CAS: (val - 4) + * The & 0x07 after (val - T0) just makes sure that, no matter what + * crazy thing may happen, we do not write outside the bits allocated + * in the register */ + u8 reg8, val, tFAW, tRRD; + u32 val32; + + /* Maximum supported DDR3 frequency is 533MHz (DDR3 1066) + * so make sure we cap it if we have faster DIMMs */ + if(ctrl->tCK < TCK_533MHZ) ctrl->tCK = TCK_533MHZ; + val32 = (1000 << 8) / ctrl->tCK; + printram("Selected DRAM frequency: %u MHz\n", val32); + + /* Now find the right DRAM frequency setting, + * and align it to the closest JEDEC standard frequency */ + if(ctrl->tCK <= TCK_533MHZ) {val = 0x07; ctrl->tCK = TCK_533MHZ;} + else if(ctrl->tCK <= TCK_400MHZ) {val = 0x06; ctrl->tCK = TCK_400MHZ;} + else if(ctrl->tCK <= TCK_333MHZ) {val = 0x05; ctrl->tCK = TCK_333MHZ;} + else if(ctrl->tCK <= TCK_266MHZ) {val = 0x04; ctrl->tCK = TCK_266MHZ;} + + /* Find CAS and CWL latencies */ + val = (ctrl->tAA + ctrl->tCK -1) / ctrl->tCK; + printram("Minimum CAS latency : %uT\n", val); + /* Find lowest supported CAS latency that satisfies the minimum value */ + while( !((ctrl->cas_supported >> (val-4))&1) + && (ctrl->cas_supported >> (val-4))) { + val++; + } + /* Is CAS supported */ + if(!(ctrl->cas_supported & (1 << (val-4))) ) + printram("CAS not supported\n"); + printram("Selected CAS latency : %uT\n", val); + ctrl->CAS = val; + ctrl->CWL = vx900_get_CWL(ctrl->CAS); + printram("Selected CWL latency : %uT\n", ctrl->CWL); + /* Write CAS and CWL */ + reg8 = ( ((ctrl->CWL - 4) &0x07) << 4 ) | ((ctrl->CAS - 4) & 0x07); + pci_write_config8(MCU, 0xc0, reg8); + + /* Find tRCD */ + val = (ctrl->tRCD + ctrl->tCK -1) / ctrl->tCK; + printram("Selected tRCD : %uT\n", val); + reg8 = ((val-4) & 0x7) << 4; + /* Find tRP */ + val = (ctrl->tRP + ctrl->tCK -1) / ctrl->tCK; + printram("Selected tRP : %uT\n", val); + reg8 |= ((val-4) & 0x7); + pci_write_config8(MCU, 0xc1, reg8); + + /* Find tRAS */ + val = (ctrl->tRAS + ctrl->tCK -1) / ctrl->tCK; + printram("Selected tRAS : %uT\n", val); + reg8 = ((val-15) & 0x7) << 4; + /* Find tWR */ + ctrl->WR = (ctrl->tWR + ctrl->tCK -1) / ctrl->tCK; + printram("Selected tWR : %uT\n", ctrl->WR); + reg8 |= ((ctrl->WR-4) & 0x7); + pci_write_config8(MCU, 0xc2, reg8); + + /* Find tFAW */ + tFAW = (ctrl->tFAW + ctrl->tCK -1) / ctrl->tCK; + printram("Selected tFAW : %uT\n", tFAW); + /* Find tRRD */ + tRRD = (ctrl->tRRD + ctrl->tCK -1) / ctrl->tCK; + printram("Selected tRRD : %uT\n", tRRD); + val = tFAW - 4*tRRD; /* number of cycles above 4*tRRD */ + reg8 = ((val-0) & 0x7) << 4; + reg8 |= ((tRRD-2) & 0x7); + pci_write_config8(MCU, 0xc3, reg8); + + /* Find tRTP */ + val = (ctrl->tRTP + ctrl->tCK -1) / ctrl->tCK; + printram("Selected tRTP : %uT\n", val); + reg8 = ((val & 0x3) << 4); + /* Find tWTR */ + val = (ctrl->tWTR + ctrl->tCK -1) / ctrl->tCK; + printram("Selected tWTR : %uT\n", val); + reg8 |= ((val - 2) & 0x7); + pci_mod_config8(MCU, 0xc4, 0x3f, reg8); + + /* DRAM Timing for All Ranks - VI + * [7:6] CKE Assertion Minimum Pulse Width + * We probably don't want to mess with this just yet. + * [5:0] Refresh-to-Active or Refresh-to-Refresh (tRFC) + * tRFC = (30 + 2 * [5:0])T + * Since we previously set RxC4[7] + */ + reg8 = pci_read_config8(MCU, 0xc5); + val = (ctrl->tRFC + ctrl->tCK -1) / ctrl->tCK; + printram("Minimum tRFC : %uT\n", val); + if(val < 30) { + val = 0; + } else { + val = (val -30 + 1 ) / 2; + } + ; + printram("Selected tRFC : %uT\n", 30 + 2 * val); + reg8 |= (val & 0x3f); + pci_write_config8(MCU, 0xc5, reg8); + + /* Where does this go??? */ + val = (ctrl->tRC + ctrl->tCK -1) / ctrl->tCK; + printram("Required tRC : %uT\n", val); +} + +static void vx900_dram_freq(ramctr_timing *ctrl) +{ + u8 val; + + /* Program the DRAM frequency */ + + /* Step 1 - Reset the PLL */ + pci_mod_config8(MCU, 0x90, 0x00, 0x0f); + /* Wait at least 10 ns; VIA code delays by 640us */ + udelay(640); + + /* Step 2 - Set target frequency */ + if(ctrl->tCK <= TCK_533MHZ) {val = 0x07; ctrl->tCK = TCK_533MHZ;} + else if(ctrl->tCK <= TCK_400MHZ) {val = 0x06; ctrl->tCK = TCK_400MHZ;} + else if(ctrl->tCK <= TCK_333MHZ) {val = 0x05; ctrl->tCK = TCK_333MHZ;} + else /*ctrl->tCK <= TCK_266MHZ*/ {val = 0x04; ctrl->tCK = TCK_266MHZ;} + /* Restart the PLL with the desired frequency */ + pci_mod_config8(MCU, 0x90, 0x0f, val); + + /* Step 3 - Wait for PLL to stabilize */ + udelay(2000); + + /* Step 4 - Reset the DLL - Clear [7,4]*/ + pci_mod_config8(MCU, 0x6b, 0x90, 0x00); + udelay(2000); + + /* Step 5 - Enable the DLL - Set bits [7,4] to 01b*/ + pci_mod_config8(MCU, 0x6b, 0x00, 0x10); + udelay(2000); + + /* Step 6 - Start DLL Calibration - Set bit [7] */ + pci_mod_config8(MCU, 0x6b, 0x00, 0x80); + udelay(5); + + /* Step 7 - Finish DLL Calibration - Clear bit [7]*/ + pci_mod_config8(MCU, 0x6b, 0x80, 0x00); + + /* Step 8 - If we have registered DIMMs, we need to set bit[0] */ + if(dimm_is_registered(ctrl->dram_type)){ + printram("Enabling RDIMM support in memory controller\n"); + pci_mod_config8(MCU, 0x6c, 0x00, 0x01); + } +} + + +void vx900_dram_ddr3_do_hw_mrs(u8 ma_swap, u8 rtt_nom, + u8 ods, u8 rtt_wr, u8 srt, u8 asr); +/*static*/ void vx900_dram_ddr3_do_hw_mrs(u8 ma_swap, u8 rtt_nom, + u8 ods, u8 rtt_wr, u8 srt, u8 asr) +{ + /* The VX900 can send the MRS commands directly through hardware + * It does the MR2->MR3->MR1->MR0->LongZQ dance*/ + u16 reg16 = 0; + if(asr) reg16 |= (1 << 8); + if(srt) reg16 |= (1 << 9); + reg16 |= ((rtt_wr & 0x03) << 12); + if(ma_swap) reg16 |= (1 << 1); + reg16 |= ((ods & 0x03) << 2); + reg16 |= ((rtt_nom & 0x7) << 4); + reg16 |= 1; /* This is the trigger bit */ + pci_write_config16(MCU, 0xcc, reg16); + /* Wait for MRS commands to be sent */ + while(pci_read_config8(MCU, 0xcc) & 1); +} +#include "forgotten.h" +#include "forgotten.c" + +static void vx900_dram_send_soft_mrs(u8 type, u16 cmd) +{ + u32 addr; + /* Set Fun3_RX6B[2:0] to 011b (MSR Enable). */ + pci_mod_config8(MCU, 0x6b, 0x07, (3<<0)); + /* Find the address corresponding to the MRS */ + addr = vx900_get_mrs_addr(type, cmd); + /* Execute the MRS */ + volatile_read(addr); + /* Set Fun3_Rx6B[2:0] to 000b (Normal SDRAM Mode). */ + pci_mod_config8(MCU, 0x6b, 0x07, 0x00); +} + +static void vx900_dram_ddr3_dimm_init(const ramctr_timing *ctrl, + const rank_layout *ranks) +{ + size_t i; + + /* Set BA[0/1/2] to [A17/18/19] */ + vx900_dram_set_ma_map(VX900_MRS_MA_MAP); + + /* Step 01 - Set Fun3_Rx6E[5] to 1b to support burst length. */ + pci_mod_config8(MCU, 0x6e, 0, 1<<5); + /* Step 02 - Set Fun3_RX69[0] to 0b (Disable Multiple Page Mode). */ + pci_mod_config8(MCU, 0x69, (1<<0), 0x00); + /* And set [7:6] to 10b ?*/ + pci_write_config8(MCU, 0x69, 0x87); + + /* Step 03 - Set the target physical rank to virtual rank0 and other + * ranks to virtual rank3. */ + vx900_pr_map_all_vr3(); + + /* Step 04 - Set Fun3_Rx50 to D8h. */ + pci_write_config8(MCU, 0x50, 0xd8); + /* Step 05 - Set Fun3_RX6B[5] to 1b to de-assert RESET# and wait for at + * least 500 us. */ + pci_mod_config8(MCU, 0x6b, 0x00, (1<<5) ); + udelay(500); + + /* Step 6 -> 15 - Set the target physical rank to virtual rank 0 and + * other ranks to virtual rank 3. + * Repeat Step 6 to 14 for every rank present, then jump to Step 16. */ + for(i = 0; i < VX900_MAX_MEM_RANKS; i++) + { + if(ranks->phys_rank_size[i] == 0) continue; + printram("Initializing rank %lu\n", i); + + /* Set target physical rank to virtual rank 0 + * other ranks to virtual rank 3*/ + vx900_map_pr_vr(i, 0); + + /* FIXME: Is this needed on HW init? */ + pci_mod_config8(MCU, 0x6b, 0x07, 0x01); /* Enable NOP */ + volatile_read(0x0); /* Do NOP */ + pci_mod_config8(MCU, 0x6b, 0x07, 0x03); /* MSR Enable */ + + /* FIXME: Values dependent on DIMM setup + * This works for 1 DIMM + * See init_dram_by_rank.c and get_basic_information.c + * in the VIA provided code */ + const u8 rtt_nom = DDR3_MR1_RTT_NOM_RZQ2; + const u8 ods = DDR3_MR1_ODS_RZQ6; + const u8 rtt_wr = DDR3_MR2_RTT_WR_OFF; + + printram("Using Hardware method\n"); + /* FIXME: MA swap dependent on module */ + vx900_dram_ddr3_do_hw_mrs(0, rtt_nom, ods, rtt_wr, 0, 0); + + /* Normal SDRAM Mode */ + pci_mod_config8(MCU, 0x6b, 0x07, 0x00); + + /* Step 15, set the rank to virtual rank 3*/ + vx900_map_pr_vr(i, 3); + } + + /* Step 16 – Set Fun3_Rx6B[2:0] to 000b (Normal SDRAM Mode). */ + pci_mod_config8(MCU, 0x6b, 0x07, 0x00); + + /* Set BA[0/1/2] to [A13/14/15] */ + vx900_dram_set_ma_map(VX900_CALIB_MA_MAP); + + /* Step 17 – Set Fun3_Rx69[0] to 1b (Enable Multiple Page Mode). */ + pci_mod_config8(MCU, 0x69, 0x00, (1<<0) ); + + printram("DIMM initialization sequence complete\n"); +} + +static void vx900_dram_enter_read_leveling(void) +{ + /* Precharge all before issuing read leveling MRS to DRAM */ + pci_mod_config8(MCU, 0x06b, 0x07, 0x02); + volatile_read(0x0); + udelay(1000); + + /* Enable read leveling: Set D0F3Rx71[7]=1 */ + pci_mod_config8(MCU, 0x71, 0x40, 0x80); + + /* Put DRAM in read leveling mode */ + u16 cmd = ddr3_get_mr3(1); + vx900_dram_send_soft_mrs(3, cmd); +} + +static void vx900_dram_exit_read_leveling(void) +{ + /* Disable read leveling, and put dram in normal operation mode */ + u16 cmd = ddr3_get_mr3(0); + vx900_dram_send_soft_mrs(3, cmd); + + /* Disable read leveling: Set D0F3Rx71[7]=0 */ + pci_mod_config8(MCU, 0x71, 1<<7, 0); +} + +static void vx900_rx_capture_range_calib(void) +{ + u8 reg8; + const u32 cal_addr = 0x20; + + /* Set IO calibration address */ + pci_mod_config16(MCU, 0x8c , 0xfff0, cal_addr&(0xfff0)); + /* Data pattern must be 0x00 for this calibration + * See paragraph describing Rx8e */ + pci_write_config8(MCU, 0x8e, 0x00); + + /* Need to put DRAM and MCU in read leveling */ + vx900_dram_enter_read_leveling(); + + /* Data pattern must be 0x00 for this calibration + * See paragraph describing Rx8e */ + pci_write_config8(MCU, 0x8e, 0x00); + /* Trigger calibration */ + reg8 = 0xa0; + pci_write_config8(MCU, 0x71, reg8); + + /* Wait for it */ + while(pci_read_config8(MCU, 0x71) & 0x10); + vx900_dram_exit_read_leveling(); +} + +static void vx900_rx_dqs_delay_calib(void) +{ + const u32 cal_addr = 0x30; + + /* We need to disable refresh commands so that they don't interfere */ + const u8 ref_cnt = pci_read_config8(MCU, 0xc7); + pci_write_config8(MCU, 0xc7, 0); + /* Set IO calibration address */ + pci_mod_config16(MCU, 0x8c , 0xfff0, cal_addr&(0xfff0)); + /* Data pattern must be 0x00 for this calibration + * See paragraph describing Rx8e */ + pci_write_config8(MCU, 0x8e, 0x00); + + /* Need to put DRAM and MCU in read leveling */ + vx900_dram_enter_read_leveling(); + + /* From VIA code; Undocumented + * In theory this enables MODT[3:0] to be asserted */ + pci_mod_config8(MCU, 0x9e, 0, 0x80); + + /* Trigger calibration: Set D0F3Rx71[1:0]=10b */ + pci_mod_config8(MCU, 0x71, 0x03, 0x02); + + /* Wait for calibration to complete */ + while( pci_read_config8(MCU, 0x71) & 0x02 ); + vx900_dram_exit_read_leveling(); + + /* Restore the refresh counter*/ + pci_write_config8(MCU, 0xc7, ref_cnt); + + /* FIXME: should we save it before, or should we just set it as is */ + vx900_dram_set_ma_map(VX900_CALIB_MA_MAP); +} + +static void vx900_tx_dqs_trigger_calib(u8 pattern) +{ + u32 i; + /* Data pattern for calibration */ + pci_write_config8(MCU, 0x8e, pattern); + /* Trigger calibration */ + pci_mod_config8(MCU, 0x75, 0, 0x20); + /* Wait for calibration */ + i = 0; + while(pci_read_config8(MCU, 0x75) & 0x20) i++; + printram(" Tx DQS calib took %u PCI cycles\n", i); +} +static void vx900_tx_dqs_delay_calib(void) +{ + const u32 cal_addr = 0x00; + /* Set IO calibration address */ + pci_mod_config16(MCU, 0x8c , 0xfff0, cal_addr&(0xfff0)); + /* Set circuit to use calibration results - Clear Rx75[0]*/ + pci_mod_config8(MCU, 0x75, 0x01, 0); + /* Run calibration with first data pattern*/ + vx900_tx_dqs_trigger_calib(0x5a); + /* Run again with different pattern */ + vx900_tx_dqs_trigger_calib(0xa5); +} + +static void vx900_tx_dq_delay_calib(void) +{ + int i = 0; + /* Data pattern for calibration */ + pci_write_config8(MCU, 0x8e, 0x5a); + /* Trigger calibration */ + pci_mod_config8(MCU, 0x75, 0, 0x02); + /* Wait for calibration */ + while(pci_read_config8(MCU, 0x75) & 0x02) i++; + printram("TX DQ calibration took %u PCI cycles\n", i); +} + +static void vx900_rxdqs_adjust(delay_range *dly) +{ + /* Adjust Rx DQS delay after calibration has been run. This is + * recommended by VIA, but no explanation was provided as to why */ + size_t i; + for(i = 0; i < 8; i++) + { + if(dly->low[i] < 3) + { + if(i == 2 || i== 4) dly->low[i] += 4; + else dly->avg[i] += 3; + + } + + if(dly->high[i] > 0x38) dly->avg[i] -= 6; + else if(dly->high[i] > 0x30) dly->avg[i] -= 4; + + if(dly->avg[i] > 0x20) dly->avg[i] = 0x20; + } + + /* Put Rx DQS delay into manual mode (Set Rx[2,0] to 01) */ + pci_mod_config8(MCU, 0x71, 0x05, 0x01); + /* Now write the new settings */ + vx900_delay_calib_mode_select(VX900_CALIB_RxDQS, VX900_CALIB_MANUAL); + vx900_write_0x78_0x7f(dly->avg); +} + +static void vx900_dram_calibrate_delays(const ramctr_timing *ctrl, + const rank_layout *ranks) +{ + timing_dly dly; + size_t i; + u8 val; + vx900_delay_calib delay_cal; + memset(&delay_cal, 0, sizeof(delay_cal)); + printram("Starting delay calibration\n"); + + /**** Read delay control ****/ + /* MD Input Data Push Timing Control; + * use values recommended in datasheet + * Setting this too low causes the Rx window to move below the range we + * need it so we can capture it with Rx_78_7f + * This causes Rx calibrations to be too close to 0, and Tx + * calibrations will fail. + * Setting this too high causes the window to move above the range. + */ + if (ctrl->tCK <= TCK_533MHZ) val = 2; + else if (ctrl->tCK <= TCK_333MHZ) val = 1; + else val = 0; + val ++; /* FIXME: vendor BIOS sets this to 3 */ + pci_mod_config8(MCU, 0x74, (0x03 << 1), ((val & 0x03) << 1) ); + + /* FIXME: The vendor BIOS increases the MD input delay - WHY ? */ + pci_mod_config8(MCU, 0xef, (3<<4), 3<<4); + + + /**** Write delay control ****/ + /* FIXME: The vendor BIOS does this, but WHY? + * Early DQ/DQS for write cycles */ + pci_mod_config8(MCU, 0x76, (3<<2), 2<<2); + /* FIXME: The vendor BIOS does this - Output preamble ?*/ + pci_write_config8(MCU, 0x77, 0x10); + + /* FIXME: Vendor BIOS goes in with + * 8 page registers + * multiple page mode + * High Priority Refresh request + * -- WHY?*/ + pci_write_config8(MCU, 0x69, 0xc7); + + /* Set BA[0/1/2] to [A17/18/19] */ + vx900_dram_set_ma_map(VX900_MRS_MA_MAP); + /* Disable Multiple Page Mode - Set Rx69[0] to 0 */ + pci_mod_config8(MCU, 0x69, (1<<0), 0x00); + + /* It's very important that we keep all ranks which are not calibrated + * mapped to VR3. Even if we disable them, if they are mapped to VR0 + * (the rank we use for calibrations), the calibrations may fail in + * unexpected ways. */ + vx900_pr_map_all_vr3(); + + for(i = 0; i < VX900_MAX_DIMM_SLOTS; i++) + { + /* Do we have a valid DIMM? */ + if(ranks->phys_rank_size[i] + ranks->phys_rank_size[i+1] == 0 ) + continue; + + /* Map the first rank of the DIMM to VR0 */ + vx900_map_pr_vr(2*i, 0); + + /* Run calibrations */ + if(0){ + /* If we run this if(0) block, everything else may fail + * putting a huge delay after this block sometimes fixes the + * issue. */ + vx900_rx_capture_range_calib(); + vx900_read_delay_range(&(delay_cal.rx_dq_cr), + VX900_CALIB_RxDQ_CR); + dump_delay_range(delay_cal.rx_dq_cr);} + + /*FIXME: Cheating with Rx CR setting + * We need to either use Rx CR calibration + * or set up a table for the calibration */ + dly[0] = 0x28; dly[1] = 0x1c; dly[2] = 0x28; dly[3] = 0x28; + dly[4] = 0x2c; dly[5] = 0x30; dly[6] = 0x30; dly[7] = 0x34; + printram("Bypassing RxCR 78-7f calibration with:\n"); + dump_delay(dly); + /* We need to put the setting on manual mode */ + pci_mod_config8(MCU, 0x71, 0, 0x10); + vx900_delay_calib_mode_select(VX900_CALIB_RxDQ_CR, VX900_CALIB_MANUAL); + vx900_write_0x78_0x7f(dly); + + /************* RxDQS *************/ + vx900_rx_dqs_delay_calib(); + vx900_read_delay_range(&(delay_cal.rx_dqs), VX900_CALIB_RxDQS); + printram("RX DQS calibration results\n"); + dump_delay_range(delay_cal.rx_dqs); + + vx900_rxdqs_adjust(&(delay_cal.rx_dqs)); + + vx900_read_delay_range(&(delay_cal.rx_dqs), VX900_CALIB_RxDQS); + printram("RX DQS calibration results after adjustment\n"); + dump_delay_range(delay_cal.rx_dqs); + + /* Enable multiple page mode */ + pci_mod_config8(MCU, 0x69, 0, 1<<1); + + /* FIXME: this is done by vendor BIOS, and recommended by VIA + * However, datasheet says that bit[7] is reserved, and + * calibration works just as well if we don't set this to 1b . + * Should we really do this, or can we drop it ? */ + if(ctrl->tCK <= TCK_533MHZ){ + for( i = 0; i< 8; i++) dly[i] = 0x80; + pci_mod_config8(MCU, 0x75, 0x00, 0x01); /* manual Tx DQ DQS */ + vx900_delay_calib_mode_select(VX900_CALIB_TxDQ, VX900_CALIB_MANUAL); + vx900_write_0x78_0x7f(dly); + vx900_delay_calib_mode_select(VX900_CALIB_TxDQS, VX900_CALIB_MANUAL); + vx900_write_0x78_0x7f(dly); + } + + /************* TxDQS *************/ + vx900_tx_dqs_delay_calib(); + + vx900_read_delay_range(&(delay_cal.tx_dqs), VX900_CALIB_TxDQS); + printram("Tx DQS calibration results\n"); + dump_delay_range(delay_cal.tx_dqs); + /************* TxDQ *************/ + /* FIXME: not sure if multiple page mode should be enabled here + * Vendor BIOS does it */ + pci_mod_config8(MCU, 0x69, 0 , 0x01); + + vx900_tx_dq_delay_calib(); + vx900_read_delay_range(&(delay_cal.tx_dq), VX900_CALIB_TxDQ); + printram("TX DQ delay calibration results:\n"); + dump_delay_range(delay_cal.tx_dq); + + /* write manual settings */ + pci_mod_config8(MCU, 0x75, 0, 0x01); + vx900_delay_calib_mode_select(VX900_CALIB_TxDQS, VX900_CALIB_MANUAL); + vx900_write_0x78_0x7f(delay_cal.tx_dqs.avg); + vx900_delay_calib_mode_select(VX900_CALIB_TxDQ, VX900_CALIB_MANUAL); + vx900_write_0x78_0x7f(delay_cal.tx_dq.avg); + } +} + +static void vx900_dram_set_refresh_counter(ramctr_timing *ctrl) +{ + u8 reg8; + /* Set DRAM refresh counter + * Based on a refresh counter of 0x61 at 400MHz */ + reg8 = (TCK_400MHZ * 0x61) / ctrl->tCK; + pci_write_config8(MCU, 0xc7, reg8); +} + +static void vx900_dram_range(ramctr_timing *ctrl, rank_layout *ranks) +{ + size_t i, vrank = 0; + u8 reg8; + u32 ramsize = 0; + /* All unused physical ranks go to VR3. Otherwise, the MCU might be + * trying to read or write from unused ranks, or even worse, write some + * bits to the rank we want, and some to the unused ranks, even though + * they are disabled. Since VR3 is the last virtual rank to be used, we + * eliminate any ambiguities that the MCU may face. */ + vx900_pr_map_all_vr3(); + for(i = 0; i < VX900_MAX_MEM_RANKS; i++) + { + u32 rank_size = ranks->phys_rank_size[i]; + if(!rank_size) continue; + ranks->virt[vrank].start_addr = ramsize; + ramsize += rank_size; + ranks->virt[vrank].end_addr = ramsize; + + /* Rank memory range */ + reg8 = (ranks->virt[vrank].start_addr >> 2); + pci_write_config8(MCU, 0x48 + vrank, reg8); + reg8 = (ranks->virt[vrank].end_addr >> 2); + pci_write_config8(MCU, 0x40 + vrank, reg8); + + vx900_map_pr_vr(i, vrank); + + printram("Mapped Physical rank %u, to virtual rank %u\n" + " Start address: 0x%.8x000000\n" + " End address: 0x%.8x000000\n", + (int) i, (int) vrank, + ranks->virt[vrank].start_addr, + ranks->virt[vrank].end_addr); + /* Move on to next virtual rank */ + vrank++; + } + + /* FIXME: What if our RAM overlaps the PCI config space? */ + /* We need to write the top low address to the MCU */ + u32 tolmk = ramsize * (RAM_UNIT >> 10); + u16 chip_tolm = (tolmk >> 6) & 0xfff0; + pci_mod_config16(MCU, 0x84, 0xfff0, chip_tolm); + + printram("Initialized %u virtual ranks, with a total size of %u MB\n", + (int) vrank, ramsize << 4); +} + +static void vx900_dram_write_final_config(ramctr_timing *ctrl) +{ + + /* FIXME: These are quick cheats */ + pci_write_config8(MCU, 0x50, 0xa0); /* DRAM MA map */ + vx900_dram_set_ma_map(VX900_CALIB_MA_MAP); /* Rank interleave */ + + pci_write_config8(MCU, 0x69, 0xe7); + //pci_write_config8(MCU, 0x72, 0x0f); + + //pci_write_config8(MCU, 0x97, 0xa4); /* self-refresh */ + //pci_write_config8(MCU, 0x98, 0xba); /* self-refresh II */ + //pci_write_config8(MCU, 0x9a, 0x80); /* self-refresh III */ + + /* Enable automatic triggering of short ZQ calibration */ + pci_write_config8(MCU, 0xc8, 0x80); +} + +static void print_debug_pci_dev(device_t dev) +{ + print_debug("PCI: "); + print_debug_hex8((dev >> 20) & 0xff); + print_debug_char(':'); + print_debug_hex8((dev >> 15) & 0x1f); + print_debug_char('.'); + print_debug_hex8((dev >> 12) & 7); +} + +static void dump_pci_device(device_t dev) +{ + int i; + print_debug_pci_dev(dev); + print_debug("\n"); + + for (i = 0; i <= 0xff; i++) { + unsigned char val; + if ((i & 0x0f) == 0) { + print_debug_hex8(i); + print_debug_char(':'); + } + + if ((i & 0x0f) == 0x08) { + print_debug(" |"); + } + + val = pci_read_config8(dev, i); + print_debug_char(' '); + print_debug_hex8(val); + + if ((i & 0x0f) == 0x0f) { + print_debug("\n"); + } + } +} + +void vx900_init_dram_ddr3(const dimm_layout *dimm_addr) +{ + dimm_info dimm_prop; + ramctr_timing ctrl_prop; + rank_layout ranks; + device_t mcu; + + if(!ram_check_noprint_nodie(1<<20, 1<<20)) { + printram("RAM is already initialized. Skipping init\n"); + return; + } + /* Locate the Memory controller */ + mcu = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VX900_MEMCTRL), 0); + + if (mcu == PCI_DEV_INVALID) { + die("Memory Controller not found\n"); + } + memset(&dimm_prop, 0, sizeof(dimm_prop)); + memset(&ctrl_prop, 0, sizeof(ctrl_prop)); + memset(&ranks, 0, sizeof(ranks)); + /* This isn't even a step - Keep GFX away from our unintialized RAM */ + //vx900_disable_gfx(); + /* 1) Write some initial "safe" parameters */ + vx900_dram_write_init_config(); + /* 2) Get timing information from SPDs */ + dram_find_spds_ddr3(dimm_addr, &dimm_prop); + /* 3) Find lowest common denominator for all modules */ + dram_find_common_params(&dimm_prop, &ctrl_prop); + /* 4) Find the size of each memory rank */ + vx900_dram_phys_bank_range(&dimm_prop, &ranks); + /* 5) Set DRAM driving strength */ + vx900_dram_driving_ctrl(&dimm_prop); + /* 6) Set DRAM frequency and latencies */ + vx900_dram_timing(&ctrl_prop); + vx900_dram_freq(&ctrl_prop); + /* 7) Initialize the modules themselves */ + vx900_dram_ddr3_dimm_init(&ctrl_prop, &ranks); + /* 8) Set refresh counter based on DRAM frequency */ + vx900_dram_set_refresh_counter(&ctrl_prop); + /* 9) Calibrate receive and transmit delays */ + vx900_dram_calibrate_delays(&ctrl_prop, &ranks); + /* 10) Enable Physical to Virtual Rank mapping */ + vx900_dram_range(&ctrl_prop, &ranks); + /* 99) Some final adjustments */ + vx900_dram_write_final_config(&ctrl_prop); + /* A0) What about our beloved GFX */ + //vx900_dram_set_gfx_resources(); + /* Take a dump */ + dump_pci_device(mcu); + +} diff --git a/src/northbridge/via/vx900/romstrap.inc b/src/northbridge/via/vx900/romstrap.inc new file mode 100644 index 0000000..2eb2de5 --- /dev/null +++ b/src/northbridge/via/vx900/romstrap.inc @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * (Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer) + * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * Copyright (C) 2009 One Laptop per Child, Association, Inc. + * Copyright (C) 2011-2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This file constructs the ROM strap table for VX900 */ + + .section ".romstrap", "a", @progbits + + .globl __romstrap_start +__romstrap_start: +tblpointer: + .long 0x77886047 + .long 0x00777777 + .long 0x00000000 + .long 0x00000000 + .long 0x00888888 + .long 0x00AA1111 + .long 0x00000000 + .long 0x00000000 + +/* + * The pointer to above table should be at 0xffffffd0, + * the table itself MUST be aligned to 128B it seems! + */ +rspointers: + .long tblpointer // It will be 0xffffffd0 + + .globl __romstrap_end + +__romstrap_end: +.previous diff --git a/src/northbridge/via/vx900/romstrap.lds b/src/northbridge/via/vx900/romstrap.lds new file mode 100644 index 0000000..fc63c05 --- /dev/null +++ b/src/northbridge/via/vx900/romstrap.lds @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * (Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD) + * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/> + */ + +SECTIONS { + . = (0x100000000 - 0x2c) - (__romstrap_end - __romstrap_start); + .romstrap (.): { + *(.romstrap) + } +} diff --git a/src/northbridge/via/vx900/traf_ctrl.c b/src/northbridge/via/vx900/traf_ctrl.c new file mode 100644 index 0000000..cc620cc --- /dev/null +++ b/src/northbridge/via/vx900/traf_ctrl.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <device/pci.h> +#include <device/pci_ids.h> + +static struct device_operations vga_operations = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = pci_dev_init, + .ops_pci = 0, +}; + +static const struct pci_driver vga_driver_900 __pci_driver = { + .ops = &vga_operations, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_VX900_TRAF, +}; \ No newline at end of file diff --git a/src/northbridge/via/vx900/vx900.h b/src/northbridge/via/vx900/vx900.h new file mode 100644 index 0000000..21a24b2 --- /dev/null +++ b/src/northbridge/via/vx900/vx900.h @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#define VX900_ACPI_IO_BASE 0x0400 + +#define VX900_NB_IOAPIC_ID 0x2 +#define VX900_NB_IOAPIC_BASE 0xfecc000 + +#define VX900_SB_IOAPIC_ID 0x1 +#define VX900_SB_IOAPIC_BASE 0xfec0000 + +#define SMBUS_IO_BASE 0x500 + +/* The maximum number of DIMM slots that the VX900 supports */ +#define VX900_MAX_DIMM_SLOTS 2 +#define VX900_MAX_MEM_RANKS 4 + +#define min(a,b) a<b?a:b +#define max(a,b) a>b?a:b + +#ifndef __PRE_RAM__ + +#include <arch/io.h> +#include <device/pci.h> + +/* We use these throughout the code. They really belong in a generic part of + * coreboot, but until beuraucracy gets them there, we still need them */ +static inline __attribute__((always_inline)) +void pci_mod_config8(device_t dev, unsigned int where, + uint8_t clr_mask, uint8_t set_mask) +{ + uint8_t reg8 = pci_read_config8(dev, where); + reg8 &= ~clr_mask; + reg8 |= set_mask; + pci_write_config8(dev, where, reg8); +} +static inline __attribute__((always_inline)) +void pci_mod_config16(device_t dev, unsigned int where, + uint16_t clr_mask, uint16_t set_mask) +{ + uint16_t reg16 = pci_read_config16(dev, where); + reg16 &= ~clr_mask; + reg16 |= set_mask; + pci_write_config16(dev, where, reg16); +} +static inline __attribute__((always_inline)) +void pci_mod_config32(device_t dev, unsigned int where, + uint32_t clr_mask, uint32_t set_mask) +{ + uint32_t reg32 = pci_read_config32(dev, where); + reg32 &= ~clr_mask; + reg32 |= set_mask; + pci_write_config32(dev, where, reg32); +} + +u32 chrome9hd_fb_size(void); + +#endif /* __PRE_RAM__ */ \ No newline at end of file

1 0

New patch to review for coreboot: ff1292b Fix SMBIOS generation
by Stefan Reinauer 08 Aug '12

08 Aug '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1421 -gerrit commit ff1292bfbf725f05d4dc4915f536aea8a5487021 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Aug 7 14:50:47 2012 -0700 Fix SMBIOS generation Dropping mainboard's chip.h broke execution of the mainboard's enable function and the addition of mainboard specific smbios tables. The former was fixed by Kyosti in http://review.coreboot.org/1374 This patch fixes the breakage in static.c and also backs out a small portion of Kyosti's patch (because it's not needed anymore) Change-Id: I6fdea9cbb8c6041663bd36f68f1cae4b435c1f9b Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/devices/device.c | 4 ++-- src/include/device/device.h | 1 - util/sconfig/main.c | 4 ++++ 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/src/devices/device.c b/src/devices/device.c index 344f824..6b1902d 100644 --- a/src/devices/device.c +++ b/src/devices/device.c @@ -923,8 +923,8 @@ void dev_enumerate(void) printk(BIOS_SPEW, "Compare with tree...\n"); show_devs_tree(root, BIOS_SPEW, 0, 0); - if (mainboard_ops.enable_dev) - mainboard_ops.enable_dev(root); + if (root->chip_ops && root->chip_ops->enable_dev) + root->chip_ops->enable_dev(root); if (!root->ops || !root->ops->scan_bus) { printk(BIOS_ERR, "dev_root missing scan_bus operation"); diff --git a/src/include/device/device.h b/src/include/device/device.h index b44a551..cd9221d 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -171,7 +171,6 @@ void show_all_devs_resources(int debug_level, const char* msg); #define DEVICE_MEM_ALIGN 4096 extern struct device_operations default_dev_ops_root; -extern struct chip_operations mainboard_ops; void pci_domain_read_resources(struct device *dev); unsigned int pci_domain_scan_bus(struct device *dev, unsigned int max); unsigned int scan_static_bus(device_t bus, unsigned int max); diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 82a7491..b404d66 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -423,6 +423,8 @@ static void pass1(FILE *fil, struct device *ptr) fprintf(fil, "\t.chip_ops = &%s_ops,\n", ptr->chip->name_underscore); fprintf(fil, "#endif\n"); fprintf(fil, "\t.chip_info = &%s_info_%d,\n", ptr->chip->name_underscore, ptr->chip->id); + } else if (ptr->chip->chip == &mainboard) { + fprintf(fil, "\t.chip_ops = &%s_ops,\n", ptr->chip->name_underscore); } if (ptr->nextdev) fprintf(fil, "\t.next=&%s\n", ptr->nextdev->name); @@ -628,6 +630,8 @@ int main(int argc, char** argv) { "ROMSTAGE_CONST struct device * ROMSTAGE_CONST last_dev = &%s;\n", lastdev->name); #ifdef MAINBOARDS_HAVE_CHIP_H fprintf(autogen, "static ROMSTAGE_CONST struct mainboard_config ROMSTAGE_CONST mainboard_info_0;\n"); +#else + fprintf(autogen, "extern struct chip_operations mainboard_ops;\n"); #endif walk_device_tree(autogen, &root, pass1, NULL);

1 0

New patch to review for coreboot: 8bf93e4 Revert "Drop mainboard chip.h"
by Stefan Reinauer 07 Aug '12

07 Aug '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1420 -gerrit commit 8bf93e4c4cb2458a046fdd94ecb3a85c30b2c590 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Aug 7 22:12:09 2012 +0200 Revert "Drop mainboard chip.h" This reverts commit 188e3c2ff06a82f61d7d71e610b32b1a250c0a45 There is more stuff broken, hence reverting this one. --- src/mainboard/a-trend/atc-6220/chip.h | 22 +++++++++++++++ src/mainboard/a-trend/atc-6220/mainboard.c | 1 + src/mainboard/a-trend/atc-6240/chip.h | 22 +++++++++++++++ src/mainboard/a-trend/atc-6240/mainboard.c | 1 + src/mainboard/aaeon/pfm-540i_revb/chip.h | 23 +++++++++++++++ src/mainboard/aaeon/pfm-540i_revb/mainboard.c | 1 + src/mainboard/abit/be6-ii_v2_0/chip.h | 22 +++++++++++++++ src/mainboard/abit/be6-ii_v2_0/mainboard.c | 1 + src/mainboard/advansus/a785e-i/chip.h | 22 +++++++++++++++ src/mainboard/advansus/a785e-i/mainboard.c | 5 +++ src/mainboard/advantech/pcm-5820/chip.h | 22 +++++++++++++++ src/mainboard/advantech/pcm-5820/mainboard.c | 1 + src/mainboard/amd/bimini_fam10/chip.h | 22 +++++++++++++++ src/mainboard/amd/bimini_fam10/mainboard.c | 5 +++ src/mainboard/amd/db800/chip.h | 23 +++++++++++++++ src/mainboard/amd/db800/mainboard.c | 1 + src/mainboard/amd/dbm690t/chip.h | 21 ++++++++++++++ src/mainboard/amd/dbm690t/mainboard.c | 1 + src/mainboard/amd/dinar/chip.h | 23 +++++++++++++++ src/mainboard/amd/dinar/mainboard.c | 1 + src/mainboard/amd/inagua/chip.h | 23 +++++++++++++++ src/mainboard/amd/inagua/mainboard.c | 1 + src/mainboard/amd/mahogany/chip.h | 21 ++++++++++++++ src/mainboard/amd/mahogany/mainboard.c | 1 + src/mainboard/amd/mahogany_fam10/chip.h | 23 +++++++++++++++ src/mainboard/amd/mahogany_fam10/mainboard.c | 1 + src/mainboard/amd/norwich/chip.h | 23 +++++++++++++++ src/mainboard/amd/norwich/mainboard.c | 1 + src/mainboard/amd/parmer/chip.h | 22 +++++++++++++++ src/mainboard/amd/parmer/mainboard.c | 1 + src/mainboard/amd/persimmon/chip.h | 23 +++++++++++++++ src/mainboard/amd/persimmon/mainboard.c | 1 + src/mainboard/amd/pistachio/chip.h | 23 +++++++++++++++ src/mainboard/amd/pistachio/mainboard.c | 1 + src/mainboard/amd/rumba/chip.h | 5 +++ src/mainboard/amd/rumba/mainboard.c | 8 ++++- src/mainboard/amd/serengeti_cheetah/chip.h | 3 ++ src/mainboard/amd/serengeti_cheetah/mainboard.c | 1 + src/mainboard/amd/serengeti_cheetah_fam10/chip.h | 23 +++++++++++++++ .../amd/serengeti_cheetah_fam10/mainboard.c | 1 + src/mainboard/amd/south_station/chip.h | 23 +++++++++++++++ src/mainboard/amd/south_station/mainboard.c | 1 + src/mainboard/amd/tilapia_fam10/chip.h | 23 +++++++++++++++ src/mainboard/amd/tilapia_fam10/mainboard.c | 1 + src/mainboard/amd/torpedo/chip.h | 23 +++++++++++++++ src/mainboard/amd/torpedo/mainboard.c | 1 + src/mainboard/amd/union_station/chip.h | 23 +++++++++++++++ src/mainboard/amd/union_station/mainboard.c | 1 + src/mainboard/aopen/dxplplusu/chip.h | 4 +++ src/mainboard/aopen/dxplplusu/mainboard.c | 1 + src/mainboard/arima/hdama/chip.h | 3 ++ src/mainboard/arima/hdama/mainboard.c | 1 + src/mainboard/artecgroup/dbe61/chip.h | 3 ++ src/mainboard/artecgroup/dbe61/mainboard.c | 1 + src/mainboard/asi/mb_5blgp/chip.h | 22 +++++++++++++++ src/mainboard/asi/mb_5blgp/mainboard.c | 1 + src/mainboard/asi/mb_5blmp/chip.h | 23 +++++++++++++++ src/mainboard/asi/mb_5blmp/mainboard.c | 1 + src/mainboard/asrock/939a785gmh/chip.h | 23 +++++++++++++++ src/mainboard/asrock/939a785gmh/mainboard.c | 1 + src/mainboard/asrock/e350m1/chip.h | 23 +++++++++++++++ src/mainboard/asrock/e350m1/mainboard.c | 1 + src/mainboard/asus/a8n_e/chip.h | 24 ++++++++++++++++ src/mainboard/asus/a8n_e/mainboard.c | 1 + src/mainboard/asus/a8v-e_deluxe/chip.h | 22 +++++++++++++++ src/mainboard/asus/a8v-e_deluxe/mainboard.c | 1 + src/mainboard/asus/a8v-e_se/chip.h | 22 +++++++++++++++ src/mainboard/asus/a8v-e_se/mainboard.c | 1 + src/mainboard/asus/dsbf/chip.h | 21 ++++++++++++++ src/mainboard/asus/dsbf/mainboard.c | 1 + src/mainboard/asus/k8v-x/chip.h | 22 +++++++++++++++ src/mainboard/asus/k8v-x/mainboard.c | 1 + src/mainboard/asus/m2n-e/chip.h | 23 +++++++++++++++ src/mainboard/asus/m2n-e/mainboard.c | 1 + src/mainboard/asus/m2v-mx_se/chip.h | 22 +++++++++++++++ src/mainboard/asus/m2v-mx_se/mainboard.c | 1 + src/mainboard/asus/m2v/chip.h | 22 +++++++++++++++ src/mainboard/asus/m2v/mainboard.c | 1 + src/mainboard/asus/m4a78-em/chip.h | 23 +++++++++++++++ src/mainboard/asus/m4a78-em/mainboard.c | 1 + src/mainboard/asus/m4a785-m/chip.h | 23 +++++++++++++++ src/mainboard/asus/m4a785-m/mainboard.c | 1 + src/mainboard/asus/m4a785t-m/chip.h | 23 +++++++++++++++ src/mainboard/asus/m5a88-v/chip.h | 22 +++++++++++++++ src/mainboard/asus/m5a88-v/mainboard.c | 1 + src/mainboard/asus/mew-am/chip.h | 22 +++++++++++++++ src/mainboard/asus/mew-am/mainboard.c | 1 + src/mainboard/asus/mew-vm/chip.h | 3 ++ src/mainboard/asus/mew-vm/mainboard.c | 1 + src/mainboard/asus/p2b-d/chip.h | 22 +++++++++++++++ src/mainboard/asus/p2b-d/mainboard.c | 1 + src/mainboard/asus/p2b-ds/chip.h | 22 +++++++++++++++ src/mainboard/asus/p2b-ds/mainboard.c | 1 + src/mainboard/asus/p2b-f/chip.h | 22 +++++++++++++++ src/mainboard/asus/p2b-f/mainboard.c | 1 + src/mainboard/asus/p2b-ls/chip.h | 22 +++++++++++++++ src/mainboard/asus/p2b-ls/mainboard.c | 1 + src/mainboard/asus/p2b/chip.h | 22 +++++++++++++++ src/mainboard/asus/p2b/mainboard.c | 1 + src/mainboard/asus/p3b-f/chip.h | 22 +++++++++++++++ src/mainboard/asus/p3b-f/mainboard.c | 1 + src/mainboard/avalue/eax-785e/chip.h | 22 +++++++++++++++ src/mainboard/avalue/eax-785e/mainboard.c | 5 +++ src/mainboard/axus/tc320/chip.h | 22 +++++++++++++++ src/mainboard/axus/tc320/mainboard.c | 1 + src/mainboard/azza/pt-6ibd/chip.h | 22 +++++++++++++++ src/mainboard/azza/pt-6ibd/mainboard.c | 1 + src/mainboard/bachmann/ot200/chip.h | 23 +++++++++++++++ src/mainboard/bcom/winnet100/chip.h | 23 +++++++++++++++ src/mainboard/bcom/winnet100/mainboard.c | 1 + src/mainboard/bcom/winnetp680/chip.h | 24 ++++++++++++++++ src/mainboard/bcom/winnetp680/mainboard.c | 1 + src/mainboard/bifferos/bifferboard/chip.h | 23 +++++++++++++++ src/mainboard/bifferos/bifferboard/mainboard.c | 1 + src/mainboard/biostar/m6tba/chip.h | 22 +++++++++++++++ src/mainboard/biostar/m6tba/mainboard.c | 1 + src/mainboard/broadcom/blast/chip.h | 3 ++ src/mainboard/broadcom/blast/mainboard.c | 1 + src/mainboard/compaq/deskpro_en_sff_p600/chip.h | 22 +++++++++++++++ .../compaq/deskpro_en_sff_p600/mainboard.c | 1 + src/mainboard/digitallogic/adl855pc/chip.h | 3 ++ src/mainboard/digitallogic/adl855pc/mainboard.c | 1 + src/mainboard/digitallogic/msm586seg/chip.h | 3 ++ src/mainboard/digitallogic/msm586seg/mainboard.c | 1 + src/mainboard/digitallogic/msm800sev/chip.h | 3 ++ src/mainboard/digitallogic/msm800sev/mainboard.c | 1 + src/mainboard/eaglelion/5bcm/chip.h | 3 ++ src/mainboard/eaglelion/5bcm/mainboard.c | 1 + src/mainboard/ecs/p6iwp-fe/chip.h | 22 +++++++++++++++ src/mainboard/ecs/p6iwp-fe/mainboard.c | 1 + src/mainboard/emulation/qemu-x86/mainboard.c | 1 + src/mainboard/getac/p470/chip.h | 23 +++++++++++++++ src/mainboard/getac/p470/mainboard.c | 1 + src/mainboard/gigabyte/ga-6bxc/chip.h | 22 +++++++++++++++ src/mainboard/gigabyte/ga-6bxc/mainboard.c | 1 + src/mainboard/gigabyte/ga-6bxe/chip.h | 22 +++++++++++++++ src/mainboard/gigabyte/ga-6bxe/mainboard.c | 1 + src/mainboard/gigabyte/ga_2761gxdk/chip.h | 24 ++++++++++++++++ src/mainboard/gigabyte/ga_2761gxdk/mainboard.c | 1 + src/mainboard/gigabyte/m57sli/chip.h | 24 ++++++++++++++++ src/mainboard/gigabyte/m57sli/mainboard.c | 1 + src/mainboard/gigabyte/ma785gm/chip.h | 23 +++++++++++++++ src/mainboard/gigabyte/ma785gm/mainboard.c | 1 + src/mainboard/gigabyte/ma785gmt/chip.h | 23 +++++++++++++++ src/mainboard/gigabyte/ma785gmt/mainboard.c | 1 + src/mainboard/gigabyte/ma78gm/chip.h | 23 +++++++++++++++ src/mainboard/gigabyte/ma78gm/mainboard.c | 1 + src/mainboard/hp/dl145_g1/chip.h | 3 ++ src/mainboard/hp/dl145_g1/mainboard.c | 1 + src/mainboard/hp/dl145_g3/chip.h | 24 ++++++++++++++++ src/mainboard/hp/dl145_g3/mainboard.c | 1 + src/mainboard/hp/dl165_g6_fam10/chip.h | 26 +++++++++++++++++ src/mainboard/hp/dl165_g6_fam10/mainboard.c | 1 + src/mainboard/hp/e_vectra_p2706t/chip.h | 23 +++++++++++++++ src/mainboard/hp/e_vectra_p2706t/mainboard.c | 1 + src/mainboard/ibase/mb899/chip.h | 21 ++++++++++++++ src/mainboard/ibase/mb899/mainboard.c | 1 + src/mainboard/ibm/e325/chip.h | 3 ++ src/mainboard/ibm/e325/mainboard.c | 1 + src/mainboard/ibm/e326/chip.h | 3 ++ src/mainboard/ibm/e326/mainboard.c | 1 + src/mainboard/iei/juki-511p/chip.h | 23 +++++++++++++++ src/mainboard/iei/juki-511p/mainboard.c | 1 + src/mainboard/iei/kino-780am2-fam10/chip.h | 23 +++++++++++++++ src/mainboard/iei/kino-780am2-fam10/mainboard.c | 1 + src/mainboard/iei/nova4899r/chip.h | 23 +++++++++++++++ src/mainboard/iei/nova4899r/mainboard.c | 1 + src/mainboard/iei/pcisa-lx-800-r10/chip.h | 23 +++++++++++++++ src/mainboard/iei/pm-lx-800-r11/chip.h | 23 +++++++++++++++ src/mainboard/intel/d810e2cb/chip.h | 21 ++++++++++++++ src/mainboard/intel/d810e2cb/mainboard.c | 1 + src/mainboard/intel/d945gclf/chip.h | 21 ++++++++++++++ src/mainboard/intel/d945gclf/mainboard.c | 1 + src/mainboard/intel/eagleheights/chip.h | 22 +++++++++++++++ src/mainboard/intel/eagleheights/mainboard.c | 1 + src/mainboard/intel/emeraldlake2/chip.h | 21 ++++++++++++++ src/mainboard/intel/emeraldlake2/mainboard.c | 1 + src/mainboard/intel/jarrell/chip.h | 3 ++ src/mainboard/intel/jarrell/mainboard.c | 1 + src/mainboard/intel/mtarvon/chip.h | 22 +++++++++++++++ src/mainboard/intel/mtarvon/mainboard.c | 1 + src/mainboard/intel/truxton/chip.h | 22 +++++++++++++++ src/mainboard/intel/truxton/mainboard.c | 1 + src/mainboard/intel/xe7501devkit/chip.h | 3 ++ src/mainboard/intel/xe7501devkit/mainboard.c | 1 + src/mainboard/iwave/iWRainbowG6/chip.h | 21 ++++++++++++++ src/mainboard/iwave/iWRainbowG6/mainboard.c | 1 + src/mainboard/iwill/dk8_htx/chip.h | 3 ++ src/mainboard/iwill/dk8_htx/mainboard.c | 1 + src/mainboard/iwill/dk8s2/chip.h | 3 ++ src/mainboard/iwill/dk8s2/mainboard.c | 1 + src/mainboard/iwill/dk8x/chip.h | 3 ++ src/mainboard/iwill/dk8x/mainboard.c | 1 + src/mainboard/jetway/j7f24/chip.h | 24 ++++++++++++++++ src/mainboard/jetway/j7f24/mainboard.c | 1 + src/mainboard/jetway/pa78vm5/chip.h | 24 ++++++++++++++++ src/mainboard/jetway/pa78vm5/mainboard.c | 1 + src/mainboard/kontron/986lcd-m/chip.h | 21 ++++++++++++++ src/mainboard/kontron/986lcd-m/mainboard.c | 1 + src/mainboard/kontron/kt690/chip.h | 23 +++++++++++++++ src/mainboard/kontron/kt690/mainboard.c | 1 + src/mainboard/lanner/em8510/chip.h | 23 +++++++++++++++ src/mainboard/lanner/em8510/mainboard.c | 1 + src/mainboard/lenovo/t60/chip.h | 21 ++++++++++++++ src/mainboard/lenovo/t60/mainboard.c | 1 + src/mainboard/lenovo/x60/chip.h | 21 ++++++++++++++ src/mainboard/lenovo/x60/mainboard.c | 1 + src/mainboard/lippert/frontrunner/chip.h | 3 ++ src/mainboard/lippert/frontrunner/mainboard.c | 1 + src/mainboard/lippert/hurricane-lx/chip.h | 23 +++++++++++++++ src/mainboard/lippert/hurricane-lx/mainboard.c | 1 + src/mainboard/lippert/literunner-lx/chip.h | 23 +++++++++++++++ src/mainboard/lippert/literunner-lx/mainboard.c | 1 + src/mainboard/lippert/roadrunner-lx/chip.h | 23 +++++++++++++++ src/mainboard/lippert/roadrunner-lx/mainboard.c | 1 + src/mainboard/lippert/spacerunner-lx/chip.h | 23 +++++++++++++++ src/mainboard/lippert/spacerunner-lx/mainboard.c | 1 + src/mainboard/mitac/6513wu/chip.h | 22 +++++++++++++++ src/mainboard/mitac/6513wu/mainboard.c | 1 + src/mainboard/msi/ms6119/chip.h | 22 +++++++++++++++ src/mainboard/msi/ms6119/mainboard.c | 1 + src/mainboard/msi/ms6147/chip.h | 22 +++++++++++++++ src/mainboard/msi/ms6147/mainboard.c | 1 + src/mainboard/msi/ms6156/chip.h | 22 +++++++++++++++ src/mainboard/msi/ms6156/mainboard.c | 1 + src/mainboard/msi/ms6178/chip.h | 23 +++++++++++++++ src/mainboard/msi/ms6178/mainboard.c | 1 + src/mainboard/msi/ms7135/chip.h | 23 +++++++++++++++ src/mainboard/msi/ms7135/mainboard.c | 1 + src/mainboard/msi/ms7260/chip.h | 23 +++++++++++++++ src/mainboard/msi/ms7260/mainboard.c | 1 + src/mainboard/msi/ms9185/chip.h | 25 +++++++++++++++++ src/mainboard/msi/ms9185/mainboard.c | 1 + src/mainboard/msi/ms9282/chip.h | 24 ++++++++++++++++ src/mainboard/msi/ms9282/mainboard.c | 1 + src/mainboard/msi/ms9652_fam10/chip.h | 24 ++++++++++++++++ src/mainboard/msi/ms9652_fam10/mainboard.c | 1 + src/mainboard/nec/powermate2000/chip.h | 23 +++++++++++++++ src/mainboard/nec/powermate2000/mainboard.c | 1 + src/mainboard/newisys/khepri/chip.h | 3 ++ src/mainboard/newisys/khepri/mainboard.c | 1 + src/mainboard/nokia/ip530/chip.h | 22 +++++++++++++++ src/mainboard/nokia/ip530/mainboard.c | 1 + src/mainboard/nvidia/l1_2pvv/chip.h | 24 ++++++++++++++++ src/mainboard/nvidia/l1_2pvv/mainboard.c | 1 + src/mainboard/pcengines/alix1c/chip.h | 22 +++++++++++++++ src/mainboard/pcengines/alix1c/mainboard.c | 1 + src/mainboard/pcengines/alix2d/chip.h | 22 +++++++++++++++ src/mainboard/pcengines/alix2d/mainboard.c | 1 + src/mainboard/rca/rm4100/chip.h | 23 +++++++++++++++ src/mainboard/rca/rm4100/mainboard.c | 1 + src/mainboard/roda/rk886ex/chip.h | 21 ++++++++++++++ src/mainboard/roda/rk886ex/mainboard.c | 1 + src/mainboard/samsung/lumpy/chip.h | 21 ++++++++++++++ src/mainboard/samsung/lumpy/mainboard.c | 1 + src/mainboard/samsung/stumpy/chip.h | 21 ++++++++++++++ src/mainboard/samsung/stumpy/mainboard.c | 1 + src/mainboard/siemens/sitemp_g1p1/chip.h | 29 ++++++++++++++++++++ src/mainboard/siemens/sitemp_g1p1/mainboard.c | 16 +++++----- src/mainboard/soyo/sy-6ba-plus-iii/chip.h | 22 +++++++++++++++ src/mainboard/soyo/sy-6ba-plus-iii/mainboard.c | 1 + src/mainboard/sunw/ultra40/chip.h | 3 ++ src/mainboard/sunw/ultra40/mainboard.c | 1 + src/mainboard/supermicro/h8dme/chip.h | 21 ++++++++++++++ src/mainboard/supermicro/h8dme/mainboard.c | 1 + src/mainboard/supermicro/h8dmr/chip.h | 24 ++++++++++++++++ src/mainboard/supermicro/h8dmr/mainboard.c | 1 + src/mainboard/supermicro/h8dmr_fam10/chip.h | 24 ++++++++++++++++ src/mainboard/supermicro/h8dmr_fam10/mainboard.c | 1 + src/mainboard/supermicro/h8qgi/chip.h | 23 +++++++++++++++ src/mainboard/supermicro/h8qgi/mainboard.c | 1 + src/mainboard/supermicro/h8qme_fam10/chip.h | 24 ++++++++++++++++ src/mainboard/supermicro/h8qme_fam10/mainboard.c | 1 + src/mainboard/supermicro/h8scm_fam10/chip.h | 23 +++++++++++++++ src/mainboard/supermicro/h8scm_fam10/mainboard.c | 5 +++ src/mainboard/supermicro/x6dai_g/chip.h | 3 ++ src/mainboard/supermicro/x6dai_g/mainboard.c | 1 + src/mainboard/supermicro/x6dhe_g/chip.h | 3 ++ src/mainboard/supermicro/x6dhe_g/mainboard.c | 1 + src/mainboard/supermicro/x6dhe_g2/chip.h | 3 ++ src/mainboard/supermicro/x6dhe_g2/mainboard.c | 1 + src/mainboard/supermicro/x6dhr_ig/chip.h | 3 ++ src/mainboard/supermicro/x6dhr_ig/mainboard.c | 1 + src/mainboard/supermicro/x6dhr_ig2/chip.h | 3 ++ src/mainboard/supermicro/x6dhr_ig2/mainboard.c | 1 + src/mainboard/supermicro/x7db8/chip.h | 21 ++++++++++++++ src/mainboard/supermicro/x7db8/mainboard.c | 1 + src/mainboard/technexion/tim5690/chip.h | 23 +++++++++++++++ src/mainboard/technexion/tim5690/mainboard.c | 1 + src/mainboard/technexion/tim8690/chip.h | 23 +++++++++++++++ src/mainboard/technexion/tim8690/mainboard.c | 1 + src/mainboard/technologic/ts5300/chip.h | 3 ++ src/mainboard/technologic/ts5300/mainboard.c | 1 + src/mainboard/televideo/tc7020/chip.h | 23 +++++++++++++++ src/mainboard/televideo/tc7020/mainboard.c | 1 + src/mainboard/thomson/ip1000/chip.h | 23 +++++++++++++++ src/mainboard/thomson/ip1000/mainboard.c | 1 + src/mainboard/traverse/geos/chip.h | 23 +++++++++++++++ src/mainboard/traverse/geos/mainboard.c | 1 + src/mainboard/tyan/s1846/chip.h | 22 +++++++++++++++ src/mainboard/tyan/s1846/mainboard.c | 1 + src/mainboard/tyan/s2735/chip.h | 3 ++ src/mainboard/tyan/s2735/mainboard.c | 1 + src/mainboard/tyan/s2850/chip.h | 3 ++ src/mainboard/tyan/s2850/mainboard.c | 1 + src/mainboard/tyan/s2875/chip.h | 3 ++ src/mainboard/tyan/s2875/mainboard.c | 1 + src/mainboard/tyan/s2880/chip.h | 3 ++ src/mainboard/tyan/s2880/mainboard.c | 1 + src/mainboard/tyan/s2881/chip.h | 3 ++ src/mainboard/tyan/s2881/mainboard.c | 1 + src/mainboard/tyan/s2882/chip.h | 3 ++ src/mainboard/tyan/s2882/mainboard.c | 1 + src/mainboard/tyan/s2885/chip.h | 3 ++ src/mainboard/tyan/s2885/mainboard.c | 1 + src/mainboard/tyan/s2891/chip.h | 3 ++ src/mainboard/tyan/s2891/mainboard.c | 1 + src/mainboard/tyan/s2892/chip.h | 3 ++ src/mainboard/tyan/s2892/mainboard.c | 1 + src/mainboard/tyan/s2895/chip.h | 3 ++ src/mainboard/tyan/s2895/mainboard.c | 1 + src/mainboard/tyan/s2912/chip.h | 24 ++++++++++++++++ src/mainboard/tyan/s2912/mainboard.c | 1 + src/mainboard/tyan/s2912_fam10/chip.h | 24 ++++++++++++++++ src/mainboard/tyan/s2912_fam10/mainboard.c | 1 + src/mainboard/tyan/s4880/chip.h | 3 ++ src/mainboard/tyan/s4880/mainboard.c | 1 + src/mainboard/tyan/s4882/chip.h | 3 ++ src/mainboard/tyan/s4882/mainboard.c | 1 + src/mainboard/via/epia-cn/chip.h | 24 ++++++++++++++++ src/mainboard/via/epia-cn/mainboard.c | 1 + src/mainboard/via/epia-m/chip.h | 3 ++ src/mainboard/via/epia-m/mainboard.c | 1 + src/mainboard/via/epia-m700/chip.h | 23 +++++++++++++++ src/mainboard/via/epia-m700/mainboard.c | 1 + src/mainboard/via/epia-n/chip.h | 24 ++++++++++++++++ src/mainboard/via/epia-n/mainboard.c | 1 + src/mainboard/via/epia/chip.h | 3 ++ src/mainboard/via/epia/mainboard.c | 1 + src/mainboard/via/pc2500e/chip.h | 23 +++++++++++++++ src/mainboard/via/pc2500e/mainboard.c | 1 + src/mainboard/via/vt8454c/chip.h | 22 +++++++++++++++ src/mainboard/via/vt8454c/mainboard.c | 1 + src/mainboard/winent/pl6064/chip.h | 23 +++++++++++++++ src/mainboard/winent/pl6064/mainboard.c | 1 + src/mainboard/wyse/s50/chip.h | 22 +++++++++++++++ src/mainboard/wyse/s50/mainboard.c | 1 + util/sconfig/main.c | 13 +------- 348 files changed, 3343 insertions(+), 21 deletions(-) diff --git a/src/mainboard/a-trend/atc-6220/chip.h b/src/mainboard/a-trend/atc-6220/chip.h new file mode 100644 index 0000000..dc9bed3 --- /dev/null +++ b/src/mainboard/a-trend/atc-6220/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/a-trend/atc-6220/mainboard.c b/src/mainboard/a-trend/atc-6220/mainboard.c index 26f18dd..f30ebfa 100644 --- a/src/mainboard/a-trend/atc-6220/mainboard.c +++ b/src/mainboard/a-trend/atc-6220/mainboard.c @@ -19,6 +19,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("A-Trend ATC-6220 Mainboard") diff --git a/src/mainboard/a-trend/atc-6240/chip.h b/src/mainboard/a-trend/atc-6240/chip.h new file mode 100644 index 0000000..56e17ca --- /dev/null +++ b/src/mainboard/a-trend/atc-6240/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/a-trend/atc-6240/mainboard.c b/src/mainboard/a-trend/atc-6240/mainboard.c index 13f6e3f..0e09ea3 100644 --- a/src/mainboard/a-trend/atc-6240/mainboard.c +++ b/src/mainboard/a-trend/atc-6240/mainboard.c @@ -19,6 +19,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("A-Trend ATC-6240 Mainboard") diff --git a/src/mainboard/aaeon/pfm-540i_revb/chip.h b/src/mainboard/aaeon/pfm-540i_revb/chip.h new file mode 100644 index 0000000..c8c54b0 --- /dev/null +++ b/src/mainboard/aaeon/pfm-540i_revb/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Mark Norman <mpnorman(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/aaeon/pfm-540i_revb/mainboard.c b/src/mainboard/aaeon/pfm-540i_revb/mainboard.c index 8f1412f..72e500c 100644 --- a/src/mainboard/aaeon/pfm-540i_revb/mainboard.c +++ b/src/mainboard/aaeon/pfm-540i_revb/mainboard.c @@ -19,6 +19,7 @@ #include <console/console.h> #include <device/device.h> +#include "chip.h" static void init(struct device *dev) { diff --git a/src/mainboard/abit/be6-ii_v2_0/chip.h b/src/mainboard/abit/be6-ii_v2_0/chip.h new file mode 100644 index 0000000..dc9bed3 --- /dev/null +++ b/src/mainboard/abit/be6-ii_v2_0/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/abit/be6-ii_v2_0/mainboard.c b/src/mainboard/abit/be6-ii_v2_0/mainboard.c index c70df95..6fc23ec 100644 --- a/src/mainboard/abit/be6-ii_v2_0/mainboard.c +++ b/src/mainboard/abit/be6-ii_v2_0/mainboard.c @@ -19,6 +19,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Abit BE6-II V2.0 Mainboard") diff --git a/src/mainboard/advansus/a785e-i/chip.h b/src/mainboard/advansus/a785e-i/chip.h new file mode 100644 index 0000000..5957589 --- /dev/null +++ b/src/mainboard/advansus/a785e-i/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/advansus/a785e-i/mainboard.c b/src/mainboard/advansus/a785e-i/mainboard.c index 6c190f0..d3530cf 100644 --- a/src/mainboard/advansus/a785e-i/mainboard.c +++ b/src/mainboard/advansus/a785e-i/mainboard.c @@ -26,6 +26,7 @@ #include <cpu/amd/mtrr.h> #include <device/pci_def.h> #include "SBPLATFORM.h" +#include "chip.h" u8 is_dev3_present(void); @@ -76,6 +77,10 @@ u8 is_dev3_present(void) *************************************************/ static void a785e_i_enable(device_t dev) { + /* Leave it for furture use. */ + /* struct mainboard_config *mainboard = + (struct mainboard_config *)dev->chip_info; */ + printk(BIOS_INFO, "Mainboard A785E-I Enable. dev=0x%p\n", dev); setup_uma_memory(); diff --git a/src/mainboard/advantech/pcm-5820/chip.h b/src/mainboard/advantech/pcm-5820/chip.h new file mode 100644 index 0000000..dc9bed3 --- /dev/null +++ b/src/mainboard/advantech/pcm-5820/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/advantech/pcm-5820/mainboard.c b/src/mainboard/advantech/pcm-5820/mainboard.c index 345c6f8..4256059 100644 --- a/src/mainboard/advantech/pcm-5820/mainboard.c +++ b/src/mainboard/advantech/pcm-5820/mainboard.c @@ -19,6 +19,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Advantech PCM-5820 Mainboard") diff --git a/src/mainboard/amd/bimini_fam10/chip.h b/src/mainboard/amd/bimini_fam10/chip.h new file mode 100644 index 0000000..2013516 --- /dev/null +++ b/src/mainboard/amd/bimini_fam10/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/amd/bimini_fam10/mainboard.c b/src/mainboard/amd/bimini_fam10/mainboard.c index f587ac1..e2706c5 100644 --- a/src/mainboard/amd/bimini_fam10/mainboard.c +++ b/src/mainboard/amd/bimini_fam10/mainboard.c @@ -26,6 +26,7 @@ #include <cpu/amd/mtrr.h> #include <device/pci_def.h> #include <southbridge/amd/sb800/sb800.h> +#include "chip.h" u8 is_dev3_present(void); @@ -126,6 +127,10 @@ static void get_ide_dma66(void) *************************************************/ static void bimini_enable(device_t dev) { + /* Leave it for furture use. */ + /* struct mainboard_config *mainboard = + (struct mainboard_config *)dev->chip_info; */ + printk(BIOS_INFO, "Mainboard BIMINI Enable. dev=0x%p\n", dev); setup_uma_memory(); diff --git a/src/mainboard/amd/db800/chip.h b/src/mainboard/amd/db800/chip.h new file mode 100644 index 0000000..ae69536 --- /dev/null +++ b/src/mainboard/amd/db800/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/amd/db800/mainboard.c b/src/mainboard/amd/db800/mainboard.c index e841d07..f95ea22 100644 --- a/src/mainboard/amd/db800/mainboard.c +++ b/src/mainboard/amd/db800/mainboard.c @@ -19,6 +19,7 @@ #include <console/console.h> #include <device/device.h> +#include "chip.h" static void init(struct device *dev) { diff --git a/src/mainboard/amd/dbm690t/chip.h b/src/mainboard/amd/dbm690t/chip.h new file mode 100644 index 0000000..9ee2dc8 --- /dev/null +++ b/src/mainboard/amd/dbm690t/chip.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/amd/dbm690t/mainboard.c b/src/mainboard/amd/dbm690t/mainboard.c index fbff55b..df79b34 100644 --- a/src/mainboard/amd/dbm690t/mainboard.c +++ b/src/mainboard/amd/dbm690t/mainboard.c @@ -26,6 +26,7 @@ #include <cpu/amd/mtrr.h> #include <device/pci_def.h> #include <southbridge/amd/sb600/sb600.h> +#include "chip.h" #define ADT7461_ADDRESS 0x4C #define ARA_ADDRESS 0x0C /* Alert Response Address */ diff --git a/src/mainboard/amd/dinar/chip.h b/src/mainboard/amd/dinar/chip.h new file mode 100644 index 0000000..42630fa --- /dev/null +++ b/src/mainboard/amd/dinar/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/amd/dinar/mainboard.c b/src/mainboard/amd/dinar/mainboard.c index 6301b4f..0d4015b 100644 --- a/src/mainboard/amd/dinar/mainboard.c +++ b/src/mainboard/amd/dinar/mainboard.c @@ -26,6 +26,7 @@ #include <cpu/amd/mtrr.h> #include <device/pci_def.h> #include <NbPlatform.h> +#include "chip.h" //#define SMBUS_IO_BASE 0x6000 diff --git a/src/mainboard/amd/inagua/chip.h b/src/mainboard/amd/inagua/chip.h new file mode 100644 index 0000000..a252705 --- /dev/null +++ b/src/mainboard/amd/inagua/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c index dc83258..5291165 100644 --- a/src/mainboard/amd/inagua/mainboard.c +++ b/src/mainboard/amd/inagua/mainboard.c @@ -27,6 +27,7 @@ #include <device/pci_def.h> //#include <southbridge/amd/sb800/sb800.h> #include "SBPLATFORM.h" /* Platfrom Specific Definitions */ +#include "chip.h" void set_pcie_reset(void); void set_pcie_dereset(void); diff --git a/src/mainboard/amd/mahogany/chip.h b/src/mainboard/amd/mahogany/chip.h new file mode 100644 index 0000000..42664d0 --- /dev/null +++ b/src/mainboard/amd/mahogany/chip.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/amd/mahogany/mainboard.c b/src/mainboard/amd/mahogany/mainboard.c index 43ea66f..46ce2d2 100644 --- a/src/mainboard/amd/mahogany/mainboard.c +++ b/src/mainboard/amd/mahogany/mainboard.c @@ -27,6 +27,7 @@ #include <device/pci_def.h> #include "southbridge/amd/sb700/sb700.h" #include "southbridge/amd/sb700/smbus.h" +#include "chip.h" void set_pcie_dereset(void); void set_pcie_reset(void); diff --git a/src/mainboard/amd/mahogany_fam10/chip.h b/src/mainboard/amd/mahogany_fam10/chip.h new file mode 100644 index 0000000..a98b97e --- /dev/null +++ b/src/mainboard/amd/mahogany_fam10/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/amd/mahogany_fam10/mainboard.c b/src/mainboard/amd/mahogany_fam10/mainboard.c index b47cdff..6245e5f 100644 --- a/src/mainboard/amd/mahogany_fam10/mainboard.c +++ b/src/mainboard/amd/mahogany_fam10/mainboard.c @@ -27,6 +27,7 @@ #include <device/pci_def.h> #include "southbridge/amd/sb700/sb700.h" #include "southbridge/amd/sb700/smbus.h" +#include "chip.h" void set_pcie_dereset(void); void set_pcie_reset(void); diff --git a/src/mainboard/amd/norwich/chip.h b/src/mainboard/amd/norwich/chip.h new file mode 100644 index 0000000..ae69536 --- /dev/null +++ b/src/mainboard/amd/norwich/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/amd/norwich/mainboard.c b/src/mainboard/amd/norwich/mainboard.c index c735abb..0814a16 100644 --- a/src/mainboard/amd/norwich/mainboard.c +++ b/src/mainboard/amd/norwich/mainboard.c @@ -19,6 +19,7 @@ #include <console/console.h> #include <device/device.h> +#include "chip.h" static void init(struct device *dev) { diff --git a/src/mainboard/amd/parmer/chip.h b/src/mainboard/amd/parmer/chip.h new file mode 100644 index 0000000..352a6ff --- /dev/null +++ b/src/mainboard/amd/parmer/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/amd/parmer/mainboard.c b/src/mainboard/amd/parmer/mainboard.c index dae70c1..bf04d30 100644 --- a/src/mainboard/amd/parmer/mainboard.c +++ b/src/mainboard/amd/parmer/mainboard.c @@ -28,6 +28,7 @@ #include <arch/acpi.h> #include "BiosCallOuts.h" #include <cpu/amd/agesa/s3_resume.h> +#include "chip.h" #include "agesawrapper.h" /************************************************* diff --git a/src/mainboard/amd/persimmon/chip.h b/src/mainboard/amd/persimmon/chip.h new file mode 100644 index 0000000..a252705 --- /dev/null +++ b/src/mainboard/amd/persimmon/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c index aa3bc1b..86172ba 100644 --- a/src/mainboard/amd/persimmon/mainboard.c +++ b/src/mainboard/amd/persimmon/mainboard.c @@ -26,6 +26,7 @@ #include <device/pci_def.h> #include <southbridge/amd/sb800/sb800.h> #include <arch/acpi.h> +#include "chip.h" #include "BiosCallOuts.h" #include <cpu/amd/agesa/s3_resume.h> #include <cpu/amd/mtrr.h> diff --git a/src/mainboard/amd/pistachio/chip.h b/src/mainboard/amd/pistachio/chip.h new file mode 100644 index 0000000..05e1582 --- /dev/null +++ b/src/mainboard/amd/pistachio/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; + diff --git a/src/mainboard/amd/pistachio/mainboard.c b/src/mainboard/amd/pistachio/mainboard.c index 1355c37..4cd1c94 100644 --- a/src/mainboard/amd/pistachio/mainboard.c +++ b/src/mainboard/amd/pistachio/mainboard.c @@ -26,6 +26,7 @@ #include <cpu/amd/mtrr.h> #include <device/pci_def.h> #include <southbridge/amd/sb600/sb600.h> +#include "chip.h" #define ADT7475_ADDRESS 0x2E #define SMBUS_IO_BASE 0x1000 diff --git a/src/mainboard/amd/rumba/chip.h b/src/mainboard/amd/rumba/chip.h new file mode 100644 index 0000000..2094b23 --- /dev/null +++ b/src/mainboard/amd/rumba/chip.h @@ -0,0 +1,5 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config { + int nicirq; +}; diff --git a/src/mainboard/amd/rumba/mainboard.c b/src/mainboard/amd/rumba/mainboard.c index 42547cc..0e7bbb6 100644 --- a/src/mainboard/amd/rumba/mainboard.c +++ b/src/mainboard/amd/rumba/mainboard.c @@ -4,14 +4,18 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <arch/io.h> +#include "chip.h" -static void init(struct device *dev) -{ +static void init(struct device *dev) { + struct mainboard_config *mainboard = (struct mainboard_config*)dev->chip_info; device_t nic = NULL; unsigned bus = 0; unsigned devfn = PCI_DEVFN(0xd, 0); int nicirq = 1; + if (mainboard->nicirq) + nicirq = mainboard->nicirq; + printk(BIOS_DEBUG, "AMD RUMBA ENTER %s\n", __func__); if (nicirq) { diff --git a/src/mainboard/amd/serengeti_cheetah/chip.h b/src/mainboard/amd/serengeti_cheetah/chip.h new file mode 100644 index 0000000..d138e51 --- /dev/null +++ b/src/mainboard/amd/serengeti_cheetah/chip.h @@ -0,0 +1,3 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/amd/serengeti_cheetah/mainboard.c b/src/mainboard/amd/serengeti_cheetah/mainboard.c index a156f2e..4fb715f 100644 --- a/src/mainboard/amd/serengeti_cheetah/mainboard.c +++ b/src/mainboard/amd/serengeti_cheetah/mainboard.c @@ -1,4 +1,5 @@ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("AMD Serengeti Cheetah Mainboard") diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/chip.h b/src/mainboard/amd/serengeti_cheetah_fam10/chip.h new file mode 100644 index 0000000..df1a3eb --- /dev/null +++ b/src/mainboard/amd/serengeti_cheetah_fam10/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.c b/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.c index 9984bd6..ba1ee9c 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.c @@ -23,6 +23,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("AMD family 10 Cheetah mainboard") diff --git a/src/mainboard/amd/south_station/chip.h b/src/mainboard/amd/south_station/chip.h new file mode 100644 index 0000000..a252705 --- /dev/null +++ b/src/mainboard/amd/south_station/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c index 715b40a..3d5137c 100644 --- a/src/mainboard/amd/south_station/mainboard.c +++ b/src/mainboard/amd/south_station/mainboard.c @@ -26,6 +26,7 @@ #include <cpu/amd/mtrr.h> #include <device/pci_def.h> #include "SBPLATFORM.h" /* Platfrom Specific Definitions */ +#include "chip.h" void set_pcie_reset(void); diff --git a/src/mainboard/amd/tilapia_fam10/chip.h b/src/mainboard/amd/tilapia_fam10/chip.h new file mode 100644 index 0000000..a98b97e --- /dev/null +++ b/src/mainboard/amd/tilapia_fam10/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c index cf3e3d3..03735f4 100644 --- a/src/mainboard/amd/tilapia_fam10/mainboard.c +++ b/src/mainboard/amd/tilapia_fam10/mainboard.c @@ -27,6 +27,7 @@ #include <device/pci_def.h> #include <southbridge/amd/sb700/sb700.h> #include "southbridge/amd/sb700/smbus.h" +#include "chip.h" #define ADT7461_ADDRESS 0x4C #define ARA_ADDRESS 0x0C /* Alert Response Address */ diff --git a/src/mainboard/amd/torpedo/chip.h b/src/mainboard/amd/torpedo/chip.h new file mode 100644 index 0000000..a252705 --- /dev/null +++ b/src/mainboard/amd/torpedo/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/amd/torpedo/mainboard.c b/src/mainboard/amd/torpedo/mainboard.c index 839ec5c..29909b0 100644 --- a/src/mainboard/amd/torpedo/mainboard.c +++ b/src/mainboard/amd/torpedo/mainboard.c @@ -26,6 +26,7 @@ #include <cpu/amd/mtrr.h> #include <device/pci_def.h> //#include <southbridge/amd/sb900/sb900.h> +#include "chip.h" #define ONE_MB 0x100000 //#define SMBUS_IO_BASE 0x6000 diff --git a/src/mainboard/amd/union_station/chip.h b/src/mainboard/amd/union_station/chip.h new file mode 100644 index 0000000..a252705 --- /dev/null +++ b/src/mainboard/amd/union_station/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c index f0f610a..a08938c 100644 --- a/src/mainboard/amd/union_station/mainboard.c +++ b/src/mainboard/amd/union_station/mainboard.c @@ -26,6 +26,7 @@ #include <cpu/amd/mtrr.h> #include <device/pci_def.h> #include "SBPLATFORM.h" /* Platfrom Specific Definitions */ +#include "chip.h" void set_pcie_reset(void); void set_pcie_dereset(void); diff --git a/src/mainboard/aopen/dxplplusu/chip.h b/src/mainboard/aopen/dxplplusu/chip.h new file mode 100644 index 0000000..06f11d0 --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/chip.h @@ -0,0 +1,4 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config { +}; diff --git a/src/mainboard/aopen/dxplplusu/mainboard.c b/src/mainboard/aopen/dxplplusu/mainboard.c index 0688914..2d41509 100644 --- a/src/mainboard/aopen/dxplplusu/mainboard.c +++ b/src/mainboard/aopen/dxplplusu/mainboard.c @@ -1,4 +1,5 @@ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("AOpen DXPL Plus-U Mainboard") diff --git a/src/mainboard/arima/hdama/chip.h b/src/mainboard/arima/hdama/chip.h new file mode 100644 index 0000000..d138e51 --- /dev/null +++ b/src/mainboard/arima/hdama/chip.h @@ -0,0 +1,3 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/arima/hdama/mainboard.c b/src/mainboard/arima/hdama/mainboard.c index df658e2..688a01c 100644 --- a/src/mainboard/arima/hdama/mainboard.c +++ b/src/mainboard/arima/hdama/mainboard.c @@ -1,4 +1,5 @@ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Arima HDAMA Mainboard") diff --git a/src/mainboard/artecgroup/dbe61/chip.h b/src/mainboard/artecgroup/dbe61/chip.h new file mode 100644 index 0000000..d138e51 --- /dev/null +++ b/src/mainboard/artecgroup/dbe61/chip.h @@ -0,0 +1,3 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/artecgroup/dbe61/mainboard.c b/src/mainboard/artecgroup/dbe61/mainboard.c index 649f955..f49c215 100644 --- a/src/mainboard/artecgroup/dbe61/mainboard.c +++ b/src/mainboard/artecgroup/dbe61/mainboard.c @@ -26,6 +26,7 @@ #include <cpu/x86/msr.h> #include <cpu/amd/lxdef.h> #include "southbridge/amd/cs5536/cs5536.h" +#include "chip.h" static void init_gpio(void) { diff --git a/src/mainboard/asi/mb_5blgp/chip.h b/src/mainboard/asi/mb_5blgp/chip.h new file mode 100644 index 0000000..56e17ca --- /dev/null +++ b/src/mainboard/asi/mb_5blgp/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/asi/mb_5blgp/mainboard.c b/src/mainboard/asi/mb_5blgp/mainboard.c index 7a466bd..22bc52d 100644 --- a/src/mainboard/asi/mb_5blgp/mainboard.c +++ b/src/mainboard/asi/mb_5blgp/mainboard.c @@ -19,6 +19,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("ASI MB-5BLGP Mainboard") diff --git a/src/mainboard/asi/mb_5blmp/chip.h b/src/mainboard/asi/mb_5blmp/chip.h new file mode 100644 index 0000000..982cfb3 --- /dev/null +++ b/src/mainboard/asi/mb_5blmp/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/asi/mb_5blmp/mainboard.c b/src/mainboard/asi/mb_5blmp/mainboard.c index 9aaf14d..78366ba 100644 --- a/src/mainboard/asi/mb_5blmp/mainboard.c +++ b/src/mainboard/asi/mb_5blmp/mainboard.c @@ -19,6 +19,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("ASI/BCom MB-5BLMP Mainboard") diff --git a/src/mainboard/asrock/939a785gmh/chip.h b/src/mainboard/asrock/939a785gmh/chip.h new file mode 100644 index 0000000..be42783 --- /dev/null +++ b/src/mainboard/asrock/939a785gmh/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; + diff --git a/src/mainboard/asrock/939a785gmh/mainboard.c b/src/mainboard/asrock/939a785gmh/mainboard.c index d3ea27e..ec050cb 100644 --- a/src/mainboard/asrock/939a785gmh/mainboard.c +++ b/src/mainboard/asrock/939a785gmh/mainboard.c @@ -27,6 +27,7 @@ #include <device/pci_def.h> #include "southbridge/amd/sb700/sb700.h" #include "southbridge/amd/sb700/smbus.h" +#include "chip.h" void set_pcie_dereset(void); void set_pcie_reset(void); diff --git a/src/mainboard/asrock/e350m1/chip.h b/src/mainboard/asrock/e350m1/chip.h new file mode 100644 index 0000000..a252705 --- /dev/null +++ b/src/mainboard/asrock/e350m1/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c index d0151be..5859ae4 100644 --- a/src/mainboard/asrock/e350m1/mainboard.c +++ b/src/mainboard/asrock/e350m1/mainboard.c @@ -26,6 +26,7 @@ #include <cpu/amd/mtrr.h> #include <device/pci_def.h> //#include <southbridge/amd/sb800/sb800.h> +#include "chip.h" //#define SMBUS_IO_BASE 0x6000 diff --git a/src/mainboard/asus/a8n_e/chip.h b/src/mainboard/asus/a8n_e/chip.h new file mode 100644 index 0000000..1b910e6 --- /dev/null +++ b/src/mainboard/asus/a8n_e/chip.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Philipp Degler <pdegler(a)rumms.uni-mannheim.de> + * (Thanks to LSRA University of Mannheim for their support) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/asus/a8n_e/mainboard.c b/src/mainboard/asus/a8n_e/mainboard.c index aedca67..4bd6311 100644 --- a/src/mainboard/asus/a8n_e/mainboard.c +++ b/src/mainboard/asus/a8n_e/mainboard.c @@ -20,6 +20,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("ASUS A8N-E Mainboard") diff --git a/src/mainboard/asus/a8v-e_deluxe/chip.h b/src/mainboard/asus/a8v-e_deluxe/chip.h new file mode 100644 index 0000000..c2849ef --- /dev/null +++ b/src/mainboard/asus/a8v-e_deluxe/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/asus/a8v-e_deluxe/mainboard.c b/src/mainboard/asus/a8v-e_deluxe/mainboard.c index cb38be2..0180a2f 100644 --- a/src/mainboard/asus/a8v-e_deluxe/mainboard.c +++ b/src/mainboard/asus/a8v-e_deluxe/mainboard.c @@ -21,6 +21,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("ASUS A8V-E Deluxe Mainboard") diff --git a/src/mainboard/asus/a8v-e_se/chip.h b/src/mainboard/asus/a8v-e_se/chip.h new file mode 100644 index 0000000..c2849ef --- /dev/null +++ b/src/mainboard/asus/a8v-e_se/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/asus/a8v-e_se/mainboard.c b/src/mainboard/asus/a8v-e_se/mainboard.c index c119e1c..b70f396 100644 --- a/src/mainboard/asus/a8v-e_se/mainboard.c +++ b/src/mainboard/asus/a8v-e_se/mainboard.c @@ -21,6 +21,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("ASUS A8V-E SE Mainboard") diff --git a/src/mainboard/asus/dsbf/chip.h b/src/mainboard/asus/dsbf/chip.h new file mode 100644 index 0000000..70f9bb4 --- /dev/null +++ b/src/mainboard/asus/dsbf/chip.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/asus/dsbf/mainboard.c b/src/mainboard/asus/dsbf/mainboard.c index 618eca9..27a26f9 100644 --- a/src/mainboard/asus/dsbf/mainboard.c +++ b/src/mainboard/asus/dsbf/mainboard.c @@ -25,6 +25,7 @@ #include <boot/tables.h> #include <delay.h> #include <arch/coreboot_tables.h> +#include "chip.h" #include <device/pci_def.h> #include <device/pci_ops.h> #include <arch/io.h> diff --git a/src/mainboard/asus/k8v-x/chip.h b/src/mainboard/asus/k8v-x/chip.h new file mode 100644 index 0000000..c2849ef --- /dev/null +++ b/src/mainboard/asus/k8v-x/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/asus/k8v-x/mainboard.c b/src/mainboard/asus/k8v-x/mainboard.c index 82d8ba0..3e294b8 100644 --- a/src/mainboard/asus/k8v-x/mainboard.c +++ b/src/mainboard/asus/k8v-x/mainboard.c @@ -24,6 +24,7 @@ #include <device/pci_ids.h> #include <arch/io.h> #include "southbridge/via/vt8237r/vt8237r.h" +#include "chip.h" u32 vt8237_ide_80pin_detect(struct device *dev) { diff --git a/src/mainboard/asus/m2n-e/chip.h b/src/mainboard/asus/m2n-e/chip.h new file mode 100644 index 0000000..a69b9ef --- /dev/null +++ b/src/mainboard/asus/m2n-e/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/asus/m2n-e/mainboard.c b/src/mainboard/asus/m2n-e/mainboard.c index 0d7013f..aa0cc5c 100644 --- a/src/mainboard/asus/m2n-e/mainboard.c +++ b/src/mainboard/asus/m2n-e/mainboard.c @@ -20,6 +20,7 @@ #include <device/device.h> #include "hda_verb.h" +#include "chip.h" static void verb_setup(void) { diff --git a/src/mainboard/asus/m2v-mx_se/chip.h b/src/mainboard/asus/m2v-mx_se/chip.h new file mode 100644 index 0000000..c2849ef --- /dev/null +++ b/src/mainboard/asus/m2v-mx_se/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/asus/m2v-mx_se/mainboard.c b/src/mainboard/asus/m2v-mx_se/mainboard.c index 5e3c720..c592282 100644 --- a/src/mainboard/asus/m2v-mx_se/mainboard.c +++ b/src/mainboard/asus/m2v-mx_se/mainboard.c @@ -22,6 +22,7 @@ #include <device/pci_ids.h> #include <boot/tables.h> #include <southbridge/via/k8t890/k8t890.h> +#include "chip.h" int add_mainboard_resources(struct lb_memory *mem) { diff --git a/src/mainboard/asus/m2v/chip.h b/src/mainboard/asus/m2v/chip.h new file mode 100644 index 0000000..c2849ef --- /dev/null +++ b/src/mainboard/asus/m2v/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/asus/m2v/mainboard.c b/src/mainboard/asus/m2v/mainboard.c index 2a44851..2f20fe0 100644 --- a/src/mainboard/asus/m2v/mainboard.c +++ b/src/mainboard/asus/m2v/mainboard.c @@ -23,6 +23,7 @@ #include <device/pci_ids.h> #include <console/console.h> #include "southbridge/via/vt8237r/vt8237r.h" +#include "chip.h" u32 vt8237_ide_80pin_detect(struct device *dev) { diff --git a/src/mainboard/asus/m4a78-em/chip.h b/src/mainboard/asus/m4a78-em/chip.h new file mode 100644 index 0000000..a98b97e --- /dev/null +++ b/src/mainboard/asus/m4a78-em/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/asus/m4a78-em/mainboard.c b/src/mainboard/asus/m4a78-em/mainboard.c index eea8c0d..6b87177 100644 --- a/src/mainboard/asus/m4a78-em/mainboard.c +++ b/src/mainboard/asus/m4a78-em/mainboard.c @@ -26,6 +26,7 @@ #include <device/pci_def.h> #include "southbridge/amd/sb700/sb700.h" #include "southbridge/amd/sb700/smbus.h" +#include "chip.h" void set_pcie_dereset(void); diff --git a/src/mainboard/asus/m4a785-m/chip.h b/src/mainboard/asus/m4a785-m/chip.h new file mode 100644 index 0000000..a98b97e --- /dev/null +++ b/src/mainboard/asus/m4a785-m/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/asus/m4a785-m/mainboard.c b/src/mainboard/asus/m4a785-m/mainboard.c index 45af025..1bfeda5 100644 --- a/src/mainboard/asus/m4a785-m/mainboard.c +++ b/src/mainboard/asus/m4a785-m/mainboard.c @@ -26,6 +26,7 @@ #include <device/pci_def.h> #include "southbridge/amd/sb700/sb700.h" #include "southbridge/amd/sb700/smbus.h" +#include "chip.h" #define ADT7461_ADDRESS 0x4C #define ARA_ADDRESS 0x0C /* Alert Response Address */ diff --git a/src/mainboard/asus/m4a785t-m/chip.h b/src/mainboard/asus/m4a785t-m/chip.h new file mode 100644 index 0000000..a98b97e --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/asus/m5a88-v/chip.h b/src/mainboard/asus/m5a88-v/chip.h new file mode 100644 index 0000000..d5b991d --- /dev/null +++ b/src/mainboard/asus/m5a88-v/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 QingPei Wang <wangqingpei(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/asus/m5a88-v/mainboard.c b/src/mainboard/asus/m5a88-v/mainboard.c index 866e8c2..2042f9b 100644 --- a/src/mainboard/asus/m5a88-v/mainboard.c +++ b/src/mainboard/asus/m5a88-v/mainboard.c @@ -26,6 +26,7 @@ #include <cpu/amd/mtrr.h> #include <device/pci_def.h> #include "SBPLATFORM.h" +#include "chip.h" u8 is_dev3_present(void); diff --git a/src/mainboard/asus/mew-am/chip.h b/src/mainboard/asus/mew-am/chip.h new file mode 100644 index 0000000..dc9bed3 --- /dev/null +++ b/src/mainboard/asus/mew-am/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/asus/mew-am/mainboard.c b/src/mainboard/asus/mew-am/mainboard.c index 8887218..e5008b9 100644 --- a/src/mainboard/asus/mew-am/mainboard.c +++ b/src/mainboard/asus/mew-am/mainboard.c @@ -20,6 +20,7 @@ #include <device/device.h> #include <boot/tables.h> +#include "chip.h" int add_mainboard_resources(struct lb_memory *mem) { diff --git a/src/mainboard/asus/mew-vm/chip.h b/src/mainboard/asus/mew-vm/chip.h new file mode 100644 index 0000000..d138e51 --- /dev/null +++ b/src/mainboard/asus/mew-vm/chip.h @@ -0,0 +1,3 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/asus/mew-vm/mainboard.c b/src/mainboard/asus/mew-vm/mainboard.c index e278565..831be01 100644 --- a/src/mainboard/asus/mew-vm/mainboard.c +++ b/src/mainboard/asus/mew-vm/mainboard.c @@ -1,5 +1,6 @@ #include <device/device.h> #include <boot/tables.h> +#include "chip.h" int add_mainboard_resources(struct lb_memory *mem) { diff --git a/src/mainboard/asus/p2b-d/chip.h b/src/mainboard/asus/p2b-d/chip.h new file mode 100644 index 0000000..1c3876d --- /dev/null +++ b/src/mainboard/asus/p2b-d/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/asus/p2b-d/mainboard.c b/src/mainboard/asus/p2b-d/mainboard.c index 3fe9dc4..58cce0a 100644 --- a/src/mainboard/asus/p2b-d/mainboard.c +++ b/src/mainboard/asus/p2b-d/mainboard.c @@ -19,6 +19,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("ASUS P2B-D Mainboard") diff --git a/src/mainboard/asus/p2b-ds/chip.h b/src/mainboard/asus/p2b-ds/chip.h new file mode 100644 index 0000000..56e17ca --- /dev/null +++ b/src/mainboard/asus/p2b-ds/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/asus/p2b-ds/mainboard.c b/src/mainboard/asus/p2b-ds/mainboard.c index c874137..910b130 100644 --- a/src/mainboard/asus/p2b-ds/mainboard.c +++ b/src/mainboard/asus/p2b-ds/mainboard.c @@ -19,6 +19,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("ASUS P2B-DS Mainboard") diff --git a/src/mainboard/asus/p2b-f/chip.h b/src/mainboard/asus/p2b-f/chip.h new file mode 100644 index 0000000..dc9bed3 --- /dev/null +++ b/src/mainboard/asus/p2b-f/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/asus/p2b-f/mainboard.c b/src/mainboard/asus/p2b-f/mainboard.c index e5d2e14..e2b022a 100644 --- a/src/mainboard/asus/p2b-f/mainboard.c +++ b/src/mainboard/asus/p2b-f/mainboard.c @@ -19,6 +19,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("ASUS P2B-F Mainboard") diff --git a/src/mainboard/asus/p2b-ls/chip.h b/src/mainboard/asus/p2b-ls/chip.h new file mode 100644 index 0000000..dc9bed3 --- /dev/null +++ b/src/mainboard/asus/p2b-ls/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/asus/p2b-ls/mainboard.c b/src/mainboard/asus/p2b-ls/mainboard.c index 9f250f4..fec75e3 100644 --- a/src/mainboard/asus/p2b-ls/mainboard.c +++ b/src/mainboard/asus/p2b-ls/mainboard.c @@ -19,6 +19,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("ASUS P2B-LS Mainboard") diff --git a/src/mainboard/asus/p2b/chip.h b/src/mainboard/asus/p2b/chip.h new file mode 100644 index 0000000..dc9bed3 --- /dev/null +++ b/src/mainboard/asus/p2b/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/asus/p2b/mainboard.c b/src/mainboard/asus/p2b/mainboard.c index 527dc7a..21e5a4e 100644 --- a/src/mainboard/asus/p2b/mainboard.c +++ b/src/mainboard/asus/p2b/mainboard.c @@ -19,6 +19,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("ASUS P2B Mainboard") diff --git a/src/mainboard/asus/p3b-f/chip.h b/src/mainboard/asus/p3b-f/chip.h new file mode 100644 index 0000000..dc9bed3 --- /dev/null +++ b/src/mainboard/asus/p3b-f/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/asus/p3b-f/mainboard.c b/src/mainboard/asus/p3b-f/mainboard.c index 9b41c79..c234fc2 100644 --- a/src/mainboard/asus/p3b-f/mainboard.c +++ b/src/mainboard/asus/p3b-f/mainboard.c @@ -19,6 +19,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("ASUS P3B-F Mainboard") diff --git a/src/mainboard/avalue/eax-785e/chip.h b/src/mainboard/avalue/eax-785e/chip.h new file mode 100644 index 0000000..5957589 --- /dev/null +++ b/src/mainboard/avalue/eax-785e/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/avalue/eax-785e/mainboard.c b/src/mainboard/avalue/eax-785e/mainboard.c index 5e50efa..0aa20e1 100644 --- a/src/mainboard/avalue/eax-785e/mainboard.c +++ b/src/mainboard/avalue/eax-785e/mainboard.c @@ -26,6 +26,7 @@ #include <cpu/amd/mtrr.h> #include <device/pci_def.h> #include "SBPLATFORM.h" +#include "chip.h" u8 is_dev3_present(void); @@ -76,6 +77,10 @@ u8 is_dev3_present(void) *************************************************/ static void eax_785e(device_t dev) { + /* Leave it for furture use. */ + /* struct mainboard_config *mainboard = + (struct mainboard_config *)dev->chip_info; */ + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); setup_uma_memory(); diff --git a/src/mainboard/axus/tc320/chip.h b/src/mainboard/axus/tc320/chip.h new file mode 100644 index 0000000..6e6f190 --- /dev/null +++ b/src/mainboard/axus/tc320/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Juergen Beisert <juergen(a)kreuzholzen.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/axus/tc320/mainboard.c b/src/mainboard/axus/tc320/mainboard.c index af52755..89c3dca 100644 --- a/src/mainboard/axus/tc320/mainboard.c +++ b/src/mainboard/axus/tc320/mainboard.c @@ -19,6 +19,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("AXUS TC320 Mainboard") diff --git a/src/mainboard/azza/pt-6ibd/chip.h b/src/mainboard/azza/pt-6ibd/chip.h new file mode 100644 index 0000000..dc9bed3 --- /dev/null +++ b/src/mainboard/azza/pt-6ibd/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/azza/pt-6ibd/mainboard.c b/src/mainboard/azza/pt-6ibd/mainboard.c index 483f328..45efc16 100644 --- a/src/mainboard/azza/pt-6ibd/mainboard.c +++ b/src/mainboard/azza/pt-6ibd/mainboard.c @@ -19,6 +19,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("AZZA PT-6IBD Mainboard") diff --git a/src/mainboard/bachmann/ot200/chip.h b/src/mainboard/bachmann/ot200/chip.h new file mode 100644 index 0000000..6acb1ff --- /dev/null +++ b/src/mainboard/bachmann/ot200/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Bachmann electronic GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/bcom/winnet100/chip.h b/src/mainboard/bcom/winnet100/chip.h new file mode 100644 index 0000000..4bce558 --- /dev/null +++ b/src/mainboard/bcom/winnet100/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Juergen Beisert <juergen(a)kreuzholzen.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/bcom/winnet100/mainboard.c b/src/mainboard/bcom/winnet100/mainboard.c index 13089df..279701d 100644 --- a/src/mainboard/bcom/winnet100/mainboard.c +++ b/src/mainboard/bcom/winnet100/mainboard.c @@ -19,6 +19,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("BCOM WinNET100 Mainboard") diff --git a/src/mainboard/bcom/winnetp680/chip.h b/src/mainboard/bcom/winnetp680/chip.h new file mode 100644 index 0000000..0a2badb --- /dev/null +++ b/src/mainboard/bcom/winnetp680/chip.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 VIA Technologies, Inc. + * (Written by Aaron Lwe <aaron.lwe(a)gmail.com> for VIA) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/bcom/winnetp680/mainboard.c b/src/mainboard/bcom/winnetp680/mainboard.c index 26fc5e3..f467e1b 100644 --- a/src/mainboard/bcom/winnetp680/mainboard.c +++ b/src/mainboard/bcom/winnetp680/mainboard.c @@ -20,6 +20,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("BCOM WinNET P680 Mainboard") diff --git a/src/mainboard/bifferos/bifferboard/chip.h b/src/mainboard/bifferos/bifferboard/chip.h new file mode 100644 index 0000000..be42783 --- /dev/null +++ b/src/mainboard/bifferos/bifferboard/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; + diff --git a/src/mainboard/bifferos/bifferboard/mainboard.c b/src/mainboard/bifferos/bifferboard/mainboard.c index f3387a3..5840f95 100644 --- a/src/mainboard/bifferos/bifferboard/mainboard.c +++ b/src/mainboard/bifferos/bifferboard/mainboard.c @@ -18,6 +18,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Bifferos Bifferboard") diff --git a/src/mainboard/biostar/m6tba/chip.h b/src/mainboard/biostar/m6tba/chip.h new file mode 100644 index 0000000..dc9bed3 --- /dev/null +++ b/src/mainboard/biostar/m6tba/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/biostar/m6tba/mainboard.c b/src/mainboard/biostar/m6tba/mainboard.c index 6795284..fb6896a 100644 --- a/src/mainboard/biostar/m6tba/mainboard.c +++ b/src/mainboard/biostar/m6tba/mainboard.c @@ -19,6 +19,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Biostar M6TBA Mainboard") diff --git a/src/mainboard/broadcom/blast/chip.h b/src/mainboard/broadcom/blast/chip.h new file mode 100644 index 0000000..d138e51 --- /dev/null +++ b/src/mainboard/broadcom/blast/chip.h @@ -0,0 +1,3 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/broadcom/blast/mainboard.c b/src/mainboard/broadcom/blast/mainboard.c index c556bd5..5f4b525 100644 --- a/src/mainboard/broadcom/blast/mainboard.c +++ b/src/mainboard/broadcom/blast/mainboard.c @@ -1,4 +1,5 @@ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Broadcom Blast Mainboard") diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/chip.h b/src/mainboard/compaq/deskpro_en_sff_p600/chip.h new file mode 100644 index 0000000..dc9bed3 --- /dev/null +++ b/src/mainboard/compaq/deskpro_en_sff_p600/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/mainboard.c b/src/mainboard/compaq/deskpro_en_sff_p600/mainboard.c index d4abb63..75d7876 100644 --- a/src/mainboard/compaq/deskpro_en_sff_p600/mainboard.c +++ b/src/mainboard/compaq/deskpro_en_sff_p600/mainboard.c @@ -19,6 +19,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Compaq Deskpro EN SFF P600 Mainboard") diff --git a/src/mainboard/digitallogic/adl855pc/chip.h b/src/mainboard/digitallogic/adl855pc/chip.h new file mode 100644 index 0000000..d138e51 --- /dev/null +++ b/src/mainboard/digitallogic/adl855pc/chip.h @@ -0,0 +1,3 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/digitallogic/adl855pc/mainboard.c b/src/mainboard/digitallogic/adl855pc/mainboard.c index 41c34e4..c6ab63e 100644 --- a/src/mainboard/digitallogic/adl855pc/mainboard.c +++ b/src/mainboard/digitallogic/adl855pc/mainboard.c @@ -1,4 +1,5 @@ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("DIGITAL-LOGIC ADL855PC Mainboard") diff --git a/src/mainboard/digitallogic/msm586seg/chip.h b/src/mainboard/digitallogic/msm586seg/chip.h new file mode 100644 index 0000000..d138e51 --- /dev/null +++ b/src/mainboard/digitallogic/msm586seg/chip.h @@ -0,0 +1,3 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/digitallogic/msm586seg/mainboard.c b/src/mainboard/digitallogic/msm586seg/mainboard.c index 8f2d8c6..2361059 100644 --- a/src/mainboard/digitallogic/msm586seg/mainboard.c +++ b/src/mainboard/digitallogic/msm586seg/mainboard.c @@ -4,6 +4,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <cpu/amd/sc520.h> +#include "chip.h" static void irqdump(void) diff --git a/src/mainboard/digitallogic/msm800sev/chip.h b/src/mainboard/digitallogic/msm800sev/chip.h new file mode 100644 index 0000000..d138e51 --- /dev/null +++ b/src/mainboard/digitallogic/msm800sev/chip.h @@ -0,0 +1,3 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/digitallogic/msm800sev/mainboard.c b/src/mainboard/digitallogic/msm800sev/mainboard.c index 3ade3d6..f4d0e0e 100644 --- a/src/mainboard/digitallogic/msm800sev/mainboard.c +++ b/src/mainboard/digitallogic/msm800sev/mainboard.c @@ -19,6 +19,7 @@ #include <console/console.h> #include <device/device.h> +#include "chip.h" static void init(struct device *dev) { diff --git a/src/mainboard/eaglelion/5bcm/chip.h b/src/mainboard/eaglelion/5bcm/chip.h new file mode 100644 index 0000000..d138e51 --- /dev/null +++ b/src/mainboard/eaglelion/5bcm/chip.h @@ -0,0 +1,3 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/eaglelion/5bcm/mainboard.c b/src/mainboard/eaglelion/5bcm/mainboard.c index e1c499e..c0b3ae0 100644 --- a/src/mainboard/eaglelion/5bcm/mainboard.c +++ b/src/mainboard/eaglelion/5bcm/mainboard.c @@ -1,4 +1,5 @@ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Eaglelion 5BCM Mainboard") diff --git a/src/mainboard/ecs/p6iwp-fe/chip.h b/src/mainboard/ecs/p6iwp-fe/chip.h new file mode 100644 index 0000000..dc9bed3 --- /dev/null +++ b/src/mainboard/ecs/p6iwp-fe/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/ecs/p6iwp-fe/mainboard.c b/src/mainboard/ecs/p6iwp-fe/mainboard.c index 9031ac7..aec1250 100644 --- a/src/mainboard/ecs/p6iwp-fe/mainboard.c +++ b/src/mainboard/ecs/p6iwp-fe/mainboard.c @@ -20,6 +20,7 @@ #include <device/device.h> #include <boot/tables.h> +#include "chip.h" int add_mainboard_resources(struct lb_memory *mem) { diff --git a/src/mainboard/emulation/qemu-x86/mainboard.c b/src/mainboard/emulation/qemu-x86/mainboard.c index f8d0da7..e4c9785 100644 --- a/src/mainboard/emulation/qemu-x86/mainboard.c +++ b/src/mainboard/emulation/qemu-x86/mainboard.c @@ -5,6 +5,7 @@ #include <device/pci_ops.h> #include <pc80/keyboard.h> #include <arch/io.h> +#include "chip.h" /* not sure how these are routed in qemu */ static const unsigned char enetIrqs[4] = { 11, 0, 0, 0 }; diff --git a/src/mainboard/getac/p470/chip.h b/src/mainboard/getac/p470/chip.h new file mode 100644 index 0000000..b75c381 --- /dev/null +++ b/src/mainboard/getac/p470/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/getac/p470/mainboard.c b/src/mainboard/getac/p470/mainboard.c index 83b4718..b7a248d 100644 --- a/src/mainboard/getac/p470/mainboard.c +++ b/src/mainboard/getac/p470/mainboard.c @@ -25,6 +25,7 @@ #include <arch/io.h> #include <boot/tables.h> #include <delay.h> +#include "chip.h" #include "hda_verb.h" #include "ec_oem.c" diff --git a/src/mainboard/gigabyte/ga-6bxc/chip.h b/src/mainboard/gigabyte/ga-6bxc/chip.h new file mode 100644 index 0000000..dc9bed3 --- /dev/null +++ b/src/mainboard/gigabyte/ga-6bxc/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/gigabyte/ga-6bxc/mainboard.c b/src/mainboard/gigabyte/ga-6bxc/mainboard.c index d43a577..01411f3 100644 --- a/src/mainboard/gigabyte/ga-6bxc/mainboard.c +++ b/src/mainboard/gigabyte/ga-6bxc/mainboard.c @@ -19,6 +19,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("GIGABYTE GA-6BXC Mainboard") diff --git a/src/mainboard/gigabyte/ga-6bxe/chip.h b/src/mainboard/gigabyte/ga-6bxe/chip.h new file mode 100644 index 0000000..8e3af56 --- /dev/null +++ b/src/mainboard/gigabyte/ga-6bxe/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Anders Jenbo <anders(a)jenbo.dk> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/gigabyte/ga-6bxe/mainboard.c b/src/mainboard/gigabyte/ga-6bxe/mainboard.c index 281d841..2d04794 100644 --- a/src/mainboard/gigabyte/ga-6bxe/mainboard.c +++ b/src/mainboard/gigabyte/ga-6bxe/mainboard.c @@ -19,6 +19,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("GIGABYTE GA-6BXE Mainboard") diff --git a/src/mainboard/gigabyte/ga_2761gxdk/chip.h b/src/mainboard/gigabyte/ga_2761gxdk/chip.h new file mode 100644 index 0000000..3c303ee --- /dev/null +++ b/src/mainboard/gigabyte/ga_2761gxdk/chip.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) + * Written by Morgan Tsai <my_tsai(a)sis.com> for SiS. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/gigabyte/ga_2761gxdk/mainboard.c b/src/mainboard/gigabyte/ga_2761gxdk/mainboard.c index e8b8969..e365575 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/mainboard.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/mainboard.c @@ -24,6 +24,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("GIGABYTE GA-2761GXDK Mainboard") diff --git a/src/mainboard/gigabyte/m57sli/chip.h b/src/mainboard/gigabyte/m57sli/chip.h new file mode 100644 index 0000000..ebd990b --- /dev/null +++ b/src/mainboard/gigabyte/m57sli/chip.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/gigabyte/m57sli/mainboard.c b/src/mainboard/gigabyte/m57sli/mainboard.c index dffa769..b198fb6 100644 --- a/src/mainboard/gigabyte/m57sli/mainboard.c +++ b/src/mainboard/gigabyte/m57sli/mainboard.c @@ -25,6 +25,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> // #include "hda_verb.h" +#include "chip.h" static void verb_setup(void) { diff --git a/src/mainboard/gigabyte/ma785gm/chip.h b/src/mainboard/gigabyte/ma785gm/chip.h new file mode 100644 index 0000000..70102aa --- /dev/null +++ b/src/mainboard/gigabyte/ma785gm/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Wang Qing Pei <wangqingpei(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/gigabyte/ma785gm/mainboard.c b/src/mainboard/gigabyte/ma785gm/mainboard.c index 680bb2e..6303778 100644 --- a/src/mainboard/gigabyte/ma785gm/mainboard.c +++ b/src/mainboard/gigabyte/ma785gm/mainboard.c @@ -27,6 +27,7 @@ #include <device/pci_def.h> #include "southbridge/amd/sb700/sb700.h" #include "southbridge/amd/sb700/smbus.h" +#include "chip.h" void set_pcie_dereset(void); void set_pcie_reset(void); diff --git a/src/mainboard/gigabyte/ma785gmt/chip.h b/src/mainboard/gigabyte/ma785gmt/chip.h new file mode 100644 index 0000000..70102aa --- /dev/null +++ b/src/mainboard/gigabyte/ma785gmt/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Wang Qing Pei <wangqingpei(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/gigabyte/ma785gmt/mainboard.c b/src/mainboard/gigabyte/ma785gmt/mainboard.c index b7ecf9f..fdfe38b 100644 --- a/src/mainboard/gigabyte/ma785gmt/mainboard.c +++ b/src/mainboard/gigabyte/ma785gmt/mainboard.c @@ -27,6 +27,7 @@ #include <device/pci_def.h> #include "southbridge/amd/sb700/sb700.h" #include "southbridge/amd/sb700/smbus.h" +#include "chip.h" #define ADT7461_ADDRESS 0x4C #define ARA_ADDRESS 0x0C /* Alert Response Address */ diff --git a/src/mainboard/gigabyte/ma78gm/chip.h b/src/mainboard/gigabyte/ma78gm/chip.h new file mode 100644 index 0000000..a98b97e --- /dev/null +++ b/src/mainboard/gigabyte/ma78gm/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/gigabyte/ma78gm/mainboard.c b/src/mainboard/gigabyte/ma78gm/mainboard.c index 6756690..6ab63ac 100644 --- a/src/mainboard/gigabyte/ma78gm/mainboard.c +++ b/src/mainboard/gigabyte/ma78gm/mainboard.c @@ -28,6 +28,7 @@ #include <device/pci_def.h> #include "southbridge/amd/sb700/sb700.h" #include "southbridge/amd/sb700/smbus.h" +#include "chip.h" void set_pcie_dereset(void); void set_pcie_reset(void); diff --git a/src/mainboard/hp/dl145_g1/chip.h b/src/mainboard/hp/dl145_g1/chip.h new file mode 100644 index 0000000..d138e51 --- /dev/null +++ b/src/mainboard/hp/dl145_g1/chip.h @@ -0,0 +1,3 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/hp/dl145_g1/mainboard.c b/src/mainboard/hp/dl145_g1/mainboard.c index fde9d22..d68e720 100644 --- a/src/mainboard/hp/dl145_g1/mainboard.c +++ b/src/mainboard/hp/dl145_g1/mainboard.c @@ -22,6 +22,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("HP ProLiant DL145 G1 Mainboard") diff --git a/src/mainboard/hp/dl145_g3/chip.h b/src/mainboard/hp/dl145_g3/chip.h new file mode 100644 index 0000000..04039f1 --- /dev/null +++ b/src/mainboard/hp/dl145_g3/chip.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 University of Mannheim + * Written by Philipp Degler <pdegler(a)rumms.uni-mannheim.de> for University of Mannheim. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/hp/dl145_g3/mainboard.c b/src/mainboard/hp/dl145_g3/mainboard.c index 81f074e..7799c16 100644 --- a/src/mainboard/hp/dl145_g3/mainboard.c +++ b/src/mainboard/hp/dl145_g3/mainboard.c @@ -27,6 +27,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("HP ProLiant DL145 G3 Mainboard") diff --git a/src/mainboard/hp/dl165_g6_fam10/chip.h b/src/mainboard/hp/dl165_g6_fam10/chip.h new file mode 100644 index 0000000..6c54f71 --- /dev/null +++ b/src/mainboard/hp/dl165_g6_fam10/chip.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 University of Mannheim + * Written by Philipp Degler <pdegler(a)rumms.uni-mannheim.de> for University of Mannheim. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config { +}; + diff --git a/src/mainboard/hp/dl165_g6_fam10/mainboard.c b/src/mainboard/hp/dl165_g6_fam10/mainboard.c index 97f2fb7..d84ba47 100644 --- a/src/mainboard/hp/dl165_g6_fam10/mainboard.c +++ b/src/mainboard/hp/dl165_g6_fam10/mainboard.c @@ -27,6 +27,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("HP ProLiant DL165 G6 Mainboard (Fam10h)") diff --git a/src/mainboard/hp/e_vectra_p2706t/chip.h b/src/mainboard/hp/e_vectra_p2706t/chip.h new file mode 100644 index 0000000..f354ee8 --- /dev/null +++ b/src/mainboard/hp/e_vectra_p2706t/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/hp/e_vectra_p2706t/mainboard.c b/src/mainboard/hp/e_vectra_p2706t/mainboard.c index 0f9b75e..74339e9 100644 --- a/src/mainboard/hp/e_vectra_p2706t/mainboard.c +++ b/src/mainboard/hp/e_vectra_p2706t/mainboard.c @@ -20,6 +20,7 @@ #include <device/device.h> #include <boot/tables.h> +#include "chip.h" int add_mainboard_resources(struct lb_memory *mem) { diff --git a/src/mainboard/ibase/mb899/chip.h b/src/mainboard/ibase/mb899/chip.h new file mode 100644 index 0000000..831a973 --- /dev/null +++ b/src/mainboard/ibase/mb899/chip.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/ibase/mb899/mainboard.c b/src/mainboard/ibase/mb899/mainboard.c index 4e3d606..5989685 100644 --- a/src/mainboard/ibase/mb899/mainboard.c +++ b/src/mainboard/ibase/mb899/mainboard.c @@ -27,6 +27,7 @@ #include <pc80/mc146818rtc.h> #include <arch/io.h> #include <arch/coreboot_tables.h> +#include "chip.h" #if CONFIG_PCI_OPTION_ROM_RUN_YABEL static int int15_handler(void) diff --git a/src/mainboard/ibm/e325/chip.h b/src/mainboard/ibm/e325/chip.h new file mode 100644 index 0000000..d138e51 --- /dev/null +++ b/src/mainboard/ibm/e325/chip.h @@ -0,0 +1,3 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/ibm/e325/mainboard.c b/src/mainboard/ibm/e325/mainboard.c index 136ffaf..49a8c41 100644 --- a/src/mainboard/ibm/e325/mainboard.c +++ b/src/mainboard/ibm/e325/mainboard.c @@ -1,4 +1,5 @@ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("IBM eServer 325 Mainboard") diff --git a/src/mainboard/ibm/e326/chip.h b/src/mainboard/ibm/e326/chip.h new file mode 100644 index 0000000..d138e51 --- /dev/null +++ b/src/mainboard/ibm/e326/chip.h @@ -0,0 +1,3 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/ibm/e326/mainboard.c b/src/mainboard/ibm/e326/mainboard.c index bd5ebc5..70b59a9 100644 --- a/src/mainboard/ibm/e326/mainboard.c +++ b/src/mainboard/ibm/e326/mainboard.c @@ -1,4 +1,5 @@ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("IBM eServer 326 Mainboard") diff --git a/src/mainboard/iei/juki-511p/chip.h b/src/mainboard/iei/juki-511p/chip.h new file mode 100644 index 0000000..f5f5b7a --- /dev/null +++ b/src/mainboard/iei/juki-511p/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/iei/juki-511p/mainboard.c b/src/mainboard/iei/juki-511p/mainboard.c index e5714cf..e44a07c 100644 --- a/src/mainboard/iei/juki-511p/mainboard.c +++ b/src/mainboard/iei/juki-511p/mainboard.c @@ -24,6 +24,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <arch/io.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("IEI JUKI-511P Mainboard") diff --git a/src/mainboard/iei/kino-780am2-fam10/chip.h b/src/mainboard/iei/kino-780am2-fam10/chip.h new file mode 100644 index 0000000..a98b97e --- /dev/null +++ b/src/mainboard/iei/kino-780am2-fam10/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/iei/kino-780am2-fam10/mainboard.c b/src/mainboard/iei/kino-780am2-fam10/mainboard.c index e9ef596..b18e5a6 100644 --- a/src/mainboard/iei/kino-780am2-fam10/mainboard.c +++ b/src/mainboard/iei/kino-780am2-fam10/mainboard.c @@ -27,6 +27,7 @@ #include <device/pci_def.h> #include "southbridge/amd/sb700/sb700.h" #include "southbridge/amd/sb700/smbus.h" +#include "chip.h" void set_pcie_dereset(void); void set_pcie_reset(void); diff --git a/src/mainboard/iei/nova4899r/chip.h b/src/mainboard/iei/nova4899r/chip.h new file mode 100644 index 0000000..271b02c --- /dev/null +++ b/src/mainboard/iei/nova4899r/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Luis Correia <luis.f.correia(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/iei/nova4899r/mainboard.c b/src/mainboard/iei/nova4899r/mainboard.c index 85c6521..7ca0a14 100644 --- a/src/mainboard/iei/nova4899r/mainboard.c +++ b/src/mainboard/iei/nova4899r/mainboard.c @@ -24,6 +24,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <arch/io.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("IEI NOVA-4899R Mainboard") diff --git a/src/mainboard/iei/pcisa-lx-800-r10/chip.h b/src/mainboard/iei/pcisa-lx-800-r10/chip.h new file mode 100644 index 0000000..f5f5b7a --- /dev/null +++ b/src/mainboard/iei/pcisa-lx-800-r10/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/iei/pm-lx-800-r11/chip.h b/src/mainboard/iei/pm-lx-800-r11/chip.h new file mode 100644 index 0000000..d69f9b6 --- /dev/null +++ b/src/mainboard/iei/pm-lx-800-r11/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/intel/d810e2cb/chip.h b/src/mainboard/intel/d810e2cb/chip.h new file mode 100644 index 0000000..1f9a793 --- /dev/null +++ b/src/mainboard/intel/d810e2cb/chip.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Joseph Smith <joe(a)settoplinux.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/intel/d810e2cb/mainboard.c b/src/mainboard/intel/d810e2cb/mainboard.c index 7589d6e..c55a680 100644 --- a/src/mainboard/intel/d810e2cb/mainboard.c +++ b/src/mainboard/intel/d810e2cb/mainboard.c @@ -19,6 +19,7 @@ #include <device/device.h> #include <boot/tables.h> +#include "chip.h" int add_mainboard_resources(struct lb_memory *mem) { diff --git a/src/mainboard/intel/d945gclf/chip.h b/src/mainboard/intel/d945gclf/chip.h new file mode 100644 index 0000000..491eebd --- /dev/null +++ b/src/mainboard/intel/d945gclf/chip.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/intel/d945gclf/mainboard.c b/src/mainboard/intel/d945gclf/mainboard.c index ca920bc..ff08b8a 100644 --- a/src/mainboard/intel/d945gclf/mainboard.c +++ b/src/mainboard/intel/d945gclf/mainboard.c @@ -21,6 +21,7 @@ #include <console/console.h> #include <boot/tables.h> #include <arch/coreboot_tables.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Intel D945GCLF Mainboard") diff --git a/src/mainboard/intel/eagleheights/chip.h b/src/mainboard/intel/eagleheights/chip.h new file mode 100644 index 0000000..3ae8657 --- /dev/null +++ b/src/mainboard/intel/eagleheights/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/intel/eagleheights/mainboard.c b/src/mainboard/intel/eagleheights/mainboard.c index d6bc10f..7974dbc 100644 --- a/src/mainboard/intel/eagleheights/mainboard.c +++ b/src/mainboard/intel/eagleheights/mainboard.c @@ -23,6 +23,7 @@ #include <device/device.h> #include <boot/tables.h> #include <arch/coreboot_tables.h> +#include "chip.h" int add_mainboard_resources(struct lb_memory *mem) { diff --git a/src/mainboard/intel/emeraldlake2/chip.h b/src/mainboard/intel/emeraldlake2/chip.h new file mode 100644 index 0000000..fbe2477 --- /dev/null +++ b/src/mainboard/intel/emeraldlake2/chip.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/intel/emeraldlake2/mainboard.c b/src/mainboard/intel/emeraldlake2/mainboard.c index 5717edf..0bf33fc 100644 --- a/src/mainboard/intel/emeraldlake2/mainboard.c +++ b/src/mainboard/intel/emeraldlake2/mainboard.c @@ -34,6 +34,7 @@ #include <arch/interrupt.h> #include <arch/coreboot_tables.h> #include "hda_verb.h" +#include "chip.h" #include <southbridge/intel/bd82x6x/pch.h> void mainboard_suspend_resume(void) diff --git a/src/mainboard/intel/jarrell/chip.h b/src/mainboard/intel/jarrell/chip.h new file mode 100644 index 0000000..d138e51 --- /dev/null +++ b/src/mainboard/intel/jarrell/chip.h @@ -0,0 +1,3 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/intel/jarrell/mainboard.c b/src/mainboard/intel/jarrell/mainboard.c index f66431d..ba2bfc5 100644 --- a/src/mainboard/intel/jarrell/mainboard.c +++ b/src/mainboard/intel/jarrell/mainboard.c @@ -1,4 +1,5 @@ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Intel Jarell Mainboard") diff --git a/src/mainboard/intel/mtarvon/chip.h b/src/mainboard/intel/mtarvon/chip.h new file mode 100644 index 0000000..9c9114d --- /dev/null +++ b/src/mainboard/intel/mtarvon/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Arastra, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/intel/mtarvon/mainboard.c b/src/mainboard/intel/mtarvon/mainboard.c index b69df9b..26111f5 100644 --- a/src/mainboard/intel/mtarvon/mainboard.c +++ b/src/mainboard/intel/mtarvon/mainboard.c @@ -19,6 +19,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Intel Mt. Arvon Mainboard") diff --git a/src/mainboard/intel/truxton/chip.h b/src/mainboard/intel/truxton/chip.h new file mode 100644 index 0000000..9c9114d --- /dev/null +++ b/src/mainboard/intel/truxton/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Arastra, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/intel/truxton/mainboard.c b/src/mainboard/intel/truxton/mainboard.c index 754ba0d..78a16a9 100644 --- a/src/mainboard/intel/truxton/mainboard.c +++ b/src/mainboard/intel/truxton/mainboard.c @@ -19,6 +19,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Intel Truxton Mainboard") diff --git a/src/mainboard/intel/xe7501devkit/chip.h b/src/mainboard/intel/xe7501devkit/chip.h new file mode 100644 index 0000000..d138e51 --- /dev/null +++ b/src/mainboard/intel/xe7501devkit/chip.h @@ -0,0 +1,3 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/intel/xe7501devkit/mainboard.c b/src/mainboard/intel/xe7501devkit/mainboard.c index c605624..3b757d6 100644 --- a/src/mainboard/intel/xe7501devkit/mainboard.c +++ b/src/mainboard/intel/xe7501devkit/mainboard.c @@ -1,4 +1,5 @@ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Intel Xeon E7501 DevKit Mainboard") diff --git a/src/mainboard/iwave/iWRainbowG6/chip.h b/src/mainboard/iwave/iWRainbowG6/chip.h new file mode 100644 index 0000000..831a973 --- /dev/null +++ b/src/mainboard/iwave/iWRainbowG6/chip.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/iwave/iWRainbowG6/mainboard.c b/src/mainboard/iwave/iWRainbowG6/mainboard.c index f3fc20f..7d0c61d 100644 --- a/src/mainboard/iwave/iWRainbowG6/mainboard.c +++ b/src/mainboard/iwave/iWRainbowG6/mainboard.c @@ -21,6 +21,7 @@ #include <device/device.h> #include <console/console.h> #include <boot/tables.h> +#include "chip.h" #include "hda_verb.h" static void verb_setup(void) diff --git a/src/mainboard/iwill/dk8_htx/chip.h b/src/mainboard/iwill/dk8_htx/chip.h new file mode 100644 index 0000000..d138e51 --- /dev/null +++ b/src/mainboard/iwill/dk8_htx/chip.h @@ -0,0 +1,3 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/iwill/dk8_htx/mainboard.c b/src/mainboard/iwill/dk8_htx/mainboard.c index 251852f..cbbd3f2 100644 --- a/src/mainboard/iwill/dk8_htx/mainboard.c +++ b/src/mainboard/iwill/dk8_htx/mainboard.c @@ -1,4 +1,5 @@ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("IWILL DK8-HTX Mainboard") diff --git a/src/mainboard/iwill/dk8s2/chip.h b/src/mainboard/iwill/dk8s2/chip.h new file mode 100644 index 0000000..d138e51 --- /dev/null +++ b/src/mainboard/iwill/dk8s2/chip.h @@ -0,0 +1,3 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/iwill/dk8s2/mainboard.c b/src/mainboard/iwill/dk8s2/mainboard.c index 18ab152..7559da6 100644 --- a/src/mainboard/iwill/dk8s2/mainboard.c +++ b/src/mainboard/iwill/dk8s2/mainboard.c @@ -1,4 +1,5 @@ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("IWILL DK8S2 Mainboard") diff --git a/src/mainboard/iwill/dk8x/chip.h b/src/mainboard/iwill/dk8x/chip.h new file mode 100644 index 0000000..d138e51 --- /dev/null +++ b/src/mainboard/iwill/dk8x/chip.h @@ -0,0 +1,3 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/iwill/dk8x/mainboard.c b/src/mainboard/iwill/dk8x/mainboard.c index 3e062de..a936f40 100644 --- a/src/mainboard/iwill/dk8x/mainboard.c +++ b/src/mainboard/iwill/dk8x/mainboard.c @@ -1,4 +1,5 @@ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("IWILL DK8X Mainboard") diff --git a/src/mainboard/jetway/j7f24/chip.h b/src/mainboard/jetway/j7f24/chip.h new file mode 100644 index 0000000..0a2badb --- /dev/null +++ b/src/mainboard/jetway/j7f24/chip.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 VIA Technologies, Inc. + * (Written by Aaron Lwe <aaron.lwe(a)gmail.com> for VIA) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/jetway/j7f24/mainboard.c b/src/mainboard/jetway/j7f24/mainboard.c index 4b1ee39..6693747 100644 --- a/src/mainboard/jetway/j7f24/mainboard.c +++ b/src/mainboard/jetway/j7f24/mainboard.c @@ -20,6 +20,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Jetway J7F[24]* Mainboard") diff --git a/src/mainboard/jetway/pa78vm5/chip.h b/src/mainboard/jetway/pa78vm5/chip.h new file mode 100644 index 0000000..d081720 --- /dev/null +++ b/src/mainboard/jetway/pa78vm5/chip.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Wang Qing Pei <wangqingpei(a)gmail.com> + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/jetway/pa78vm5/mainboard.c b/src/mainboard/jetway/pa78vm5/mainboard.c index cb37c11..585a2a4 100644 --- a/src/mainboard/jetway/pa78vm5/mainboard.c +++ b/src/mainboard/jetway/pa78vm5/mainboard.c @@ -28,6 +28,7 @@ #include <device/pci_def.h> #include "southbridge/amd/sb700/sb700.h" #include "southbridge/amd/sb700/smbus.h" +#include "chip.h" void set_pcie_dereset(void); void set_pcie_reset(void); diff --git a/src/mainboard/kontron/986lcd-m/chip.h b/src/mainboard/kontron/986lcd-m/chip.h new file mode 100644 index 0000000..831a973 --- /dev/null +++ b/src/mainboard/kontron/986lcd-m/chip.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c index b9686bd..d7b1f13 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard.c +++ b/src/mainboard/kontron/986lcd-m/mainboard.c @@ -26,6 +26,7 @@ #include <pc80/mc146818rtc.h> #include <arch/io.h> #include <arch/interrupt.h> +#include "chip.h" #if CONFIG_PCI_OPTION_ROM_RUN_YABEL static int int15_handler(void) diff --git a/src/mainboard/kontron/kt690/chip.h b/src/mainboard/kontron/kt690/chip.h new file mode 100644 index 0000000..05e1582 --- /dev/null +++ b/src/mainboard/kontron/kt690/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; + diff --git a/src/mainboard/kontron/kt690/mainboard.c b/src/mainboard/kontron/kt690/mainboard.c index dbd4141..d24d97d 100644 --- a/src/mainboard/kontron/kt690/mainboard.c +++ b/src/mainboard/kontron/kt690/mainboard.c @@ -26,6 +26,7 @@ #include <cpu/amd/mtrr.h> #include <device/pci_def.h> #include <southbridge/amd/sb600/sb600.h> +#include "chip.h" #define ADT7461_ADDRESS 0x4C #define ARA_ADDRESS 0x0C /* Alert Response Address */ diff --git a/src/mainboard/lanner/em8510/chip.h b/src/mainboard/lanner/em8510/chip.h new file mode 100644 index 0000000..96d8705 --- /dev/null +++ b/src/mainboard/lanner/em8510/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Travelping GmbH <info(a)travelping.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/lanner/em8510/mainboard.c b/src/mainboard/lanner/em8510/mainboard.c index 9317944..4a20d25 100644 --- a/src/mainboard/lanner/em8510/mainboard.c +++ b/src/mainboard/lanner/em8510/mainboard.c @@ -19,6 +19,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("LANNER EM-8510 Mainboard") diff --git a/src/mainboard/lenovo/t60/chip.h b/src/mainboard/lenovo/t60/chip.h new file mode 100644 index 0000000..70f9bb4 --- /dev/null +++ b/src/mainboard/lenovo/t60/chip.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index bd4c4a7..a9f4117 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -26,6 +26,7 @@ #include <boot/tables.h> #include <delay.h> #include <arch/coreboot_tables.h> +#include "chip.h" #include <device/pci_def.h> #include <device/pci_ops.h> #include <arch/io.h> diff --git a/src/mainboard/lenovo/x60/chip.h b/src/mainboard/lenovo/x60/chip.h new file mode 100644 index 0000000..70f9bb4 --- /dev/null +++ b/src/mainboard/lenovo/x60/chip.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 4ded239..453cf38 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -26,6 +26,7 @@ #include <boot/tables.h> #include <delay.h> #include <arch/coreboot_tables.h> +#include "chip.h" #include <device/pci_def.h> #include <device/pci_ops.h> #include <device/pci_ids.h> diff --git a/src/mainboard/lippert/frontrunner/chip.h b/src/mainboard/lippert/frontrunner/chip.h new file mode 100644 index 0000000..d138e51 --- /dev/null +++ b/src/mainboard/lippert/frontrunner/chip.h @@ -0,0 +1,3 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/lippert/frontrunner/mainboard.c b/src/mainboard/lippert/frontrunner/mainboard.c index ec1503e..7cd9f1d 100644 --- a/src/mainboard/lippert/frontrunner/mainboard.c +++ b/src/mainboard/lippert/frontrunner/mainboard.c @@ -1,4 +1,5 @@ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Lippert Cool Frontrunner Mainboard") diff --git a/src/mainboard/lippert/hurricane-lx/chip.h b/src/mainboard/lippert/hurricane-lx/chip.h new file mode 100644 index 0000000..0c70fcd --- /dev/null +++ b/src/mainboard/lippert/hurricane-lx/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 LiPPERT Embedded Computers GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/lippert/hurricane-lx/mainboard.c b/src/mainboard/lippert/hurricane-lx/mainboard.c index 9b7ad98..959966c 100644 --- a/src/mainboard/lippert/hurricane-lx/mainboard.c +++ b/src/mainboard/lippert/hurricane-lx/mainboard.c @@ -27,6 +27,7 @@ #include <arch/io.h> #include <device/pci.h> #include <device/pci_ids.h> +#include "chip.h" /* Bit1 switches Com1 to RS485, bit2 same for Com2. */ #if CONFIG_ONBOARD_UARTS_RS485 diff --git a/src/mainboard/lippert/literunner-lx/chip.h b/src/mainboard/lippert/literunner-lx/chip.h new file mode 100644 index 0000000..0c70fcd --- /dev/null +++ b/src/mainboard/lippert/literunner-lx/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 LiPPERT Embedded Computers GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/lippert/literunner-lx/mainboard.c b/src/mainboard/lippert/literunner-lx/mainboard.c index cfec2a8..65ea12a 100644 --- a/src/mainboard/lippert/literunner-lx/mainboard.c +++ b/src/mainboard/lippert/literunner-lx/mainboard.c @@ -27,6 +27,7 @@ #include <arch/io.h> #include <device/pci.h> #include <device/pci_ids.h> +#include "chip.h" /* Bit0 turns off the Live LED, bit1 switches Com1 to RS485, bit2 same for Com2. */ #if CONFIG_ONBOARD_UARTS_RS485 diff --git a/src/mainboard/lippert/roadrunner-lx/chip.h b/src/mainboard/lippert/roadrunner-lx/chip.h new file mode 100644 index 0000000..398d424 --- /dev/null +++ b/src/mainboard/lippert/roadrunner-lx/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 LiPPERT Embedded Computers GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/lippert/roadrunner-lx/mainboard.c b/src/mainboard/lippert/roadrunner-lx/mainboard.c index 26adb2f..31fdd46 100644 --- a/src/mainboard/lippert/roadrunner-lx/mainboard.c +++ b/src/mainboard/lippert/roadrunner-lx/mainboard.c @@ -27,6 +27,7 @@ #include <arch/io.h> #include <device/pci.h> #include <device/pci_ids.h> +#include "chip.h" /* Bit1 switches Com1 to RS485, bit2 same for Com2, bit5 turns off the Live LED. */ #if CONFIG_ONBOARD_UARTS_RS485 diff --git a/src/mainboard/lippert/spacerunner-lx/chip.h b/src/mainboard/lippert/spacerunner-lx/chip.h new file mode 100644 index 0000000..398d424 --- /dev/null +++ b/src/mainboard/lippert/spacerunner-lx/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 LiPPERT Embedded Computers GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/lippert/spacerunner-lx/mainboard.c b/src/mainboard/lippert/spacerunner-lx/mainboard.c index f2aeb10..34cd8c4 100644 --- a/src/mainboard/lippert/spacerunner-lx/mainboard.c +++ b/src/mainboard/lippert/spacerunner-lx/mainboard.c @@ -27,6 +27,7 @@ #include <arch/io.h> #include <device/pci.h> #include <device/pci_ids.h> +#include "chip.h" /* Bit0 turns off the Live LED, bit1 switches Com1 to RS485, bit2 same for Com2. */ #if CONFIG_ONBOARD_UARTS_RS485 diff --git a/src/mainboard/mitac/6513wu/chip.h b/src/mainboard/mitac/6513wu/chip.h new file mode 100644 index 0000000..0421977 --- /dev/null +++ b/src/mainboard/mitac/6513wu/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Michael Gold <mgold(a)ncf.ca> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/mitac/6513wu/mainboard.c b/src/mainboard/mitac/6513wu/mainboard.c index 968b9e9..9e4ec8d 100644 --- a/src/mainboard/mitac/6513wu/mainboard.c +++ b/src/mainboard/mitac/6513wu/mainboard.c @@ -20,6 +20,7 @@ #include <device/device.h> #include <boot/tables.h> +#include "chip.h" int add_mainboard_resources(struct lb_memory *mem) { diff --git a/src/mainboard/msi/ms6119/chip.h b/src/mainboard/msi/ms6119/chip.h new file mode 100644 index 0000000..56e17ca --- /dev/null +++ b/src/mainboard/msi/ms6119/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/msi/ms6119/mainboard.c b/src/mainboard/msi/ms6119/mainboard.c index 7ef3d4b..9c4ef29 100644 --- a/src/mainboard/msi/ms6119/mainboard.c +++ b/src/mainboard/msi/ms6119/mainboard.c @@ -19,6 +19,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("MSI MS-6119 Mainboard") diff --git a/src/mainboard/msi/ms6147/chip.h b/src/mainboard/msi/ms6147/chip.h new file mode 100644 index 0000000..fbf5d32 --- /dev/null +++ b/src/mainboard/msi/ms6147/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Mats Erik Andersson <mats.andersson(a)gisladisker.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/msi/ms6147/mainboard.c b/src/mainboard/msi/ms6147/mainboard.c index 091de54..b7c7386 100644 --- a/src/mainboard/msi/ms6147/mainboard.c +++ b/src/mainboard/msi/ms6147/mainboard.c @@ -19,6 +19,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("MSI MS-6147 Mainboard") diff --git a/src/mainboard/msi/ms6156/chip.h b/src/mainboard/msi/ms6156/chip.h new file mode 100644 index 0000000..1c3876d --- /dev/null +++ b/src/mainboard/msi/ms6156/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/msi/ms6156/mainboard.c b/src/mainboard/msi/ms6156/mainboard.c index 28b5e81..1864f0b 100644 --- a/src/mainboard/msi/ms6156/mainboard.c +++ b/src/mainboard/msi/ms6156/mainboard.c @@ -19,6 +19,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("MSI MS-6156 Mainboard") diff --git a/src/mainboard/msi/ms6178/chip.h b/src/mainboard/msi/ms6178/chip.h new file mode 100644 index 0000000..982cfb3 --- /dev/null +++ b/src/mainboard/msi/ms6178/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/msi/ms6178/mainboard.c b/src/mainboard/msi/ms6178/mainboard.c index 0aeedb8..e4ba148 100644 --- a/src/mainboard/msi/ms6178/mainboard.c +++ b/src/mainboard/msi/ms6178/mainboard.c @@ -20,6 +20,7 @@ #include <device/device.h> #include <boot/tables.h> +#include "chip.h" int add_mainboard_resources(struct lb_memory *mem) { diff --git a/src/mainboard/msi/ms7135/chip.h b/src/mainboard/msi/ms7135/chip.h new file mode 100644 index 0000000..063d25b --- /dev/null +++ b/src/mainboard/msi/ms7135/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Jonathan A. Kollasch <jakllsch(a)kollasch.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/msi/ms7135/mainboard.c b/src/mainboard/msi/ms7135/mainboard.c index 3ed0c6b..586f9c5 100644 --- a/src/mainboard/msi/ms7135/mainboard.c +++ b/src/mainboard/msi/ms7135/mainboard.c @@ -19,6 +19,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("MSI MS7135 Mainboard") diff --git a/src/mainboard/msi/ms7260/chip.h b/src/mainboard/msi/ms7260/chip.h new file mode 100644 index 0000000..982cfb3 --- /dev/null +++ b/src/mainboard/msi/ms7260/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/msi/ms7260/mainboard.c b/src/mainboard/msi/ms7260/mainboard.c index 06d606f..2b61736 100644 --- a/src/mainboard/msi/ms7260/mainboard.c +++ b/src/mainboard/msi/ms7260/mainboard.c @@ -19,6 +19,7 @@ */ #include <device/device.h> +#include "chip.h" #if 0 #include "hda_verb.h" diff --git a/src/mainboard/msi/ms9185/chip.h b/src/mainboard/msi/ms9185/chip.h new file mode 100644 index 0000000..6638ef1 --- /dev/null +++ b/src/mainboard/msi/ms9185/chip.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 MSI + * Written by bxshi <bingxunshi(a)gmail.com> for MSI. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; + diff --git a/src/mainboard/msi/ms9185/mainboard.c b/src/mainboard/msi/ms9185/mainboard.c index f3e28d4..873a490 100644 --- a/src/mainboard/msi/ms9185/mainboard.c +++ b/src/mainboard/msi/ms9185/mainboard.c @@ -24,6 +24,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("MSI MS-9185 Mainboard") diff --git a/src/mainboard/msi/ms9282/chip.h b/src/mainboard/msi/ms9282/chip.h new file mode 100644 index 0000000..0831119 --- /dev/null +++ b/src/mainboard/msi/ms9282/chip.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 MSI + * Written by Bingxun Shi <bingxunshi(a)gmail.com> for MSI. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/msi/ms9282/mainboard.c b/src/mainboard/msi/ms9282/mainboard.c index 800fd25..99f7e22 100644 --- a/src/mainboard/msi/ms9282/mainboard.c +++ b/src/mainboard/msi/ms9282/mainboard.c @@ -25,6 +25,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> // #include "hda_verb.h" +#include "chip.h" static void verb_setup(void) { diff --git a/src/mainboard/msi/ms9652_fam10/chip.h b/src/mainboard/msi/ms9652_fam10/chip.h new file mode 100644 index 0000000..ebd990b --- /dev/null +++ b/src/mainboard/msi/ms9652_fam10/chip.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/msi/ms9652_fam10/mainboard.c b/src/mainboard/msi/ms9652_fam10/mainboard.c index e570607..255b22d 100644 --- a/src/mainboard/msi/ms9652_fam10/mainboard.c +++ b/src/mainboard/msi/ms9652_fam10/mainboard.c @@ -25,6 +25,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> // #include "hda_verb.h" +#include "chip.h" static void verb_setup(void) { diff --git a/src/mainboard/nec/powermate2000/chip.h b/src/mainboard/nec/powermate2000/chip.h new file mode 100644 index 0000000..41784c9 --- /dev/null +++ b/src/mainboard/nec/powermate2000/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/nec/powermate2000/mainboard.c b/src/mainboard/nec/powermate2000/mainboard.c index 3b29c7c..a26e8df 100644 --- a/src/mainboard/nec/powermate2000/mainboard.c +++ b/src/mainboard/nec/powermate2000/mainboard.c @@ -20,6 +20,7 @@ #include <device/device.h> #include <boot/tables.h> +#include "chip.h" int add_mainboard_resources(struct lb_memory *mem) { diff --git a/src/mainboard/newisys/khepri/chip.h b/src/mainboard/newisys/khepri/chip.h new file mode 100644 index 0000000..d138e51 --- /dev/null +++ b/src/mainboard/newisys/khepri/chip.h @@ -0,0 +1,3 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/newisys/khepri/mainboard.c b/src/mainboard/newisys/khepri/mainboard.c index 11e7032..d278fd2 100644 --- a/src/mainboard/newisys/khepri/mainboard.c +++ b/src/mainboard/newisys/khepri/mainboard.c @@ -1,4 +1,5 @@ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Newisys 2100 Mainboard") diff --git a/src/mainboard/nokia/ip530/chip.h b/src/mainboard/nokia/ip530/chip.h new file mode 100644 index 0000000..1046412 --- /dev/null +++ b/src/mainboard/nokia/ip530/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Marc Bertens <mbertens(a)xs4all.nl> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/nokia/ip530/mainboard.c b/src/mainboard/nokia/ip530/mainboard.c index 8b934ff..b0dd27b 100644 --- a/src/mainboard/nokia/ip530/mainboard.c +++ b/src/mainboard/nokia/ip530/mainboard.c @@ -19,6 +19,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Nokia IP530 Mainboard") diff --git a/src/mainboard/nvidia/l1_2pvv/chip.h b/src/mainboard/nvidia/l1_2pvv/chip.h new file mode 100644 index 0000000..ebd990b --- /dev/null +++ b/src/mainboard/nvidia/l1_2pvv/chip.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/nvidia/l1_2pvv/mainboard.c b/src/mainboard/nvidia/l1_2pvv/mainboard.c index 5836571..b425c3d 100644 --- a/src/mainboard/nvidia/l1_2pvv/mainboard.c +++ b/src/mainboard/nvidia/l1_2pvv/mainboard.c @@ -25,6 +25,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include "hda_verb.h" +#include "chip.h" static void verb_setup(void) { diff --git a/src/mainboard/pcengines/alix1c/chip.h b/src/mainboard/pcengines/alix1c/chip.h new file mode 100644 index 0000000..fb321d5 --- /dev/null +++ b/src/mainboard/pcengines/alix1c/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/pcengines/alix1c/mainboard.c b/src/mainboard/pcengines/alix1c/mainboard.c index 74c1cc4..a32cb14 100644 --- a/src/mainboard/pcengines/alix1c/mainboard.c +++ b/src/mainboard/pcengines/alix1c/mainboard.c @@ -19,6 +19,7 @@ #include <console/console.h> #include <device/device.h> +#include "chip.h" static void init(struct device *dev) { diff --git a/src/mainboard/pcengines/alix2d/chip.h b/src/mainboard/pcengines/alix2d/chip.h new file mode 100644 index 0000000..fb321d5 --- /dev/null +++ b/src/mainboard/pcengines/alix2d/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/pcengines/alix2d/mainboard.c b/src/mainboard/pcengines/alix2d/mainboard.c index 1b526c9..b227d66 100644 --- a/src/mainboard/pcengines/alix2d/mainboard.c +++ b/src/mainboard/pcengines/alix2d/mainboard.c @@ -19,6 +19,7 @@ #include <console/console.h> #include <device/device.h> +#include "chip.h" static void init(struct device *dev) { diff --git a/src/mainboard/rca/rm4100/chip.h b/src/mainboard/rca/rm4100/chip.h new file mode 100644 index 0000000..4aec17f --- /dev/null +++ b/src/mainboard/rca/rm4100/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Joseph Smith <joe(a)settoplinux.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/rca/rm4100/mainboard.c b/src/mainboard/rca/rm4100/mainboard.c index 613c1d7..653b22a 100644 --- a/src/mainboard/rca/rm4100/mainboard.c +++ b/src/mainboard/rca/rm4100/mainboard.c @@ -21,6 +21,7 @@ #include <device/device.h> #include <boot/tables.h> #include <arch/coreboot_tables.h> +#include "chip.h" int add_mainboard_resources(struct lb_memory *mem) { diff --git a/src/mainboard/roda/rk886ex/chip.h b/src/mainboard/roda/rk886ex/chip.h new file mode 100644 index 0000000..6f24f71 --- /dev/null +++ b/src/mainboard/roda/rk886ex/chip.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/roda/rk886ex/mainboard.c b/src/mainboard/roda/rk886ex/mainboard.c index 1f4ebc7..d87d712 100644 --- a/src/mainboard/roda/rk886ex/mainboard.c +++ b/src/mainboard/roda/rk886ex/mainboard.c @@ -29,6 +29,7 @@ #include <x86emu/x86emu.h> #endif #include <arch/coreboot_tables.h> +#include "chip.h" #include <ec/acpi/ec.h> #include "m3885.h" diff --git a/src/mainboard/samsung/lumpy/chip.h b/src/mainboard/samsung/lumpy/chip.h new file mode 100644 index 0000000..831a973 --- /dev/null +++ b/src/mainboard/samsung/lumpy/chip.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c index 20b59b7..c5db0d3 100644 --- a/src/mainboard/samsung/lumpy/mainboard.c +++ b/src/mainboard/samsung/lumpy/mainboard.c @@ -34,6 +34,7 @@ #include <arch/coreboot_tables.h> #include <ec/smsc/mec1308/ec.h> #include "hda_verb.h" +#include "chip.h" #include "ec.h" #include "onboard.h" #include <southbridge/intel/bd82x6x/pch.h> diff --git a/src/mainboard/samsung/stumpy/chip.h b/src/mainboard/samsung/stumpy/chip.h new file mode 100644 index 0000000..831a973 --- /dev/null +++ b/src/mainboard/samsung/stumpy/chip.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/samsung/stumpy/mainboard.c b/src/mainboard/samsung/stumpy/mainboard.c index 2456e70..9152a3b 100644 --- a/src/mainboard/samsung/stumpy/mainboard.c +++ b/src/mainboard/samsung/stumpy/mainboard.c @@ -34,6 +34,7 @@ #include <arch/interrupt.h> #include <arch/coreboot_tables.h> #include "hda_verb.h" +#include "chip.h" #include <southbridge/intel/bd82x6x/pch.h> void mainboard_suspend_resume(void) diff --git a/src/mainboard/siemens/sitemp_g1p1/chip.h b/src/mainboard/siemens/sitemp_g1p1/chip.h new file mode 100644 index 0000000..ff426e0 --- /dev/null +++ b/src/mainboard/siemens/sitemp_g1p1/chip.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2010 Siemens AG, Inc. + * (Written by Josef Kellermann <joseph.kellermann(a)heitec.de> for Siemens AG, Inc.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config +{ + u32 uma_size; /* How many UMA should be used in memory for TOP. */ + unsigned int plx_present : 1; +}; + diff --git a/src/mainboard/siemens/sitemp_g1p1/mainboard.c b/src/mainboard/siemens/sitemp_g1p1/mainboard.c index 905d23f..05435d8 100644 --- a/src/mainboard/siemens/sitemp_g1p1/mainboard.c +++ b/src/mainboard/siemens/sitemp_g1p1/mainboard.c @@ -34,6 +34,7 @@ #include <southbridge/amd/rs690/chip.h> #include <southbridge/amd/rs690/rs690.h> #include <superio/ite/it8712f/it8712f.h> +#include "chip.h" #if CONFIG_PCI_OPTION_ROM_RUN_YABEL #include <x86emu/x86emu.h> #endif @@ -672,14 +673,13 @@ struct { }; -unsigned int plx_present = 0; +static void update_subsystemid( device_t dev ) { -static void update_subsystemid( device_t dev ) -{ int i; + struct mainboard_config *mb = dev->chip_info; dev->subsystem_vendor = 0x110a; - if( plx_present ){ + if( mb->plx_present ){ dev->subsystem_device = 0x4076; // U1P1 = 0x4076, U1P0 = 0x4077 } else { dev->subsystem_device = 0x4077; // U1P0 = 0x4077 @@ -701,12 +701,12 @@ static void update_subsystemid( device_t dev ) * @param */ -static void detect_hw_variant( device_t dev ) -{ +static void detect_hw_variant( device_t dev ) { device_t nb_dev =0, dev2 = 0; struct southbridge_amd_rs690_config *cfg; u32 lc_state, id = 0; + struct mainboard_config *mb = dev->chip_info; printk(BIOS_INFO, "Scan for PLX device ...\n"); nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); @@ -782,10 +782,10 @@ static void detect_hw_variant( device_t dev ) break; } - plx_present = 0; + mb->plx_present = 0; if( id == PLX_VIDDID ){ printk(BIOS_INFO, "found PLX device\n"); - plx_present = 1; + mb->plx_present = 1; cfg = (struct southbridge_amd_rs690_config *)dev2->chip_info; if( cfg->gfx_tmds ) { printk(BIOS_INFO, "Disable 'gfx_tmds' support\n"); diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/chip.h b/src/mainboard/soyo/sy-6ba-plus-iii/chip.h new file mode 100644 index 0000000..1c3876d --- /dev/null +++ b/src/mainboard/soyo/sy-6ba-plus-iii/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/mainboard.c b/src/mainboard/soyo/sy-6ba-plus-iii/mainboard.c index 9e7b1f2..4cead76 100644 --- a/src/mainboard/soyo/sy-6ba-plus-iii/mainboard.c +++ b/src/mainboard/soyo/sy-6ba-plus-iii/mainboard.c @@ -19,6 +19,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Soyo SY-6BA+ III Mainboard") diff --git a/src/mainboard/sunw/ultra40/chip.h b/src/mainboard/sunw/ultra40/chip.h new file mode 100644 index 0000000..d138e51 --- /dev/null +++ b/src/mainboard/sunw/ultra40/chip.h @@ -0,0 +1,3 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/sunw/ultra40/mainboard.c b/src/mainboard/sunw/ultra40/mainboard.c index d46ea38..b5e865d 100644 --- a/src/mainboard/sunw/ultra40/mainboard.c +++ b/src/mainboard/sunw/ultra40/mainboard.c @@ -1,4 +1,5 @@ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Sun Ultra 40 Mainboard") diff --git a/src/mainboard/supermicro/h8dme/chip.h b/src/mainboard/supermicro/h8dme/chip.h new file mode 100644 index 0000000..2076c6f --- /dev/null +++ b/src/mainboard/supermicro/h8dme/chip.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/supermicro/h8dme/mainboard.c b/src/mainboard/supermicro/h8dme/mainboard.c index c092c71..c1b9635 100644 --- a/src/mainboard/supermicro/h8dme/mainboard.c +++ b/src/mainboard/supermicro/h8dme/mainboard.c @@ -19,6 +19,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Supermicro H8DME Mainboard") diff --git a/src/mainboard/supermicro/h8dmr/chip.h b/src/mainboard/supermicro/h8dmr/chip.h new file mode 100644 index 0000000..ebd990b --- /dev/null +++ b/src/mainboard/supermicro/h8dmr/chip.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/supermicro/h8dmr/mainboard.c b/src/mainboard/supermicro/h8dmr/mainboard.c index 45536af..a00d9e8 100644 --- a/src/mainboard/supermicro/h8dmr/mainboard.c +++ b/src/mainboard/supermicro/h8dmr/mainboard.c @@ -20,6 +20,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Supermicro H8DMR Mainboard") diff --git a/src/mainboard/supermicro/h8dmr_fam10/chip.h b/src/mainboard/supermicro/h8dmr_fam10/chip.h new file mode 100644 index 0000000..ebd990b --- /dev/null +++ b/src/mainboard/supermicro/h8dmr_fam10/chip.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/supermicro/h8dmr_fam10/mainboard.c b/src/mainboard/supermicro/h8dmr_fam10/mainboard.c index 24736a9..e59a980 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/mainboard.c +++ b/src/mainboard/supermicro/h8dmr_fam10/mainboard.c @@ -20,6 +20,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Supermicro H8DMR Mainboard (Family 10)") diff --git a/src/mainboard/supermicro/h8qgi/chip.h b/src/mainboard/supermicro/h8qgi/chip.h new file mode 100644 index 0000000..a252705 --- /dev/null +++ b/src/mainboard/supermicro/h8qgi/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/supermicro/h8qgi/mainboard.c b/src/mainboard/supermicro/h8qgi/mainboard.c index 1f02c73..f6d437e 100644 --- a/src/mainboard/supermicro/h8qgi/mainboard.c +++ b/src/mainboard/supermicro/h8qgi/mainboard.c @@ -26,6 +26,7 @@ #include <cpu/amd/mtrr.h> #include <device/pci_def.h> #include <NbPlatform.h> +#include "chip.h" void set_pcie_dereset(void *nbconfig); void set_pcie_reset(void *nbconfig); diff --git a/src/mainboard/supermicro/h8qme_fam10/chip.h b/src/mainboard/supermicro/h8qme_fam10/chip.h new file mode 100644 index 0000000..ebd990b --- /dev/null +++ b/src/mainboard/supermicro/h8qme_fam10/chip.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/supermicro/h8qme_fam10/mainboard.c b/src/mainboard/supermicro/h8qme_fam10/mainboard.c index 647f623..45b0920 100644 --- a/src/mainboard/supermicro/h8qme_fam10/mainboard.c +++ b/src/mainboard/supermicro/h8qme_fam10/mainboard.c @@ -20,6 +20,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Supermicro H8QME-2+ Mainboard (Family 10)") diff --git a/src/mainboard/supermicro/h8scm_fam10/chip.h b/src/mainboard/supermicro/h8scm_fam10/chip.h new file mode 100644 index 0000000..a98b97e --- /dev/null +++ b/src/mainboard/supermicro/h8scm_fam10/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/supermicro/h8scm_fam10/mainboard.c b/src/mainboard/supermicro/h8scm_fam10/mainboard.c index e5a58fe..d0fb541 100644 --- a/src/mainboard/supermicro/h8scm_fam10/mainboard.c +++ b/src/mainboard/supermicro/h8scm_fam10/mainboard.c @@ -27,6 +27,7 @@ #include <device/pci_def.h> #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sr5650/cmn.h> +#include "chip.h" void set_pcie_reset(void); @@ -72,6 +73,10 @@ void set_pcie_dereset(void) *************************************************/ static void h8scm_enable(device_t dev) { + /* Leave it for furture use. */ + /* struct mainboard_config *mainboard = + (struct mainboard_config *)dev->chip_info; */ + printk(BIOS_INFO, "Mainboard H8SCM Enable. dev=0x%p\n", dev); msr_t msr, msr2; diff --git a/src/mainboard/supermicro/x6dai_g/chip.h b/src/mainboard/supermicro/x6dai_g/chip.h new file mode 100644 index 0000000..d138e51 --- /dev/null +++ b/src/mainboard/supermicro/x6dai_g/chip.h @@ -0,0 +1,3 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/supermicro/x6dai_g/mainboard.c b/src/mainboard/supermicro/x6dai_g/mainboard.c index d9b4bc4..1db8cd4 100644 --- a/src/mainboard/supermicro/x6dai_g/mainboard.c +++ b/src/mainboard/supermicro/x6dai_g/mainboard.c @@ -1,4 +1,5 @@ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Supermicro X6DAi-G Mainboard") diff --git a/src/mainboard/supermicro/x6dhe_g/chip.h b/src/mainboard/supermicro/x6dhe_g/chip.h new file mode 100644 index 0000000..d138e51 --- /dev/null +++ b/src/mainboard/supermicro/x6dhe_g/chip.h @@ -0,0 +1,3 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/supermicro/x6dhe_g/mainboard.c b/src/mainboard/supermicro/x6dhe_g/mainboard.c index c09c95a..a242ddd 100644 --- a/src/mainboard/supermicro/x6dhe_g/mainboard.c +++ b/src/mainboard/supermicro/x6dhe_g/mainboard.c @@ -1,4 +1,5 @@ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Supermicro X6DHE-G Mainboard") diff --git a/src/mainboard/supermicro/x6dhe_g2/chip.h b/src/mainboard/supermicro/x6dhe_g2/chip.h new file mode 100644 index 0000000..d138e51 --- /dev/null +++ b/src/mainboard/supermicro/x6dhe_g2/chip.h @@ -0,0 +1,3 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/supermicro/x6dhe_g2/mainboard.c b/src/mainboard/supermicro/x6dhe_g2/mainboard.c index c20a842..fdb67cc 100644 --- a/src/mainboard/supermicro/x6dhe_g2/mainboard.c +++ b/src/mainboard/supermicro/x6dhe_g2/mainboard.c @@ -1,4 +1,5 @@ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Supermicro X6DHE-G2 Mainboard") diff --git a/src/mainboard/supermicro/x6dhr_ig/chip.h b/src/mainboard/supermicro/x6dhr_ig/chip.h new file mode 100644 index 0000000..d138e51 --- /dev/null +++ b/src/mainboard/supermicro/x6dhr_ig/chip.h @@ -0,0 +1,3 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/supermicro/x6dhr_ig/mainboard.c b/src/mainboard/supermicro/x6dhr_ig/mainboard.c index 3875fe0..51acb86 100644 --- a/src/mainboard/supermicro/x6dhr_ig/mainboard.c +++ b/src/mainboard/supermicro/x6dhr_ig/mainboard.c @@ -1,4 +1,5 @@ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Supermicro X6DHR-iG Mainboard") diff --git a/src/mainboard/supermicro/x6dhr_ig2/chip.h b/src/mainboard/supermicro/x6dhr_ig2/chip.h new file mode 100644 index 0000000..d138e51 --- /dev/null +++ b/src/mainboard/supermicro/x6dhr_ig2/chip.h @@ -0,0 +1,3 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/supermicro/x6dhr_ig2/mainboard.c b/src/mainboard/supermicro/x6dhr_ig2/mainboard.c index 981aee8..6b6c64f 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/mainboard.c +++ b/src/mainboard/supermicro/x6dhr_ig2/mainboard.c @@ -1,4 +1,5 @@ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Supermicro X6DHR-iG2 Mainboard") diff --git a/src/mainboard/supermicro/x7db8/chip.h b/src/mainboard/supermicro/x7db8/chip.h new file mode 100644 index 0000000..70f9bb4 --- /dev/null +++ b/src/mainboard/supermicro/x7db8/chip.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/supermicro/x7db8/mainboard.c b/src/mainboard/supermicro/x7db8/mainboard.c index 618eca9..27a26f9 100644 --- a/src/mainboard/supermicro/x7db8/mainboard.c +++ b/src/mainboard/supermicro/x7db8/mainboard.c @@ -25,6 +25,7 @@ #include <boot/tables.h> #include <delay.h> #include <arch/coreboot_tables.h> +#include "chip.h" #include <device/pci_def.h> #include <device/pci_ops.h> #include <arch/io.h> diff --git a/src/mainboard/technexion/tim5690/chip.h b/src/mainboard/technexion/tim5690/chip.h new file mode 100644 index 0000000..05e1582 --- /dev/null +++ b/src/mainboard/technexion/tim5690/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; + diff --git a/src/mainboard/technexion/tim5690/mainboard.c b/src/mainboard/technexion/tim5690/mainboard.c index 2975e86..5a22182 100644 --- a/src/mainboard/technexion/tim5690/mainboard.c +++ b/src/mainboard/technexion/tim5690/mainboard.c @@ -27,6 +27,7 @@ #include <device/pci_def.h> #include <southbridge/amd/sb600/sb600.h> #include <superio/ite/it8712f/it8712f.h> +#include "chip.h" #include "tn_post_code.h" #include "vgabios.h" diff --git a/src/mainboard/technexion/tim8690/chip.h b/src/mainboard/technexion/tim8690/chip.h new file mode 100644 index 0000000..05e1582 --- /dev/null +++ b/src/mainboard/technexion/tim8690/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; + diff --git a/src/mainboard/technexion/tim8690/mainboard.c b/src/mainboard/technexion/tim8690/mainboard.c index 40ab345..f7ec110 100644 --- a/src/mainboard/technexion/tim8690/mainboard.c +++ b/src/mainboard/technexion/tim8690/mainboard.c @@ -26,6 +26,7 @@ #include <cpu/amd/mtrr.h> #include <device/pci_def.h> #include <southbridge/amd/sb600/sb600.h> +#include "chip.h" #define ADT7461_ADDRESS 0x4C #define ARA_ADDRESS 0x0C /* Alert Response Address */ diff --git a/src/mainboard/technologic/ts5300/chip.h b/src/mainboard/technologic/ts5300/chip.h new file mode 100644 index 0000000..d138e51 --- /dev/null +++ b/src/mainboard/technologic/ts5300/chip.h @@ -0,0 +1,3 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/technologic/ts5300/mainboard.c b/src/mainboard/technologic/ts5300/mainboard.c index 164b7e8..58333b8 100644 --- a/src/mainboard/technologic/ts5300/mainboard.c +++ b/src/mainboard/technologic/ts5300/mainboard.c @@ -4,6 +4,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <cpu/amd/sc520.h> +#include "chip.h" #if 0 diff --git a/src/mainboard/televideo/tc7020/chip.h b/src/mainboard/televideo/tc7020/chip.h new file mode 100644 index 0000000..6b6d455 --- /dev/null +++ b/src/mainboard/televideo/tc7020/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Kenji Noguchi <tokyo246(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/televideo/tc7020/mainboard.c b/src/mainboard/televideo/tc7020/mainboard.c index ee41109..a0919dc 100644 --- a/src/mainboard/televideo/tc7020/mainboard.c +++ b/src/mainboard/televideo/tc7020/mainboard.c @@ -19,6 +19,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("TeleVideo TC7020 Mainboard") diff --git a/src/mainboard/thomson/ip1000/chip.h b/src/mainboard/thomson/ip1000/chip.h new file mode 100644 index 0000000..4aec17f --- /dev/null +++ b/src/mainboard/thomson/ip1000/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Joseph Smith <joe(a)settoplinux.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/thomson/ip1000/mainboard.c b/src/mainboard/thomson/ip1000/mainboard.c index e5c3ea1..f6eee68 100644 --- a/src/mainboard/thomson/ip1000/mainboard.c +++ b/src/mainboard/thomson/ip1000/mainboard.c @@ -27,6 +27,7 @@ #endif #include <arch/coreboot_tables.h> #include <arch/io.h> +#include "chip.h" int add_mainboard_resources(struct lb_memory *mem) { diff --git a/src/mainboard/traverse/geos/chip.h b/src/mainboard/traverse/geos/chip.h new file mode 100644 index 0000000..ae69536 --- /dev/null +++ b/src/mainboard/traverse/geos/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/traverse/geos/mainboard.c b/src/mainboard/traverse/geos/mainboard.c index c299bc8..b578959 100644 --- a/src/mainboard/traverse/geos/mainboard.c +++ b/src/mainboard/traverse/geos/mainboard.c @@ -19,6 +19,7 @@ #include <console/console.h> #include <device/device.h> +#include "chip.h" static void init(struct device *dev) { diff --git a/src/mainboard/tyan/s1846/chip.h b/src/mainboard/tyan/s1846/chip.h new file mode 100644 index 0000000..dc9bed3 --- /dev/null +++ b/src/mainboard/tyan/s1846/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/tyan/s1846/mainboard.c b/src/mainboard/tyan/s1846/mainboard.c index fb2034c..e5ab1c9 100644 --- a/src/mainboard/tyan/s1846/mainboard.c +++ b/src/mainboard/tyan/s1846/mainboard.c @@ -19,6 +19,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Tyan S1846 Mainboard") diff --git a/src/mainboard/tyan/s2735/chip.h b/src/mainboard/tyan/s2735/chip.h new file mode 100644 index 0000000..d138e51 --- /dev/null +++ b/src/mainboard/tyan/s2735/chip.h @@ -0,0 +1,3 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/tyan/s2735/mainboard.c b/src/mainboard/tyan/s2735/mainboard.c index 5456b9e..267755c 100644 --- a/src/mainboard/tyan/s2735/mainboard.c +++ b/src/mainboard/tyan/s2735/mainboard.c @@ -1,4 +1,5 @@ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Tyan S2735 Mainboard") diff --git a/src/mainboard/tyan/s2850/chip.h b/src/mainboard/tyan/s2850/chip.h new file mode 100644 index 0000000..d138e51 --- /dev/null +++ b/src/mainboard/tyan/s2850/chip.h @@ -0,0 +1,3 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/tyan/s2850/mainboard.c b/src/mainboard/tyan/s2850/mainboard.c index 137aa57..8afa8f0 100644 --- a/src/mainboard/tyan/s2850/mainboard.c +++ b/src/mainboard/tyan/s2850/mainboard.c @@ -1,4 +1,5 @@ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Tyan S2850 Mainboard") diff --git a/src/mainboard/tyan/s2875/chip.h b/src/mainboard/tyan/s2875/chip.h new file mode 100644 index 0000000..d138e51 --- /dev/null +++ b/src/mainboard/tyan/s2875/chip.h @@ -0,0 +1,3 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/tyan/s2875/mainboard.c b/src/mainboard/tyan/s2875/mainboard.c index cbc4c6c..49e1092 100644 --- a/src/mainboard/tyan/s2875/mainboard.c +++ b/src/mainboard/tyan/s2875/mainboard.c @@ -1,4 +1,5 @@ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Tyan S2875 Mainboard") diff --git a/src/mainboard/tyan/s2880/chip.h b/src/mainboard/tyan/s2880/chip.h new file mode 100644 index 0000000..d138e51 --- /dev/null +++ b/src/mainboard/tyan/s2880/chip.h @@ -0,0 +1,3 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/tyan/s2880/mainboard.c b/src/mainboard/tyan/s2880/mainboard.c index 96e3cf2..7fc8615 100644 --- a/src/mainboard/tyan/s2880/mainboard.c +++ b/src/mainboard/tyan/s2880/mainboard.c @@ -1,4 +1,5 @@ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Tyan S2880 Mainboard") diff --git a/src/mainboard/tyan/s2881/chip.h b/src/mainboard/tyan/s2881/chip.h new file mode 100644 index 0000000..d138e51 --- /dev/null +++ b/src/mainboard/tyan/s2881/chip.h @@ -0,0 +1,3 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/tyan/s2881/mainboard.c b/src/mainboard/tyan/s2881/mainboard.c index 5034c5d..9da5fe8 100644 --- a/src/mainboard/tyan/s2881/mainboard.c +++ b/src/mainboard/tyan/s2881/mainboard.c @@ -21,6 +21,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Tyan S2881 Mainboard") diff --git a/src/mainboard/tyan/s2882/chip.h b/src/mainboard/tyan/s2882/chip.h new file mode 100644 index 0000000..d138e51 --- /dev/null +++ b/src/mainboard/tyan/s2882/chip.h @@ -0,0 +1,3 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/tyan/s2882/mainboard.c b/src/mainboard/tyan/s2882/mainboard.c index 771d8b6..0779df1 100644 --- a/src/mainboard/tyan/s2882/mainboard.c +++ b/src/mainboard/tyan/s2882/mainboard.c @@ -1,4 +1,5 @@ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Tyan S2882 Mainboard") diff --git a/src/mainboard/tyan/s2885/chip.h b/src/mainboard/tyan/s2885/chip.h new file mode 100644 index 0000000..d138e51 --- /dev/null +++ b/src/mainboard/tyan/s2885/chip.h @@ -0,0 +1,3 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/tyan/s2885/mainboard.c b/src/mainboard/tyan/s2885/mainboard.c index 446460d..27da722 100644 --- a/src/mainboard/tyan/s2885/mainboard.c +++ b/src/mainboard/tyan/s2885/mainboard.c @@ -1,4 +1,5 @@ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Tyan S2885 Mainboard") diff --git a/src/mainboard/tyan/s2891/chip.h b/src/mainboard/tyan/s2891/chip.h new file mode 100644 index 0000000..d138e51 --- /dev/null +++ b/src/mainboard/tyan/s2891/chip.h @@ -0,0 +1,3 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/tyan/s2891/mainboard.c b/src/mainboard/tyan/s2891/mainboard.c index 155f084..c529c0a 100644 --- a/src/mainboard/tyan/s2891/mainboard.c +++ b/src/mainboard/tyan/s2891/mainboard.c @@ -1,4 +1,5 @@ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Tyan S2891 Mainboard") diff --git a/src/mainboard/tyan/s2892/chip.h b/src/mainboard/tyan/s2892/chip.h new file mode 100644 index 0000000..d138e51 --- /dev/null +++ b/src/mainboard/tyan/s2892/chip.h @@ -0,0 +1,3 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/tyan/s2892/mainboard.c b/src/mainboard/tyan/s2892/mainboard.c index 10fd0c0..299f836 100644 --- a/src/mainboard/tyan/s2892/mainboard.c +++ b/src/mainboard/tyan/s2892/mainboard.c @@ -1,4 +1,5 @@ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Tyan S2892 Mainboard") diff --git a/src/mainboard/tyan/s2895/chip.h b/src/mainboard/tyan/s2895/chip.h new file mode 100644 index 0000000..d138e51 --- /dev/null +++ b/src/mainboard/tyan/s2895/chip.h @@ -0,0 +1,3 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/tyan/s2895/mainboard.c b/src/mainboard/tyan/s2895/mainboard.c index 4de60af..f152eae 100644 --- a/src/mainboard/tyan/s2895/mainboard.c +++ b/src/mainboard/tyan/s2895/mainboard.c @@ -1,4 +1,5 @@ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Tyan S2895 Mainboard") diff --git a/src/mainboard/tyan/s2912/chip.h b/src/mainboard/tyan/s2912/chip.h new file mode 100644 index 0000000..ebd990b --- /dev/null +++ b/src/mainboard/tyan/s2912/chip.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/tyan/s2912/mainboard.c b/src/mainboard/tyan/s2912/mainboard.c index bfdb75e..6084b3d 100644 --- a/src/mainboard/tyan/s2912/mainboard.c +++ b/src/mainboard/tyan/s2912/mainboard.c @@ -20,6 +20,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Tyan S2912 Mainboard") diff --git a/src/mainboard/tyan/s2912_fam10/chip.h b/src/mainboard/tyan/s2912_fam10/chip.h new file mode 100644 index 0000000..ebd990b --- /dev/null +++ b/src/mainboard/tyan/s2912_fam10/chip.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/tyan/s2912_fam10/mainboard.c b/src/mainboard/tyan/s2912_fam10/mainboard.c index 3fed2f8..f976b14 100644 --- a/src/mainboard/tyan/s2912_fam10/mainboard.c +++ b/src/mainboard/tyan/s2912_fam10/mainboard.c @@ -20,6 +20,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Tyan S2912 Mainboard (Family 10)") diff --git a/src/mainboard/tyan/s4880/chip.h b/src/mainboard/tyan/s4880/chip.h new file mode 100644 index 0000000..d138e51 --- /dev/null +++ b/src/mainboard/tyan/s4880/chip.h @@ -0,0 +1,3 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/tyan/s4880/mainboard.c b/src/mainboard/tyan/s4880/mainboard.c index ad9adab..f2f865b 100644 --- a/src/mainboard/tyan/s4880/mainboard.c +++ b/src/mainboard/tyan/s4880/mainboard.c @@ -1,4 +1,5 @@ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Tyan S4880 Mainboard") diff --git a/src/mainboard/tyan/s4882/chip.h b/src/mainboard/tyan/s4882/chip.h new file mode 100644 index 0000000..d138e51 --- /dev/null +++ b/src/mainboard/tyan/s4882/chip.h @@ -0,0 +1,3 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/tyan/s4882/mainboard.c b/src/mainboard/tyan/s4882/mainboard.c index 0595d59..8d626c7 100644 --- a/src/mainboard/tyan/s4882/mainboard.c +++ b/src/mainboard/tyan/s4882/mainboard.c @@ -1,4 +1,5 @@ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("Tyan S4882 Mainboard") diff --git a/src/mainboard/via/epia-cn/chip.h b/src/mainboard/via/epia-cn/chip.h new file mode 100644 index 0000000..0a2badb --- /dev/null +++ b/src/mainboard/via/epia-cn/chip.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 VIA Technologies, Inc. + * (Written by Aaron Lwe <aaron.lwe(a)gmail.com> for VIA) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/via/epia-cn/mainboard.c b/src/mainboard/via/epia-cn/mainboard.c index 702b5b0..1a7210e 100644 --- a/src/mainboard/via/epia-cn/mainboard.c +++ b/src/mainboard/via/epia-cn/mainboard.c @@ -20,6 +20,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("VIA EPIA-CN Mainboard") diff --git a/src/mainboard/via/epia-m/chip.h b/src/mainboard/via/epia-m/chip.h new file mode 100644 index 0000000..d138e51 --- /dev/null +++ b/src/mainboard/via/epia-m/chip.h @@ -0,0 +1,3 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/via/epia-m/mainboard.c b/src/mainboard/via/epia-m/mainboard.c index 49f18df..2e517a3 100644 --- a/src/mainboard/via/epia-m/mainboard.c +++ b/src/mainboard/via/epia-m/mainboard.c @@ -1,4 +1,5 @@ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("VIA EPIA-M Mainboard") diff --git a/src/mainboard/via/epia-m700/chip.h b/src/mainboard/via/epia-m700/chip.h new file mode 100644 index 0000000..c44330b --- /dev/null +++ b/src/mainboard/via/epia-m700/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 One Laptop per Child, Association, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/via/epia-m700/mainboard.c b/src/mainboard/via/epia-m700/mainboard.c index 53537e0..5a21b86 100644 --- a/src/mainboard/via/epia-m700/mainboard.c +++ b/src/mainboard/via/epia-m700/mainboard.c @@ -19,6 +19,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("VIA EPIA-M700 Mainboard") diff --git a/src/mainboard/via/epia-n/chip.h b/src/mainboard/via/epia-n/chip.h new file mode 100644 index 0000000..0a2badb --- /dev/null +++ b/src/mainboard/via/epia-n/chip.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 VIA Technologies, Inc. + * (Written by Aaron Lwe <aaron.lwe(a)gmail.com> for VIA) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/via/epia-n/mainboard.c b/src/mainboard/via/epia-n/mainboard.c index 0dfbd3c..cf5ae96 100644 --- a/src/mainboard/via/epia-n/mainboard.c +++ b/src/mainboard/via/epia-n/mainboard.c @@ -26,6 +26,7 @@ #include <arch/ioapic.h> #include <southbridge/via/vt8237r/vt8237r.h> #include <cpu/x86/lapic_def.h> +#include "chip.h" int add_mainboard_resources(struct lb_memory *mem) { diff --git a/src/mainboard/via/epia/chip.h b/src/mainboard/via/epia/chip.h new file mode 100644 index 0000000..d138e51 --- /dev/null +++ b/src/mainboard/via/epia/chip.h @@ -0,0 +1,3 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/via/epia/mainboard.c b/src/mainboard/via/epia/mainboard.c index 95edf46..25d72a5 100644 --- a/src/mainboard/via/epia/mainboard.c +++ b/src/mainboard/via/epia/mainboard.c @@ -1,4 +1,5 @@ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("VIA EPIA Mainboard") diff --git a/src/mainboard/via/pc2500e/chip.h b/src/mainboard/via/pc2500e/chip.h new file mode 100644 index 0000000..41784c9 --- /dev/null +++ b/src/mainboard/via/pc2500e/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/via/pc2500e/mainboard.c b/src/mainboard/via/pc2500e/mainboard.c index 65aed56..9fcee55 100644 --- a/src/mainboard/via/pc2500e/mainboard.c +++ b/src/mainboard/via/pc2500e/mainboard.c @@ -19,6 +19,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("VIA pc2500e Mainboard") diff --git a/src/mainboard/via/vt8454c/chip.h b/src/mainboard/via/vt8454c/chip.h new file mode 100644 index 0000000..5101c16 --- /dev/null +++ b/src/mainboard/via/vt8454c/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/via/vt8454c/mainboard.c b/src/mainboard/via/vt8454c/mainboard.c index c6e1b92..e931ccd 100644 --- a/src/mainboard/via/vt8454c/mainboard.c +++ b/src/mainboard/via/vt8454c/mainboard.c @@ -20,6 +20,7 @@ */ #include <device/device.h> +#include "chip.h" struct chip_operations mainboard_ops = { CHIP_NAME("VIA VT8454c Mainboard") diff --git a/src/mainboard/winent/pl6064/chip.h b/src/mainboard/winent/pl6064/chip.h new file mode 100644 index 0000000..ae69536 --- /dev/null +++ b/src/mainboard/winent/pl6064/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/winent/pl6064/mainboard.c b/src/mainboard/winent/pl6064/mainboard.c index 0293c7a..cd664f6 100644 --- a/src/mainboard/winent/pl6064/mainboard.c +++ b/src/mainboard/winent/pl6064/mainboard.c @@ -19,6 +19,7 @@ #include <console/console.h> #include <device/device.h> +#include "chip.h" static void init(struct device *dev) { diff --git a/src/mainboard/wyse/s50/chip.h b/src/mainboard/wyse/s50/chip.h new file mode 100644 index 0000000..e0e9727 --- /dev/null +++ b/src/mainboard/wyse/s50/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Nils Jacobs + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/wyse/s50/mainboard.c b/src/mainboard/wyse/s50/mainboard.c index 99dfb42..8497b24 100644 --- a/src/mainboard/wyse/s50/mainboard.c +++ b/src/mainboard/wyse/s50/mainboard.c @@ -21,6 +21,7 @@ #include <console/console.h> #include <device/device.h> +#include "chip.h" static void init(struct device *dev) { diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 824bc6c..989f747 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -45,11 +45,7 @@ static struct device mainboard = { .id = 0, .chip = &mainboard, .type = chip, -#ifdef MAINBOARDS_HAVE_CHIP_H .chiph_exists = 1, -#else - .chiph_exists = 0, -#endif .children = &root }; @@ -565,14 +561,12 @@ int main(int argc, char** argv) { } headers.next = 0; -#ifdef MAINBOARDS_HAVE_CHIP_H if (scan_mode == STATIC_MODE) { headers.next = malloc(sizeof(struct header)); headers.next->name = malloc(strlen(mainboard)+12); headers.next->next = 0; sprintf(headers.next->name, "mainboard/%s", mainboard); } -#endif FILE *filec = fopen(devtree, "r"); if (!filec) { @@ -616,11 +610,8 @@ int main(int argc, char** argv) { walk_device_tree(autogen, &root, inherit_subsystem_ids, NULL); fprintf(autogen, "\n/* pass 0 */\n"); walk_device_tree(autogen, &root, pass0, NULL); - fprintf(autogen, "\n/* pass 1 */\n" - "struct device *last_dev = &%s;\n", lastdev->name); -#ifdef MAINBOARDS_HAVE_CHIP_H - fprintf(autogen, "struct mainboard_config mainboard_info_0;\n"); -#endif + fprintf(autogen, "\n/* pass 1 */\nstruct mainboard_config mainboard_info_0;\n" + "struct device *last_dev = &%s;\n", lastdev->name); walk_device_tree(autogen, &root, pass1, NULL); } else if (scan_mode == BOOTBLOCK_MODE) {

1 0

New patch to review for coreboot: 760338b Revert "Fix mainboard level enable_dev()"
by Stefan Reinauer 07 Aug '12

07 Aug '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1419 -gerrit commit 760338b6a17e992c8cdf918c6a1dbdd322bee3f0 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Aug 7 22:11:42 2012 +0200 Revert "Fix mainboard level enable_dev()" This reverts commit 15cf0adc3edaf184d98a3b3c228e0858ff7b24d3 There is more stuff broken. Hence backing out the complete chip.h removal. --- src/devices/device.c | 4 ++-- src/include/device/device.h | 1 - src/mainboard/emulation/qemu-x86/chip.h | 4 ++++ 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/src/devices/device.c b/src/devices/device.c index 344f824..6b1902d 100644 --- a/src/devices/device.c +++ b/src/devices/device.c @@ -923,8 +923,8 @@ void dev_enumerate(void) printk(BIOS_SPEW, "Compare with tree...\n"); show_devs_tree(root, BIOS_SPEW, 0, 0); - if (mainboard_ops.enable_dev) - mainboard_ops.enable_dev(root); + if (root->chip_ops && root->chip_ops->enable_dev) + root->chip_ops->enable_dev(root); if (!root->ops || !root->ops->scan_bus) { printk(BIOS_ERR, "dev_root missing scan_bus operation"); diff --git a/src/include/device/device.h b/src/include/device/device.h index 0b15ac5..9e9d000 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -165,7 +165,6 @@ void show_all_devs_resources(int debug_level, const char* msg); #define DEVICE_MEM_ALIGN 4096 extern struct device_operations default_dev_ops_root; -extern struct chip_operations mainboard_ops; void pci_domain_read_resources(struct device *dev); unsigned int pci_domain_scan_bus(struct device *dev, unsigned int max); unsigned int scan_static_bus(device_t bus, unsigned int max); diff --git a/src/mainboard/emulation/qemu-x86/chip.h b/src/mainboard/emulation/qemu-x86/chip.h index ff9301f..56a14ed 100644 --- a/src/mainboard/emulation/qemu-x86/chip.h +++ b/src/mainboard/emulation/qemu-x86/chip.h @@ -1,3 +1,7 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; + struct mainboard_emulation_qemu_x86_config {}; extern struct chip_operations mainboard_emulation_qemu_x86_ops;

1 0

New patch to review for coreboot: 2ed8104 AMD northbridges: factor out CPU allocation
by Kyösti Mälkki 07 Aug '12

07 Aug '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1418 -gerrit commit 2ed8104b9e82e59391138c256b3b2b1b94d802ed Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Aug 7 17:12:11 2012 +0300 AMD northbridges: factor out CPU allocation Factor CPU allocation out of AMD northbridge codes. As CPU topology information is required for generation of certain ACPI tables, make this code globally available. For AMDK8 and AMDFAM10 northbridge, there is a possible case of BSP CPU with lapicid!=0. We do not want to leave the lapic 0 from devicetree unused, so always use that node for BSP CPU. Change-Id: I8b1e73ed5b20b314f71dfd69a7b781ac05aea120 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/devices/Makefile.inc | 1 + src/devices/cpu_device.c | 71 ++++++++++++++++++++ src/include/device/device.h | 10 +++ src/include/device/path.h | 2 + src/northbridge/amd/agesa/family10/northbridge.c | 23 +----- src/northbridge/amd/agesa/family14/northbridge.c | 17 +---- src/northbridge/amd/agesa/family15/northbridge.c | 26 ++------ src/northbridge/amd/agesa/family15tn/northbridge.c | 26 ++------ src/northbridge/amd/amdfam10/northbridge.c | 32 +++------ src/northbridge/amd/amdk8/northbridge.c | 36 +++------- 10 files changed, 124 insertions(+), 120 deletions(-) diff --git a/src/devices/Makefile.inc b/src/devices/Makefile.inc index 9a2f71e..9d4b391 100644 --- a/src/devices/Makefile.inc +++ b/src/devices/Makefile.inc @@ -1,5 +1,6 @@ ramstage-y += device.c ramstage-y += root_device.c +ramstage-y += cpu_device.c ramstage-y += device_util.c ramstage-y += pci_device.c ramstage-$(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT) += hypertransport.c diff --git a/src/devices/cpu_device.c b/src/devices/cpu_device.c new file mode 100644 index 0000000..b689f1a --- /dev/null +++ b/src/devices/cpu_device.c @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include <console/console.h> +#include <cpu/x86/lapic.h> + +void remap_bsp_lapic(struct bus *cpu_bus) +{ + struct device_path cpu_path; + device_t cpu; + u32 bsp_lapic_id = lapicid(); + + if (bsp_lapic_id) { + cpu_path.type = DEVICE_PATH_APIC; + cpu_path.apic.apic_id = 0; + cpu = find_dev_path(cpu_bus, &cpu_path); + if (cpu) + cpu->path.apic.apic_id = bsp_lapic_id; + } +} + +device_t add_cpu_device(struct bus *cpu_bus, unsigned apic_id, int enabled) +{ + struct device_path cpu_path; + device_t cpu; + + /* Build the cpu device path */ + cpu_path.type = DEVICE_PATH_APIC; + cpu_path.apic.apic_id = apic_id; + + /* Update CPU in devicetree. */ + if (enabled) + cpu = alloc_find_dev(cpu_bus, &cpu_path); + else + cpu = find_dev_path(cpu_bus, &cpu_path); + if (!cpu) + return NULL; + + cpu->enabled = enabled; + printk(BIOS_DEBUG, "CPU: %s %s\n", + dev_path(cpu), cpu->enabled?"enabled":"disabled"); + + return cpu; +} + +void set_cpu_topology(device_t cpu, unsigned node, unsigned package, unsigned core, unsigned thread) +{ + cpu->path.apic.node_id = node; + cpu->path.apic.package_id = package; + cpu->path.apic.core_id = core; + cpu->path.apic.thread_id = thread; +} + diff --git a/src/include/device/device.h b/src/include/device/device.h index b44a551..8e26d34 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -153,6 +153,16 @@ device_t dev_find_slot_on_smbus (unsigned int bus, unsigned int addr); device_t dev_find_lapic(unsigned apic_id); int dev_count_cpu(void); +void remap_bsp_lapic(struct bus *cpu_bus); +device_t add_cpu_device(struct bus *cpu_bus, unsigned apic_id, int enabled); +void set_cpu_topology(device_t cpu, unsigned node, unsigned package, unsigned core, unsigned thread); + +#define amd_cpu_topology(cpu, node, core) \ + set_cpu_topology(cpu, node, 0, core, 0) + +#define intel_cpu_topology(cpu, package, core, thread) \ + set_cpu_topology(cpu, 0, package, core, thread) + /* Debug functions */ void print_resource_tree(struct device * root, int debug_level, const char *msg); diff --git a/src/include/device/path.h b/src/include/device/path.h index 5af761e..16ad8f9 100644 --- a/src/include/device/path.h +++ b/src/include/device/path.h @@ -39,8 +39,10 @@ struct i2c_path struct apic_path { unsigned apic_id; + unsigned package_id; unsigned node_id; unsigned core_id; + unsigned thread_id; }; struct ioapic_path diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 55be491..9baff23 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -1373,11 +1373,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration; u32 modules = TopologyConfiguration.PlatformNumberOfModules; u32 lapicid_start = 0; - struct device_path cpu_path; - device_t cpu; - /* Build the cpu device path */ - cpu_path.type = DEVICE_PATH_APIC; /* * APIC ID calucation is tightly coupled with AGESA v5 code. * This calculation MUST match the assignment calculation done @@ -1393,22 +1389,11 @@ static u32 cpu_bus_scan(device_t dev, u32 max) if (nodes * (cores_found + 1) >= 0x10) { lapicid_start = 0x10; } - cpu_path.apic.apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (cores_found + 1)) : j); - - /* Update CPU in devicetree. */ - if (enable_node) - cpu = alloc_find_dev(cpu_bus, &cpu_path); - else - cpu = find_dev_path(cpu_bus, &cpu_path); - if (!cpu) - continue; - - cpu->enabled = enable_node; - cpu->path.apic.node_id = i; - cpu->path.apic.core_id = j; - printk(BIOS_DEBUG, "CPU: %s %s\n", - dev_path(cpu), cpu->enabled?"enabled":"disabled"); + u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (cores_found + 1)) : j); + device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + if (cpu) + amd_cpu_topology(cpu, i, j); } //j } return max; diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 1d9ef64..f9bd76f 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -844,6 +844,7 @@ static void cpu_bus_set_resources(device_t dev) { static u32 cpu_bus_scan(device_t dev, u32 max) { + struct bus *cpu_bus = dev->link_list; device_t cpu; int apic_id, cores_found; @@ -855,20 +856,10 @@ static u32 cpu_bus_scan(device_t dev, u32 max) cores_found = (pci_read_config32(dev_find_slot(0,PCI_DEVFN(0x18,0x3)), 0xe8) >> 12) & 3; printk(BIOS_DEBUG, " AP siblings=%d\n", cores_found); - for (apic_id = 0; apic_id <= cores_found; apic_id++) { - struct device_path cpu_path; - - cpu_path.type = DEVICE_PATH_APIC; - cpu_path.apic.apic_id = apic_id; - cpu = alloc_find_dev(dev->link_list, &cpu_path); - if (!cpu) - continue; - cpu->enabled = 1; - cpu->path.apic.node_id = 0; - cpu->path.apic.core_id = apic_id; - printk(BIOS_DEBUG, "CPU: %s %s\n", - dev_path(cpu), cpu->enabled?"enabled":"disabled"); + cpu = add_cpu_device(cpu_bus, apic_id, 1); + if (cpu) + amd_cpu_topology(cpu, 0, apic_id); } return max; } diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 3092735..66754e2 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -1064,11 +1064,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration; u32 modules = TopologyConfiguration.PlatformNumberOfModules; u32 lapicid_start = 0; - struct device_path cpu_path; - device_t cpu; - /* Build the cpu device path */ - cpu_path.type = DEVICE_PATH_APIC; /* * APIC ID calucation is tightly coupled with AGESA v5 code. * This calculation MUST match the assignment calculation done @@ -1090,23 +1086,13 @@ static u32 cpu_bus_scan(device_t dev, u32 max) lapicid_start = (lapicid_start + 1) * core_max; printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start); } - cpu_path.apic.apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); + u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", - i, j, cpu_path.apic.apic_id); - - /* Update CPU in devicetree. */ - if (enable_node) - cpu = alloc_find_dev(cpu_bus, &cpu_path); - else - cpu = find_dev_path(cpu_bus, &cpu_path); - if (!cpu) - continue; - - cpu->enabled = enable_node; - cpu->path.apic.node_id = i; - cpu->path.apic.core_id = j; - printk(BIOS_DEBUG, "CPU: %s %s\n", - dev_path(cpu), cpu->enabled?"enabled":"disabled"); + i, j, apic_id); + + device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + if (cpu) + amd_cpu_topology(cpu, i, j); } //j } return max; diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 36ded65..079e37f 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -1071,11 +1071,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration; u32 modules = TopologyConfiguration.PlatformNumberOfModules; u32 lapicid_start = 0; - struct device_path cpu_path; - device_t cpu; - /* Build the cpu device path */ - cpu_path.type = DEVICE_PATH_APIC; /* * APIC ID calucation is tightly coupled with AGESA v5 code. * This calculation MUST match the assignment calculation done @@ -1097,23 +1093,13 @@ static u32 cpu_bus_scan(device_t dev, u32 max) lapicid_start = (lapicid_start + 1) * core_max; printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start); } - cpu_path.apic.apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); + u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", - i, j, cpu_path.apic.apic_id); - - /* Update CPU in devicetree. */ - if (enable_node) - cpu = alloc_find_dev(cpu_bus, &cpu_path); - else - cpu = find_dev_path(cpu_bus, &cpu_path); - if (!cpu) - continue; - - cpu->enabled = enable_node; - cpu->path.apic.node_id = i; - cpu->path.apic.core_id = j; - printk(BIOS_DEBUG, "CPU: %s %s\n", - dev_path(cpu), cpu->enabled?"enabled":"disabled"); + i, j, apic_id); + + device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + if (cpu) + amd_cpu_topology(cpu, i, j); } //j } return max; diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index b061acf..135b8f7 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -1358,6 +1358,10 @@ static u32 cpu_bus_scan(device_t dev, u32 max) #endif /* Find which cpus are present */ cpu_bus = dev->link_list; + + /* Always use the devicetree node with lapic_id 0 for BSP. */ + remap_bsp_lapic(cpu_bus); + for(i = 0; i < nodes; i++) { device_t cdb_dev; unsigned busn, devn; @@ -1420,34 +1424,18 @@ static u32 cpu_bus_scan(device_t dev, u32 max) } for (j = 0; j <=jj; j++ ) { - struct device_path cpu_path; - device_t cpu; - - /* Build the cpu device path */ - cpu_path.type = DEVICE_PATH_APIC; - cpu_path.apic.apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:64); // ? - - /* Update CPU in devicetree. */ - if (enable_node) - cpu = alloc_find_dev(cpu_bus, &cpu_path); - else - cpu = find_dev_path(cpu_bus, &cpu_path); - if (!cpu) - continue; + u32 apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:64); // ? #if CONFIG_ENABLE_APIC_EXT_ID && (CONFIG_APIC_ID_OFFSET>0) if(sysconf.enabled_apic_ext_id) { - if (cpu->path.apic.apic_id != 0 || sysconf.lift_bsp_apicid) { - cpu->path.apic.apic_id += sysconf.apicid_offset; + if (apic_id != 0 || sysconf.lift_bsp_apicid) { + apic_id += sysconf.apicid_offset; } } #endif - cpu->enabled = enable_node; - cpu->path.apic.node_id = i; - cpu->path.apic.core_id = j; - printk(BIOS_DEBUG, "CPU: %s %s\n", - dev_path(cpu), cpu->enabled?"enabled":"disabled"); - + device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + if (cpu) + amd_cpu_topology(cpu, i, j); } //j } return max; diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index a7538a6..343a07b 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -1249,6 +1249,10 @@ static u32 cpu_bus_scan(device_t dev, u32 max) /* Find which cpus are present */ cpu_bus = dev->link_list; + + /* Always use the devicetree node with lapic_id 0 for BSP. */ + remap_bsp_lapic(cpu_bus); + for(i = 0; i < sysconf.nodes; i++) { device_t cpu_dev; @@ -1317,38 +1321,18 @@ static u32 cpu_bus_scan(device_t dev, u32 max) { jj = siblings; } -#if 0 - jj = 0; // if create cpu core1 path in amd_siblings by core0 -#endif for (j = 0; j <=jj; j++ ) { - struct device_path cpu_path; - device_t cpu; - - /* Build the cpu device path */ - cpu_path.type = DEVICE_PATH_APIC; - cpu_path.apic.apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8); - - /* Update CPU in devicetree. */ - if (enable_node) - cpu = alloc_find_dev(cpu_bus, &cpu_path); - else - cpu = find_dev_path(cpu_bus, &cpu_path); - if (!cpu) - continue; - + u32 apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8); if(sysconf.enabled_apic_ext_id) { - if (cpu->path.apic.apic_id != 0 || sysconf.lift_bsp_apicid) { - cpu->path.apic.apic_id += sysconf.apicid_offset; + if (apic_id != 0 || sysconf.lift_bsp_apicid) { + apic_id += sysconf.apicid_offset; } } - cpu->enabled = enable_node; - cpu->path.apic.node_id = i; - cpu->path.apic.core_id = j; - printk(BIOS_DEBUG, "CPU: %s %s\n", - dev_path(cpu), cpu->enabled?"enabled":"disabled"); - + device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + if (cpu) + amd_cpu_topology(cpu, i, j); } //j } return max;

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Patch set updated for coreboot: c7166bd AMD Hudson: Move the combining firmware from Python to Makefile
by Zheng Bao 07 Aug '12

07 Aug '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1417 -gerrit commit c7166bd959b05113daded9350b5e392fd5430f3d Author: zbao <fishbaozi(a)gmail.com> Date: Tue Aug 7 19:29:33 2012 +0800 AMD Hudson: Move the combining firmware from Python to Makefile Maybe sooner or later python is not a default tools to build coreboot. Most of the work is done by awk now. GNU extension of gawk is not used, isn't? expr, cat, awk, test, mv are the external tools. If XHCI or IMC firmware is not available and not defined, this script can skip integrating them. Change-Id: I9944b22b0b755672a46d472c355d138abafd6393 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/southbridge/amd/agesa/hudson/Makefile.inc | 30 +++++++++++- src/southbridge/amd/agesa/hudson/hudson_fwm.py | 64 ------------------------ 2 files changed, 29 insertions(+), 65 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 19ffae1..094a342 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -15,7 +15,35 @@ romstage-y += early_setup.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c $(obj)/hudson.bin: - python $(src)/southbridge/amd/agesa/hudson/hudson_fwm.py $(CONFIG_HUDSON_FWM_POSITION) $@ $(CONFIG_HUDSON_XHCI_FWM_FILE) $(CONFIG_HUDSON_IMC_FWM_FILE) "" + echo $(CONFIG_HUDSON_FWM_POSITION) | LC_ALL=C awk ' \ + function cbstrtonum(str, n,ret,i,c,k) \ + { \ + str = substr(str, 3); \ + n = length(str); \ + ret = 0; \ + for (i = 1; i <= n; i++) { \ + c = substr(str, i, 1); \ + c = tolower(c); \ + k = index("123456789abcdef", c); \ + ret = ret * 16 + k; \ + } \ + return ret; \ + } \ + function print_raw_32bit(number) \ + { \ + printf ("%c%c%c%c", number % 0x100, number/0x100 % 0x100, number/0x10000 % 0x100, number/0x1000000); \ + } \ + { #main \ + print_raw_32bit(0x55AA55AA) \ + print_raw_32bit(cbstrtonum($$1) + 65536) #imc \ + print_raw_32bit(0) #gec \ + print_raw_32bit(cbstrtonum($$1) + 16) #xhci \ + }' > $@.tmp + [ -z $(CONFIG_HUDSON_XHCI_FWM_FILE) ] || cat $(CONFIG_HUDSON_XHCI_FWM_FILE) >> $@.tmp + expr 65536 - `ls -l $@.tmp | awk '{ print $$5 }'` | LC_ALL=C awk '{for (i=0; i<$$1; i++) {printf "%c", 255}}' >> $@.tmp # fill stub + [ -z $(CONFIG_HUDSON_IMC_FWM_FILE) ] || cat $(CONFIG_HUDSON_IMC_FWM_FILE) >> $@.tmp + #TODO: GEC + mv -f $@.tmp $@ ifeq ($(CONFIG_HUDSON_FWM), y) cbfs-files-y += hudson/fwm diff --git a/src/southbridge/amd/agesa/hudson/hudson_fwm.py b/src/southbridge/amd/agesa/hudson/hudson_fwm.py deleted file mode 100644 index ad60b3b..0000000 --- a/src/southbridge/amd/agesa/hudson/hudson_fwm.py +++ /dev/null @@ -1,64 +0,0 @@ -import sys, os, re -import struct -from Queue import Queue - -def main(start_addr, file_name, xhci_name, imc_name, gec_name): - fwm_sig = 0x55AA55AA # Hudson-2/3/4 firmware signature - fwm_header_len = 0x10 # 55AA55AA, imc_off, gec_off, xhci_off - - if not os.path.exists(xhci_name): - print "XHCI firmware %s does not exist\n" % xhci_name - sys.exit(1) - if not os.path.exists(imc_name): - print "IMC firmware %s does not exist\n" % imc_name - sys.exit(1) - - f = open(file_name, "w") - print "write to file " + file_name - - imc_offset = 0x10000 # 64K Bytes offset, hardcoded - imc_addr = start_addr + imc_offset; #startaddr + 0x10000 - gec_offset = 0 #TODO - gec_addr = 0 #TODO - xhci_addr = start_addr + fwm_header_len #ROMSIG take 0x10 bytes - - format="I" # one unsigned integer - data=struct.pack(format, fwm_sig) - f.write(data) - data=struct.pack(format, imc_addr) - f.write(data) - data=struct.pack(format, gec_addr) - f.write(data) - data=struct.pack(format, xhci_addr) - f.write(data) - - fwm_content = open(xhci_name).read() - f.write(fwm_content) - - imc_content = open(imc_name).read() - f.seek(0) - f.seek(imc_offset) - f.write(imc_content) -# if os.path.exists(gec_name): -# gec_conent = open(gec_name).read() -# f.seek(0) -# f.seek(gec_offset) -# f.write(gec_content) - - f.close() - print "done\n" - - -if __name__ == '__main__': - if (len(sys.argv) < 6): - print "\nUsage: %s <rom_addr> <rom_file> <xhci_rom> <imc_rom> <gec_rom>\n" % sys.argv[0] - print "Example: %s 0xFFF20000 hudson.bin xhci.bin imc.bin gec.bin\n" % sys.argv[0] - sys.exit(1) - rom_addr = int(sys.argv[1], 16) - rom_file = sys.argv[2] - xhci_file = sys.argv[3] - imc_file = sys.argv[4] - gec_file = sys.argv[5] - print "%x %s %s %s %s" % (rom_addr, rom_file, xhci_file, imc_file, gec_file) - - main(rom_addr, rom_file, xhci_file, imc_file, gec_file)

1 0

Patch set updated for coreboot: 618cc0c AMD S3: Add a document about S3 on AMD platform
by Zheng Bao 07 Aug '12

07 Aug '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1400 -gerrit commit 618cc0c676150e1085a1afe31178e8043bbd5c8c Author: zbao <fishbaozi(a)gmail.com> Date: Fri Aug 3 13:53:10 2012 +0800 AMD S3: Add a document about S3 on AMD platform See the document. Need review. Everything should be in Authentic English. Change-Id: Idc528b8c6b0d5afe08fc4f4387b7bff30698f677 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- documentation/AMD-S3.txt | 95 ++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 95 insertions(+), 0 deletions(-) diff --git a/documentation/AMD-S3.txt b/documentation/AMD-S3.txt new file mode 100644 index 0000000..58ee0d7 --- /dev/null +++ b/documentation/AMD-S3.txt @@ -0,0 +1,95 @@ + _____ ____ _____ ______ ____ ____ ____ _______ + / ____/ __ \| __ \| ____| _ \ / __ \ / __ \__ __| + | | | | | | |__) | |__ | |_) | | | | | | | | | + | | | | | | _ /| __| | _ <| | | | | | | | | + | |___| |__| | | \ \| |____| |_) | |__| | |__| | | | + \_____\____/|_| \_\______|____/ \____/ \____/ |_| + + __ __ _____ _____ ____ + /\ | \/ | __ \ / ____| |___ \ + / \ | \ / | | | | | (___ __) | + / /\ \ | |\/| | | | | \___ \ |__ < + / ____ \| | | | |__| | ____) | ___) | + /_/ \_\_| |_|_____/ |_____/ |____/ + + + S3 in Coreboot +---------------------------------------- + Zheng Bao + <zheng.bao(a)amd.com> + <fishbaozi(a)gmail.com> + +Introduction +============ +This document is about how the feature S3 is implemented on coreboot, +specificly on AMD platform. This topic deals with ACPI spec, hardware, +BIOS, OS. We try to help coreboot users to realize their own S3. + +S3 in a nutshell +================ +The S3 sleeping state is a low wake latency sleeping state where all +system context is lost except system memory. [1]. S3 is a ACPI +definition. +To enter S3, write 3 in SLP_TYPx and setting the SLP_EN bit. But if +you do that, board can not resume at where it sleeps, because you +don't save the context. More often than not, we make the board go into +S3 by the tools which OSes provide. For windows, click +Start->sleep. For linux, some distribution provide a tools called +pm-suspend, which can make the system goto S3. If pm-suspend is not +available, we can run "echo mem > /sys/power/state", but this way may +not save all the needed context. +In S3 state, the power is off. So when the power button is pressed, +BIOS runs as it does in cold boot. If BIOS didn't detect whether +board boots or resume, it would go the same way as boot. It is not +what we expect. BIOS detects the SLP_TYPx. If it is 3, it means BIOS +are waking up. +BIOS is responsible for restore the machine state as it is before +sleep. It needs restore the memory controller, not overwriting memory +which is marked as reserved. For the peripheral which loses its +registers, BIOS needs to write the original value. +When everything is done, BIOS needs to find out the wakeup vector +provided by OSes and jump there. OSes also have work to do. We can go +to linux kernel or some other open source projects to find out how they +handle S3 resume. + +Memory Layout +============= +Restoring memory is the most important job done by BIOS. When the +power is off, the memory is maintained by standby power. BIOS need to +make sure that when flow goes to OS, everything in memory should be +the same as it was. + +The chip vendor will provide a way, or code, to wake up the memory +from sleeping. In AGESA 2008 arch, it is called AmdInitResume. + +The BIOS itself needs some memory to run. Either, BIOS marks the erea +as reserved in e820, or BIOS saves the content into reserved space. + +Here is the address Map for S3 Resume. Assumingly the total memory is 1GB. +00000000 --- 00100000 BIOS Reserved area. +00100000 --- 00200000 Free +00200000 --- 01000000 Coreboot ramstage area. +01000000 --- 2e160000 Free +2e160000 --- 2e170000 ACPI table +2e170000 --- 2ef70000 OSRAM +2ef70000 --- 2efe0000 Stack in highmem +2efe0000 --- 2f000000 heap in highmem +2f000000 TOM + +AMD requirements in S3 +====================== +Chip vendor like AMD will provide bunch of routines to restore the +board.[2] + * AmdS3Save: It is called in cold boot, save required register into + non-volatile storage. Currently, we use SPI flash to store the data. + * AmdInitResume: Restore the memory controller. + * AmdS3LateRestore: Called after AmdInitResume, restore other + register that memory. + * (SouthBridge)InitS3EarlyRestore, (SouthBridge)InitS3LateRestore: + Provided by Southbridge vendor code. Early is called before PCI + enumeration, and Late is called after that. + +Reference +========= +[1] ACPI40 +[2] Coreboot Vendorcode

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New patch to review for coreboot: 42fef8a AMD Hudson: Move the combining firmware from Python to Makefile
by Zheng Bao 07 Aug '12

07 Aug '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1417 -gerrit commit 42fef8afef605caa27218db9fe22502f595b55d5 Author: zbao <fishbaozi(a)gmail.com> Date: Tue Aug 7 19:26:14 2012 +0800 AMD Hudson: Move the combining firmware from Python to Makefile Maybe sooner or later python is not a default tools to build coreboot. Most of the work is done by awk now. GNU extension of gawk is not used, isn't? expr, cat, awk, test, mv are the external tools. If XHCI or IMC firmware is not available and not defined, this script can skip integrating them. Change-Id: I9944b22b0b755672a46d472c355d138abafd6393 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/southbridge/amd/agesa/hudson/Makefile.inc | 31 +++++++++++- src/southbridge/amd/agesa/hudson/hudson_fwm.py | 64 ------------------------ 2 files changed, 30 insertions(+), 65 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 19ffae1..24adb88 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -14,8 +14,37 @@ romstage-y += early_setup.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c + $(obj)/hudson.bin: - python $(src)/southbridge/amd/agesa/hudson/hudson_fwm.py $(CONFIG_HUDSON_FWM_POSITION) $@ $(CONFIG_HUDSON_XHCI_FWM_FILE) $(CONFIG_HUDSON_IMC_FWM_FILE) "" + echo $(CONFIG_HUDSON_FWM_POSITION) | LC_ALL=C awk ' \ + function cbstrtonum(str, n,ret,i,c,k) \ + { \ + str = substr(str, 3); \ + n = length(str); \ + ret = 0; \ + for (i = 1; i <= n; i++) { \ + c = substr(str, i, 1); \ + c = tolower(c); \ + k = index("123456789abcdef", c); \ + ret = ret * 16 + k; \ + } \ + return ret; \ + } \ + function print_raw_32bit(number) \ + { \ + printf ("%c%c%c%c", number % 0x100, number/0x100 % 0x100, number/0x10000 % 0x100, number/0x1000000); \ + } \ + { \ + print_raw_32bit(0x55AA55AA) \ + print_raw_32bit(cbstrtonum($$1) + 65535) #imc \ + print_raw_32bit(0) #gec \ + print_raw_32bit(cbstrtonum($$1) + 16) #xhci \ + }' > $@.tmp + [ -z $(CONFIG_HUDSON_XHCI_FWM_FILE) ] || cat $(CONFIG_HUDSON_XHCI_FWM_FILE) >> $@.tmp + expr 65536 - `ls -l $@.tmp | awk '{ print $$5 }'` | LC_ALL=C awk '{for (i=0; i<$$1; i++) {printf "%c", 0}}' >> $@.tmp # fill stub + [ -z $(CONFIG_HUDSON_IMC_FWM_FILE) ] || cat $(CONFIG_HUDSON_IMC_FWM_FILE) >> $@.tmp + #TODO: GEC + mv -f $@.tmp $@ ifeq ($(CONFIG_HUDSON_FWM), y) cbfs-files-y += hudson/fwm diff --git a/src/southbridge/amd/agesa/hudson/hudson_fwm.py b/src/southbridge/amd/agesa/hudson/hudson_fwm.py deleted file mode 100644 index ad60b3b..0000000 --- a/src/southbridge/amd/agesa/hudson/hudson_fwm.py +++ /dev/null @@ -1,64 +0,0 @@ -import sys, os, re -import struct -from Queue import Queue - -def main(start_addr, file_name, xhci_name, imc_name, gec_name): - fwm_sig = 0x55AA55AA # Hudson-2/3/4 firmware signature - fwm_header_len = 0x10 # 55AA55AA, imc_off, gec_off, xhci_off - - if not os.path.exists(xhci_name): - print "XHCI firmware %s does not exist\n" % xhci_name - sys.exit(1) - if not os.path.exists(imc_name): - print "IMC firmware %s does not exist\n" % imc_name - sys.exit(1) - - f = open(file_name, "w") - print "write to file " + file_name - - imc_offset = 0x10000 # 64K Bytes offset, hardcoded - imc_addr = start_addr + imc_offset; #startaddr + 0x10000 - gec_offset = 0 #TODO - gec_addr = 0 #TODO - xhci_addr = start_addr + fwm_header_len #ROMSIG take 0x10 bytes - - format="I" # one unsigned integer - data=struct.pack(format, fwm_sig) - f.write(data) - data=struct.pack(format, imc_addr) - f.write(data) - data=struct.pack(format, gec_addr) - f.write(data) - data=struct.pack(format, xhci_addr) - f.write(data) - - fwm_content = open(xhci_name).read() - f.write(fwm_content) - - imc_content = open(imc_name).read() - f.seek(0) - f.seek(imc_offset) - f.write(imc_content) -# if os.path.exists(gec_name): -# gec_conent = open(gec_name).read() -# f.seek(0) -# f.seek(gec_offset) -# f.write(gec_content) - - f.close() - print "done\n" - - -if __name__ == '__main__': - if (len(sys.argv) < 6): - print "\nUsage: %s <rom_addr> <rom_file> <xhci_rom> <imc_rom> <gec_rom>\n" % sys.argv[0] - print "Example: %s 0xFFF20000 hudson.bin xhci.bin imc.bin gec.bin\n" % sys.argv[0] - sys.exit(1) - rom_addr = int(sys.argv[1], 16) - rom_file = sys.argv[2] - xhci_file = sys.argv[3] - imc_file = sys.argv[4] - gec_file = sys.argv[5] - print "%x %s %s %s %s" % (rom_addr, rom_file, xhci_file, imc_file, gec_file) - - main(rom_addr, rom_file, xhci_file, imc_file, gec_file)

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coreboot August 2012