coreboot July 2012

coreboot@coreboot.org

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New patch to review for coreboot: 687a036 i5000: Add PCI ids for all i5000 flavours
by Sven Schnelle 05 Jul '12

05 Jul '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1174 -gerrit commit 687a036e86fa3070639858cb8bded15b73b7b86d Author: Sven Schnelle <svens(a)stackframe.org> Date: Thu Jul 5 17:17:45 2012 +0200 i5000: Add PCI ids for all i5000 flavours Change-Id: I48be647e3f38038830200bcc64429cbf86990ad7 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/northbridge/intel/i5000/northbridge.c | 9 ++++++++- 1 files changed, 8 insertions(+), 1 deletions(-) diff --git a/src/northbridge/intel/i5000/northbridge.c b/src/northbridge/intel/i5000/northbridge.c index 3db755c..f5cc0ba 100644 --- a/src/northbridge/intel/i5000/northbridge.c +++ b/src/northbridge/intel/i5000/northbridge.c @@ -55,10 +55,17 @@ static struct device_operations mc_ops = { .ops_pci = &intel_pci_ops, }; +static const unsigned short nb_ids[] = { + 0x25c0, /* 5000X */ + 0x25d0, /* 5000Z */ + 0x25d4, /* 5000V */ + 0x25d8, /* 5000P */ + 0}; + static const struct pci_driver mc_driver __pci_driver = { .ops = &mc_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x25d8, + .devices = nb_ids, }; static void cpu_bus_init(device_t dev)

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Patch merged into coreboot/master: 9666a19 Only copy real-mode section of SIPI vector
by gerrit＠coreboot.org 05 Jul '12

05 Jul '12

the following patch was just integrated into master: commit 9666a19f8b2df673c8a523274e98a707e8610de5 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jul 5 06:31:15 2012 +0300 Only copy real-mode section of SIPI vector The SIPI vector copy can use a static location below 1MB, aligned to 4kB. Jump out of the copy once in protected mode. Change-Id: I6299aa3448270663941cf2c4113efee74bcc7993 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Build-Tested: build bot (Jenkins) at Thu Jul 5 06:55:41 2012, giving +1 Reviewed-By: Sven Schnelle <svens(a)stackframe.org> at Thu Jul 5 22:49:30 2012, giving +2 See http://review.coreboot.org/1165 for details. -gerrit

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Patch merged into coreboot/master: 43c9618 Fix the CPU index parameter passed to secondary_cpu_init().
by gerrit＠coreboot.org 05 Jul '12

05 Jul '12

the following patch was just integrated into master: commit 43c9618eaf9e9c0455020040c47eb4cf74e93329 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jul 5 06:30:29 2012 +0300 Fix the CPU index parameter passed to secondary_cpu_init(). Count 0,1,2,3,... instead of 0,2,3,4,... Change-Id: I3c6b85e5e71b32deac5470809e1618d28f19c00f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Build-Tested: build bot (Jenkins) at Thu Jul 5 06:37:38 2012, giving +1 Reviewed-By: Sven Schnelle <svens(a)stackframe.org> at Thu Jul 5 22:47:43 2012, giving +2 See http://review.coreboot.org/1173 for details. -gerrit

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Patch set updated for coreboot: 9666a19 Only copy real-mode section of SIPI vector
by Kyösti Mälkki 05 Jul '12

05 Jul '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1165 -gerrit commit 9666a19f8b2df673c8a523274e98a707e8610de5 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jul 5 06:31:15 2012 +0300 Only copy real-mode section of SIPI vector The SIPI vector copy can use a static location below 1MB, aligned to 4kB. Jump out of the copy once in protected mode. Change-Id: I6299aa3448270663941cf2c4113efee74bcc7993 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/x86/lapic/lapic_cpu_init.c | 23 ++++++++--------------- src/cpu/x86/lapic/secondary.S | 24 +++++++++++++++--------- 2 files changed, 23 insertions(+), 24 deletions(-) diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 061d3d3..b6dc560 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -24,10 +24,9 @@ * We actually handling that case by noting which cpus startup * and not telling anyone about the ones that dont. */ -static unsigned long get_valid_start_eip(unsigned long orig_start_eip) -{ - return (unsigned long)orig_start_eip & 0xffff; // 16 bit to avoid 0xa0000 -} + +/* Start-UP IPI vector must be 4kB aligned and below 1MB. */ +#define AP_SIPI_VECTOR 0x1000 #if CONFIG_HAVE_ACPI_RESUME char *lowmem_backup; @@ -41,19 +40,14 @@ static void copy_secondary_start_to_1m_below(void) { extern char _secondary_start_end[]; unsigned long code_size; - unsigned long start_eip; - /* _secondary_start need to be masked 20 above bit, because 16 bit code in secondary.S - Also We need to copy the _secondary_start to the below 1M region - */ - start_eip = get_valid_start_eip((unsigned long)_secondary_start); code_size = (unsigned long)_secondary_start_end - (unsigned long)_secondary_start; #if CONFIG_HAVE_ACPI_RESUME /* need to save it for RAM resume */ lowmem_backup_size = code_size; lowmem_backup = malloc(code_size); - lowmem_backup_ptr = (char *)start_eip; + lowmem_backup_ptr = (char *)AP_SIPI_VECTOR; if (lowmem_backup == NULL) die("Out of backup memory\n"); @@ -61,9 +55,9 @@ static void copy_secondary_start_to_1m_below(void) memcpy(lowmem_backup, lowmem_backup_ptr, lowmem_backup_size); #endif /* copy the _secondary_start to the ram below 1M*/ - memcpy((unsigned char *)start_eip, (unsigned char *)_secondary_start, code_size); + memcpy((unsigned char *)AP_SIPI_VECTOR, (unsigned char *)_secondary_start, code_size); - printk(BIOS_DEBUG, "start_eip=0x%08lx, offset=0x%08lx, code_size=0x%08lx\n", start_eip, ((unsigned long)_secondary_start - start_eip), code_size); + printk(BIOS_DEBUG, "start_eip=0x%08lx, code_size=0x%08lx\n", (long unsigned int)AP_SIPI_VECTOR, code_size); } static struct bus *current_cpu_bus; @@ -71,7 +65,7 @@ static struct bus *current_cpu_bus; static int lapic_start_cpus(struct bus *cpu_bus) { int timeout; - unsigned long send_status, accept_status, start_eip; + unsigned long send_status, accept_status; int maxlvt; /* @@ -105,7 +99,6 @@ static int lapic_start_cpus(struct bus *cpu_bus) } return 0; } - start_eip = get_valid_start_eip((unsigned long)_secondary_start); maxlvt = 4; @@ -125,7 +118,7 @@ static int lapic_start_cpus(struct bus *cpu_bus) /* Boot on the stack */ /* Kick the second */ lapic_write_around(LAPIC_ICR, LAPIC_INT_ASSERT | LAPIC_DM_STARTUP | LAPIC_DEST_ALLBUT - | (start_eip >> 12)); + | ((AP_SIPI_VECTOR >> 12) & 0xff)); /* * Give the other CPU some time to accept the IPI. diff --git a/src/cpu/x86/lapic/secondary.S b/src/cpu/x86/lapic/secondary.S index 2ad7029..15bae5e 100644 --- a/src/cpu/x86/lapic/secondary.S +++ b/src/cpu/x86/lapic/secondary.S @@ -2,8 +2,7 @@ #include <cpu/x86/lapic_def.h> .text - .globl _secondary_start, _secondary_start_end, cpucount - .balign 4096 + .globl _secondary_start, _secondary_start_end, cpucount, ap_protected_start _secondary_start: .code16 cli @@ -25,9 +24,21 @@ _secondary_start: orl $0x60000001, %eax /* CD, NW, PE = 1 */ movl %eax, %cr0 - ljmpl $0x10, $1f -1: + ljmpl $0x10, $__ap_protected_start + +gdtaddr: + .word gdt_limit /* the table limit */ + .long gdt /* we know the offset */ + +_secondary_start_end: + +ap_protected_start: .code32 + lgdt gdtaddr + ljmpl $0x10, $__ap_protected_start + +__ap_protected_start: + movw $0x18, %ax movw %ax, %ds movw %ax, %es @@ -57,9 +68,4 @@ _secondary_start: cpucount: .long 1 -gdtaddr: - .word gdt_limit /* the table limit */ - .long gdt /* we know the offset */ - -_secondary_start_end: .code32

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New patch to review for coreboot: 43c9618 Fix the CPU index parameter passed to secondary_cpu_init().
by Kyösti Mälkki 05 Jul '12

05 Jul '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1173 -gerrit commit 43c9618eaf9e9c0455020040c47eb4cf74e93329 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jul 5 06:30:29 2012 +0300 Fix the CPU index parameter passed to secondary_cpu_init(). Count 0,1,2,3,... instead of 0,2,3,4,... Change-Id: I3c6b85e5e71b32deac5470809e1618d28f19c00f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/x86/lapic/secondary.S | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/cpu/x86/lapic/secondary.S b/src/cpu/x86/lapic/secondary.S index 67e44c4..2ad7029 100644 --- a/src/cpu/x86/lapic/secondary.S +++ b/src/cpu/x86/lapic/secondary.S @@ -41,8 +41,8 @@ _secondary_start: /* increment our cpu index */ movl $1, %eax lock xadd %eax, cpucount - incl %eax movl %eax, %ecx + incl %eax /* assign stack for this specific cpu */ mov _stack, %esp

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Re: [coreboot] How to make graphical issue go away with 4GB of ram
by Denis 'GNUtoo' Carikli 04 Jul '12

04 Jul '12

On Sat, 2012-06-30 at 12:44 -0600, Marc Jones wrote: > On Sat, Jun 30, 2012 at 12:01 PM, Kyösti Mälkki <kyosti.malkki(a)gmail.com> wrote: > > On Sat, 2012-06-30 at 18:18 +0200, Denis 'GNUtoo' Carikli wrote: > >> Hi, > >> > >> me and Kyösti Mälkki(kmalkki on IRC) figured out how to workarround the > >> following problem: > >> If I installed 4GB of ram in the m4a785t-m the screen comes up,however > >> it's black. > >> If I only installed 2GB of ram it worked fine. > >> > >> I made a patch(I'll send it right after that email) but it seem to break > >> graphics for the case where 2GB of ram is installed. > >> > >> So I wonder what would be the correct fix(a fix that would work for > >> every cases). > >> > >> Explanation of the patch that will be sent right after the mail: > >> "basek - mmio_basek;" should be 1048576 (1G): > >> According to Kyösti Mälkki the correct value for the sizek is 1048576. > >> So I looked for what could create that size and found that. > >> I'm not convinced that "basek - mmio_basek" is the right fix but at > >> least we're in the right direction. > > > > My explanation of the issue: uma_memory_size must reduce the size of the > > last RAM resource _below_ 4GB. It now touches the last RAM resource, > > even if located over 4GB. > > Yes, The UMA graphics memory is allocated in the lower 4GB. I think > that should be happening in mainboard.c. See the AMD reference > platforms. Do you mean the following: #if CONFIG_GFXUMA uint64_t uma_memory_base, uma_memory_size; #endif int add_mainboard_resources(struct lb_memory *mem) { #if CONFIG_GFXUMA lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, uma_memory_size); #endif return 0; } With the addition of "select HAVE_MAINBOARD_RESOURCES" in Kconfig ? if so I already tried that change alone(without other changes) and it didn't work, I don't remember what it did exactly tough, I can retry if needed. Denis.

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ASUS m5a88-v AGESA port (bulldozer)
by darkdefende＠gmail.com 04 Jul '12

04 Jul '12

Hi! I bought a asus m5a88-v mainboard and was hoping to run coreboot on it. Sadly I found out that the current implementation only supports famlily 10 type CPUs. After looking at other motherboards supported by coreboot I found that all (?) motherboards that supports greater than family 10 uses the AMD AGESA wrapper. So I thought I might just port the m5a88-v to use that instead and hopefully it would be able to run both family 10 and 15 type CPUs. After copy, pasting mostly from asrock/e350m1 (SB800) and supermicro/h8ggi (family 10 & 15 support) and modifying the current source files I've managed to get quite far in the the boot process. However after starting seabios and printing "Press F12 for boot menu." it doesn't go any further. Here is the complete coreboot log: http://pastebin.com/Tyze9fMU I suspect that the "ASSERTION FAILED:" errors might have something to do with it. And also perhaps a ugly hack I had to do to work around the PCI pci_scan_bus to not lock up. I limited the bus scan to only 0 if the bus is greater than 0 then it will skip that code. If I didn't do this it would stop booting and freeze at line 505 in the boot log ,when it tries to scan for bus 01. It seems to freeze if it tries to scan on anything else that bus 00. I have no idea why it tries to scan on bus 1-9. In most other coreboot log I've seen it stop automagicly on bus 00. Anyhow, I would really like some help with this as it seems like I'm quite close to get this working. If someone wants to look at the code please tell me where and how to upload it.

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Patch merged into coreboot/master: 08500eb Intel cpus: Extend cache to cover complete Flash Device
by gerrit＠coreboot.org 04 Jul '12

04 Jul '12

the following patch was just integrated into master: commit 08500ebe42116adc95bd2db59948e0d6197903fb Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jun 30 11:41:08 2012 +0300 Intel cpus: Extend cache to cover complete Flash Device CACHE_ROM_SIZE default is ROM_SIZE, the Flash device size set in menuconfig. This fixes a case where 8 MB SPI flash MTRR setup would not cover the bottom 4 MB when ramstage is decompressed. Verify CACHE_ROM_SIZE is power of two. One may set CACHE_ROM_SIZE==0 to disable this cache. Change-Id: Ib2b4ea528a092b96ff954894e60406d64f250783 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Jul 4 11:32:26 2012, giving +1 Reviewed-By: Sven Schnelle <svens(a)stackframe.org> at Wed Jul 4 14:47:23 2012, giving +2 See http://review.coreboot.org/1146 for details. -gerrit

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Patch merged into coreboot/master: a8aad29 Intel model_106cx: change CAR to model_6ex
by gerrit＠coreboot.org 04 Jul '12

04 Jul '12

the following patch was just integrated into master: commit a8aad29c8d4cd14fcc141f51bdc490771c9841fb Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jun 28 21:50:43 2012 +0300 Intel model_106cx: change CAR to model_6ex Diff between model_106cx and model_6ex CAR codes suggests currently used model_106cx CAR is not optimal - destination RAM and source ROM of ramstage copy_and_run are only partly set cacheable. It appears variable MTRR setting for XIP cache is left enabled on model_106cx code, where it should have extended to cover all of Flash. Introduces untested functional change on boards: intel/d945gclf iwave/iWRainbowG6 Deletes file: model_106cx/cache_as_ram.inc Change-Id: I35229f8433927e83821e72e9d9a9fc8fb09c3f1d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Jul 4 12:21:14 2012, giving +1 Reviewed-By: Sven Schnelle <svens(a)stackframe.org> at Wed Jul 4 14:45:38 2012, giving +2 See http://review.coreboot.org/642 for details. -gerrit

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Patch merged into coreboot/master: 895c173 Intel cpus: delete dead CAR code and whitespace fixes
by gerrit＠coreboot.org 04 Jul '12

04 Jul '12

the following patch was just integrated into master: commit 895c1739ca61c2e47d784629cab39718b306d806 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jun 28 12:16:12 2012 +0300 Intel cpus: delete dead CAR code and whitespace fixes A diff from model_6fx to model_106cx suggests there is little CORE2 specific code that was once considered useful to have. In its current status however, sockets supporting model_6fx use model_6ex CAR init, so that specific code is actually never used. Deletes file: model_6fx/cache_as_ram.inc Change-Id: I6c0204446fa98207e31f91895e1cf30fde42382c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Jul 4 12:03:53 2012, giving +1 Reviewed-By: Sven Schnelle <svens(a)stackframe.org> at Wed Jul 4 14:44:28 2012, giving +2 See http://review.coreboot.org/640 for details. -gerrit

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coreboot July 2012