coreboot July 2012

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New patch to review for coreboot: 74f763f Add basic ipmi support
by Sven Schnelle 08 Jul '12

08 Jul '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1190 -gerrit commit 74f763f19e2fc582b4ab064e66a9c82bec0e65e2 Author: Sven Schnelle <svens(a)stackframe.org> Date: Sun Jul 8 18:32:23 2012 +0200 Add basic ipmi support Implements support code for talking to IPMI hardware that uses a KCS style interface. Change-Id: I9895cc1bf29676115b167081b63b8a430e23eee5 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/drivers/Kconfig | 1 + src/drivers/Makefile.inc | 1 + src/drivers/ipmi/Kconfig | 3 + src/drivers/ipmi/Makefile.inc | 1 + src/drivers/ipmi/ipmi_kcs.c | 232 +++++++++++++++++++++++++++++++++++++++++ src/drivers/ipmi/ipmi_kcs.h | 37 +++++++ 6 files changed, 275 insertions(+), 0 deletions(-) diff --git a/src/drivers/Kconfig b/src/drivers/Kconfig index 60e5b65..89cdf6a 100644 --- a/src/drivers/Kconfig +++ b/src/drivers/Kconfig @@ -27,3 +27,4 @@ source src/drivers/sil/Kconfig source src/drivers/trident/Kconfig source src/drivers/ics/Kconfig source src/drivers/spi/Kconfig +source src/drivers/ipmi/Kconfig diff --git a/src/drivers/Makefile.inc b/src/drivers/Makefile.inc index 851a4df..6c63a6a 100644 --- a/src/drivers/Makefile.inc +++ b/src/drivers/Makefile.inc @@ -27,4 +27,5 @@ subdirs-y += sil subdirs-y += trident subdirs-y += ics subdirs-y += spi +subdirs-y += ipmi subdirs-$(CONFIG_ARCH_X86) += pc80 diff --git a/src/drivers/ipmi/Kconfig b/src/drivers/ipmi/Kconfig new file mode 100644 index 0000000..55c85ea --- /dev/null +++ b/src/drivers/ipmi/Kconfig @@ -0,0 +1,3 @@ +config IPMI_KCS + bool + default n diff --git a/src/drivers/ipmi/Makefile.inc b/src/drivers/ipmi/Makefile.inc new file mode 100644 index 0000000..ecee28f --- /dev/null +++ b/src/drivers/ipmi/Makefile.inc @@ -0,0 +1 @@ +driver-$(CONFIG_IPMI_KCS) += ipmi_kcs.c diff --git a/src/drivers/ipmi/ipmi_kcs.c b/src/drivers/ipmi/ipmi_kcs.c new file mode 100644 index 0000000..9be1433 --- /dev/null +++ b/src/drivers/ipmi/ipmi_kcs.c @@ -0,0 +1,232 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <arch/io.h> +#include <string.h> +#include <delay.h> +#include "ipmi_kcs.h" + +#define IPMI_KCS_STATE(_x) ((_x) >> 6) + +#define IPMI_KCS_GET_STATUS_ABORT +#define IPMI_KCS_START_WRITE 0x61 +#define IPMI_KCS_END_WRITE 0x62 +#define IPMI_KCS_READ_BYTE 0x68 + +#define IPMI_KCS_OBF 0x01 +#define IPMI_KCS_IBF 0x02 +#define IPMI_KCS_ATN 0x04 + +#define IPMI_KCS_STATE_IDLE 0x00 +#define IPMI_KCS_STATE_READ 0x01 +#define IPMI_KCS_STATE_WRITE 0x02 +#define IPMI_KCS_STATE_ERROR 0x03 + +#define IPMI_CMD(_x) ((_x) + 1) +#define IPMI_DATA(_x) ((_x)) +#define IPMI_STAT(_x) ((_x) + 1) + +static unsigned char ipmi_kcs_status(int port) +{ + unsigned char status = inb(IPMI_STAT(port)); + printk(BIOS_DEBUG, "%s: 0x%02x\n", __func__, status); + return status; +} + +static int wait_ibf_timeout(int port) +{ + int timeout = 1000; + do { + if (!(ipmi_kcs_status(port) & IPMI_KCS_IBF)) + return 0; + udelay(100); + } while(timeout--); + printk(BIOS_ERR, "wait_ibf timeout!\n"); + return timeout; +} + +static int wait_obf_timeout(int port) +{ + int timeout = 1000; + do { + if ((ipmi_kcs_status(port) & IPMI_KCS_OBF)) + return 0; + udelay(100); + } while(timeout--); + + printk(BIOS_ERR, "wait_obf timeout!\n"); + return timeout; +} + + +static int ipmi_kcs_send_data_byte(int port, const unsigned char byte) +{ + unsigned char status; + + printk(BIOS_DEBUG, "%s: %02x\n", __func__, byte); + + outb(byte, IPMI_DATA(port)); + + if (wait_ibf_timeout(port)) + return 1; + + status = ipmi_kcs_status(port); + if ((status & IPMI_KCS_OBF) && + IPMI_KCS_STATE(status) != IPMI_KCS_STATE_WRITE) { + printk(BIOS_ERR, "%s: status %02x\n", __func__, status); + return 1; + } + + if (ipmi_kcs_status(port) & IPMI_KCS_OBF) + inb(IPMI_DATA(port)); + return 0; +} + +static int ipmi_kcs_send_last_data_byte(int port, const unsigned char byte) +{ + unsigned char status; + + printk(BIOS_DEBUG, "%s: %02x\n", __func__, byte); + + if (wait_ibf_timeout(port)) + return 1; + + status = ipmi_kcs_status(port); + if ((status & IPMI_KCS_OBF) && + IPMI_KCS_STATE(status) != IPMI_KCS_STATE_WRITE) { + printk(BIOS_ERR, "%s: status %02x\n", __func__, status); + return 1; + } + + if (ipmi_kcs_status(port) & IPMI_KCS_OBF) + inb(IPMI_DATA(port)); + + outb(byte, IPMI_DATA(port)); + return 0; +} + +static int ipmi_kcs_send_cmd_byte(int port, const unsigned char byte) +{ + printk(BIOS_DEBUG, "%s: 0x%02x\n", __func__, byte); + + if (wait_ibf_timeout(port)) + return 1; + + if (ipmi_kcs_status(port) & IPMI_KCS_OBF) + inb(IPMI_DATA(port)); + outb(byte, IPMI_CMD(port)); + + if (wait_ibf_timeout(port)) + return 1; + + if (ipmi_kcs_status(port) & IPMI_KCS_OBF) + inb(IPMI_DATA(port)); + + return 0; +} + +static int ipmi_kcs_send_message(int port, int netfn, int lun, int cmd, + const unsigned char *msg, int len) +{ + int ret; + + if ((ret = ipmi_kcs_send_cmd_byte(port, IPMI_KCS_START_WRITE))) { + printk(BIOS_ERR, "IPMI START WRITE failed\n"); + return ret; + } + + if ((ret = ipmi_kcs_send_data_byte(port, (netfn << 2) | (lun & 3)))) { + printk(BIOS_ERR, "IPMI NETFN failed\n"); + return ret; + } + + if ((ret = ipmi_kcs_send_data_byte(port, cmd))) { + printk(BIOS_ERR, "IPMI CMD failed\n"); + return ret; + } + + while(len-- > 1) { + if ((ret = ipmi_kcs_send_data_byte(port, *msg++))) { + printk(BIOS_ERR, "IPMI BYTE WRITE failed\n"); + return ret; + } + } + + if ((ret = ipmi_kcs_send_cmd_byte(port, IPMI_KCS_END_WRITE))) { + printk(BIOS_ERR, "IPMI END WRITE failed\n"); + return ret; + } + + if ((ret = ipmi_kcs_send_last_data_byte(port, *msg++))) { + printk(BIOS_ERR, "IPMI BYTE WRITE failed\n"); + return ret; + } + return 0; +} + +static int ipmi_kcs_read_message(int port, unsigned char *msg, int len) +{ + int status, ret = 0; + + if (!msg) + return 0; + + if (wait_ibf_timeout(port)) + return 1; + + for(;;) { + status = ipmi_kcs_status(port); + + if (IPMI_KCS_STATE(status) == IPMI_KCS_STATE_IDLE) + return ret; + + if (IPMI_KCS_STATE(status) != IPMI_KCS_STATE_READ) { + printk(BIOS_ERR, "%s: wrong state: 0x%02x\n", __func__, status); + return -1; + } + + if (wait_obf_timeout(port)) + return -1; + + *msg++ = inb(IPMI_DATA(port)); + ret++; + + if (wait_ibf_timeout(port)) + return -1; + + outb(IPMI_KCS_READ_BYTE, IPMI_DATA(port)); + } + return ret; +} + +int ipmi_kcs_message(int port, int netfn, int lun, int cmd, + const unsigned char *inmsg, int inlen, + unsigned char *outmsg, int outlen) +{ + if (ipmi_kcs_send_message(port, netfn, lun, cmd, inmsg, inlen)) { + printk(BIOS_ERR, "ipmi_kcs_send_message failed\n"); + return -1; + } + + return ipmi_kcs_read_message(port, outmsg, outlen); +} diff --git a/src/drivers/ipmi/ipmi_kcs.h b/src/drivers/ipmi/ipmi_kcs.h new file mode 100644 index 0000000..cc4156a --- /dev/null +++ b/src/drivers/ipmi/ipmi_kcs.h @@ -0,0 +1,37 @@ +#ifndef __IPMI_KCS_H +#define __IPMI_KCS_H +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#define IPMI_NETFN_CHASSIS 0x00 +#define IPMI_NETFN_BRIDGE 0x02 +#define IPMI_NETFN_SENSOREVENT 0x04 +#define IPMI_NETFN_APPLICATION 0x06 +#define IPMI_NETFN_FIRMWARE 0x08 +#define IPMI_NETFN_STORAGE 0x0a +#define IPMI_NETFN_TRANSPORT 0x0c + +#define IPMI_CMD_ACPI_POWERON 0x06 + +extern int ipmi_kcs_message(int port, int netfn, int lun, int cmd, + const unsigned char *inmsg, int inlen, + unsigned char *outmsg, int outlen); +#endif

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Re: [coreboot] [ltp] Re: [Thinkpad] Free T60
by Peter Stuge 08 Jul '12

08 Jul '12

Idwer Vollering wrote: > I have a X60 (1707-CTO / 1707YAU) that won't boot Linux (it > segfaults while booting either a 32- or 64-bit kernel/distribution) > at all, with ACPI enabled. What does the failed boot look like? Maybe you could try netconsole or at least take a photo of the screen from the crash? //Peter

2 1

Re: [coreboot] [ltp] Re: [Thinkpad] Free T60
by Carl-Daniel Hailfinger 08 Jul '12

08 Jul '12

[adding coreboot mailing list to CC] Am 29.06.2012 16:49 schrieb Stefan Monnier: >> You do know that all Thinkpad T60/X60 can replace the BIOS with coreboot? > No, I didn't, that would be wonderful news. > I see a few mentions of T60 support when googling for it, but nothing > sufficiently clear to make me confident I would know how to flash it and > I'd be able to assess whether I'm flashing the right firmware. Admittedly the information about coreboot on a T60/X60 is spread around quite a bit: http://www.coreboot.org/Thinkpad_X60s has some status info http://www.coreboot.org/pipermail/coreboot/2012-January/067959.html has some info on how to replace the BIOS on that machine with coreboot, but read the WHOLE thread because the linked mail had a few typos in the description. > Any pointers to information about it would be very welcome (e.g. which > T60 are "supported" or at least expected to work? AFAIK all T60/X60 variants work with coreboot. Sven Schnelle knows more, he is the one who ported coreboot to those thinkpads. > does flashrom work or do I need some hardware-mod? You need a small flashrom patch and the bucts utility, no hardware mod needed. > how easily can I revert to the proprietary > firmware if something (e.g. suspend) doesn't work quite right?) You can simply reflash the original BIOS to the flash chip if you're running coreboot. Regards, Carl-Daniel

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Patch set updated for coreboot: d7c5f67 Drop invalid device ops on Agesa northbridge
by Kyösti Mälkki 07 Jul '12

07 Jul '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1180 -gerrit commit d7c5f67d76a7995ac4f0667ab7a875c60f583799 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jul 6 17:27:37 2012 +0300 Drop invalid device ops on Agesa northbridge One could not pass a device of type APIC to PCI resource functions. The correct CPU model specific cpu->ops is set at later time in cpu_initialize(). Change-Id: Ifa274185e4db3080433c1f07e3a48f2b55c0514f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/agesa/family10/northbridge.c | 18 ------------------ src/northbridge/amd/agesa/family15/northbridge.c | 18 ------------------ src/northbridge/amd/agesa/family15tn/northbridge.c | 18 ------------------ 3 files changed, 0 insertions(+), 54 deletions(-) diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 7b73987..3088f54 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -1231,21 +1231,6 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -/* dummy read_resources */ -static void lapic_read_resources(device_t dev) -{ -} - -static struct device_operations lapic_ops = { - .read_resources = lapic_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, - .enable = 0, - .ops_pci = 0, -}; - static u32 cpu_bus_scan(device_t dev, u32 max) { struct bus *cpu_bus; @@ -1447,9 +1432,6 @@ static u32 cpu_bus_scan(device_t dev, u32 max) if (cpu) { cpu->path.apic.node_id = i; cpu->path.apic.core_id = j; - if (cpu->path.type == DEVICE_PATH_APIC) { - cpu->ops = &lapic_ops; - } printk(BIOS_DEBUG, "CPU: %s %s\n", dev_path(cpu), cpu->enabled?"enabled":"disabled"); } diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 130086e..5b22707 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -889,21 +889,6 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -/* dummy read_resources */ -static void lapic_read_resources(device_t dev) -{ -} - -static struct device_operations lapic_ops = { - .read_resources = lapic_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, - .enable = 0, - .ops_pci = 0, -}; - static u32 cpu_bus_scan(device_t dev, u32 max) { struct bus *cpu_bus; @@ -1100,9 +1085,6 @@ static u32 cpu_bus_scan(device_t dev, u32 max) if (cpu) { cpu->path.apic.node_id = i; cpu->path.apic.core_id = j; - if (cpu->path.type == DEVICE_PATH_APIC) { - cpu->ops = &lapic_ops; - } printk(BIOS_DEBUG, "CPU: %s %s\n", dev_path(cpu), cpu->enabled?"enabled":"disabled"); } diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 3df5c60..d967793 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -873,21 +873,6 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -/* dummy read_resources */ -static void lapic_read_resources(device_t dev) -{ -} - -static struct device_operations lapic_ops = { - .read_resources = lapic_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, - .enable = 0, - .ops_pci = 0, -}; - static u32 cpu_bus_scan(device_t dev, u32 max) { struct bus *cpu_bus; @@ -1084,9 +1069,6 @@ static u32 cpu_bus_scan(device_t dev, u32 max) if (cpu) { cpu->path.apic.node_id = i; cpu->path.apic.core_id = j; - if (cpu->path.type == DEVICE_PATH_APIC) { - cpu->ops = &lapic_ops; - } printk(BIOS_DEBUG, "CPU: %s %s\n", dev_path(cpu), cpu->enabled?"enabled":"disabled"); }

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New patch to review for coreboot: 5da88b0 Use dev_lock for alloc_find_dev()
by Kyösti Mälkki 07 Jul '12

07 Jul '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1188 -gerrit commit 5da88b005c2b1114d49ba345893f457f44353ff3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jul 7 17:15:51 2012 +0300 Use dev_lock for alloc_find_dev() If threads called alloc_find_dev() with same device_path simultaneously, two device nodes could be allocated. This bug is not triggered by current code. Change-Id: Ifc87021c8d6f422901c5de5dd17392e3e2309afa Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/devices/device.c | 30 +++++++++++++++++++++++++++--- src/devices/device_util.c | 16 ---------------- 2 files changed, 27 insertions(+), 19 deletions(-) diff --git a/src/devices/device.c b/src/devices/device.c index ebac1a0..fafa599 100644 --- a/src/devices/device.c +++ b/src/devices/device.c @@ -66,12 +66,10 @@ DECLARE_SPIN_LOCK(dev_lock) * * @see device_path */ -device_t alloc_dev(struct bus *parent, struct device_path *path) +static device_t __alloc_dev(struct bus *parent, struct device_path *path) { device_t dev, child; - spin_lock(&dev_lock); - /* Find the last child of our parent. */ for (child = parent->children; child && child->sibling; /* */ ) child = child->sibling; @@ -99,11 +97,37 @@ device_t alloc_dev(struct bus *parent, struct device_path *path) last_dev->next = dev; last_dev = dev; + return dev; +} + +device_t alloc_dev(struct bus *parent, struct device_path *path) +{ + device_t dev; + spin_lock(&dev_lock); + dev = __alloc_dev(parent, path); spin_unlock(&dev_lock); return dev; } /** + * See if a device structure already exists and if not allocate it. + * + * @param parent The bus to find the device on. + * @param path The relative path from the bus to the appropriate device. + * @return Pointer to a device structure for the device on bus at path. + */ +device_t alloc_find_dev(struct bus *parent, struct device_path *path) +{ + device_t child; + spin_lock(&dev_lock); + child = find_dev_path(parent, path); + if (!child) + child = __alloc_dev(parent, path); + spin_unlock(&dev_lock); + return child; +} + +/** * Round a number up to an alignment. * * @param val The starting value. diff --git a/src/devices/device_util.c b/src/devices/device_util.c index 5225938..ecc2c13 100644 --- a/src/devices/device_util.c +++ b/src/devices/device_util.c @@ -48,22 +48,6 @@ device_t find_dev_path(struct bus *parent, struct device_path *path) } /** - * See if a device structure already exists and if not allocate it. - * - * @param parent The bus to find the device on. - * @param path The relative path from the bus to the appropriate device. - * @return Pointer to a device structure for the device on bus at path. - */ -device_t alloc_find_dev(struct bus *parent, struct device_path *path) -{ - device_t child; - child = find_dev_path(parent, path); - if (!child) - child = alloc_dev(parent, path); - return child; -} - -/** * Given a PCI bus and a devfn number, find the device structure. * * @param bus The bus number.

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New patch to review for coreboot: 3198466 AMD northbridges: improve appearance
by Kyösti Mälkki 07 Jul '12

07 Jul '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1187 -gerrit commit 3198466a0556b6c6d8fb0b6dda23034d9c7d7e0f Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jul 7 19:28:22 2012 +0300 AMD northbridges: improve appearance Like alloc_dev(), alloc_find_dev() will die() on allocation failure, so I skip test for cpu==NULL on that execution path. Change-Id: I03949722ac3a127319a0ad3f812d77ba7b8f139f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/agesa/family10/northbridge.c | 11 +++----- src/northbridge/amd/agesa/family14/northbridge.c | 13 +++------- src/northbridge/amd/agesa/family15/northbridge.c | 12 ++++----- src/northbridge/amd/agesa/family15tn/northbridge.c | 12 ++++----- src/northbridge/amd/amdfam10/northbridge.c | 25 +++++++------------ src/northbridge/amd/amdk8/northbridge.c | 22 ++++++----------- 6 files changed, 35 insertions(+), 60 deletions(-) diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 616a1c1..1f7b242 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -1421,13 +1421,10 @@ static u32 cpu_bus_scan(device_t dev, u32 max) cpu->enabled = 0; } - /* Report what I have done */ - if (cpu) { - cpu->path.apic.node_id = i; - cpu->path.apic.core_id = j; - printk(BIOS_DEBUG, "CPU: %s %s\n", - dev_path(cpu), cpu->enabled?"enabled":"disabled"); - } + cpu->path.apic.node_id = i; + cpu->path.apic.core_id = j; + printk(BIOS_DEBUG, "CPU: %s %s\n", + dev_path(cpu), cpu->enabled?"enabled":"disabled"); } //j } diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index f7c3b8e..de1d4a0 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -833,15 +833,10 @@ static u32 cpu_bus_scan(device_t dev, u32 max) cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = apic_id; cpu = alloc_find_dev(dev->link_list, &cpu_path); - if (cpu) { - cpu->enabled = 1; - cpu->path.apic.node_id = 0; - cpu->path.apic.core_id = apic_id; - printk(BIOS_DEBUG, "CPU: %s %s\n", - dev_path(cpu), cpu->enabled?"enabled":"disabled"); - } else { - cpu->enabled = 0; - } + cpu->path.apic.node_id = 0; + cpu->path.apic.core_id = apic_id; + printk(BIOS_DEBUG, "CPU: %s %s\n", + dev_path(cpu), cpu->enabled?"enabled":"disabled"); } return max; } diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 53629ed..5b339f2 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -1076,13 +1076,11 @@ static u32 cpu_bus_scan(device_t dev, u32 max) continue; cpu->enabled = 0; } - /* Report what I have done */ - if (cpu) { - cpu->path.apic.node_id = i; - cpu->path.apic.core_id = j; - printk(BIOS_DEBUG, "CPU: %s %s\n", - dev_path(cpu), cpu->enabled?"enabled":"disabled"); - } + + cpu->path.apic.node_id = i; + cpu->path.apic.core_id = j; + printk(BIOS_DEBUG, "CPU: %s %s\n", + dev_path(cpu), cpu->enabled?"enabled":"disabled"); } //j } return max; diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 73aebad..133940c 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -1060,13 +1060,11 @@ static u32 cpu_bus_scan(device_t dev, u32 max) continue; cpu->enabled = 0; } - /* Report what I have done */ - if (cpu) { - cpu->path.apic.node_id = i; - cpu->path.apic.core_id = j; - printk(BIOS_DEBUG, "CPU: %s %s\n", - dev_path(cpu), cpu->enabled?"enabled":"disabled"); - } + + cpu->path.apic.node_id = i; + cpu->path.apic.core_id = j; + printk(BIOS_DEBUG, "CPU: %s %s\n", + dev_path(cpu), cpu->enabled?"enabled":"disabled"); } //j } return max; diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 8d654bd..4f49a0f 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -1414,24 +1414,17 @@ static u32 cpu_bus_scan(device_t dev, u32 max) cpu->enabled = 0; } - /* Report what I have done */ - if (cpu) { - cpu->path.apic.node_id = i; - cpu->path.apic.core_id = j; - #if CONFIG_ENABLE_APIC_EXT_ID && (CONFIG_APIC_ID_OFFSET>0) - if(sysconf.enabled_apic_ext_id) { - if(sysconf.lift_bsp_apicid) { - cpu->path.apic.apic_id += sysconf.apicid_offset; - } else - { - if (cpu->path.apic.apic_id != 0) - cpu->path.apic.apic_id += sysconf.apicid_offset; - } +#if CONFIG_ENABLE_APIC_EXT_ID && (CONFIG_APIC_ID_OFFSET>0) + if(sysconf.enabled_apic_ext_id) { + if (cpu->path.apic.apic_id != 0 || sysconf.lift_bsp_apicid) { + cpu->path.apic.apic_id += sysconf.apicid_offset; } - #endif - printk(BIOS_DEBUG, "CPU: %s %s\n", - dev_path(cpu), cpu->enabled?"enabled":"disabled"); } +#endif + cpu->path.apic.node_id = i; + cpu->path.apic.core_id = j; + printk(BIOS_DEBUG, "CPU: %s %s\n", + dev_path(cpu), cpu->enabled?"enabled":"disabled"); } //j } diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 17ea4f6..383a774 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -1300,23 +1300,17 @@ static u32 cpu_bus_scan(device_t dev, u32 max) cpu->enabled = 0; } - /* Report what I have done */ - if (cpu) { - cpu->path.apic.node_id = i; - cpu->path.apic.core_id = j; - if(sysconf.enabled_apic_ext_id) { - if(sysconf.lift_bsp_apicid) { - cpu->path.apic.apic_id += sysconf.apicid_offset; - } else - { - if (cpu->path.apic.apic_id != 0) - cpu->path.apic.apic_id += sysconf.apicid_offset; - } + if(sysconf.enabled_apic_ext_id) { + if (cpu->path.apic.apic_id != 0 || sysconf.lift_bsp_apicid) { + cpu->path.apic.apic_id += sysconf.apicid_offset; } - printk(BIOS_DEBUG, "CPU: %s %s\n", - dev_path(cpu), cpu->enabled?"enabled":"disabled"); } + cpu->path.apic.node_id = i; + cpu->path.apic.core_id = j; + printk(BIOS_DEBUG, "CPU: %s %s\n", + dev_path(cpu), cpu->enabled?"enabled":"disabled"); + } //j } return max;

1 0

New patch to review for coreboot: eb5dc56 AMD northbridges: replace alloc_dev() with alloc_find_dev()
by Kyösti Mälkki 07 Jul '12

07 Jul '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1186 -gerrit commit eb5dc565c3f0604d8f501fb4273687b2b9ce2bd4 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jul 6 19:02:56 2012 +0300 AMD northbridges: replace alloc_dev() with alloc_find_dev() Use of alloc_find_dev() prevents creation of a device duplicating existing device_path and can be made SMP safe. Change-Id: I153dc1a5cab4f2eae4ab3a57af02841cb1a261c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/agesa/family10/northbridge.c | 21 ++++++------------- src/northbridge/amd/agesa/family15/northbridge.c | 19 ++++++----------- src/northbridge/amd/agesa/family15tn/northbridge.c | 19 ++++++----------- src/northbridge/amd/amdfam10/northbridge.c | 21 ++++++------------- src/northbridge/amd/amdk8/northbridge.c | 21 ++++++------------- 5 files changed, 35 insertions(+), 66 deletions(-) diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 3088f54..616a1c1 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -1410,21 +1410,14 @@ static u32 cpu_bus_scan(device_t dev, u32 max) } cpu_path.apic.apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (cores_found + 1)) : j); - /* See if I can find the cpu */ - cpu = find_dev_path(cpu_bus, &cpu_path); - - /* Enable the cpu if I have the processor */ if (cdb_dev && cdb_dev->enabled) { - if (!cpu) { - cpu = alloc_dev(cpu_bus, &cpu_path); - } - if (cpu) { - cpu->enabled = 1; - } - } - - /* Disable the cpu if I don't have the processor */ - if (cpu && (!cdb_dev || !cdb_dev->enabled)) { + /* Enable the cpu if I have the processor */ + cpu = alloc_find_dev(cpu_bus, &cpu_path); + } else { + /* Disable the cpu if I don't have the processor */ + cpu = find_dev_path(cpu_bus, &cpu_path); + if (!cpu) + continue; cpu->enabled = 0; } diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 5b22707..53629ed 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -1066,19 +1066,14 @@ static u32 cpu_bus_scan(device_t dev, u32 max) printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", i, j, cpu_path.apic.apic_id); - /* See if I can find the cpu */ - cpu = find_dev_path(cpu_bus, &cpu_path); - /* Enable the cpu if I have the processor */ if (cdb_dev && cdb_dev->enabled) { - if (!cpu) { - cpu = alloc_dev(cpu_bus, &cpu_path); - } - if (cpu) { - cpu->enabled = 1; - } - } - /* Disable the cpu if I don't have the processor */ - if (cpu && (!cdb_dev || !cdb_dev->enabled)) { + /* Enable the cpu if I have the processor */ + cpu = alloc_find_dev(cpu_bus, &cpu_path); + } else { + /* Disable the cpu if I don't have the processor */ + cpu = find_dev_path(cpu_bus, &cpu_path); + if (!cpu) + continue; cpu->enabled = 0; } /* Report what I have done */ diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index d967793..73aebad 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -1050,19 +1050,14 @@ static u32 cpu_bus_scan(device_t dev, u32 max) printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", i, j, cpu_path.apic.apic_id); - /* See if I can find the cpu */ - cpu = find_dev_path(cpu_bus, &cpu_path); - /* Enable the cpu if I have the processor */ if (cdb_dev && cdb_dev->enabled) { - if (!cpu) { - cpu = alloc_dev(cpu_bus, &cpu_path); - } - if (cpu) { - cpu->enabled = 1; - } - } - /* Disable the cpu if I don't have the processor */ - if (cpu && (!cdb_dev || !cdb_dev->enabled)) { + /* Enable the cpu if I have the processor */ + cpu = alloc_find_dev(cpu_bus, &cpu_path); + } else { + /* Disable the cpu if I don't have the processor */ + cpu = find_dev_path(cpu_bus, &cpu_path); + if (!cpu) + continue; cpu->enabled = 0; } /* Report what I have done */ diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 3b20684..8d654bd 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -1403,21 +1403,14 @@ static u32 cpu_bus_scan(device_t dev, u32 max) cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:64); // ? - /* See if I can find the cpu */ - cpu = find_dev_path(cpu_bus, &cpu_path); - - /* Enable the cpu if I have the processor */ if (cdb_dev && cdb_dev->enabled) { - if (!cpu) { - cpu = alloc_dev(cpu_bus, &cpu_path); - } - if (cpu) { - cpu->enabled = 1; - } - } - - /* Disable the cpu if I don't have the processor */ - if (cpu && (!cdb_dev || !cdb_dev->enabled)) { + /* Enable the cpu if I have the processor */ + cpu = alloc_find_dev(cpu_bus, &cpu_path); + } else { + /* Disable the cpu if I don't have the processor */ + cpu = find_dev_path(cpu_bus, &cpu_path); + if (!cpu) + continue; cpu->enabled = 0; } diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 5eeeda2..17ea4f6 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -1289,21 +1289,14 @@ static u32 cpu_bus_scan(device_t dev, u32 max) cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8); - /* See if I can find the cpu */ - cpu = find_dev_path(cpu_bus, &cpu_path); - - /* Enable the cpu if I have the processor */ if (cpu_dev && cpu_dev->enabled) { - if (!cpu) { - cpu = alloc_dev(cpu_bus, &cpu_path); - } - if (cpu) { - cpu->enabled = 1; - } - } - - /* Disable the cpu if I don't have the processor */ - if (cpu && (!cpu_dev || !cpu_dev->enabled)) { + /* Enable the cpu if I have the processor */ + cpu = alloc_find_dev(cpu_bus, &cpu_path); + } else { + /* Disable the cpu if I don't have the processor */ + cpu = find_dev_path(cpu_bus, &cpu_path); + if (!cpu) + continue; cpu->enabled = 0; }

1 0

Patch set updated for coreboot: b2c03e9 Move cpus_ready_for_init() to AMD K8
by Kyösti Mälkki 07 Jul '12

07 Jul '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1184 -gerrit commit b2c03e9311306b5710c1e2c4eb32b747094d996e Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jul 7 13:42:03 2012 +0300 Move cpus_ready_for_init() to AMD K8 The function is a noop for all but amd/serengeti_cheetah. Change-Id: I09e2e710aa964c2f31e35fcea4f14856cc1e1dca Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/x86/Kconfig | 4 ---- src/cpu/x86/lapic/lapic_cpu_init.c | 2 -- src/include/cpu/cpu.h | 6 ------ src/mainboard/amd/pistachio/Kconfig | 1 - src/mainboard/ibm/e325/Kconfig | 1 - src/mainboard/ibm/e326/Kconfig | 1 - src/mainboard/iwill/dk8_htx/Kconfig | 1 - src/mainboard/iwill/dk8s2/Kconfig | 1 - src/mainboard/iwill/dk8x/Kconfig | 1 - src/mainboard/msi/ms9652_fam10/Kconfig | 4 ---- src/mainboard/technexion/tim8690/Kconfig | 1 - src/northbridge/amd/amdk8/Kconfig | 4 ++++ src/northbridge/amd/amdk8/amdk8.h | 2 ++ src/northbridge/amd/amdk8/northbridge.c | 3 +++ 14 files changed, 9 insertions(+), 23 deletions(-) diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index de40c05..d7240de 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -1,7 +1,3 @@ -config WAIT_BEFORE_CPUS_INIT - bool - default n - config UDELAY_IO bool default y if !UDELAY_LAPIC && !UDELAY_TSC diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index b6dc560..302eeba 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -286,8 +286,6 @@ void initialize_cpus(struct bus *cpu_bus) smm_init(); #endif - cpus_ready_for_init(); - /* Initialize the bootstrap processor */ cpu_initialize(cpu_bus, 0); diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index 9765dfd..90e4620 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -11,12 +11,6 @@ void secondary_cpu_init(int index); extern unsigned int cpucount; -#if !CONFIG_WAIT_BEFORE_CPUS_INIT - #define cpus_ready_for_init() do {} while(0) -#else - void cpus_ready_for_init(void); -#endif - #if CONFIG_HAVE_SMI_HANDLER void smm_init(void); void smm_lock(void); diff --git a/src/mainboard/amd/pistachio/Kconfig b/src/mainboard/amd/pistachio/Kconfig index d140878..a83fbcf 100644 --- a/src/mainboard/amd/pistachio/Kconfig +++ b/src/mainboard/amd/pistachio/Kconfig @@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select WAIT_BEFORE_CPUS_INIT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 select RAMINIT_SYSINFO diff --git a/src/mainboard/ibm/e325/Kconfig b/src/mainboard/ibm/e325/Kconfig index 9ef4c48..839ea8f 100644 --- a/src/mainboard/ibm/e325/Kconfig +++ b/src/mainboard/ibm/e325/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select WAIT_BEFORE_CPUS_INIT select BOARD_ROMSIZE_KB_512 select QRANK_DIMM_SUPPORT diff --git a/src/mainboard/ibm/e326/Kconfig b/src/mainboard/ibm/e326/Kconfig index 475cb85..ac52534 100644 --- a/src/mainboard/ibm/e326/Kconfig +++ b/src/mainboard/ibm/e326/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select WAIT_BEFORE_CPUS_INIT select BOARD_ROMSIZE_KB_512 select QRANK_DIMM_SUPPORT diff --git a/src/mainboard/iwill/dk8_htx/Kconfig b/src/mainboard/iwill/dk8_htx/Kconfig index 5ad70f3..5f9920a 100644 --- a/src/mainboard/iwill/dk8_htx/Kconfig +++ b/src/mainboard/iwill/dk8_htx/Kconfig @@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select LIFT_BSP_APIC_ID select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select WAIT_BEFORE_CPUS_INIT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO diff --git a/src/mainboard/iwill/dk8s2/Kconfig b/src/mainboard/iwill/dk8s2/Kconfig index 7fda0a6..f13d06a 100644 --- a/src/mainboard/iwill/dk8s2/Kconfig +++ b/src/mainboard/iwill/dk8s2/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_MP_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select WAIT_BEFORE_CPUS_INIT select DRIVERS_ATI_RAGEXL select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO diff --git a/src/mainboard/iwill/dk8x/Kconfig b/src/mainboard/iwill/dk8x/Kconfig index 452b6e6..a17f104 100644 --- a/src/mainboard/iwill/dk8x/Kconfig +++ b/src/mainboard/iwill/dk8x/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select WAIT_BEFORE_CPUS_INIT select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT diff --git a/src/mainboard/msi/ms9652_fam10/Kconfig b/src/mainboard/msi/ms9652_fam10/Kconfig index a1f69c8..0856ff8 100644 --- a/src/mainboard/msi/ms9652_fam10/Kconfig +++ b/src/mainboard/msi/ms9652_fam10/Kconfig @@ -157,10 +157,6 @@ config MEM_TRAIN_SEQ int default 2 -config WAIT_BEFORE_CPUS_INIT - bool - default n - config AMD_UCODE_PATCH_FILE string default "mc_patch_01000096.h" diff --git a/src/mainboard/technexion/tim8690/Kconfig b/src/mainboard/technexion/tim8690/Kconfig index 293590c..6bfa814 100644 --- a/src/mainboard/technexion/tim8690/Kconfig +++ b/src/mainboard/technexion/tim8690/Kconfig @@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select WAIT_BEFORE_CPUS_INIT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index 70e75e9..9ea5404 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -33,6 +33,10 @@ config K8_HT_FREQ_1G_SUPPORT bool default n +config WAIT_BEFORE_CPUS_INIT + bool + default n + config MEM_TRAIN_SEQ int default 0 diff --git a/src/northbridge/amd/amdk8/amdk8.h b/src/northbridge/amd/amdk8/amdk8.h index 5aa3b31..e001706 100644 --- a/src/northbridge/amd/amdk8/amdk8.h +++ b/src/northbridge/amd/amdk8/amdk8.h @@ -14,4 +14,6 @@ void setup_resource_map_offset(const unsigned int *register_values, int max, uns void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const uint16_t *spd_addr); #endif +void cpus_ready_for_init(void); + #endif /* AMDK8_H */ diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 5eeeda2..cf80389 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -1331,6 +1331,9 @@ static u32 cpu_bus_scan(device_t dev, u32 max) static void cpu_bus_init(device_t dev) { +#if CONFIG_WAIT_BEFORE_CPUS_INIT + cpus_ready_for_init(); +#endif initialize_cpus(dev->link_list); }

1 0

New patch to review for coreboot: 763eae2 IEI PM-LX-800-R11: Removed Core/GLIU Kconfig options
by Ricardo Martins 07 Jul '12

07 Jul '12

Ricardo Martins (rasmartins(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1185 -gerrit commit 763eae221a6037f67773080eefeea9327cfea9c9 Author: Ricardo Martins <rasmartins(a)gmail.com> Date: Sat Jul 7 14:33:18 2012 +0100 IEI PM-LX-800-R11: Removed Core/GLIU Kconfig options Configuring the Core/GLIU frequencies in the Kconfig file was deemed a bad solution. This change hard-codes safe values and removes the Kconfig options. Change-Id: I952ef0c3955e87ad1f113e14b4649578ba32f476 Signed-off-by: Ricardo Martins <rasmartins(a)gmail.com> --- src/mainboard/iei/pm-lx-800-r11/Kconfig | 15 --------------- src/mainboard/iei/pm-lx-800-r11/romstage.c | 11 ++--------- 2 files changed, 2 insertions(+), 24 deletions(-) diff --git a/src/mainboard/iei/pm-lx-800-r11/Kconfig b/src/mainboard/iei/pm-lx-800-r11/Kconfig index a897106..d3b97b8 100644 --- a/src/mainboard/iei/pm-lx-800-r11/Kconfig +++ b/src/mainboard/iei/pm-lx-800-r11/Kconfig @@ -45,19 +45,4 @@ config IRQ_SLOT_COUNT int default 7 -choice - prompt "Core/GLIU Frequency" - default CORE_GLIU_500_266 - -config CORE_GLIU_500_266 - bool "500MHz / 266MHz" - -config CORE_GLIU_500_333 - bool "500MHz / 333MHz" - -config CORE_GLIU_500_400 - bool "500MHz / 400MHz" - -endchoice - endif # BOARD_IEI_PM_LX_800_R11 diff --git a/src/mainboard/iei/pm-lx-800-r11/romstage.c b/src/mainboard/iei/pm-lx-800-r11/romstage.c index f756622..d91140f 100644 --- a/src/mainboard/iei/pm-lx-800-r11/romstage.c +++ b/src/mainboard/iei/pm-lx-800-r11/romstage.c @@ -46,15 +46,8 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#if CONFIG_CORE_GLIU_500_400 -# define PLLMSRhi 0x0000059c -#elif CONFIG_CORE_GLIU_500_333 -# define PLLMSRhi 0x0000049c -#else -# define PLLMSRhi 0x0000039c -#endif - -#define PLLMSRlo 0x07de000 +#define PLLMSRhi 0x0000039c +#define PLLMSRlo 0x07de0000 #include <northbridge/amd/lx/raminit.h> #include <northbridge/amd/lx/pll_reset.c>

1 0

Patch set updated for coreboot: 8e42230 IEI PM-LX2-800-R10: Added preliminary mainboard support
by Ricardo Martins 07 Jul '12

07 Jul '12

Ricardo Martins (rasmartins(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1152 -gerrit commit 8e42230abc34bc105f70325f5fa2aab68bda40ee Author: Ricardo Martins <rasmartins(a)gmail.com> Date: Sat Jul 7 14:27:03 2012 +0100 IEI PM-LX2-800-R10: Added preliminary mainboard support Details for this board are available at http://usa.ieiworld.com/product_groups/industrial/content.aspx?gid=00001000… Most of the functionality provided by the original BIOS is implemented. The Geode Link Speed is hardcoded to a safe value. I'll add automatic configuration in a later patch. Change-Id: Iaefe47f5ad405a56d230c929e5850156eb0f60ae Signed-off-by: Ricardo Martins <rasmartins(a)gmail.com> --- src/mainboard/iei/Kconfig | 3 + src/mainboard/iei/pm-lx2-800-r10/Kconfig | 56 ++++++++++ src/mainboard/iei/pm-lx2-800-r10/chip.h | 23 ++++ src/mainboard/iei/pm-lx2-800-r10/cmos.layout | 103 ++++++++++++++++++ src/mainboard/iei/pm-lx2-800-r10/devicetree.cb | 87 +++++++++++++++ src/mainboard/iei/pm-lx2-800-r10/irq_tables.c | 134 ++++++++++++++++++++++++ src/mainboard/iei/pm-lx2-800-r10/it8888_io.def | 27 +++++ src/mainboard/iei/pm-lx2-800-r10/mainboard.c | 103 ++++++++++++++++++ src/mainboard/iei/pm-lx2-800-r10/romstage.c | 94 +++++++++++++++++ 9 files changed, 630 insertions(+), 0 deletions(-) diff --git a/src/mainboard/iei/Kconfig b/src/mainboard/iei/Kconfig index ea26922..537252d 100644 --- a/src/mainboard/iei/Kconfig +++ b/src/mainboard/iei/Kconfig @@ -31,6 +31,8 @@ config BOARD_IEI_PCISA_LX_800_R10 bool "PCISA LX-800-R10" config BOARD_IEI_PM_LX_800_R11 bool "PM LX-800-R11" +config BOARD_IEI_PM_LX2_800_R10 + bool "PM-LX2-800-R10" endchoice @@ -39,6 +41,7 @@ source "src/mainboard/iei/kino-780am2-fam10/Kconfig" source "src/mainboard/iei/nova4899r/Kconfig" source "src/mainboard/iei/pcisa-lx-800-r10/Kconfig" source "src/mainboard/iei/pm-lx-800-r11/Kconfig" +source "src/mainboard/iei/pm-lx2-800-r10/Kconfig" config MAINBOARD_VENDOR string diff --git a/src/mainboard/iei/pm-lx2-800-r10/Kconfig b/src/mainboard/iei/pm-lx2-800-r10/Kconfig new file mode 100644 index 0000000..ee88ce4 --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/Kconfig @@ -0,0 +1,56 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +if BOARD_IEI_PM_LX2_800_R10 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ARCH_X86 + select CPU_AMD_GEODE_LX + select NORTHBRIDGE_AMD_LX + select SOUTHBRIDGE_AMD_CS5536 + select SUPERIO_SMSC_SMSCSUPERIO + select HAVE_PIRQ_TABLE + select HAVE_OPTION_TABLE + select PIRQ_ROUTE + select BOARD_ROMSIZE_KB_512 + select POWER_BUTTON_FORCE_ENABLE + +config MAINBOARD_DIR + string + default iei/pm-lx2-800-r10 + +config MAINBOARD_PART_NUMBER + string + default "PM-LX2-800-R10" + +config IRQ_SLOT_COUNT + int + default 3 + +config SCH3114_COM3_AUTO_DIR + bool "COM3 Automatic Direction Control" + default y + help + If selected, COM3 automatic direction control will + be enabled by default. + +endif # BOARD_IEI_PM_LX2_800_R10 diff --git a/src/mainboard/iei/pm-lx2-800-r10/chip.h b/src/mainboard/iei/pm-lx2-800-r10/chip.h new file mode 100644 index 0000000..d69f9b6 --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/iei/pm-lx2-800-r10/cmos.layout b/src/mainboard/iei/pm-lx2-800-r10/cmos.layout new file mode 100644 index 0000000..e09cfb6 --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/cmos.layout @@ -0,0 +1,103 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +entries + # RTC + 0 384 r 0 reserved_rtc + # Coreboot + 384 1 e 3 boot_option + 385 1 e 3 last_boot + 386 4 r 0 reboot_bits + 390 3 e 4 baud_rate + 393 4 e 5 debug_level + 397 2 r 0 unused + # PM-LX2-800-R10 + 399 1 e 1 com3_auto_direction + 400 1 e 2 it8888_io_space0 + 401 1 e 2 it8888_io_space1 + 402 1 e 2 it8888_io_space2 + 403 1 e 2 it8888_io_space3 + 404 2 e 6 it8888_io_space0_speed + 406 2 e 6 it8888_io_space1_speed + 408 2 e 6 it8888_io_space2_speed + 410 2 e 6 it8888_io_space3_speed + 412 3 e 7 it8888_io_space0_size + 415 3 e 7 it8888_io_space1_size + 418 3 e 7 it8888_io_space2_size + 421 3 e 7 it8888_io_space3_size + 424 16 h 0 it8888_io_space0_addr + 440 16 h 0 it8888_io_space1_addr + 456 16 h 0 it8888_io_space2_addr + 472 16 h 0 it8888_io_space3_addr + 488 16 h 0 check_sum + +enumerations + # Yes / No + 1 0 No + 1 1 Yes + + # Enabled / Disabled + 2 0 Disabled + 2 1 Enabled + + # Normal / Fallback + 3 0 Fallback + 3 1 Normal + + # Console Baud Rate + 4 0 115200 + 4 1 57600 + 4 2 38400 + 4 3 19200 + 4 4 9600 + 4 5 4800 + 4 6 2400 + 4 7 1200 + + # Console Log Level + 5 0 Emergency + 5 1 Alert + 5 2 Critical + 5 3 Error + 5 4 Warning + 5 5 Notice + 5 6 Info + 5 7 Debug + 5 8 Spew + + # IT8888 Decoding Speeds + 6 0 Subtractive + 6 1 Slow + 6 2 Medium + 6 3 Fast + + # IT8888 Decoding Sizes + 7 0 1 + 7 1 2 + 7 2 4 + 7 3 8 + 7 4 16 + 7 5 32 + 7 6 64 + 7 7 128 + +checksums + checksum 384 487 488 diff --git a/src/mainboard/iei/pm-lx2-800-r10/devicetree.cb b/src/mainboard/iei/pm-lx2-800-r10/devicetree.cb new file mode 100644 index 0000000..f5721a3 --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/devicetree.cb @@ -0,0 +1,87 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +chip northbridge/amd/lx + device pci_domain 0 on + device pci 1.0 on end # Northbridge + device pci 1.1 on end # Video Adapter + device pci 1.2 on end # AES Security Block + chip southbridge/amd/cs5536 + register "lpc_serirq_enable" = "0x000010da" + register "lpc_serirq_polarity" = "0x0000ef25" + register "lpc_serirq_mode" = "1" + register "enable_gpio_int_route" = "0x0d0c0700" + register "enable_ide_nand_flash" = "0" + register "enable_USBP4_device" = "0" # 0:host, 1:device + register "enable_USBP4_overcurrent" = "0" + register "com1_enable" = "0" + register "com2_enable" = "0" + register "unwanted_vpci[0]" = "0" # End of list has a zero + device pci 11.0 on end # IT8888 + device pci e.0 on end # RTL8100C + device pci f.0 on # ISA Bridge + chip superio/smsc/smscsuperio # SMSC SCH3114 + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + + device pnp 2e.3 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + + device pnp 2e.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + + device pnp 2e.5 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + + device pnp 2e.7 on # PS/2 keyboard/mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # Keyboard + irq 0x72 = 12 # Mouse + end + + device pnp 2e.a on # Runtime Register + io 0x60 = 0x400 + end + end + end + device pci f.2 on end # IDE Controller + device pci f.3 on end # Audio + device pci f.4 on end # OHCI + device pci f.5 on end # EHCI + end + end + # APIC cluster is late CPU init. + device lapic_cluster 0 on + chip cpu/amd/geode_lx + device lapic 0 on end + end + end +end diff --git a/src/mainboard/iei/pm-lx2-800-r10/irq_tables.c b/src/mainboard/iei/pm-lx2-800-r10/irq_tables.c new file mode 100644 index 0000000..2bbf218 --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/irq_tables.c @@ -0,0 +1,134 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/pci_ids.h> +#include <arch/pirq_routing.h> + +/* Platform IRQs */ +#define PIRQA 10 +#define PIRQB 10 +#define PIRQC 11 +#define PIRQD 11 + +/* Links */ +#define L_PIRQN 0 +#define L_PIRQA 1 +#define L_PIRQB 2 +#define L_PIRQC 3 +#define L_PIRQD 4 + +/* Bitmaps */ +#define B_LINKN (0) +#define B_LINK0 (1 << PIRQA) +#define B_LINK1 (1 << PIRQB) +#define B_LINK2 (1 << PIRQC) +#define B_LINK3 (1 << PIRQD) + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x0f << 3) | 0x0, /* Interrupt router dev */ + (B_LINK0 | B_LINK1 | B_LINK2 | B_LINK3),/* IRQs devoted exclusively to PCI usage */ + PCI_VENDOR_ID_AMD, /* Vendor */ + PCI_DEVICE_ID_AMD_CS5536_ISA, /* Device */ + 0, /* Miniport */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + 0x27, /* Checksum */ + { + [0] = { /* Host bridge */ + .slot = 0x00, + .bus = 0x00, + .devfn = (0x01 << 3) | 0x0, + .irq = { + [0] = { + .link = L_PIRQA, + .bitmap = B_LINK0 + }, + [1] = { + .link = L_PIRQN, + .bitmap = B_LINKN + }, + [2] = { + .link = L_PIRQN, + .bitmap = B_LINKN + }, + [3] = { + .link = L_PIRQN, + .bitmap = B_LINKN + } + } + }, + + [1] = { /* ISA bridge */ + .slot = 0x00, + .bus = 0x00, + .devfn = (0x0f << 3) | 0x0, + .irq = { + [0] = { + .link = L_PIRQN, + .bitmap = B_LINKN + }, + [1] = { + .link = L_PIRQB, + .bitmap = B_LINK1 + }, + [2] = { + .link = L_PIRQN, + .bitmap = B_LINKN + }, + [3] = { + .link = L_PIRQD, + .bitmap = B_LINK3 + } + } + }, + + [2] = { /* Ethernet */ + .slot = 0x00, + .bus = 0x00, + .devfn = (0x0e << 3) | 0x0, + .irq = { + [0] = { + .link = L_PIRQD, + .bitmap = B_LINK3 + }, + [1] = { + .link = L_PIRQN, + .bitmap = B_LINKN + }, + [2] = { + .link = L_PIRQN, + .bitmap = B_LINKN + }, + [3] = { + .link = L_PIRQN, + .bitmap = B_LINKN + } + } + } + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} diff --git a/src/mainboard/iei/pm-lx2-800-r10/it8888_io.def b/src/mainboard/iei/pm-lx2-800-r10/it8888_io.def new file mode 100644 index 0000000..5920abc --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/it8888_io.def @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Name, Register, Enabled/Disabled, Speed, Size, Address. */ +IT8888_IO("it8888_io_space0", 0x58, 0, 0, 0, 0) +IT8888_IO("it8888_io_space1", 0x5c, 0, 0, 0, 0) +IT8888_IO("it8888_io_space2", 0x60, 0, 0, 0, 0) +IT8888_IO("it8888_io_space3", 0x64, 0, 0, 0, 0) +IT8888_IO("it8888_io_space4", 0x68, 0, 0, 0, 0) +IT8888_IO("it8888_io_space5", 0x6c, 0, 0, 0, 0) diff --git a/src/mainboard/iei/pm-lx2-800-r10/mainboard.c b/src/mainboard/iei/pm-lx2-800-r10/mainboard.c new file mode 100644 index 0000000..170a67a --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/mainboard.c @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/pci.h> +#include <device/device.h> +#include <boot/tables.h> +#include <pc80/mc146818rtc.h> +#include "chip.h" + +#if CONFIG_USE_OPTION_TABLE +# include "option_table.h" +#endif + +/* SCH3114 runtime register (RTR) address. */ +#define SCH3114_RTR_ADDR (0x400) +/* SP34 option register. */ +#define SCH3114_RTR_SP34_OPT (SCH3114_RTR_ADDR + 0x13) +/* H/W Monitoring register block index. */ +#define SCH3114_RTR_HWM_IDX (SCH3114_RTR_ADDR + 0x70) +/* H/W Monitoring register block data. */ +#define SCH3114_RTR_HWM_DAT (SCH3114_RTR_ADDR + 0x71) +/* H/W Monitoring Ready/Lock/Start register. */ +#define SCH3114_HWM_RLS_REG (0x40) +/* IT8888 PCI Vendor ID. */ +#define IT8888_PCI_VID (0x1283) +/* IT8888 PCI Device ID. */ +#define IT8888_PCI_DID (0x8888) + +static u16 opt(const char* option, u16 def_value) +{ +#if CONFIG_USE_OPTION_TABLE + u16 value = 0; + if (get_option(&value, option) != 0) + value = def_value; + return value; +#else + return def_value; +#endif +} + +static void init(struct device *dev) +{ + /* SCH3114: enable hardware monitor. */ + printk(BIOS_INFO, "Enabling SCH3114 hardware monitor\n"); + outb(SCH3114_HWM_RLS_REG, SCH3114_RTR_HWM_IDX); + outb(inb(SCH3114_RTR_HWM_DAT) | 0x01, SCH3114_RTR_HWM_DAT); + + /* SCH3114: COM3 Automatic Direction Control / nRTS control. */ + if (opt("com3_auto_direction", CONFIG_SCH3114_COM3_AUTO_DIR) != 0) { + printk(BIOS_INFO, "Enabling RS858 Auto Direction Control\n"); + outb(inb(SCH3114_RTR_SP34_OPT) | 0x03, SCH3114_RTR_SP34_OPT); + } + + /* IT8888. */ + device_t it8x = dev_find_device(IT8888_PCI_VID, IT8888_PCI_DID, 0); + if (!it8x) { + printk(BIOS_ERR, "IT8888 not found\n"); + return; + } + + u32 cfg = 0; +#define IT8888_IO(name, reg, dena, dspeed, dsize, daddr) \ + if (opt(name, dena) != 0) { \ + cfg = (1 << 31); \ + cfg |= opt(name "_addr", daddr); \ + cfg |= opt(name "_speed", dspeed) << 29; \ + cfg |= opt(name "_size", dsize) << 24; \ + } else { \ + cfg = 0; \ + } \ + pci_write_config32(it8x, reg, cfg); + +#include "it8888_io.def" +} + +static void enable_dev(struct device *dev) +{ + dev->ops->init = init; +} + +struct chip_operations mainboard_ops = { + CHIP_NAME("IEI PM-LX2-800-R10 Mainboard") + .enable_dev = enable_dev, +}; diff --git a/src/mainboard/iei/pm-lx2-800-r10/romstage.c b/src/mainboard/iei/pm-lx2-800-r10/romstage.c new file mode 100644 index 0000000..f632ba6 --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/romstage.c @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <stdlib.h> + +#include <spd.h> +#include <arch/io.h> +#include <arch/hlt.h> +#include <arch/llshell.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <console/console.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/lxdef.h> +#include <southbridge/amd/cs5536/cs5536.h> +#include <southbridge/amd/cs5536/early_smbus.c> +#include <southbridge/amd/cs5536/early_setup.c> +#include <superio/smsc/smscsuperio/early_serial.c> + +#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) + +static inline int spd_read_byte(unsigned int device, unsigned int address) +{ + /* Only DIMM0 is available. */ + if (device != DIMM0) + return 0xFF; + + return smbus_read_byte(device, address); +} + +#define PLLMSRhi 0x0000039c +#define PLLMSRlo 0x07de0000 + +#include <northbridge/amd/lx/raminit.h> +#include <northbridge/amd/lx/pll_reset.c> +#include <northbridge/amd/lx/raminit.c> +#include <lib/generic_sdram.c> +#include <cpu/amd/geode_lx/cpureginit.c> +#include <cpu/amd/geode_lx/syspreinit.c> +#include <cpu/amd/geode_lx/msrinit.c> + +void main(unsigned long bist) +{ + static const struct mem_controller memctrl[] = { + {.channel0 = {DIMM0, DIMM1}} + }; + + SystemPreInit(); + msr_init(); + + cs5536_early_setup(); + + smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + + /* Enable COM3. */ + device_t dev = PNP_DEV(0x2e, 0x0b); + u16 port = dev >> 8; + outb(0x55, port); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x3e8); + pnp_set_irq(dev, PNP_IDX_IRQ0, 4); + pnp_set_enable(dev, 1); + outb(0xaa, port); + + report_bist_failure(bist); + + pll_reset(1); + + cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); + + sdram_initialize(1, memctrl); +}

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coreboot July 2012