coreboot July 2012

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Patch merged into coreboot/master: f3ef4c4 IEI PM-LX-800-R11: Removed bogus Kconfig option
by gerrit＠coreboot.org 07 Jul '12

07 Jul '12

the following patch was just integrated into master: commit f3ef4c4e3777c08694dce20dd6e3a657bb8489e8 Author: Ricardo Martins <rasmartins(a)gmail.com> Date: Fri Jul 6 17:41:29 2012 +0100 IEI PM-LX-800-R11: Removed bogus Kconfig option The Kconfig file for this board contains a bogus option called CORE_GLIU, this change removes it. Change-Id: I4ea069bdd76be53085ebc9c0fb3dd71ffb2a12e1 Signed-off-by: Ricardo Martins <rasmartins(a)gmail.com> Build-Tested: build bot (Jenkins) at Sat Jul 7 10:28:22 2012, giving +1 Reviewed-By: Peter Stuge <peter(a)stuge.se> at Fri Jul 6 23:12:26 2012, giving +2 See http://review.coreboot.org/1179 for details. -gerrit

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Patch merged into coreboot/master: 8a1dbc8 inteltool: fixup intel 5000 chipset pci ids
by gerrit＠coreboot.org 07 Jul '12

07 Jul '12

the following patch was just integrated into master: commit 8a1dbc8c8be9b8c6bf28505b4faadaa51de204ee Author: Sven Schnelle <svens(a)stackframe.org> Date: Thu Jul 5 22:53:57 2012 +0200 inteltool: fixup intel 5000 chipset pci ids Change-Id: I2cd1dac0dd9a5da1000a3ffa3e1c8ee4c5c8ba43 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Build-Tested: build bot (Jenkins) at Fri Jul 6 00:20:13 2012, giving +1 Reviewed-By: Sven Schnelle <svens(a)stackframe.org> at Fri Jul 6 16:40:46 2012, giving +2 See http://review.coreboot.org/1175 for details. -gerrit

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Patch merged into coreboot/master: 687a036 i5000: Add PCI ids for all i5000 flavours
by gerrit＠coreboot.org 07 Jul '12

07 Jul '12

the following patch was just integrated into master: commit 687a036e86fa3070639858cb8bded15b73b7b86d Author: Sven Schnelle <svens(a)stackframe.org> Date: Thu Jul 5 17:17:45 2012 +0200 i5000: Add PCI ids for all i5000 flavours Change-Id: I48be647e3f38038830200bcc64429cbf86990ad7 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Build-Tested: build bot (Jenkins) at Thu Jul 5 23:36:04 2012, giving +1 Reviewed-By: Sven Schnelle <svens(a)stackframe.org> at Fri Jul 6 16:40:30 2012, giving +2 See http://review.coreboot.org/1174 for details. -gerrit

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Patch set updated for coreboot: f3ef4c4 IEI PM-LX-800-R11: Removed bogus Kconfig option
by Ricardo Martins 06 Jul '12

06 Jul '12

Ricardo Martins (rasmartins(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1179 -gerrit commit f3ef4c4e3777c08694dce20dd6e3a657bb8489e8 Author: Ricardo Martins <rasmartins(a)gmail.com> Date: Fri Jul 6 17:41:29 2012 +0100 IEI PM-LX-800-R11: Removed bogus Kconfig option The Kconfig file for this board contains a bogus option called CORE_GLIU, this change removes it. Change-Id: I4ea069bdd76be53085ebc9c0fb3dd71ffb2a12e1 Signed-off-by: Ricardo Martins <rasmartins(a)gmail.com> --- src/mainboard/iei/pm-lx-800-r11/Kconfig | 4 ---- 1 files changed, 0 insertions(+), 4 deletions(-) diff --git a/src/mainboard/iei/pm-lx-800-r11/Kconfig b/src/mainboard/iei/pm-lx-800-r11/Kconfig index 2c8675d..a897106 100644 --- a/src/mainboard/iei/pm-lx-800-r11/Kconfig +++ b/src/mainboard/iei/pm-lx-800-r11/Kconfig @@ -60,8 +60,4 @@ config CORE_GLIU_500_400 endchoice -config CORE_GLIU - int - default 7 - endif # BOARD_IEI_PM_LX_800_R11

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SIGILL on an ASUS A8V-E Deluxe
by Michael Büchler 06 Jul '12

06 Jul '12

Hi, I'm trying to run coreboot on an ASUS A8V-E Deluxe. It stops with a SIGILL after saying the following (tail of the log I got over serial): POST: 0x9d Adding CBMEM entry as no. 5 Writing high table forward entry at 0x00000500 Wrote coreboot table at: 00000500, 0x10 bytes, checksum efdf New low_table_end: 0x00000528 Now going to write high coreboot table at 0x3ffed000 rom_table_end = 0x3ffed000 Adjust low_table_end from 0x00000528 to 0x00001000 Adjust rom_table_end from 0x3ffed000 to 0x3fff0000 $S04#b7 I don't know much about programming but I ran gdb to take a look: (gdb) target remote /dev/ttyS0 Remote debugging using /dev/ttyS0 unpack_lb64 (value=...) at src/include/boot/coreboot_tables.h:54 54 result = value.hi; (gdb) info program Debugging a target over a serial line. Program stopped at 0x1127be. It stopped with signal SIGILL, Illegal instruction. (gdb) x/i $pc => 0x1127be <lb_cleanup_memory_ranges+79>: movd 0xc(%eax),%xmm0 (gdb) bt full #0 unpack_lb64 (value=...) at src/include/boot/coreboot_tables.h:54 result = <optimized out> #1 lb_cleanup_memory_ranges (mem=0x3ffed018) at src/arch/x86/boot/coreboot_table.c:413 entry_start = 4967675138670599 entries = 2 i = 0 j = <optimized out> #2 0x0011306b in build_lb_mem (head=0x3ffed000) at src/arch/x86/boot/coreboot_table.c:574 No locals. #3 write_coreboot_table (low_table_start=0, low_table_end=<optimized out>, rom_table_start=1073610752, rom_table_end=<optimized out>) at src/arch/x86/boot/coreboot_table.c:650 head = 0x3ffed000 mem = 0x3ffed018 #4 0x00104c51 in write_tables () at src/arch/x86/boot/tables.c:214 new_high_table_pointer = <optimized out> rom_table_end = 984143 high_table_pointer = 1073664000 __func__ = "write_tables" #5 0x00105623 in hardwaremain (boot_complete=0) at src/boot/hardwaremain.c:143 lb_mem = <optimized out> #6 0x00100099 in _text () at src/arch/x86/lib/c_start.S:82 No locals. Does this say that 'movd 0xc(%eax),%xmm0' is an Illegal Instruction? "Google says" it's an MMX instruction, but how can that be a problem when my Athlon64 3500+ is definitely MMX capable? Does MMX have to be initialized which probably didn't happen? I would try to compile coreboot without MMX but I don't know how. Disabling CONFIG_MMX has no effect on the coreboot code, right? Thanks is advance for any help on this. I just hope it's not an issue because of a stupid mistake by me ;) It's the first time I try to use coreboot.

3 4

New patch to review for coreboot: 9ca4f70 Drop invalid device ops on Agesa northbridge
by Kyösti Mälkki 06 Jul '12

06 Jul '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1180 -gerrit commit 9ca4f704ef9e79459d14c6aa27cf5568a98fd4bb Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jul 6 17:27:37 2012 +0300 Drop invalid device ops on Agesa northbridge One could not pass a device of type APIC to PCI resource functions. The correct CPU model specific cpu->ops is set at later time in cpu_initialize(). Change-Id: Ifa274185e4db3080433c1f07e3a48f2b55c0514f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/agesa/family10/northbridge.c | 18 ------------------ src/northbridge/amd/agesa/family15/northbridge.c | 18 ------------------ src/northbridge/amd/agesa/family15tn/northbridge.c | 18 ------------------ 3 files changed, 0 insertions(+), 54 deletions(-) diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 7b73987..3088f54 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -1231,21 +1231,6 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -/* dummy read_resources */ -static void lapic_read_resources(device_t dev) -{ -} - -static struct device_operations lapic_ops = { - .read_resources = lapic_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, - .enable = 0, - .ops_pci = 0, -}; - static u32 cpu_bus_scan(device_t dev, u32 max) { struct bus *cpu_bus; @@ -1447,9 +1432,6 @@ static u32 cpu_bus_scan(device_t dev, u32 max) if (cpu) { cpu->path.apic.node_id = i; cpu->path.apic.core_id = j; - if (cpu->path.type == DEVICE_PATH_APIC) { - cpu->ops = &lapic_ops; - } printk(BIOS_DEBUG, "CPU: %s %s\n", dev_path(cpu), cpu->enabled?"enabled":"disabled"); } diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 130086e..5b22707 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -889,21 +889,6 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -/* dummy read_resources */ -static void lapic_read_resources(device_t dev) -{ -} - -static struct device_operations lapic_ops = { - .read_resources = lapic_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, - .enable = 0, - .ops_pci = 0, -}; - static u32 cpu_bus_scan(device_t dev, u32 max) { struct bus *cpu_bus; @@ -1100,9 +1085,6 @@ static u32 cpu_bus_scan(device_t dev, u32 max) if (cpu) { cpu->path.apic.node_id = i; cpu->path.apic.core_id = j; - if (cpu->path.type == DEVICE_PATH_APIC) { - cpu->ops = &lapic_ops; - } printk(BIOS_DEBUG, "CPU: %s %s\n", dev_path(cpu), cpu->enabled?"enabled":"disabled"); } diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 3df5c60..d967793 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -873,21 +873,6 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -/* dummy read_resources */ -static void lapic_read_resources(device_t dev) -{ -} - -static struct device_operations lapic_ops = { - .read_resources = lapic_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, - .enable = 0, - .ops_pci = 0, -}; - static u32 cpu_bus_scan(device_t dev, u32 max) { struct bus *cpu_bus; @@ -1084,9 +1069,6 @@ static u32 cpu_bus_scan(device_t dev, u32 max) if (cpu) { cpu->path.apic.node_id = i; cpu->path.apic.core_id = j; - if (cpu->path.type == DEVICE_PATH_APIC) { - cpu->ops = &lapic_ops; - } printk(BIOS_DEBUG, "CPU: %s %s\n", dev_path(cpu), cpu->enabled?"enabled":"disabled"); }

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New patch to review for coreboot: 9da2d37 IEI PM-LX2-800-R10: Removed bogus Kconfig option
by Ricardo Martins 06 Jul '12

06 Jul '12

Ricardo Martins (rasmartins(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1179 -gerrit commit 9da2d3700d0b4d98327bbca9cace5f7bccf2ae17 Author: Ricardo Martins <rasmartins(a)gmail.com> Date: Fri Jul 6 13:49:52 2012 +0100 IEI PM-LX2-800-R10: Removed bogus Kconfig option The Kconfig file for this board contains a bogus option called CORE_GLIU, this change removes it. Change-Id: I4ea069bdd76be53085ebc9c0fb3dd71ffb2a12e1 Signed-off-by: Ricardo Martins <rasmartins(a)gmail.com> --- src/mainboard/iei/pm-lx-800-r11/Kconfig | 4 ---- 1 files changed, 0 insertions(+), 4 deletions(-) diff --git a/src/mainboard/iei/pm-lx-800-r11/Kconfig b/src/mainboard/iei/pm-lx-800-r11/Kconfig index 2c8675d..a897106 100644 --- a/src/mainboard/iei/pm-lx-800-r11/Kconfig +++ b/src/mainboard/iei/pm-lx-800-r11/Kconfig @@ -60,8 +60,4 @@ config CORE_GLIU_500_400 endchoice -config CORE_GLIU - int - default 7 - endif # BOARD_IEI_PM_LX_800_R11

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Patch set updated for coreboot: 4c8a557 IEI PM-LX2-800-R10: Added preliminary mainboard support
by Ricardo Martins 06 Jul '12

06 Jul '12

Ricardo Martins (rasmartins(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1152 -gerrit commit 4c8a557d3ea3728773e1d9dcd59edb22436199ec Author: Ricardo Martins <rasmartins(a)gmail.com> Date: Fri Jul 6 13:44:41 2012 +0100 IEI PM-LX2-800-R10: Added preliminary mainboard support Details for this board are available at http://usa.ieiworld.com/product_groups/industrial/content.aspx?gid=00001000… Most of the functionality provided by the original BIOS is implemented. Change-Id: Iaefe47f5ad405a56d230c929e5850156eb0f60ae Signed-off-by: Ricardo Martins <rasmartins(a)gmail.com> --- src/mainboard/iei/Kconfig | 3 + src/mainboard/iei/pm-lx2-800-r10/Kconfig | 71 +++++++++++++ src/mainboard/iei/pm-lx2-800-r10/chip.h | 23 ++++ src/mainboard/iei/pm-lx2-800-r10/cmos.layout | 103 ++++++++++++++++++ src/mainboard/iei/pm-lx2-800-r10/devicetree.cb | 87 +++++++++++++++ src/mainboard/iei/pm-lx2-800-r10/irq_tables.c | 134 ++++++++++++++++++++++++ src/mainboard/iei/pm-lx2-800-r10/it8888_io.def | 27 +++++ src/mainboard/iei/pm-lx2-800-r10/mainboard.c | 103 ++++++++++++++++++ src/mainboard/iei/pm-lx2-800-r10/romstage.c | 101 ++++++++++++++++++ 9 files changed, 652 insertions(+), 0 deletions(-) diff --git a/src/mainboard/iei/Kconfig b/src/mainboard/iei/Kconfig index ea26922..537252d 100644 --- a/src/mainboard/iei/Kconfig +++ b/src/mainboard/iei/Kconfig @@ -31,6 +31,8 @@ config BOARD_IEI_PCISA_LX_800_R10 bool "PCISA LX-800-R10" config BOARD_IEI_PM_LX_800_R11 bool "PM LX-800-R11" +config BOARD_IEI_PM_LX2_800_R10 + bool "PM-LX2-800-R10" endchoice @@ -39,6 +41,7 @@ source "src/mainboard/iei/kino-780am2-fam10/Kconfig" source "src/mainboard/iei/nova4899r/Kconfig" source "src/mainboard/iei/pcisa-lx-800-r10/Kconfig" source "src/mainboard/iei/pm-lx-800-r11/Kconfig" +source "src/mainboard/iei/pm-lx2-800-r10/Kconfig" config MAINBOARD_VENDOR string diff --git a/src/mainboard/iei/pm-lx2-800-r10/Kconfig b/src/mainboard/iei/pm-lx2-800-r10/Kconfig new file mode 100644 index 0000000..194db4d --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/Kconfig @@ -0,0 +1,71 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +if BOARD_IEI_PM_LX2_800_R10 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ARCH_X86 + select CPU_AMD_GEODE_LX + select NORTHBRIDGE_AMD_LX + select SOUTHBRIDGE_AMD_CS5536 + select SUPERIO_SMSC_SMSCSUPERIO + select HAVE_PIRQ_TABLE + select HAVE_OPTION_TABLE + select PIRQ_ROUTE + select BOARD_ROMSIZE_KB_512 + select POWER_BUTTON_FORCE_ENABLE + +config MAINBOARD_DIR + string + default iei/pm-lx2-800-r10 + +config MAINBOARD_PART_NUMBER + string + default "PM-LX2-800-R10" + +config IRQ_SLOT_COUNT + int + default 3 + +config SCH3114_COM3_AUTO_DIR + bool "COM3 Automatic Direction Control" + default y + help + If selected, COM3 automatic direction control will + be enabled by default. + +choice + prompt "Core/GLIU Frequency" + default CORE_GLIU_500_266 + +config CORE_GLIU_500_266 + bool "500MHz / 266MHz" + +config CORE_GLIU_500_333 + bool "500MHz / 333MHz" + +config CORE_GLIU_500_400 + bool "500MHz / 400MHz" + +endchoice + +endif # BOARD_IEI_PM_LX2_800_R10 diff --git a/src/mainboard/iei/pm-lx2-800-r10/chip.h b/src/mainboard/iei/pm-lx2-800-r10/chip.h new file mode 100644 index 0000000..d69f9b6 --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/iei/pm-lx2-800-r10/cmos.layout b/src/mainboard/iei/pm-lx2-800-r10/cmos.layout new file mode 100644 index 0000000..e09cfb6 --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/cmos.layout @@ -0,0 +1,103 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +entries + # RTC + 0 384 r 0 reserved_rtc + # Coreboot + 384 1 e 3 boot_option + 385 1 e 3 last_boot + 386 4 r 0 reboot_bits + 390 3 e 4 baud_rate + 393 4 e 5 debug_level + 397 2 r 0 unused + # PM-LX2-800-R10 + 399 1 e 1 com3_auto_direction + 400 1 e 2 it8888_io_space0 + 401 1 e 2 it8888_io_space1 + 402 1 e 2 it8888_io_space2 + 403 1 e 2 it8888_io_space3 + 404 2 e 6 it8888_io_space0_speed + 406 2 e 6 it8888_io_space1_speed + 408 2 e 6 it8888_io_space2_speed + 410 2 e 6 it8888_io_space3_speed + 412 3 e 7 it8888_io_space0_size + 415 3 e 7 it8888_io_space1_size + 418 3 e 7 it8888_io_space2_size + 421 3 e 7 it8888_io_space3_size + 424 16 h 0 it8888_io_space0_addr + 440 16 h 0 it8888_io_space1_addr + 456 16 h 0 it8888_io_space2_addr + 472 16 h 0 it8888_io_space3_addr + 488 16 h 0 check_sum + +enumerations + # Yes / No + 1 0 No + 1 1 Yes + + # Enabled / Disabled + 2 0 Disabled + 2 1 Enabled + + # Normal / Fallback + 3 0 Fallback + 3 1 Normal + + # Console Baud Rate + 4 0 115200 + 4 1 57600 + 4 2 38400 + 4 3 19200 + 4 4 9600 + 4 5 4800 + 4 6 2400 + 4 7 1200 + + # Console Log Level + 5 0 Emergency + 5 1 Alert + 5 2 Critical + 5 3 Error + 5 4 Warning + 5 5 Notice + 5 6 Info + 5 7 Debug + 5 8 Spew + + # IT8888 Decoding Speeds + 6 0 Subtractive + 6 1 Slow + 6 2 Medium + 6 3 Fast + + # IT8888 Decoding Sizes + 7 0 1 + 7 1 2 + 7 2 4 + 7 3 8 + 7 4 16 + 7 5 32 + 7 6 64 + 7 7 128 + +checksums + checksum 384 487 488 diff --git a/src/mainboard/iei/pm-lx2-800-r10/devicetree.cb b/src/mainboard/iei/pm-lx2-800-r10/devicetree.cb new file mode 100644 index 0000000..f5721a3 --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/devicetree.cb @@ -0,0 +1,87 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +chip northbridge/amd/lx + device pci_domain 0 on + device pci 1.0 on end # Northbridge + device pci 1.1 on end # Video Adapter + device pci 1.2 on end # AES Security Block + chip southbridge/amd/cs5536 + register "lpc_serirq_enable" = "0x000010da" + register "lpc_serirq_polarity" = "0x0000ef25" + register "lpc_serirq_mode" = "1" + register "enable_gpio_int_route" = "0x0d0c0700" + register "enable_ide_nand_flash" = "0" + register "enable_USBP4_device" = "0" # 0:host, 1:device + register "enable_USBP4_overcurrent" = "0" + register "com1_enable" = "0" + register "com2_enable" = "0" + register "unwanted_vpci[0]" = "0" # End of list has a zero + device pci 11.0 on end # IT8888 + device pci e.0 on end # RTL8100C + device pci f.0 on # ISA Bridge + chip superio/smsc/smscsuperio # SMSC SCH3114 + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + + device pnp 2e.3 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + + device pnp 2e.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + + device pnp 2e.5 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + + device pnp 2e.7 on # PS/2 keyboard/mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # Keyboard + irq 0x72 = 12 # Mouse + end + + device pnp 2e.a on # Runtime Register + io 0x60 = 0x400 + end + end + end + device pci f.2 on end # IDE Controller + device pci f.3 on end # Audio + device pci f.4 on end # OHCI + device pci f.5 on end # EHCI + end + end + # APIC cluster is late CPU init. + device lapic_cluster 0 on + chip cpu/amd/geode_lx + device lapic 0 on end + end + end +end diff --git a/src/mainboard/iei/pm-lx2-800-r10/irq_tables.c b/src/mainboard/iei/pm-lx2-800-r10/irq_tables.c new file mode 100644 index 0000000..2bbf218 --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/irq_tables.c @@ -0,0 +1,134 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/pci_ids.h> +#include <arch/pirq_routing.h> + +/* Platform IRQs */ +#define PIRQA 10 +#define PIRQB 10 +#define PIRQC 11 +#define PIRQD 11 + +/* Links */ +#define L_PIRQN 0 +#define L_PIRQA 1 +#define L_PIRQB 2 +#define L_PIRQC 3 +#define L_PIRQD 4 + +/* Bitmaps */ +#define B_LINKN (0) +#define B_LINK0 (1 << PIRQA) +#define B_LINK1 (1 << PIRQB) +#define B_LINK2 (1 << PIRQC) +#define B_LINK3 (1 << PIRQD) + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x0f << 3) | 0x0, /* Interrupt router dev */ + (B_LINK0 | B_LINK1 | B_LINK2 | B_LINK3),/* IRQs devoted exclusively to PCI usage */ + PCI_VENDOR_ID_AMD, /* Vendor */ + PCI_DEVICE_ID_AMD_CS5536_ISA, /* Device */ + 0, /* Miniport */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + 0x27, /* Checksum */ + { + [0] = { /* Host bridge */ + .slot = 0x00, + .bus = 0x00, + .devfn = (0x01 << 3) | 0x0, + .irq = { + [0] = { + .link = L_PIRQA, + .bitmap = B_LINK0 + }, + [1] = { + .link = L_PIRQN, + .bitmap = B_LINKN + }, + [2] = { + .link = L_PIRQN, + .bitmap = B_LINKN + }, + [3] = { + .link = L_PIRQN, + .bitmap = B_LINKN + } + } + }, + + [1] = { /* ISA bridge */ + .slot = 0x00, + .bus = 0x00, + .devfn = (0x0f << 3) | 0x0, + .irq = { + [0] = { + .link = L_PIRQN, + .bitmap = B_LINKN + }, + [1] = { + .link = L_PIRQB, + .bitmap = B_LINK1 + }, + [2] = { + .link = L_PIRQN, + .bitmap = B_LINKN + }, + [3] = { + .link = L_PIRQD, + .bitmap = B_LINK3 + } + } + }, + + [2] = { /* Ethernet */ + .slot = 0x00, + .bus = 0x00, + .devfn = (0x0e << 3) | 0x0, + .irq = { + [0] = { + .link = L_PIRQD, + .bitmap = B_LINK3 + }, + [1] = { + .link = L_PIRQN, + .bitmap = B_LINKN + }, + [2] = { + .link = L_PIRQN, + .bitmap = B_LINKN + }, + [3] = { + .link = L_PIRQN, + .bitmap = B_LINKN + } + } + } + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} diff --git a/src/mainboard/iei/pm-lx2-800-r10/it8888_io.def b/src/mainboard/iei/pm-lx2-800-r10/it8888_io.def new file mode 100644 index 0000000..5920abc --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/it8888_io.def @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Name, Register, Enabled/Disabled, Speed, Size, Address. */ +IT8888_IO("it8888_io_space0", 0x58, 0, 0, 0, 0) +IT8888_IO("it8888_io_space1", 0x5c, 0, 0, 0, 0) +IT8888_IO("it8888_io_space2", 0x60, 0, 0, 0, 0) +IT8888_IO("it8888_io_space3", 0x64, 0, 0, 0, 0) +IT8888_IO("it8888_io_space4", 0x68, 0, 0, 0, 0) +IT8888_IO("it8888_io_space5", 0x6c, 0, 0, 0, 0) diff --git a/src/mainboard/iei/pm-lx2-800-r10/mainboard.c b/src/mainboard/iei/pm-lx2-800-r10/mainboard.c new file mode 100644 index 0000000..170a67a --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/mainboard.c @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/pci.h> +#include <device/device.h> +#include <boot/tables.h> +#include <pc80/mc146818rtc.h> +#include "chip.h" + +#if CONFIG_USE_OPTION_TABLE +# include "option_table.h" +#endif + +/* SCH3114 runtime register (RTR) address. */ +#define SCH3114_RTR_ADDR (0x400) +/* SP34 option register. */ +#define SCH3114_RTR_SP34_OPT (SCH3114_RTR_ADDR + 0x13) +/* H/W Monitoring register block index. */ +#define SCH3114_RTR_HWM_IDX (SCH3114_RTR_ADDR + 0x70) +/* H/W Monitoring register block data. */ +#define SCH3114_RTR_HWM_DAT (SCH3114_RTR_ADDR + 0x71) +/* H/W Monitoring Ready/Lock/Start register. */ +#define SCH3114_HWM_RLS_REG (0x40) +/* IT8888 PCI Vendor ID. */ +#define IT8888_PCI_VID (0x1283) +/* IT8888 PCI Device ID. */ +#define IT8888_PCI_DID (0x8888) + +static u16 opt(const char* option, u16 def_value) +{ +#if CONFIG_USE_OPTION_TABLE + u16 value = 0; + if (get_option(&value, option) != 0) + value = def_value; + return value; +#else + return def_value; +#endif +} + +static void init(struct device *dev) +{ + /* SCH3114: enable hardware monitor. */ + printk(BIOS_INFO, "Enabling SCH3114 hardware monitor\n"); + outb(SCH3114_HWM_RLS_REG, SCH3114_RTR_HWM_IDX); + outb(inb(SCH3114_RTR_HWM_DAT) | 0x01, SCH3114_RTR_HWM_DAT); + + /* SCH3114: COM3 Automatic Direction Control / nRTS control. */ + if (opt("com3_auto_direction", CONFIG_SCH3114_COM3_AUTO_DIR) != 0) { + printk(BIOS_INFO, "Enabling RS858 Auto Direction Control\n"); + outb(inb(SCH3114_RTR_SP34_OPT) | 0x03, SCH3114_RTR_SP34_OPT); + } + + /* IT8888. */ + device_t it8x = dev_find_device(IT8888_PCI_VID, IT8888_PCI_DID, 0); + if (!it8x) { + printk(BIOS_ERR, "IT8888 not found\n"); + return; + } + + u32 cfg = 0; +#define IT8888_IO(name, reg, dena, dspeed, dsize, daddr) \ + if (opt(name, dena) != 0) { \ + cfg = (1 << 31); \ + cfg |= opt(name "_addr", daddr); \ + cfg |= opt(name "_speed", dspeed) << 29; \ + cfg |= opt(name "_size", dsize) << 24; \ + } else { \ + cfg = 0; \ + } \ + pci_write_config32(it8x, reg, cfg); + +#include "it8888_io.def" +} + +static void enable_dev(struct device *dev) +{ + dev->ops->init = init; +} + +struct chip_operations mainboard_ops = { + CHIP_NAME("IEI PM-LX2-800-R10 Mainboard") + .enable_dev = enable_dev, +}; diff --git a/src/mainboard/iei/pm-lx2-800-r10/romstage.c b/src/mainboard/iei/pm-lx2-800-r10/romstage.c new file mode 100644 index 0000000..da0c769 --- /dev/null +++ b/src/mainboard/iei/pm-lx2-800-r10/romstage.c @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2012 Ricardo Martins <rasmartins(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <stdlib.h> + +#include <spd.h> +#include <arch/io.h> +#include <arch/hlt.h> +#include <arch/llshell.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <console/console.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/lxdef.h> +#include <southbridge/amd/cs5536/cs5536.h> +#include <southbridge/amd/cs5536/early_smbus.c> +#include <southbridge/amd/cs5536/early_setup.c> +#include <superio/smsc/smscsuperio/early_serial.c> + +#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) + +static inline int spd_read_byte(unsigned int device, unsigned int address) +{ + /* Only DIMM0 is available. */ + if (device != DIMM0) + return 0xFF; + + return smbus_read_byte(device, address); +} + +#if CONFIG_CORE_GLIU_500_400 +# define PLLMSRhi 0x0000059c +#elif CONFIG_CORE_GLIU_500_333 +# define PLLMSRhi 0x0000049c +#else +# define PLLMSRhi 0x0000039c +#endif + +#define PLLMSRlo 0x07de000 + +#include <northbridge/amd/lx/raminit.h> +#include <northbridge/amd/lx/pll_reset.c> +#include <northbridge/amd/lx/raminit.c> +#include <lib/generic_sdram.c> +#include <cpu/amd/geode_lx/cpureginit.c> +#include <cpu/amd/geode_lx/syspreinit.c> +#include <cpu/amd/geode_lx/msrinit.c> + +void main(unsigned long bist) +{ + static const struct mem_controller memctrl[] = { + {.channel0 = {DIMM0, DIMM1}} + }; + + SystemPreInit(); + msr_init(); + + cs5536_early_setup(); + + smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + + /* Enable COM3. */ + device_t dev = PNP_DEV(0x2e, 0x0b); + u16 port = dev >> 8; + outb(0x55, port); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x3e8); + pnp_set_irq(dev, PNP_IDX_IRQ0, 4); + pnp_set_enable(dev, 1); + outb(0xaa, port); + + report_bist_failure(bist); + + pll_reset(1); + + cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); + + sdram_initialize(1, memctrl); +}

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Patch merged into coreboot/master: bbe21b5 IEI PM-LX-800-R11: Added preliminary mainboard support
by gerrit＠coreboot.org 06 Jul '12

06 Jul '12

the following patch was just integrated into master: commit bbe21b5c3d7625a2a3d6417d3b844884ebd84eeb Author: Ricardo Martins <rasmartins(a)gmail.com> Date: Wed Jul 4 03:09:49 2012 +0100 IEI PM-LX-800-R11: Added preliminary mainboard support Details for this board are available at http://www.ieiworld.com/product_groups/industrial/content.aspx?gid=00001000… Most of the functionality provided by the original BIOS is implemented. Change-Id: Id9eb10a2f9e49377ea587bddadbba7d76223a715 Signed-off-by: Ricardo Martins <rasmartins(a)gmail.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Fri Jul 6 14:26:37 2012, giving +2 See http://review.coreboot.org/1168 for details. -gerrit

1 0

Patch merged into coreboot/master: 29cadf1 i945: Reset IGD on boot
by gerrit＠coreboot.org 06 Jul '12

06 Jul '12

the following patch was just integrated into master: commit 29cadf18204929842781120325b7301e6dbe1612 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Fri Jul 6 11:31:39 2012 +0200 i945: Reset IGD on boot This is mostly necessary for reboot, but it doesn't hurt the boot process. On reboot explicitely reset the integrated graphics, otherwise the VGABIOS might not be able to reinitialize it properly, and you either have a still of the last pre-reboot image, garbage or an empty screen, but no text-mode. Change-Id: Ic3d6932fbaf720d88daaac7e4b09c3c0b9f0b0e2 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Build-Tested: build bot (Jenkins) at Fri Jul 6 11:53:11 2012, giving +1 Reviewed-By: Peter Stuge <peter(a)stuge.se> at Fri Jul 6 11:53:49 2012, giving +2 See http://review.coreboot.org/1178 for details. -gerrit

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coreboot July 2012