coreboot July 2012

coreboot@coreboot.org

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New patch to review for coreboot: 29cadf1 i945: Reset IGD on boot
by Patrick Georgi 06 Jul '12

06 Jul '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1178 -gerrit commit 29cadf18204929842781120325b7301e6dbe1612 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Fri Jul 6 11:31:39 2012 +0200 i945: Reset IGD on boot This is mostly necessary for reboot, but it doesn't hurt the boot process. On reboot explicitely reset the integrated graphics, otherwise the VGABIOS might not be able to reinitialize it properly, and you either have a still of the last pre-reboot image, garbage or an empty screen, but no text-mode. Change-Id: Ic3d6932fbaf720d88daaac7e4b09c3c0b9f0b0e2 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- src/northbridge/intel/i945/gma.c | 10 ++++++++++ 1 files changed, 10 insertions(+), 0 deletions(-) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 340ddcd..b703a80 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -18,15 +18,25 @@ */ #include <console/console.h> +#include <delay.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <pc80/mc146818rtc.h> +#define GDRST 0xc0 + static void gma_func0_init(struct device *dev) { u32 reg32; + /* Unconditionally reset graphics */ + pci_write_config8(dev, GDRST, 1); + udelay(50); + pci_write_config8(dev, GDRST, 0); + /* wait for device to finish */ + while (pci_read_config8(dev, GDRST) & 1) { }; + /* IGD needs to be Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);

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Patch merged into coreboot/master: f419483 superiotool: Add support for git-based version number
by gerrit＠coreboot.org 06 Jul '12

06 Jul '12

the following patch was just integrated into master: commit f41948308c9360389680c1d12c5c1d406354048b Author: Guenter Roeck <linux(a)roeck-us.net> Date: Fri Jun 29 12:25:46 2012 -0700 superiotool: Add support for git-based version number The superiotool Makefile extracts a version string from SVN. This does not work with a git repository, and results in an empty version string. Use the output of 'git describe' as version string instead. Change-Id: Idf92c02753b28ef5bcdd3b6df4a08d79ae974434 Signed-off-by: Guenter Roeck <linux(a)roeck-us.net> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Fri Jul 6 10:21:02 2012, giving +2 See http://review.coreboot.org/1151 for details. -gerrit

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New patch to review for coreboot: e89ffee libpayload: Add reset function for OHCI USB driver
by Anton Kochkov 06 Jul '12

06 Jul '12

Anton Kochkov (anton.kochkov(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1177 -gerrit commit e89ffeebb93b987c833beaad39651cdd44f00cc5 Author: Anton Kochkov <a.kochkov(a)securitycode.ru> Date: Fri Jul 6 11:54:17 2012 +0400 libpayload: Add reset function for OHCI USB driver Implemented OHCI reset function ohci_reset() in ohci.c for libpayload's USB driver. Change-Id: Id6518cbe00a21202757b34926bad171909740e97 Signed-off-by: Anton Kochkov <anton.kochkov(a)gmail.com> --- payloads/libpayload/drivers/usb/ohci.c | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/payloads/libpayload/drivers/usb/ohci.c b/payloads/libpayload/drivers/usb/ohci.c index 8a01cf2..606e467 100644 --- a/payloads/libpayload/drivers/usb/ohci.c +++ b/payloads/libpayload/drivers/usb/ohci.c @@ -49,6 +49,13 @@ static void ohci_process_done_queue(ohci_t *ohci, int spew_debug); static void ohci_reset (hci_t *controller) { + if (controller == NULL) + return; + + OHCI_INST(controller)->opreg->HcCommandStatus = HostControllerReset; + mdelay(2); /* wait 2ms */ + OCHI_INST(controller)->opreg->HcControl = 0; + mdelay(10); /* wait 10ms */ } #ifdef USB_DEBUG

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Patch set updated for coreboot: 765e44d superiotool: Add support for NCT6775F(A/B) and NCT6779D
by Guenter Roeck 06 Jul '12

06 Jul '12

Guenter Roeck (linux(a)roeck-us.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1148 -gerrit commit 765e44dcb2e0f7be7a46e674cab28991e726c3a4 Author: Guenter Roeck <linux(a)roeck-us.net> Date: Fri Jun 29 12:22:51 2012 -0700 superiotool: Add support for NCT6775F(A/B) and NCT6779D Change-Id: I66667fcb58f6885460021f4a2024d6ba56b95f11 Signed-off-by: Guenter Roeck <linux(a)roeck-us.net> --- util/superiotool/nuvoton.c | 234 ++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 234 insertions(+), 0 deletions(-) diff --git a/util/superiotool/nuvoton.c b/util/superiotool/nuvoton.c index ed2eabc..46b8c2a 100644 --- a/util/superiotool/nuvoton.c +++ b/util/superiotool/nuvoton.c @@ -66,6 +66,170 @@ static const struct superio_registers reg_table[] = { {EOT}}}, {0x1a, "WPCM450", { {EOT}}}, + {0xb472, "NCT6775F (A)", { + {NOLDN, NULL, + {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, + 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, + {0xb4,0x72,0xff,0x78,0x40,0x00,0x00,0x7d,0x00, + 0x00,0x58,0x77,0xfc,0x04,0x00,MISC,EOT}}, + {0x00, "FDC", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4, + 0xf5,EOT}, + {0x03,0x03,0xf0,0x06,0x02,0x8e,0x00,0xff,0x00, + 0x00,EOT}}, + {0x01, "Parallel Port", + {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, + {0x01,0x03,0x78,0x07,0x04,0x3f,EOT}}, + {0x02, "UART A", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x01,0x03,0xf8,0x04,0x00,EOT}}, + {0x03, "UART B, IR", + {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, + {0x01,0x02,0xf8,0x03,0x00,0x00,EOT}}, + {0x05, "Keyboard Controller", + {0x30,0x60,0x61,0x62,0x63,0x70,0x72,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x83,EOT}}, + {0x06, "CIR", + {0x30,0x60,0x61,0x70,EOT}, + {0x00,0x00,0x00,0x00,EOT}}, + {0x07, "GPIO6, GPIO7, GPIO8, GPIO9", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, + 0xe8,0xe9,0xea,0xeb,0xec,0xed,0xee,0xf4,0xf5, + 0xf6,0xf7,0xf8,EOT}, + {0x18,0xff,0x00,0x00,0x00,0xef,0x00,0x00,0x00, + 0xff,0x00,0x00,0x00,0x00,0x00,0x00,0xff,0x00, + 0x00,0x00,0x00,EOT}}, + {0x08, "WDT1, GPIO0, GPIO1", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xf0, + 0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,EOT}, + {0x00,0xff,0x00,0x00,0x00,0x00,0xff, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x09, "GPIO2, GPIO3, GPIO4, GPIO5", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, + 0xe8,0xe9,0xea,0xeb,0xee,0xf0,0xf1,0xf2,0xf4, + 0xf5,0xf6,0xf7,0xfe,EOT}, + {0x05,0xff,0x00,0x00,0x00,0xff,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0xff,0x00,0x00,0xff, + 0x00,0x00,0x00,0x00,EOT}}, + {0x0a, "ACPI", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, + 0xe8,0xe9,0xea,0xeb,0xed,0xf2,0xf3,0xf4,0xf6, + 0xf7,0xfe,EOT}, + {0x00,0x01,0x00,0x00,0x00,0x00,0x02,0x1c,0x00, + 0x00,0x00,0x00,0x00,0x00,0x7c,0x00,0x00,0x00, + 0x20,0x00,EOT}}, + {0x0b, "Hardware Monitor, Front Panel LED", + {0x30,0x60,0x61,0x62,0x63,0x70,0xf0,0xf1,0xf2, + 0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb, + 0xfc,0xfd,0xfe, + EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0xc1,0x00,0x00, + 0x00,0x00,0x10,0x00,0x87,0x47,0x00,0x00,0x00, + 0x00,0x00,0x00, + EOT}}, + {0x0c, "PECI, SST", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe9, + 0xee,0xef,0xf1,0xf2,0xf3,0xfa,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x0f, + 0x47,0x5b,0x40,0x50,0x10,0x00,EOT}}, + {0x0d, "VID, VIDDAC, BUSSEL", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xeb, + 0xec,0xed,0xee,0xef,0xf3,0xf4,0xf5,0xf6,0xf7, + 0xf8,0xf9,EOT}, + {0x00,0x00,0x00,0x00,0x07,0x00,0x00,0x00,0x14, + 0x01,0x00,0x88,0x00,0x00,0x00,0x00,0x07,0x00, + 0x00,0x00,EOT}}, + {0x0e, "CIR WAKE-UP", + {0x30,0x60,0x61,0x70,EOT}, + {0x00,0x00,0x00,0x00,EOT}}, + {0x0f, "GPIO Push-Pull or Open-drain", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8, + 0xe9,0xf0,0xf2,0xf3,0xf4,0xf8,0xfe,EOT}, + {0xff,0xff,0xf7,0xff,0xfb,0xcb,0xff,0xff,0xff, + 0xff,0x00,0x00,0x00,0x00,0x70,0xff,EOT}}, + {EOT}}}, + {0xb473, "NCT6775F (B)", { + {NOLDN, NULL, + {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, + 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, + {0xb4,0x73,0xff,0x78,0x40,0x00,0x00,0x7d,0x00, + 0x00,0x58,0x77,0xfc,0x04,0x00,MISC,EOT}}, + {0x00, "FDC", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4, + 0xf5,EOT}, + {0x03,0x03,0xf0,0x06,0x02,0x8e,0x00,0xff,0x00, + 0x00,EOT}}, + {0x01, "Parallel Port", + {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, + {0x01,0x03,0x78,0x07,0x04,0x3f,EOT}}, + {0x02, "UART A", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x01,0x03,0xf8,0x04,0x00,EOT}}, + {0x03, "UART B, IR", + {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, + {0x01,0x02,0xf8,0x03,0x00,0x00,EOT}}, + {0x05, "Keyboard Controller", + {0x30,0x60,0x61,0x62,0x63,0x70,0x72,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x83,EOT}}, + {0x06, "CIR", + {0x30,0x60,0x61,0x70,EOT}, + {0x00,0x00,0x00,0x00,EOT}}, + {0x07, "GPIO6, GPIO7, GPIO8, GPIO9", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, + 0xe8,0xe9,0xea,0xeb,0xec,0xed,0xee,0xf4,0xf5, + 0xf6,0xf7,0xf8,EOT}, + {0x18,0xff,0x00,0x00,0x00,0xef,0x00,0x00,0x00, + 0xff,0x00,0x00,0x00,0x00,0x00,0x00,0xff,0x00, + 0x00,0x00,0x00,EOT}}, + {0x08, "WDT1, GPIO0, GPIO1", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xf0, + 0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,EOT}, + {0x00,0xff,0x00,0x00,0x00,0x00,0xff, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x09, "GPIO2, GPIO3, GPIO4, GPIO5", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, + 0xe8,0xe9,0xea,0xeb,0xee,0xf0,0xf1,0xf2,0xf4, + 0xf5,0xf6,0xf7,0xfe,EOT}, + {0x05,0xff,0x00,0x00,0x00,0xff,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0xff,0x00,0x00,0xff, + 0x00,0x00,0x00,0x00,EOT}}, + {0x0a, "ACPI", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, + 0xe8,0xe9,0xea,0xeb,0xed,0xf2,0xf3,0xf4,0xf6, + 0xf7,0xfe,EOT}, + {0x00,0x01,0x00,0x00,0x00,0x00,0x02,0x1c,0x00, + 0x00,0x00,0x00,0x00,0x00,0x7c,0x00,0x00,0x00, + 0x20,0x00,EOT}}, + {0x0b, "Hardware Monitor, Front Panel LED", + {0x30,0x60,0x61,0x62,0x63,0x70,0xf0,0xf1,0xf2, + 0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb, + 0xfc,0xfd,0xfe, + EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0xc1,0x00,0x00, + 0x00,0x00,0x10,0x00,0x87,0x47,0x00,0x00,0x00, + 0x00,0x00,0x00, + EOT}}, + {0x0c, "PECI, SST", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe9, + 0xee,0xef,0xf1,0xf2,0xf3,0xfa,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x0f, + 0x47,0x5b,0x40,0x50,0x10,0x00,EOT}}, + {0x0d, "VID, VIDDAC, BUSSEL", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xeb, + 0xec,0xed,0xee,0xef,0xf3,0xf4,0xf5,0xf6,0xf7, + 0xf8,0xf9,EOT}, + {0x00,0x00,0x00,0x00,0x07,0x00,0x00,0x00,0x14, + 0x01,0x00,0x88,0x00,0x00,0x00,0x00,0x07,0x00, + 0x00,0x00,EOT}}, + {0x0e, "CIR WAKE-UP", + {0x30,0x60,0x61,0x70,EOT}, + {0x00,0x00,0x00,0x00,EOT}}, + {0x0f, "GPIO Push-Pull or Open-drain", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8, + 0xe9,0xf0,0xf2,0xf3,0xf4,0xf8,0xfe,EOT}, + {0xff,0xff,0xf7,0xff,0xfb,0xcb,0xff,0xff,0xff, + 0xff,0x00,0x00,0x00,0x00,0x70,0xff,EOT}}, + {EOT}}}, {0xc332, "NCT6776F (B)", { {NOLDN, NULL, {0x10,0x11,0x13,0x14,0x16,0x17,0x18,0x19,0x1a, @@ -234,6 +398,76 @@ static const struct superio_registers reg_table[] = { {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,EOT}, {0x01,0x00,0x00,0x00,0x01,0x00,EOT}}, {EOT}}}, + {0xc562, "NCT6779D", { + {NOLDN, NULL, + {0x10,0x11,0x13,0x14,0x1a,0x1b,0x1c,0x1d,0x20, + 0x21,0x22,0x24,0x25,0x26,0x27,0x28,0x2a,0x2b, + 0x2c,0x2f,EOT}, + {0xff,0xff,0x00,0x00,0x30,0x70,0x10,0x00,0xc5, + 0x62,0xff,0x04,0x00,MISC,0x00,0x00,0xc0,0x00, + 0x01,MISC,EOT}}, + {0x01, "Parallel Port", + {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, + {0x01,0x03,0x78,0x07,0x04,0x3f,EOT}}, + {0x02, "UART A", + {0x30,0x60,0x61,0x70,0xf0,0xf2,EOT}, + {0x01,0x03,0xf8,0x04,0x00,0x00,EOT}}, + {0x03, "UART B, IR", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,EOT}, + {0x01,0x02,0xf8,0x03,0x00,0x00,0x00,EOT}}, + {0x05, "Keyboard Controller", + {0x30,0x60,0x61,0x62,0x63,0x70,0x72,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x83,EOT}}, + {0x06, "CIR", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,0xf3,EOT}, + {0x00,0x00,0x00,0x00,0x08,0x09,0x32,0x00,EOT}}, + {0x07, "GPIO6, GPIO7, GPIO8", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, + 0xec,0xed,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, + {0x0f,0x00,0x00,0x00,0xff,0x00,0x00,0x00, + 0x00,0x00,0xff,0x00,0x00,0x00,0x00,EOT}}, + {0x08, "WDT1, GPIO0, GPIO1", + {0x30,0x60,0x61,0xe0,0xe1,0xe2,0xe3,0xe4,0xf0, + 0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,EOT}, + {0x00,0x00,0x00,0xff,0x00,0x00,0x00,0x00,0xff, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x09, "GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, + 0xe8,0xe9,0xea,0xeb,0xee,0xf0,0xf1,0xf2,0xf4, + 0xf5,0xf6,0xf7,0xfe,EOT}, + {0x00,0xff,0x00,0x00,0x00,0x7f,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0xff,0x00,0x00,0xff, + 0x00,0x00,0x00,0x00,EOT}}, + {0x0a, "ACPI", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe9, + 0xee,0xf0,0xf2,0xf3,0xf4,0xf6,0xf7,0xfe,EOT}, + {0x01,0x00,0x00,0x00,0x00,0x02,0x1c,0x00,0x00, + 0x00,0x10,0x5c,0x00,0x00,0x00,0xc0,0x00,EOT}}, + {0x0b, "Hardware Monitor, Front Panel LED", + {0x30,0x60,0x61,0x62,0x63,0x70,0xe0,0xe1,0xe2, + 0xe4,0xf0,0xf1,0xf2,0xf5,0xf6,0xf7,0xf8,0xf9, + 0xfa,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x7f,0x7f,0xff, + 0xff,0x00,0x00,0x00,0x10,0x00,0x87,0x47,0x00, + 0x00,EOT}}, + {0x0d, "WDT1", + {0xf0,EOT}, + {0x00,EOT}}, + {0x0e, "CIR WAKE-UP", + {0x30,0x60,0x61,0x70,EOT}, + {0x00,0x00,0x00,0x00,EOT}}, + {0x0f, "GPIO Push-Pull or Open-drain", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe9, + 0xf0,0xf1,0xf2,EOT}, + {0xff,0xff,0x7f,0xff,0xff,0xff,0x0f,0xff,0xff, + 0x9d,0x00,0x00,EOT}}, + {0x14, "Port 80 UART", + {0xe0,0xe1,0xe2,0xe3,0xe4,EOT}, + {0x80,0x00,0x00,0x10,0x00,EOT}}, + {0x16, "Deep Sleep", + {0x30,0xe0,0xe1,0xe2,EOT}, + {0x20,0x20,0x04,0x05,EOT}}, + {EOT}}}, {EOT} };

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Patch set updated for coreboot: 7eedcba superiotool: Add support for function to dump superio chip data registers
by Guenter Roeck 06 Jul '12

06 Jul '12

Guenter Roeck (linux(a)roeck-us.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1149 -gerrit commit 7eedcba9fb8b1bd1100dca290b4d3a8544ae14d5 Author: Guenter Roeck <linux(a)roeck-us.net> Date: Fri Jun 29 12:23:50 2012 -0700 superiotool: Add support for function to dump superio chip data registers Add new function dump_data() to dump a bank of superio data registers. Change-Id: I13a58d87c14d319cfcdea1ec1d54c2b110d90f9f Signed-off-by: Guenter Roeck <linux(a)roeck-us.net> --- util/superiotool/superiotool.c | 29 +++++++++++++++++++++++++++++ util/superiotool/superiotool.h | 1 + 2 files changed, 30 insertions(+), 0 deletions(-) diff --git a/util/superiotool/superiotool.c b/util/superiotool/superiotool.c index 293aaa6..538aa09 100644 --- a/util/superiotool/superiotool.c +++ b/util/superiotool/superiotool.c @@ -34,6 +34,18 @@ int dump = 0, verbose = 0, extra_dump = 0; /* Global flag which indicates whether a chip was detected at all. */ int chip_found = 0; +static void set_bank(uint16_t port, uint8_t bank) +{ + OUTB(0x4E, port); + OUTB(bank, port + 1); +} + +static uint8_t datareg(uint16_t port, uint8_t reg) +{ + OUTB(reg, port); + return INB(port + 1); +} + uint8_t regval(uint16_t port, uint8_t reg) { OUTB(reg, port); @@ -186,6 +198,23 @@ void dump_io(uint16_t iobase, uint16_t length) printf("\n"); } +void dump_data(uint16_t iobase, int bank) +{ + uint16_t i; + + printf("Bank %d:\n", bank); + printf(" "); + for (i = 0; i < 16; i++) + printf("%02x ", i); + set_bank(iobase, bank); + for (i = 0; i < 256; i++) { + if (i % 16 == 0) + printf("\n%02x: ", i / 16); + printf("%02x ", datareg(iobase, i)); + } + printf("\n"); +} + void probing_for(const char *vendor, const char *info, uint16_t port) { if (!verbose) diff --git a/util/superiotool/superiotool.h b/util/superiotool/superiotool.h index 94918b8..7a0b7f6 100644 --- a/util/superiotool/superiotool.h +++ b/util/superiotool/superiotool.h @@ -174,6 +174,7 @@ const char *get_superio_name(const struct superio_registers reg_table[], void dump_superio(const char *name, const struct superio_registers reg_table[], uint16_t port, uint16_t id, uint8_t ldn_sel); void dump_io(uint16_t iobase, uint16_t length); +void dump_data(uint16_t iobase, int bank); void probing_for(const char *vendor, const char *info, uint16_t port); void print_vendor_chips(const char *vendor, const struct superio_registers reg_table[]);

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Patch set updated for coreboot: e7ae433 superiotool: Dump data registers for Nuvoton chips
by Guenter Roeck 06 Jul '12

06 Jul '12

Guenter Roeck (linux(a)roeck-us.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1150 -gerrit commit e7ae433b4efa92e0649c092fa5aa05323350c355 Author: Guenter Roeck <linux(a)roeck-us.net> Date: Fri Jun 29 12:24:57 2012 -0700 superiotool: Dump data registers for Nuvoton chips Add support to dump all data registers for Nuvoton chips (NCT6775F, NCT6776F, and NCT6779D). Register contents will be dumped if the -e option is provided on the command line. Change-Id: I2b425b48c1f28a10ff3c1ca1d7f21c501eff74ad Signed-off-by: Guenter Roeck <linux(a)roeck-us.net> --- util/superiotool/nuvoton.c | 27 ++++++++++++++++++++++++++- 1 files changed, 26 insertions(+), 1 deletions(-) diff --git a/util/superiotool/nuvoton.c b/util/superiotool/nuvoton.c index 46b8c2a..2adb90a 100644 --- a/util/superiotool/nuvoton.c +++ b/util/superiotool/nuvoton.c @@ -476,12 +476,16 @@ void probe_idregs_nuvoton(uint16_t port) uint8_t sid, srid; uint16_t chip_id = 0; uint8_t chip_rev = 0; + uint16_t iobase = 0; + int i; /* Probe for the 16bit IDs first to avoid collisions */ probing_for("Nuvoton", "", port); enter_conf_mode_winbond_fintek_ite_8787(port); chip_id = (regval(port, DEVICE_ID_REG) << 8) | regval(port, DEVICE_ID_REG + 1); + regwrite(port, LDN_SEL, 0x0b); + iobase = (regval(port, 0x60) << 8) | (regval(port, 0x61) & ~7); exit_conf_mode_winbond_fintek_ite_8787(port); @@ -492,7 +496,7 @@ void probe_idregs_nuvoton(uint16_t port) enter_conf_mode_winbond_fintek_ite_8787(port); dump_superio("Nuvoton", reg_table, port, chip_id, LDN_SEL); exit_conf_mode_winbond_fintek_ite_8787(port); - return; + goto extra; } if (verbose) @@ -524,6 +528,27 @@ void probe_idregs_nuvoton(uint16_t port) get_superio_name(reg_table, sid), chip_id, chip_rev, port); chip_found = 1; dump_superio("Nuvoton", reg_table, port, sid, LDN_SEL); + +extra: + if (extra_dump && iobase) { + switch (chip_id & 0xfff0) { + case 0xb470: /* NCT6775F */ + for (i = 0; i < 7; i++) + dump_data(iobase + 5, i); + dump_data(iobase + 5, 0xa); + dump_data(iobase + 5, 0xc); + dump_data(iobase + 5, 0xd); + break; + case 0xc330: /* NCT6776F */ + for (i = 0; i < 8; i++) + dump_data(iobase + 5, i); + break; + case 0xc560: /* NCT6779D */ + for (i = 0; i < 10; i++) + dump_data(iobase + 5, i); + break; + } + } } void print_nuvoton_chips(void)

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Patch set updated for coreboot: f419483 superiotool: Add support for git-based version number
by Guenter Roeck 06 Jul '12

06 Jul '12

Guenter Roeck (linux(a)roeck-us.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1151 -gerrit commit f41948308c9360389680c1d12c5c1d406354048b Author: Guenter Roeck <linux(a)roeck-us.net> Date: Fri Jun 29 12:25:46 2012 -0700 superiotool: Add support for git-based version number The superiotool Makefile extracts a version string from SVN. This does not work with a git repository, and results in an empty version string. Use the output of 'git describe' as version string instead. Change-Id: Idf92c02753b28ef5bcdd3b6df4a08d79ae974434 Signed-off-by: Guenter Roeck <linux(a)roeck-us.net> --- util/superiotool/Makefile | 9 ++++----- 1 files changed, 4 insertions(+), 5 deletions(-) diff --git a/util/superiotool/Makefile b/util/superiotool/Makefile index e7d2f63..41625d3 100644 --- a/util/superiotool/Makefile +++ b/util/superiotool/Makefile @@ -24,13 +24,12 @@ CC = gcc INSTALL = /usr/bin/install PREFIX = /usr/local -# Set the superiotool version string from the highest revision number -# of the checked out superiotool files. -SVNDEF := -D'SUPERIOTOOL_VERSION="$(shell svnversion -cn . \ - | sed -e "s/.*://" -e "s/$[0-9]*$.*/\1/")"' +# Set the superiotool version string to the output of 'git describe'. + +VERSION := -D'SUPERIOTOOL_VERSION="$(shell git describe 2>/dev/null)"' CFLAGS += -O2 -Wall -Wstrict-prototypes -Wundef -Wstrict-aliasing \ - -Werror-implicit-function-declaration -ansi -pedantic $(SVNDEF) + -Werror-implicit-function-declaration -ansi -pedantic $(VERSION) LDFLAGS += -lz OBJS = superiotool.o serverengines.o ali.o fintek.o ite.o nsc.o nuvoton.o \

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New patch to review for coreboot: 62a9147 print CPU index on CPU initialization messages
by Sven Schnelle 05 Jul '12

05 Jul '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1176 -gerrit commit 62a9147685c7716eed051dbd7341c2f8a18501d8 Author: Sven Schnelle <svens(a)stackframe.org> Date: Thu Jul 5 23:15:19 2012 +0200 print CPU index on CPU initialization messages Change-Id: I533259f9aa985487e9146959fcc3da9b07570441 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/arch/x86/lib/cpu.c | 13 ++++++------- 1 files changed, 6 insertions(+), 7 deletions(-) diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c index 2d64be9..a5d1eb4 100644 --- a/src/arch/x86/lib/cpu.c +++ b/src/arch/x86/lib/cpu.c @@ -249,10 +249,9 @@ void cpu_initialize(struct bus *cpu_bus, int index) struct device *cpu; struct cpuinfo_x86 c; struct device_path cpu_path; - unsigned char id = lapicid(); cpu_path.type = DEVICE_PATH_APIC; - cpu_path.apic.apic_id = id; + cpu_path.apic.apic_id = lapicid(); cpu_path.apic.index = index; #if CONFIG_SMP @@ -262,16 +261,16 @@ void cpu_initialize(struct bus *cpu_bus, int index) #if CONFIG_SMP spin_unlock(&start_cpu_lock); #endif - printk(BIOS_DEBUG, "Initializing CPU #%d\n", id); + printk(BIOS_DEBUG, "Initializing CPU #%d (APIC ID %lu)\n", index, lapicid()); /* Find what type of cpu we are dealing with */ identify_cpu(cpu); - printk(BIOS_DEBUG, "CPU: vendor %s device %x\n", + printk(BIOS_DEBUG, "CPU%d: vendor %s device %x\n", index, cpu_vendor_name(cpu->vendor), cpu->device); get_fms(&c, cpu->device); - printk(BIOS_DEBUG, "CPU: family %02x, model %02x, stepping %02x\n", + printk(BIOS_DEBUG, "CPU%d: family %02x, model %02x, stepping %02x\n", index, c.x86, c.x86_model, c.x86_mask); /* Lookup the cpu's operations */ @@ -283,7 +282,7 @@ void cpu_initialize(struct bus *cpu_bus, int index) set_cpu_ops(cpu); cpu->device += c.x86_mask; if(!cpu->ops) die("Unknown cpu"); - printk(BIOS_DEBUG, "Using generic cpu ops (good)\n"); + printk(BIOS_DEBUG, "CPU%d: Using generic cpu ops (good)\n", index); } /* Initialize the cpu */ @@ -293,7 +292,7 @@ void cpu_initialize(struct bus *cpu_bus, int index) cpu->ops->init(cpu); } - printk(BIOS_INFO, "CPU #%d initialized\n", id); + printk(BIOS_INFO, "CPU #%d initialized\n", index); return; }

1 0

Patch merged into coreboot/master: 20b915f PCI Type2 config must die
by gerrit＠coreboot.org 05 Jul '12

05 Jul '12

the following patch was just integrated into master: commit 20b915f02ecd847742920f8faccea2ec8c28b7af Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Mon Jul 2 09:41:10 2012 -0700 PCI Type2 config must die PCI Type 2 config was a strange and never-used config mechanism. It is unlikely that in the 13 years of coreboot's existence that type 2 was ever used; it just made life complicated for everyone. It lived long enough in coreboot to be replaced by mmioconf. Prior to making the device tree visible in romstage we want to get rid of type2. Delete two files we don't need any more (yay!). Replace two functions with one: pci_config_default, which returns a pointer to the default config method. At some future time this may change to mmio but for now it is old type1 style. Change-Id: Icc4ccf379a89bfca8be43f305b68ab45d88bf0ab Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Jul 3 02:32:25 2012, giving +1 Reviewed-By: Sven Schnelle <svens(a)stackframe.org> at Thu Jul 5 23:00:43 2012, giving +2 See http://review.coreboot.org/1159 for details. -gerrit

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New patch to review for coreboot: 8a1dbc8 inteltool: fixup intel 5000 chipset pci ids
by Sven Schnelle 05 Jul '12

05 Jul '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1175 -gerrit commit 8a1dbc8c8be9b8c6bf28505b4faadaa51de204ee Author: Sven Schnelle <svens(a)stackframe.org> Date: Thu Jul 5 22:53:57 2012 +0200 inteltool: fixup intel 5000 chipset pci ids Change-Id: I2cd1dac0dd9a5da1000a3ffa3e1c8ee4c5c8ba43 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- util/inteltool/inteltool.c | 1 + util/inteltool/inteltool.h | 5 +++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index e5c2b86..ef354f2 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -87,6 +87,7 @@ static const struct { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000P, "Intel i5000P Memory Controller Hub" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000X, "Intel i5000X Memory Controller Hub" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000Z, "Intel i5000Z Memory Controller Hub" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000V, "Intel i5000V Memory Controller Hub" }, }; #ifndef __DARWIN__ diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index c3fa365..22ebc3d 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -86,8 +86,9 @@ #define PCI_DEVICE_ID_INTEL_ATOM_DXXX 0xa000 #define PCI_DEVICE_ID_INTEL_I63XX 0x2670 -#define PCI_DEVICE_ID_INTEL_I5000X 0x25d0 -#define PCI_DEVICE_ID_INTEL_I5000Z 0x25d4 +#define PCI_DEVICE_ID_INTEL_I5000X 0x25c0 +#define PCI_DEVICE_ID_INTEL_I5000Z 0x25d0 +#define PCI_DEVICE_ID_INTEL_I5000V 0x25d4 #define PCI_DEVICE_ID_INTEL_I5000P 0x25d8 /* untested, but almost identical to D-series */

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coreboot July 2012