the following patch was just integrated into master:
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Thu Jun 28 21:50:43 2012 +0300
Intel model_106cx: change CAR to model_6ex
Diff between model_106cx and model_6ex CAR codes suggests currently
used model_106cx CAR is not optimal - destination RAM and source ROM
of ramstage copy_and_run are only partly set cacheable.
It appears variable MTRR setting for XIP cache is left enabled on
model_106cx code, where it should have extended to cover all of Flash.
Introduces untested functional change on boards:
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Build-Tested: build bot (Jenkins) at Wed Jul 4 12:21:14 2012, giving +1
Reviewed-By: Sven Schnelle <svens(a)stackframe.org> at Wed Jul 4 14:45:38 2012,