coreboot March 2012

coreboot@coreboot.org

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New patch to review for coreboot: f2462af Don't run any option roms stored outside of the system flash
by Stefan Reinauer 05 Mar '12

05 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/730 -gerrit commit f2462af4c374f16da3fbd7bc630652623acf260e Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Oct 6 16:47:51 2011 -0700 Don't run any option roms stored outside of the system flash Right now coreboot only executes vga option roms. However, this is not good enough. For security reasons we want to execute only option roms stored in our RO CBFS. This patch adds a new option to disable execution of arbitrary option ROMs and enables it for all our boards. Change-Id: I485291c06ec5cd1f875357401831fe32ccfc5f2f Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/devices/Kconfig | 13 +++++++++++++ src/devices/pci_rom.c | 6 ++++++ 2 files changed, 19 insertions(+), 0 deletions(-) diff --git a/src/devices/Kconfig b/src/devices/Kconfig index 572addc..98e8d9f 100644 --- a/src/devices/Kconfig +++ b/src/devices/Kconfig @@ -49,6 +49,19 @@ config PCI_ROM_RUN Examples include IDE/SATA controller option ROMs and option ROMs for network cards (NICs). +config ON_DEVICE_ROM_RUN + bool "Run option ROMs on PCI devices" + default y + help + Execute option ROMs that are stored on PCI/PCIe/AGP devices. + + If disabled, only option ROMs stored in CBFS will be executed. If + you are concerned about security, you might want to disable this + option, but it might leave your system in a state of degraded + functionality. + + If unsure, say Y + choice prompt "Option ROM execution type" default PCI_OPTION_ROM_RUN_YABEL if !ARCH_X86 diff --git a/src/devices/pci_rom.c b/src/devices/pci_rom.c index 471c7e2..1b6f1da 100644 --- a/src/devices/pci_rom.c +++ b/src/devices/pci_rom.c @@ -71,9 +71,15 @@ struct rom_header *pci_rom_probe(struct device *dev) rom_address|PCI_ROM_ADDRESS_ENABLE); } +#if CONFIG_ON_DEVICE_ROM_RUN printk(BIOS_DEBUG, "On card, ROM address for %s = %lx\n", dev_path(dev), (unsigned long)rom_address); rom_header = (struct rom_header *)rom_address; +#else + printk(BIOS_DEBUG, "On card option ROM execution disabled " + "for %s\n", dev_path(dev)); + return NULL; +#endif } printk(BIOS_SPEW, "PCI expansion ROM, signature 0x%04x, "

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New patch to review for coreboot: 5133024 If the memory mapped UART isn't present, leave it out of the cb tables.
by Stefan Reinauer 05 Mar '12

05 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/729 -gerrit commit 5133024b140f999487d9af0598406f06a7bdf92e Author: Gabe Black <gabeblack(a)google.com> Date: Wed Oct 5 01:57:03 2011 -0700 If the memory mapped UART isn't present, leave it out of the cb tables. This way u-boot won't try to use a UART that isn't plugged in. Change-Id: I9a3a0d074dd03add8afbd4dad836c4c6a05abe6f Signed-off-by: Gabe Black <gabeblack(a)google.com> --- src/arch/x86/boot/coreboot_table.c | 24 ++++++++++++++---------- 1 files changed, 14 insertions(+), 10 deletions(-) diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c index f29481b..d24d7c4 100644 --- a/src/arch/x86/boot/coreboot_table.c +++ b/src/arch/x86/boot/coreboot_table.c @@ -118,16 +118,20 @@ static struct lb_serial *lb_serial(struct lb_header *header) serial->baud = CONFIG_TTYS0_BAUD; return serial; #elif CONFIG_CONSOLE_SERIAL8250MEM - struct lb_record *rec; - struct lb_serial *serial; - rec = lb_new_record(header); - serial = (struct lb_serial *)rec; - serial->tag = LB_TAG_SERIAL; - serial->size = sizeof(*serial); - serial->type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial->baseaddr = uartmem_getbaseaddr(); - serial->baud = CONFIG_TTYS0_BAUD; - return serial; + if (uartmem_getbaseaddr()) { + struct lb_record *rec; + struct lb_serial *serial; + rec = lb_new_record(header); + serial = (struct lb_serial *)rec; + serial->tag = LB_TAG_SERIAL; + serial->size = sizeof(*serial); + serial->type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial->baseaddr = uartmem_getbaseaddr(); + serial->baud = CONFIG_TTYS0_BAUD; + return serial; + } else { + return NULL; + } #else return NULL; #endif

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New patch to review for coreboot: 4b11a08 Detect whether the OXPCIE card is really present while in the ROM stage.
by Stefan Reinauer 05 Mar '12

05 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/728 -gerrit commit 4b11a084dd22603b3db7c8d58919732ec2dc063e Author: Gabe Black <gabeblack(a)google.com> Date: Wed Oct 5 01:52:08 2011 -0700 Detect whether the OXPCIE card is really present while in the ROM stage. Use an int in CAR global data to store whether or not the OXPCIE serial card is actually there. Also, time out if the card doesn't show up quickly enough, don't continue initialization if it's not there, and don't make the initialization routine default to a card if none is found. Change-Id: I9c72d3abc6ee2867b77ab2f2180e6f01f647af8c Signed-off-by: Gabe Black <gabeblack(a)google.com> --- src/arch/x86/lib/romstage_console.c | 5 ++++- src/drivers/oxford/oxpcie/oxpcie_early.c | 20 +++++++++++++++++--- src/include/uart8250.h | 5 +++++ 3 files changed, 26 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index 0f22727..25eda9b 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -35,7 +35,10 @@ static void console_tx_byte(unsigned char byte) console_tx_byte('\r'); #if CONFIG_CONSOLE_SERIAL8250MEM - uart8250_mem_tx_byte(CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte); + if (oxford_oxpcie_present) { + uart8250_mem_tx_byte( + CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte); + } #endif #if CONFIG_CONSOLE_SERIAL8250 uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c index 2c7767e..4f7a3cb 100644 --- a/src/drivers/oxford/oxpcie/oxpcie_early.c +++ b/src/drivers/oxford/oxpcie/oxpcie_early.c @@ -20,6 +20,8 @@ #include <stdint.h> #include <arch/io.h> #include <arch/romcc_io.h> +#include <cpu/x86/car.h> +#include <delay.h> #include <uart8250.h> #include <device/pci_def.h> @@ -34,9 +36,13 @@ #define OXPCIE_DEVICE_3 \ PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 3) +#if defined(__PRE_RAM__) +int oxford_oxpcie_present CAR_GLOBAL; + void oxford_init(void) { u16 reg16; + oxford_oxpcie_present = 1; /* First we reset the secondary bus */ reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL); @@ -69,11 +75,14 @@ void oxford_init(void) reg16 |= PCI_COMMAND_MEMORY; pci_write_config16(PCIE_BRIDGE, PCI_COMMAND, reg16); - // FIXME Add a timeout or this will hang forever if - // no device is in the slot. + u32 timeout = 20000; // Timeout in 10s of microseconds. u32 id = 0; - while ((id == 0) || (id == 0xffffffff)) + for (;;) { id = pci_read_config32(OXPCIE_DEVICE, PCI_VENDOR_ID); + if (!timeout-- || (id != 0 && id != 0xffffffff)) + break; + udelay(10); + } u32 device = OXPCIE_DEVICE; /* unknown default */ switch (id) { @@ -90,6 +99,10 @@ void oxford_init(void) case 0xc1581415: /* e.g. Startech MPEX2S952 */ device = OXPCIE_DEVICE; break; + default: + /* No UART here. */ + oxford_oxpcie_present = 0; + return; } /* Setup base address on device */ @@ -107,3 +120,4 @@ void oxford_init(void) uart8250_mem_init(uart0_base, (4000000 / CONFIG_TTYS0_BAUD)); } +#endif diff --git a/src/include/uart8250.h b/src/include/uart8250.h index aa510e5..71b9a5f 100644 --- a/src/include/uart8250.h +++ b/src/include/uart8250.h @@ -135,8 +135,13 @@ void uart8250_mem_init(unsigned base_port, unsigned divisor); u32 uart_mem_init(void); u32 uartmem_getbaseaddr(void); +#if defined(__PRE_RAM__) && CONFIG_DRIVERS_OXFORD_OXPCIE && \ + CONFIG_CONSOLE_SERIAL8250MEM /* and special init for OXPCIe based cards */ +extern int oxford_oxpcie_present; + void oxford_init(void); +#endif #endif /* __ROMCC__ */

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New patch to review for coreboot: 7947060 Add infrastructure for global data in the CAR phase of boot.
by Stefan Reinauer 05 Mar '12

05 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/727 -gerrit commit 79470609d653dbd34cab2ebe1126047a9425c4e1 Author: Gabe Black <gabeblack(a)google.com> Date: Sat Oct 1 04:27:32 2011 -0700 Add infrastructure for global data in the CAR phase of boot. The cbmem console structure and car global data are put in their own section, with the cbmem console coming after the global data. These areas are linked to be where CAR is available and at the very bottom of the stack. There is one shortcoming of this change: The section created by this change needs to be stripped out by the Makefile since leaving it in confuses cbfstool when it installs the stage in the image. I would like to make the tools link those symbols at the right location but leave allocation of that space out of the ELF. Change-Id: Iccfb99b128d59c5b7d6164796d21ba46d2a674e0 Signed-off-by: Gabe Black <gabeblack(a)google.com> --- src/arch/x86/Makefile.inc | 2 +- src/arch/x86/init/bootblock.ld | 7 +++++++ src/include/cpu/x86/car.h | 31 +++++++++++++++++++++++++++++++ src/lib/cbmem_console.c | 7 +++++-- 4 files changed, 44 insertions(+), 3 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 624b510..aeb4875 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -272,7 +272,7 @@ $(obj)/coreboot.pre: $(obj)/coreboot.romstage $(obj)/coreboot.pre1 $(CBFSTOOL) rm -f $@ cp $(obj)/coreboot.pre1 $@ $(CBFSTOOL) $@ add-stage $(obj)/romstage.elf \ - $(CONFIG_CBFS_PREFIX)/romstage x 0x$(shell cat $(obj)/location.txt) + $(CONFIG_CBFS_PREFIX)/romstage x 0x$(shell cat $(obj)/location.txt) #FIXME: location.txt might require an offset of header size ####################################################################### diff --git a/src/arch/x86/init/bootblock.ld b/src/arch/x86/init/bootblock.ld index bde0430..6f8ade8 100644 --- a/src/arch/x86/init/bootblock.ld +++ b/src/arch/x86/init/bootblock.ld @@ -51,5 +51,12 @@ SECTIONS *(.eh_frame); } + . = CONFIG_DCACHE_RAM_BASE; + .car.data . (NOLOAD) : { + *(.car.global_data); + *(.car.cbmem_console); + } + + _bogus = ASSERT((SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full"); _bogus = ASSERT((SIZEOF(.bss) + SIZEOF(.data)) == 0 || CONFIG_AMD_AGESA, "Do not use global variables in romstage"); } diff --git a/src/include/cpu/x86/car.h b/src/include/cpu/x86/car.h new file mode 100644 index 0000000..2d2af03 --- /dev/null +++ b/src/include/cpu/x86/car.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#ifndef CPU_X86_CAR_H +#define CPU_X86_CAR_H + +#ifdef __PRE_RAM__ +#define CAR_GLOBAL __attribute__((section(".car.global_data,\"w\",@nobits#"))) +#define CAR_CBMEM __attribute__((section(".car.cbmem_console,\"w\",@nobits#"))) +#else +#define CAR_GLOBAL +#define CAR_CBMEM +#endif + +#endif diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index b58de48..431ea1f 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -19,6 +19,7 @@ #include <console/console.h> #include <cbmem.h> +#include <cpu/x86/car.h> #include <string.h> /* @@ -39,7 +40,9 @@ struct cbmem_console { * ram space is used for the console buffer storage. The size and location of * the area are defined in the config. */ -#define cbmem_console_p ((struct cbmem_console *)CONFIG_DCACHE_RAM_BASE) + +static struct cbmem_console car_cbmem_console CAR_CBMEM; +#define cbmem_console_p (&car_cbmem_console) /* * Once DRAM is initialized and the cache as ram mode is disabled, while still @@ -92,7 +95,7 @@ void cbmemc_tx_byte(unsigned char data) * DCACHE_RAM_BASE), use the redirect pointer to find out where the * actual console buffer is. */ - if ((u32)&cursor < (u32)CONFIG_DCACHE_RAM_BASE) + if ((uintptr_t)&cursor < (uintptr_t)&car_cbmem_console) cbm_cons_p = CBMEM_CONSOLE_REDIRECT; #endif if (!cbm_cons_p)

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New patch to review for coreboot: 474841c Fix typos in src/console/Kconfig
by Stefan Reinauer 05 Mar '12

05 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/726 -gerrit commit 474841cf56e9de1b3323bcb676567bfe09e4b187 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Oct 4 16:21:17 2011 -0700 Fix typos in src/console/Kconfig - cash -> Cache - make the new size of the cbmem console buffer the default Change-Id: Ia906077257e93622ad56bc54a42f8184ade78b29 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/console/Kconfig | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index fefbe2e..2cfc4db 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -201,7 +201,7 @@ config CONSOLE_CBMEM config CONSOLE_CBMEM_BUFFER_SIZE depends on CONSOLE_CBMEM hex "Room allocated for console output in CBMEM" - default 0xae00 + default 0x10000 help Space allocated for console output storage in CBMEM. The default value (almost 45K or 0xaeoo bytes) is large enough to accommodate @@ -209,7 +209,7 @@ config CONSOLE_CBMEM_BUFFER_SIZE config CONSOLE_CAR_BUFFER_SIZE depends on CONSOLE_CBMEM - hex "Room allocated for console output in cash as RAM" + hex "Room allocated for console output in Cache as RAM" default 0xc00 help Console is used before RAM is initialized. This is the room reserved

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New patch to review for coreboot: 43da2e7 Increase CBMEM to accommodate larger console.
by Stefan Reinauer 05 Mar '12

05 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/725 -gerrit commit 43da2e7b7483f2b640a8f8d7c06be684735c1e08 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Oct 4 10:44:16 2011 -0700 Increase CBMEM to accommodate larger console. This change adds 128K to the memory amount set aside for CBMEM in case the CBMEM console is enabled (to keep the CBMEM 128K byte aligned). The console buffer size is being set to 64K, which is enough to accommodate the most verbose coreboot console and u-boot console. Change-Id: If583013dfb210de5028d69577675095c6fe2f3ab Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/include/cbmem.h | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index a19ec5a..6a48dd2 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -21,7 +21,12 @@ #define _CBMEM_H_ /* Reserve 128k for ACPI and other tables */ +#if CONFIG_CONSOLE_CBMEM +#define HIGH_MEMORY_DEF_SIZE ( 256 * 1024 ) +#else #define HIGH_MEMORY_DEF_SIZE ( 128 * 1024 ) +#endif + #ifndef __PRE_RAM__ extern uint64_t high_tables_base, high_tables_size; #endif

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New patch to review for coreboot: 34b7fda Refactor publishing CBMEM addresses through coreboot table.
by Stefan Reinauer 05 Mar '12

05 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/724 -gerrit commit 34b7fdad7c6865aeabc6024b1b3123c87b7c4ea6 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Mon Oct 3 14:58:57 2011 -0700 Refactor publishing CBMEM addresses through coreboot table. We need to provide u-boot access to several different CBMEM sections. To do that, a common coreboot table structure is used, just different tags match different coreboot table sections. Also, the code is added to export CBMEM console and MRC cache addresses through the same mechanism. Change-Id: I63adb67093b8b50ee61b0deb0b56ebb2c4856895 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/arch/x86/boot/coreboot_table.c | 59 +++++++++++++++++++++++++++++------- src/include/boot/coreboot_tables.h | 6 ++- 2 files changed, 52 insertions(+), 13 deletions(-) diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c index f189e76..f29481b 100644 --- a/src/arch/x86/boot/coreboot_table.c +++ b/src/arch/x86/boot/coreboot_table.c @@ -175,22 +175,40 @@ static void lb_framebuffer(struct lb_header *header) #endif } -#if CONFIG_COLLECT_TIMESTAMPS -static void lb_tsamp(struct lb_header *header) +static void add_cbmem_pointers(struct lb_header *header) { - struct lb_tstamp *tstamp; - void *tstamp_table = cbmem_find(CBMEM_ID_TIMESTAMP); + /* + * These CBMEM sections' addresses are included in the coreboot table + * with the appropriate tags. + */ + const struct section_id { + int cbmem_id; + int table_tag; + } section_ids[] = { + {CBMEM_ID_TIMESTAMP, LB_TAG_TIMESTAMPS}, + {CBMEM_ID_MRCDATA, LB_TAG_MRC_CACHE}, + {CBMEM_ID_CONSOLE, LB_TAG_CBMEM_CONSOLE} + }; + int i; - if (!tstamp_table) - return; + for (i = 0; i < ARRAY_SIZE(section_ids); i++) { + const struct section_id *sid = section_ids + i; + struct lb_cbmem_ref *cbmem_ref; + void *cbmem_addr = cbmem_find(sid->cbmem_id); - tstamp = (struct lb_tstamp *)lb_new_record(header); - tstamp->tag = LB_TAG_TIMESTAMPS; - tstamp->size = sizeof(*tstamp); - tstamp->tstamp_tab = tstamp_table; + if (!cbmem_addr) + continue; /* This section is not present */ + cbmem_ref = (struct lb_cbmem_ref *)lb_new_record(header); + if (!cbmem_ref) { + printk(BIOS_ERR, "No more room in coreboot table!\n"); + break; + } + cbmem_ref->tag = sid->table_tag; + cbmem_ref->size = sizeof(*cbmem_ref); + cbmem_ref->cbmem_addr = cbmem_addr; + } } -#endif static struct lb_mainboard *lb_mainboard(struct lb_header *header) { @@ -633,9 +651,28 @@ unsigned long write_coreboot_table( /* Record our framebuffer */ lb_framebuffer(head); +<<<<<<< HEAD #if CONFIG_COLLECT_TIMESTAMPS lb_tsamp(head); #endif +======= +#if CONFIG_CHROMEOS + /* Record our GPIO settings (ChromeOS specific) */ + lb_gpios(head); + + /* pass along the VDAT buffer adress */ + lb_vdat(head); +#endif +#if CONFIG_ADD_FDT + /* + * Copy FDT from CBFS into the coreboot table possibly augmenting it + * along the way. + */ + lb_fdt(head, serial); +#endif + add_cbmem_pointers(head); + +>>>>>>> 3fc47a1... Refactor publishing CBMEM addresses through coreboot table. /* Remember where my valid memory ranges are */ return lb_table_fini(head, 1); diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index 46d6489..5535a38 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -196,11 +196,13 @@ struct lb_framebuffer { }; #define LB_TAG_TIMESTAMPS 0x0016 -struct lb_tstamp { +#define LB_TAG_CBMEM_CONSOLE 0x0017 +#define LB_TAG_MRC_CACHE 0x0018 +struct lb_cbmem_ref { uint32_t tag; uint32_t size; - void *tstamp_tab; + void *cbmem_addr; }; /* The following structures are for the cmos definitions table */

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New patch to review for coreboot: c8604fe Introduce utility for parsing CBMEM contents.
by Stefan Reinauer 05 Mar '12

05 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/723 -gerrit commit c8604fe38a12fbd8cab09a6692f5574dccca234c Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri Sep 30 14:21:03 2011 -0700 Introduce utility for parsing CBMEM contents. This is a python script which is supposed to run on a target which is controlled by coreboot. The script examines top of memory looking for the CBMEM signature at addresses aligned at 128K boundary. Once the script finds the CBMEM, it iterates through the CBMEM table of contents and parses two entries: the timestamps and the console log. This submission is just a template to build upon to create a utility for displaying CBMEM information while running Linux on the target. BUG=chrome-os-partner:4200 TEST=manual See test description of d81e6b8c8d41f2d6 for test procedure. Change-Id: Id863a8598eaadc2d20d728f9186843e65cbe6f37 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Reviewed-on: https://gerrit-int.chromium.org/5942 Tested-by: Vadim Bendebury <vbendeb(a)google.com> Reviewed-by: Stefan Reinauer <reinauer(a)google.com> --- util/cbmem/cbmem.py | 204 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 204 insertions(+), 0 deletions(-) diff --git a/util/cbmem/cbmem.py b/util/cbmem/cbmem.py new file mode 100755 index 0000000..3e8476d --- /dev/null +++ b/util/cbmem/cbmem.py @@ -0,0 +1,204 @@ +#!/usr/bin/python +# +# cbmem.py - Linux space CBMEM contents parser +# +# Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +''' +Parse and display CBMEM contents. + +This module is meant to run on systems with coreboot based firmware. + +When started, it determines the amount of DRAM installed on the system, and +then scans the top area of DRAM (right above the available memory size) +looking for the CBMEM base signature at locations aligned at 0x20000 +boundaries. + +Once it finds the CBMEM signature, the utility parses the contents, reporting +the section IDs/sizes and also reporting the contents of the tiemstamp and +console sections. +''' + +import mmap +import re +import struct +import sys +import time + +# These definitions follow src/include/cbmem.h +CBMEM_MAGIC = 0x434f5245 +CBMEM_MAX_ENTRIES = 16 + +CBMEM_ENTRY_FORMAT = '@LLQQ' +CONSOLE_HEADER_FORMAT = '@LL' +TIMESTAMP_HEADER_FORMAT = '@QLL' +TIMESTAMP_ENTRY_FORMAT = '@LQ' + +mf_fileno = 0 # File number of the file providing access to memory. + +def align_up(base, alignment): + '''Increment to the alignment boundary. + + Return the next integer larger than 'base' and divisible by 'alignment'. + ''' + + return base + alignment - base % alignment + +def normalize_timer(value, freq): + '''Convert timer reading into microseconds. + + Get the free running clock counter value, divide it by the clock frequency + and multiply by 1 million to get reading in microseconds. + + Then convert the value into an ASCII string with groups of three digits + separated by commas. + + Inputs: + value: int, the clock reading + freq: float, the clock frequency + + Returns: + A string presenting 'value' in microseconds. + ''' + + result = [] + value = int(value * 1000000.0 / freq) + svalue = '%d' % value + vlength = len(svalue) + remainder = vlength % 3 + if remainder: + result.append(svalue[0:remainder]) + while remainder < vlength: + result.append(svalue[remainder:remainder+3]) + remainder = remainder + 3 + return ','.join(result) + +def get_cpu_freq(): + '''Retrieve CPU frequency from sysfs. + + Use /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq as the source. + ''' + freq_str = open('/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq' + ).read() + # Convert reading into Hertz + return float(freq_str) * 1000.0 + +def get_mem_size(): + '''Retrieve amount of memory available to the CPU from /proc/meminfo.''' + mult = { + 'kB': 1024 + } + meminfo = open('/proc/meminfo').read() + m = re.search('MemTotal:.*\n', meminfo) + mem_string = re.search('MemTotal:.*\n', meminfo).group(0) + (_, size, mult_name) = mem_string.split() + return int(size) * mult[mult_name] + +def parse_mem_at(addr, format): + '''Read and parse a memory location. + + This function reads memory at the passed in address, parses it according + to the passed in format specification and returns a list of values. + + The first value in the list is the size of data matching the format + expression, and the rest of the elements of the list are the actual values + retrieved using the format. + ''' + + size = struct.calcsize(format) + delta = addr % 4096 # mmap requires the offset to be page size aligned. + mm = mmap.mmap(mf_fileno, size + delta, + mmap.MAP_PRIVATE, offset=(addr - delta)) + buf = mm.read(size + delta) + mm.close() + rv = [size,] + list(struct.unpack(format, buf[delta:size + delta + 1])) + return rv + +def dprint(text): + '''Debug print function. + + Edit it to get the debug output. + ''' + + if False: + print text + +def process_timers(base): + '''Scan the array of timestamps found in CBMEM at address base. + + For each timestamp print the timer ID and the value in microseconds. + ''' + + (step, base_time, max_entr, entr) = parse_mem_at( + base, TIMESTAMP_HEADER_FORMAT) + + print('\ntime base %d, total entries %d' % (base_time, entr)) + clock_freq = get_cpu_freq() + base = base + step + for i in range(entr): + (step, timer_id, timer_value) = parse_mem_at( + base, TIMESTAMP_ENTRY_FORMAT) + print '%d:%s ' % (timer_id, normalize_timer(timer_value, clock_freq)), + base = base + step + print + +def process_console(base): + '''Dump the console log buffer contents found at address base.''' + + (step, size, cursor) = parse_mem_at(base, CONSOLE_HEADER_FORMAT) + print 'cursor at %d\n' % cursor + + cons_string_format = '%ds' % min(cursor, size) + (_, cons_text) = parse_mem_at(base + step, cons_string_format) + print cons_text + print '\n' + +mem_alignment = 1024 * 1024 * 1024 # 1 GBytes +table_alignment = 128 * 1024 + +mem_size = get_mem_size() + +# start at memory address aligned at 128K. +offset = align_up(mem_size, table_alignment) + +dprint('mem_size %x offset %x' %(mem_size, offset)) +mf = open("/dev/mem") +mf_fileno = mf.fileno() + +while offset % mem_alignment: # do not cross the 1G boundary while searching + (step, magic, mid, base, size) = parse_mem_at(offset, CBMEM_ENTRY_FORMAT) + if magic == CBMEM_MAGIC: + offset = offset + step + break + offset += table_alignment +else: + print 'Did not find the CBMEM' + sys.exit(0) + +for i in (range(1, CBMEM_MAX_ENTRIES)): + (_, magic, mid, base, size) = parse_mem_at(offset, CBMEM_ENTRY_FORMAT) + if mid == 0: + break + + print '%x, %x, %x' % (mid, base, size) + if mid == 0x54494d45: + process_timers(base) + if mid == 0x434f4e53: + process_console(base) + + offset = offset + step + +mf.close()

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New patch to review for coreboot: 8d75b03 CBMEM CONSOLE: Enable coreboot CBMEM console.
by Stefan Reinauer 05 Mar '12

05 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/722 -gerrit commit 8d75b037fa5d497f0a4c6d0e82cbf5241e749f88 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri Sep 30 12:02:18 2011 -0700 CBMEM CONSOLE: Enable coreboot CBMEM console. The appropriate Makefiles are modified to include the required source code in compilation. Change-Id: I91842b1ba0f89d611d3249b63c020a2713a9124f Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/console/Makefile.inc | 2 ++ src/lib/Makefile.inc | 2 ++ 2 files changed, 4 insertions(+), 0 deletions(-) diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index 4a30918..f3b8758 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -18,6 +18,8 @@ driver-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem_console.c driver-$(CONFIG_USBDEBUG) += usbdebug_console.c driver-$(CONFIG_CONSOLE_LOGBUF) += logbuf_console.c driver-$(CONFIG_CONSOLE_NE2K) += ne2k_console.c +driver-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c + $(obj)/console/console.ramstage.o : $(obj)/build.h $(obj)/console/console.romstage.o : $(obj)/build.h diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index db640dc..45cb788 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -11,6 +11,7 @@ romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c romstage-$(CONFIG_HAVE_ACPI_RESUME) += cbmem.c romstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c +romstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c romstage-$(CONFIG_CONSOLE_NE2K) += compute_ip_checksum.c romstage-$(CONFIG_USBDEBUG) += usbdebug.c @@ -34,6 +35,7 @@ ramstage-y += clog2.c ramstage-y += cbmem.c ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c +ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c ramstage-$(CONFIG_USBDEBUG) += usbdebug.c ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c ramstage-$(CONFIG_TRACE) += trace.c

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New patch to review for coreboot: 7f3e86b CBMEM CONSOLE: Add code using the new console driver.
by Stefan Reinauer 05 Mar '12

05 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/721 -gerrit commit 7f3e86be5f19f90695f5247c7ff00746b84b1183 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri Sep 30 11:16:49 2011 -0700 CBMEM CONSOLE: Add code using the new console driver. The new added code is compiled in when the CBMEM_CONSOLE config flag is enabled. Change-Id: Ifd1f492ce6321412a014333babbc5b3f14635988 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/arch/x86/lib/romcc_console.c | 3 +++ src/arch/x86/lib/romstage_console.c | 3 +++ src/boot/hardwaremain.c | 3 +++ src/console/console.c | 5 ++++- 4 files changed, 13 insertions(+), 1 deletions(-) diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c index 13ee1f0..0e1f4e6 100644 --- a/src/arch/x86/lib/romcc_console.c +++ b/src/arch/x86/lib/romcc_console.c @@ -46,6 +46,9 @@ static void __console_tx_byte(unsigned char byte) #if CONFIG_CONSOLE_NE2K ne2k_append_data_byte(byte, CONFIG_CONSOLE_NE2K_IO_PORT); #endif +#if CONFIG_CONSOLE_CBMEM + cbmemc_tx_byte(byte); +#endif } static void __console_tx_nibble(unsigned nibble) diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index 8adb3ba..0f22727 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -46,6 +46,9 @@ static void console_tx_byte(unsigned char byte) #if CONFIG_CONSOLE_NE2K ne2k_append_data(&byte, 1, CONFIG_CONSOLE_NE2K_IO_PORT); #endif +#if CONFIG_CONSOLE_CBMEM + cbmemc_tx_byte(byte); +#endif } static void console_tx_flush(void) diff --git a/src/boot/hardwaremain.c b/src/boot/hardwaremain.c index 3d15b55..9b293c0 100644 --- a/src/boot/hardwaremain.c +++ b/src/boot/hardwaremain.c @@ -92,6 +92,9 @@ void hardwaremain(int boot_complete) #if CONFIG_WRITE_HIGH_TABLES == 1 cbmem_initialize(); +#if CONFIG_CONSOLE_CBMEM + cbmemc_reinit(); +#endif #endif #if CONFIG_HAVE_ACPI_RESUME == 1 suspend_resume(); diff --git a/src/console/console.c b/src/console/console.c index d933668..8f60f04 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -87,7 +87,7 @@ int console_tst_byte(void) return 0; } -#else +#else // __PRE_RAM__ ^^^ NOT defined vvv defined void console_init(void) { @@ -104,6 +104,9 @@ void console_init(void) #if CONFIG_CONSOLE_NE2K ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT); #endif +#if CONFIG_CONSOLE_CBMEM + cbmemc_init(); +#endif static const char console_test[] = "\n\ncoreboot-" COREBOOT_VERSION

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coreboot March 2012