coreboot March 2012

coreboot@coreboot.org

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718 discussions

New patch to review for coreboot: fb66503 use movsl for copying resume memory back
by Stefan Reinauer 06 Mar '12

06 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/755 -gerrit commit fb665036abbbaf8face05df7d70fce4d0247bf0b Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Nov 17 13:03:38 2011 -0800 use movsl for copying resume memory back It's not significantly faster, but easier to read and smaller. Change-Id: Ibab0b478873912d67bf1f07743f628586353368a Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/boot/wakeup.S | 20 ++++---------------- 1 files changed, 4 insertions(+), 16 deletions(-) diff --git a/src/arch/x86/boot/wakeup.S b/src/arch/x86/boot/wakeup.S index a1df4d5..f12b176 100644 --- a/src/arch/x86/boot/wakeup.S +++ b/src/arch/x86/boot/wakeup.S @@ -38,23 +38,11 @@ __wakeup: movw %ax, (__wakeup_segment) /* Then overwrite coreboot with our backed up memory */ - movl 8(%esp), %esi - movl 12(%esp), %edi - movl 16(%esp), %ecx + movl 8(%esp), %esi + movl 12(%esp), %edi + movl 16(%esp), %ecx shrl $4, %ecx -1: - movl 0(%esi),%eax - movl 4(%esi),%edx - movl 8(%esi),%ebx - movl 12(%esi),%ebp - addl $16,%esi - subl $1,%ecx - movl %eax,0(%edi) - movl %edx,4(%edi) - movl %ebx,8(%edi) - movl %ebp,12(%edi) - leal 16(%edi),%edi - jne 1b + rep movsl /* Activate the right segment descriptor real mode. */ ljmp $0x28, $RELOCATED(1f)

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New patch to review for coreboot: 426e9a3 labels should start at the beginning of the line
by Stefan Reinauer 06 Mar '12

06 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/754 -gerrit commit 426e9a32189f52b8abf03400a0a7872ef58797af Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Nov 17 12:52:30 2011 -0800 labels should start at the beginning of the line cosmetical fix Change-Id: I60d0fa90656f85ecb8acc357fe6518baa773505b Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/x86/lapic/secondary.S | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/cpu/x86/lapic/secondary.S b/src/cpu/x86/lapic/secondary.S index 5c1e760..dc00b08 100644 --- a/src/cpu/x86/lapic/secondary.S +++ b/src/cpu/x86/lapic/secondary.S @@ -47,7 +47,7 @@ _secondary_start: 1: hlt jmp 1b - gdtaddr: +gdtaddr: .word gdt_limit /* the table limit */ .long gdt /* we know the offset */

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New patch to review for coreboot: 1fd9ee4 vga_io.c is not needed unless CONFIG_VGA is set
by Stefan Reinauer 06 Mar '12

06 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/753 -gerrit commit 1fd9ee46c839bd1db159335297bfad96b894d865 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Nov 17 11:13:36 2011 -0800 vga_io.c is not needed unless CONFIG_VGA is set hence disable it. Change-Id: I7b406251a2f3830748140a111f76f2792fe923ed Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/pc80/vga/Makefile.inc | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/pc80/vga/Makefile.inc b/src/pc80/vga/Makefile.inc index 0ca7896..d4b726a 100644 --- a/src/pc80/vga/Makefile.inc +++ b/src/pc80/vga/Makefile.inc @@ -1,4 +1,4 @@ -ramstage-y += vga_io.c +ramstage-$(CONFIG_VGA) += vga_io.c ramstage-$(CONFIG_VGA) += vga_palette.c ramstage-$(CONFIG_VGA) += vga_font_8x16.c ramstage-$(CONFIG_VGA) += vga.c

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New patch to review for coreboot: 71ce35a Fix warnings in coreboot utilities.
by Stefan Reinauer 06 Mar '12

06 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/752 -gerrit commit 71ce35ac0b8a3a2ba4a931cf9fb9284086adfec8 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Nov 14 12:40:34 2011 -0800 Fix warnings in coreboot utilities. Fix some poor programming practice (breaks of strict aliasing as well as not checking the return value of read) Change-Id: I08b2e8d1bbc908f6b1f26d25cb3a4b03d818e124 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- util/inteltool/cpu.c | 6 ++++-- util/inteltool/inteltool.c | 4 +++- util/nvramtool/cli/nvramtool.c | 3 ++- 3 files changed, 9 insertions(+), 4 deletions(-) diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c index 20748bd..3bffa4e 100644 --- a/util/inteltool/cpu.c +++ b/util/inteltool/cpu.c @@ -67,8 +67,10 @@ msr_t rdmsr(int addr) } if (read(fd_msr, buf, 8) == 8) { - msr.lo = *(uint32_t *)buf; - msr.hi = *(uint32_t *)(buf + 4); + msr.lo = buf[0] | (buf[1] << 8) | + (buf[2] << 16) | (buf[3] << 24); + msr.hi = buf[4] | (buf[5] << 8) | + (buf[6] << 16) | (buf[7] << 24); return msr; } diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 6b99605..e5c2b86 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -21,6 +21,7 @@ #include <stdio.h> #include <stdlib.h> +#include <inttypes.h> #include <getopt.h> #include <fcntl.h> #include <sys/mman.h> @@ -99,7 +100,8 @@ void *map_physical(uint64_t phys_addr, size_t len) fd_mem, (off_t) phys_addr); if (virt_addr == MAP_FAILED) { - printf("Error mapping physical memory 0x%08lx[0x%zx]\n", phys_addr, len); + printf("Error mapping physical memory 0x%08" PRIx64 "[0x%zx]\n", + phys_addr, len); return NULL; } diff --git a/util/nvramtool/cli/nvramtool.c b/util/nvramtool/cli/nvramtool.c index 11a1a70..20097b8 100644 --- a/util/nvramtool/cli/nvramtool.c +++ b/util/nvramtool/cli/nvramtool.c @@ -143,7 +143,8 @@ int main(int argc, char *argv[]) if (fd_stat.st_size < 128) { lseek(fd, 127, SEEK_SET); - write(fd, "\0", 1); + if (write(fd, "\0", 1) != 1) + fprintf(stderr, "Write failed.\n"); fsync(fd); }

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New patch to review for coreboot: 2e72f8a Allow components smaller than declared size.
by Stefan Reinauer 06 Mar '12

06 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/751 -gerrit commit 2e72f8ad4e057c8fc932902f70bc266358561020 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Nov 9 14:11:26 2011 -0800 Allow components smaller than declared size. idftool was failing to add the ME blobs into the output image in case the blob size does not exactly match the size allocated for it in the flashrom structure. It is difficult to set the field in the structure to exactly match the size (for some reason Intel flash tool fails to insert the correct size even when given the exact ME blob). On the other hand there is no harm in using am ME blob smaller than the allocated size, this change modifies the tool building the image to allow for smaller components. Change-Id: I1b04f90051b91157391943c9bad0eb06dd297431 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- util/ifdtool/ifdtool.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index eb91b2c..8c1077c 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -334,7 +334,7 @@ void inject_region(char *filename, char *image, int size, int region_type, printf("File %s is %d bytes\n", region_fname, region_size); if ( (region_size > region.size) || ((region_type != 1) && - (region_size != region.size))) { + (region_size > region.size))) { fprintf(stderr, "Region %s is %d(0x%x) bytes. File is %d(0x%x)" " bytes. Not injecting.\n", region_name(region_type), region.size,

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New patch to review for coreboot: 1e798a5 Fix coreboot makefiles not to produce half baked output.
by Stefan Reinauer 06 Mar '12

06 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/750 -gerrit commit 1e798a5792e9838f282128561ef6824785d831a7 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Sat Nov 5 02:07:01 2011 +0000 Fix coreboot makefiles not to produce half baked output. It looks like the cbfstool utility generates the output file even when it fails to generate it properly. This causes make, if started second time in a row, after cbfstool failure, to continue beyond the point of failure (as the corrupted output file is present in the output tree, the second make invocation presumes that it is valid, as it is newer than the dependencies). The output file should be created only when successful, in an atomic operation. There could be other places in the make system which require a similar fix, this needs to be investigated further. Change-Id: I7c17f033ee5937eb712b1a594122430cee5c9146 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/arch/x86/Makefile.inc | 16 +++++++++------- 1 files changed, 9 insertions(+), 7 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index aeb4875..b2b9143 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -58,13 +58,15 @@ extract_nth=$(word $(1), $(subst |, ,$(2))) ifneq ($(CONFIG_UPDATE_IMAGE),y) prebuild-files = \ $(foreach file,$(cbfs-files), \ - $(CBFSTOOL) $@ add $(call extract_nth,1,$(file)) $(call extract_nth,2,$(file)) $(call extract_nth,3,$(file)) $(call extract_nth,4,$(file)); ) + $(CBFSTOOL) $@.tmp add $(call extract_nth,1,$(file)) \ + $(call extract_nth,2,$(file)) $(call extract_nth,3,$(file)) \ + $(call extract_nth,4,$(file)) &&) prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) $(obj)/coreboot.pre1: $(obj)/coreboot.bootblock $$(prebuilt-files) $(CBFSTOOL) - rm -f $@ - $(CBFSTOOL) $@ create $(CONFIG_COREBOOT_ROMSIZE_KB)K $(obj)/coreboot.bootblock - $(prebuild-files) + $(CBFSTOOL) $@.tmp create $(CONFIG_COREBOOT_ROMSIZE_KB)K $(obj)/coreboot.bootblock + $(prebuild-files) true + mv $@.tmp $@ else .PHONY: $(obj)/coreboot.pre1 $(obj)/coreboot.pre1: $(CBFSTOOL) @@ -269,10 +271,10 @@ endif $(obj)/coreboot.pre: $(obj)/coreboot.romstage $(obj)/coreboot.pre1 $(CBFSTOOL) @printf " CBFS $(subst $(obj)/,,$(@))\n" - rm -f $@ - cp $(obj)/coreboot.pre1 $@ - $(CBFSTOOL) $@ add-stage $(obj)/romstage.elf \ + cp $(obj)/coreboot.pre1 $@.tmp + $(CBFSTOOL) $@.tmp add-stage $(obj)/romstage.elf \ $(CONFIG_CBFS_PREFIX)/romstage x 0x$(shell cat $(obj)/location.txt) + mv $@.tmp $@ #FIXME: location.txt might require an offset of header size #######################################################################

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New patch to review for coreboot: e1a7cc5 Add more timestamps in coreboot.
by Stefan Reinauer 06 Mar '12

06 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/749 -gerrit commit e1a7cc59d1dd5642d4fa83d5cbe4fe18194310d3 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Nov 4 12:31:58 2011 -0700 Add more timestamps in coreboot. This adds a number of timestamps in ramstage and romstage so we can figure out where execution time goes. Change-Id: Iea17c08774e623fc1ca3fa4505b70523ba4cbf01 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/lib/cbfs_and_run.c | 3 +++ src/boot/hardwaremain.c | 21 +++++++++++++++++++++ src/include/timestamp.h | 22 ++++++++++++++++++++-- 3 files changed, 44 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/lib/cbfs_and_run.c b/src/arch/x86/lib/cbfs_and_run.c index ad36ddc..53f06ee 100644 --- a/src/arch/x86/lib/cbfs_and_run.c +++ b/src/arch/x86/lib/cbfs_and_run.c @@ -20,16 +20,19 @@ #include <console/console.h> #include <cbfs.h> #include <arch/stages.h> +#include <timestamp.h> static void cbfs_and_run_core(const char *filename, unsigned ebp) { u8 *dst; + timestamp_add_now(TS_START_COPYRAM); print_debug("Loading image.\n"); dst = cbfs_load_stage(filename); if ((void *)dst == (void *) -1) die("FATAL: Essential component is missing.\n"); + timestamp_add_now(TS_END_COPYRAM); print_debug("Jumping to image.\n"); __asm__ volatile ( "movl %%eax, %%ebp\n" diff --git a/src/boot/hardwaremain.c b/src/boot/hardwaremain.c index 9b293c0..489caa3 100644 --- a/src/boot/hardwaremain.c +++ b/src/boot/hardwaremain.c @@ -41,6 +41,7 @@ it with the version available from LANL. #if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> #endif +#include <timestamp.h> /** * @brief Main function of the RAM part of coreboot. @@ -56,7 +57,9 @@ void hardwaremain(int boot_complete); void hardwaremain(int boot_complete) { struct lb_memory *lb_mem; + tsc_t timestamps[6]; + timestamps[0] = rdtsc(); post_code(POST_ENTRY_RAMSTAGE); /* console_init() MUST PRECEDE ALL printk()! */ @@ -78,18 +81,26 @@ void hardwaremain(int boot_complete) /* FIXME: Is there a better way to handle this? */ init_timer(); + timestamps[1] = rdtsc(); /* Find the devices we don't have hard coded knowledge about. */ dev_enumerate(); post_code(POST_DEVICE_ENUMERATION_COMPLETE); + + timestamps[2] = rdtsc(); /* Now compute and assign the bus resources. */ dev_configure(); post_code(POST_DEVICE_CONFIGURATION_COMPLETE); + + timestamps[3] = rdtsc(); /* Now actually enable devices on the bus */ dev_enable(); + + timestamps[4] = rdtsc(); /* And of course initialize devices on the bus */ dev_initialize(); post_code(POST_DEVICES_ENABLED); + timestamps[5] = rdtsc(); #if CONFIG_WRITE_HIGH_TABLES == 1 cbmem_initialize(); #if CONFIG_CONSOLE_CBMEM @@ -101,10 +112,20 @@ void hardwaremain(int boot_complete) post_code(0x8a); #endif + timestamp_add(TS_START_RAMSTAGE, timestamps[0]); + timestamp_add(TS_DEVICE_ENUMERATE, timestamps[1]); + timestamp_add(TS_DEVICE_CONFIGURE, timestamps[2]); + timestamp_add(TS_DEVICE_ENABLE, timestamps[3]); + timestamp_add(TS_DEVICE_INITIALIZE, timestamps[4]); + timestamp_add(TS_DEVICE_DONE, timestamps[5]); + timestamp_add_now(TS_WRITE_TABLES); + /* Now that we have collected all of our information * write our configuration tables. */ lb_mem = write_tables(); + + timestamp_add_now(TS_LOAD_PAYLOAD); cbfs_load_payload(lb_mem, CONFIG_CBFS_PREFIX "/payload"); printk(BIOS_ERR, "Boot failed.\n"); } diff --git a/src/include/timestamp.h b/src/include/timestamp.h index 8b9a89a..0bb323c 100644 --- a/src/include/timestamp.h +++ b/src/include/timestamp.h @@ -35,14 +35,32 @@ struct timestamp_table { } __attribute__((packed)); enum timestamp_id { - TS_BEFORE_INITRAM = 1, - TS_AFTER_INITRAM = 2, + TS_START_ROMSTAGE = 1, + TS_BEFORE_INITRAM = 2, + TS_AFTER_INITRAM = 3, + TS_END_ROMSTAGE = 4, + TS_START_COPYRAM = 8, + TS_END_COPYRAM = 9, + TS_START_RAMSTAGE = 10, + TS_DEVICE_ENUMERATE = 30, + TS_DEVICE_CONFIGURE = 40, + TS_DEVICE_ENABLE = 50, + TS_DEVICE_INITIALIZE = 60, + TS_DEVICE_DONE = 70, + TS_WRITE_TABLES = 80, + TS_LOAD_PAYLOAD = 90, TS_ACPI_WAKE_JUMP = 98, TS_SELFBOOT_JUMP = 99, }; +#if CONFIG_COLLECT_TIMESTAMPS void timestamp_init(tsc_t base); void timestamp_add(enum timestamp_id id, tsc_t ts_time); void timestamp_add_now(enum timestamp_id id); +#else +#define timestamp_init(base) +#define timestamp_add(id, time) +#define timestamp_add_now(id) +#endif #endif

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Patch merged into coreboot/master: 7c48e07 Revert "Use -mno-sse to prevent overzealous gcc optimizations"
by gerrit＠coreboot.org 06 Mar '12

06 Mar '12

the following patch was just integrated into master: commit 7c48e07a261eafda2119354d282bd05eac5a14b6 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Mar 3 10:46:26 2012 +0100 Revert "Use -mno-sse to prevent overzealous gcc optimizations" AGESA uses SSE intrinsics :-( This reverts commit 05f4b03fb64999ba373fe61256f358e5371bf8ae Build-Tested: build bot (Jenkins) at Tue Mar 6 22:24:46 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue Mar 6 21:50:48 2012, giving +2 See http://review.coreboot.org/706 for details. -gerrit

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Patch set updated for coreboot: 73392a7 xcompile: Tell gcc to use i486-class instructions
by Patrick Georgi 06 Mar '12

06 Mar '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/748 -gerrit commit 73392a7c2993a6c4dcf47cb2ae8118e89ef3b5d1 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Tue Mar 6 21:13:47 2012 +0100 xcompile: Tell gcc to use i486-class instructions Instead of hardcoding "no-sse" (which disables various intrinsics) xcompile now tests for -march=i486, which tells gcc to restrict itself to i486 class instructions (but allows the developer to override it by using intrinsics and asm). Change-Id: Ief4a6faba236f215e7dc23872cd7e4ee405a33d2 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- util/xcompile/xcompile | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index f5d43d0..d4eaab0 100644 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -87,7 +87,7 @@ testcc "$CC" "$CFLAGS-Wno-unused-but-set-variable " && \ # Use bfd linker instead of gold if available: testcc "$CC" "$CFLAGS-fuse-ld=bfd " && CFLAGS="$CFLAGS-fuse-ld=bfd " && LINKER_SUFFIX='.bfd' # Prevent SSE instructions sneaking in: -testcc "$CC" "$CFLAGS-mno-sse " && CFLAGS="$CFLAGS-mno-sse " +testcc "$CC" "$CFLAGS-march=i486 " && CFLAGS="$CFLAGS-march=i486 " if which gcc 2>/dev/null >/dev/null; then HOSTCC=gcc

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New patch to review for coreboot: 3adfa8c xcompile: Tell gcc to use pentium-class instructions
by Patrick Georgi 06 Mar '12

06 Mar '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/748 -gerrit commit 3adfa8caa49ad8f072767076725fceb4b4dfa969 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Tue Mar 6 21:13:47 2012 +0100 xcompile: Tell gcc to use pentium-class instructions Instead of hardcoding "no-sse" (which disables various intrinsics) xcompile now tests for -march=pentium, which tells gcc to restrict itself to pentium class instructions (but allows the developer to override it by using intrinsics and asm). Change-Id: Ief4a6faba236f215e7dc23872cd7e4ee405a33d2 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- util/xcompile/xcompile | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index f5d43d0..3c82eea 100644 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -87,7 +87,7 @@ testcc "$CC" "$CFLAGS-Wno-unused-but-set-variable " && \ # Use bfd linker instead of gold if available: testcc "$CC" "$CFLAGS-fuse-ld=bfd " && CFLAGS="$CFLAGS-fuse-ld=bfd " && LINKER_SUFFIX='.bfd' # Prevent SSE instructions sneaking in: -testcc "$CC" "$CFLAGS-mno-sse " && CFLAGS="$CFLAGS-mno-sse " +testcc "$CC" "$CFLAGS-march=pentium " && CFLAGS="$CFLAGS-march=pentium " if which gcc 2>/dev/null >/dev/null; then HOSTCC=gcc

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coreboot March 2012