coreboot March 2012

coreboot@coreboot.org

58 participants
718 discussions

New patch to review for coreboot: eeec1ae Revamp cbmem.py to use the coreboot tables.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/762 -gerrit commit eeec1aec41c3bc12baa1a00039c9197e352a2674 Author: Gabe Black <gabeblack(a)google.com> Date: Sat Jan 7 01:03:42 2012 -0800 Revamp cbmem.py to use the coreboot tables. This change makes significant changes to cbmem.py to make it use the coreboot tables to find the memory console and timestamp areas instead of looking for the in memory table TOC structure. That appears to be more robust and gets cbmem.py working again after some unrelated changes that affected memory layout. It also introduces some small infrastructure to make accessing C style structures in physical memory easier and more transparent. Change-Id: I51833055a50c2d76423520ba6e059bf8fc50adea Signed-off-by: Gabe Black <gabeblack(a)google.com> --- util/cbmem/cbmem.py | 267 ++++++++++++++++++++++++++++++--------------------- 1 files changed, 158 insertions(+), 109 deletions(-) diff --git a/util/cbmem/cbmem.py b/util/cbmem/cbmem.py index 3e8476d..f4f3e88 100755 --- a/util/cbmem/cbmem.py +++ b/util/cbmem/cbmem.py @@ -33,29 +33,46 @@ console sections. ''' import mmap -import re import struct import sys -import time -# These definitions follow src/include/cbmem.h -CBMEM_MAGIC = 0x434f5245 -CBMEM_MAX_ENTRIES = 16 +def get_phys_mem(addr, size): + '''Read size bytes from address addr by mmaping /dev/mem''' -CBMEM_ENTRY_FORMAT = '@LLQQ' -CONSOLE_HEADER_FORMAT = '@LL' -TIMESTAMP_HEADER_FORMAT = '@QLL' -TIMESTAMP_ENTRY_FORMAT = '@LQ' - -mf_fileno = 0 # File number of the file providing access to memory. - -def align_up(base, alignment): - '''Increment to the alignment boundary. - - Return the next integer larger than 'base' and divisible by 'alignment'. - ''' - - return base + alignment - base % alignment + mf = open("/dev/mem") + delta = addr % 4096 + mm = mmap.mmap(mf.fileno(), size + delta, + mmap.MAP_PRIVATE, offset=(addr - delta)) + buf = mm.read(size + delta) + mf.close() + return buf[delta:] + +# This class and metaclass make it easier to define and access structures +# which live in physical memory. To use them, inherit from CStruct and define +# a class member called struct_members which is a tuple of pairs. The first +# item in the pair is the type format specifier that should be used with +# struct.unpack to read that member from memory. The second item is the name +# that member should have in the resulting object. + +class MetaCStruct(type): + def __init__(cls, name, bases, dct): + struct_members = dct["struct_members"] + cls.struct_fmt = "@" + for char, name in struct_members: + cls.struct_fmt += char + cls.struct_len = struct.calcsize(cls.struct_fmt) + super(MetaCStruct, cls).__init__(name, bases, dct) + +class CStruct(object): + __metaclass__ = MetaCStruct + struct_members = () + + def __init__(self, addr): + self.raw_memory = get_phys_mem(addr, self.struct_len) + values = struct.unpack(self.struct_fmt, self.raw_memory) + names = (name for char, name in self.struct_members) + for name, value in zip(names, values): + setattr(self, name, value) def normalize_timer(value, freq): '''Convert timer reading into microseconds. @@ -96,109 +113,141 @@ def get_cpu_freq(): # Convert reading into Hertz return float(freq_str) * 1000.0 -def get_mem_size(): - '''Retrieve amount of memory available to the CPU from /proc/meminfo.''' - mult = { - 'kB': 1024 - } - meminfo = open('/proc/meminfo').read() - m = re.search('MemTotal:.*\n', meminfo) - mem_string = re.search('MemTotal:.*\n', meminfo).group(0) - (_, size, mult_name) = mem_string.split() - return int(size) * mult[mult_name] - -def parse_mem_at(addr, format): - '''Read and parse a memory location. - - This function reads memory at the passed in address, parses it according - to the passed in format specification and returns a list of values. - - The first value in the list is the size of data matching the format - expression, and the rest of the elements of the list are the actual values - retrieved using the format. - ''' - - size = struct.calcsize(format) - delta = addr % 4096 # mmap requires the offset to be page size aligned. - mm = mmap.mmap(mf_fileno, size + delta, - mmap.MAP_PRIVATE, offset=(addr - delta)) - buf = mm.read(size + delta) - mm.close() - rv = [size,] + list(struct.unpack(format, buf[delta:size + delta + 1])) - return rv - -def dprint(text): - '''Debug print function. - - Edit it to get the debug output. - ''' - - if False: - print text - def process_timers(base): '''Scan the array of timestamps found in CBMEM at address base. For each timestamp print the timer ID and the value in microseconds. ''' - (step, base_time, max_entr, entr) = parse_mem_at( - base, TIMESTAMP_HEADER_FORMAT) - - print('\ntime base %d, total entries %d' % (base_time, entr)) + class TimestampHeader(CStruct): + struct_members = ( + ("Q", "base_time"), + ("L", "max_entr"), + ("L", "entr") + ) + + class TimestampEntry(CStruct): + struct_members = ( + ("L", "timer_id"), + ("Q", "timer_value") + ) + + header = TimestampHeader(base) + print('\ntime base %d, total entries %d' % (header.base_time, header.entr)) clock_freq = get_cpu_freq() - base = base + step - for i in range(entr): - (step, timer_id, timer_value) = parse_mem_at( - base, TIMESTAMP_ENTRY_FORMAT) - print '%d:%s ' % (timer_id, normalize_timer(timer_value, clock_freq)), - base = base + step + base = base + header.struct_len + for i in range(header.entr): + timestamp = TimestampEntry(base) + print '%d:%s ' % (timestamp.timer_id, + normalize_timer(timestamp.timer_value, clock_freq)), + base = base + timestamp.struct_len print def process_console(base): '''Dump the console log buffer contents found at address base.''' - (step, size, cursor) = parse_mem_at(base, CONSOLE_HEADER_FORMAT) - print 'cursor at %d\n' % cursor + class ConsoleHeader(CStruct): + struct_members = ( + ("L", "size"), + ("L", "cursor") + ) - cons_string_format = '%ds' % min(cursor, size) - (_, cons_text) = parse_mem_at(base + step, cons_string_format) + header = ConsoleHeader(base) + print 'cursor at %d\n' % header.cursor + + cons_addr = base + header.struct_len + cons_length = min(header.cursor, header.size) + cons_text = get_phys_mem(cons_addr, cons_length) print cons_text print '\n' -mem_alignment = 1024 * 1024 * 1024 # 1 GBytes -table_alignment = 128 * 1024 - -mem_size = get_mem_size() - -# start at memory address aligned at 128K. -offset = align_up(mem_size, table_alignment) - -dprint('mem_size %x offset %x' %(mem_size, offset)) -mf = open("/dev/mem") -mf_fileno = mf.fileno() - -while offset % mem_alignment: # do not cross the 1G boundary while searching - (step, magic, mid, base, size) = parse_mem_at(offset, CBMEM_ENTRY_FORMAT) - if magic == CBMEM_MAGIC: - offset = offset + step - break - offset += table_alignment -else: - print 'Did not find the CBMEM' - sys.exit(0) - -for i in (range(1, CBMEM_MAX_ENTRIES)): - (_, magic, mid, base, size) = parse_mem_at(offset, CBMEM_ENTRY_FORMAT) - if mid == 0: - break - - print '%x, %x, %x' % (mid, base, size) - if mid == 0x54494d45: - process_timers(base) - if mid == 0x434f4e53: - process_console(base) - - offset = offset + step - -mf.close() +def ipchksum(buf): + '''Checksumming function used on the coreboot tables. The buffer being + checksummed is summed up as if it was an array of 16 bit unsigned + integers. If there are an odd number of bytes, the last element is zero + extended.''' + + size = len(buf) + odd = size % 2 + fmt = "<%dH" % ((size - odd) / 2) + if odd: + fmt += "B" + shorts = struct.unpack(fmt, buf) + checksum = sum(shorts) + checksum = (checksum >> 16) + (checksum & 0xffff) + checksum += (checksum >> 16) + checksum = ~checksum & 0xffff + return checksum + +def parse_tables(base, length): + '''Find the coreboot tables in memory and process whatever we can.''' + + class CBTableHeader(CStruct): + struct_members = ( + ("4s", "signature"), + ("I", "header_bytes"), + ("I", "header_checksum"), + ("I", "table_bytes"), + ("I", "table_checksum"), + ("I", "table_entries") + ) + + class CBTableEntry(CStruct): + struct_members = ( + ("I", "tag"), + ("I", "size") + ) + + class CBTableForward(CBTableEntry): + struct_members = CBTableEntry.struct_members + ( + ("Q", "forward"), + ) + + class CBMemTab(CBTableEntry): + struct_members = CBTableEntry.struct_members + ( + ("L", "cbmem_tab"), + ) + + for addr in range(base, base + length, 16): + header = CBTableHeader(addr) + if header.signature == "LBIO": + break + else: + return -1 + + if header.header_bytes == 0: + return -1 + + if ipchksum(header.raw_memory) != 0: + print "Bad header checksum" + return -1 + + addr += header.header_bytes + table = get_phys_mem(addr, header.table_bytes) + if ipchksum(table) != header.table_checksum: + print "Bad table checksum" + return -1 + + for i in range(header.table_entries): + entry = CBTableEntry(addr) + if entry.tag == 0x11: # Forwarding entry + return parse_tables(CBTableForward(addr).forward, length) + elif entry.tag == 0x16: # Timestamps + process_timers(CBMemTab(addr).cbmem_tab) + elif entry.tag == 0x17: # CBMEM console + process_console(CBMemTab(addr).cbmem_tab) + + addr += entry.size + + return 0 + +def main(): + for base, length in (0x00000000, 0x1000), (0x000f0000, 0x1000): + if parse_tables(base, length): + break + else: + print "Didn't find the coreboot tables" + return 0 + +if __name__ == "__main__": + sys.exit(main())

1 0

New patch to review for coreboot: 0ccdd00 MTRR: add alternate allocation method for odd memory maps With >= 4GB memory installed we get a memory map split in the middle due to remap that has boundaries that are inconveniently aligned for MTRRs due to the various UMA regions.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/761 -gerrit commit 0ccdd0053d3704f7039097ed629ef5602748816c Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Dec 22 10:59:40 2011 -0800 MTRR: add alternate allocation method for odd memory maps With >= 4GB memory installed we get a memory map split in the middle due to remap that has boundaries that are inconveniently aligned for MTRRs due to the various UMA regions. 0000MB-2780MB 2780MB RAM (writeback) 2780MB-2782MB 2MB TSEG (uncached/SMRR) 2782MB-2784MB 2MB GFX GTT (uncached) 2784MB-2816MB 32MB GFX UMA (uncached) 2816MB-4096MB 1280MB EMPTY (N/A) 4096MB-5368MB 1272MB RAM (writeback) 5368MB-5376MB 8MB ME UMA (uncached) The default MTRR allocation method of trying to cover everything with one MTRR and then carve out a single uncached region does not work for the GPU aperture which needs write-combining type, and it also has issues trying to cover the uneven boundaries in the avaiable variable MTRRs. My goal was to make a minimal set of changes and avoid modifying behavior on existing systems with an algorithm that is not always optimal for a typical memory layout. So the flag 'above4gb=2' will change these allocation behaviors: 1) Detect the number of available variable MTRRs rather than limiting to hardcoded value. We need every last MTRR. 2) Don't try to cover all RAM with one MTRR, instead let each RAM region get covered independently. 3) Don't assume uma_memory_base is part of the last region and increase the size of that region. In this case the UMA region is carved out from the lower memory region and it is already declared as part of the ram region. 4) If a memory region can't be covered with MTRRs >= 16MB then instead make a larger region and trim it with uncached MTRRs. Change-Id: I5a60a44ab6d3ae2f46ea6ffa9e3677aaad2485eb Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/cpu/x86/mtrr/mtrr.c | 52 ++++++++++++++++++++++++++++++++++++++++------ 1 files changed, 45 insertions(+), 7 deletions(-) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 9015ad4..8dccfef 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -179,6 +179,18 @@ static inline unsigned int fls(unsigned int x) #endif #define MTRRS (BIOS_MTRRS + OS_MTRRS) +static int total_mtrrs = MTRRS; +static int bios_mtrrs = BIOS_MTRRS; + +static void detect_var_mtrrs(void) +{ + msr_t msr; + + msr = rdmsr(MTRRcap_MSR); + + total_mtrrs = msr.lo & 0xff; + bios_mtrrs = total_mtrrs - 2; +} static void set_fixed_mtrrs(unsigned int first, unsigned int last, unsigned char type) { @@ -235,6 +247,8 @@ static unsigned int range_to_mtrr(unsigned int reg, unsigned long next_range_startk, unsigned char type, unsigned int address_bits, unsigned int above4gb) { + unsigned long hole_startk = 0, hole_sizek = 0; + if (!range_sizek) { /* If there's no MTRR hole, this function will bail out * here when called for the hole. @@ -243,7 +257,7 @@ static unsigned int range_to_mtrr(unsigned int reg, return reg; } - if (reg >= BIOS_MTRRS) { + if (reg >= bios_mtrrs) { printk(BIOS_ERR, "Warning: Out of MTRRs for base: %4ldMB, range: %ldMB, type %s\n", range_startk >>10, range_sizek >> 10, (type==MTRR_TYPE_UNCACHEABLE)?"UC": @@ -251,6 +265,16 @@ static unsigned int range_to_mtrr(unsigned int reg, return reg; } + if (above4gb == 2 && type == MTRR_TYPE_WRBACK && range_sizek % 0x4000) { + /* + * If this range is not divisible by 16MB then instead + * make a larger range and carve out an uncached hole. + */ + hole_startk = range_startk + range_sizek; + hole_sizek = 0x4000 - (range_sizek % 0x4000); + range_sizek += hole_sizek; + } + while(range_sizek) { unsigned long max_align, align; unsigned long sizek; @@ -274,11 +298,20 @@ static unsigned int range_to_mtrr(unsigned int reg, set_var_mtrr(reg++, range_startk, sizek, type, address_bits); range_startk += sizek; range_sizek -= sizek; - if (reg >= BIOS_MTRRS) { + if (reg >= bios_mtrrs) { printk(BIOS_ERR, "Running out of variable MTRRs!\n"); break; } } + + if (hole_sizek) { + printk(BIOS_DEBUG, "Adding hole at %ldMB-%ldMB\n", + hole_startk, hole_startk + hole_sizek); + reg = range_to_mtrr(reg, hole_startk, hole_sizek, + next_range_startk, MTRR_TYPE_UNCACHEABLE, + address_bits, above4gb); + } + return reg; } @@ -325,7 +358,7 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res) { struct var_mtrr_state *state = gp; unsigned long basek, sizek; - if (state->reg >= BIOS_MTRRS) + if (state->reg >= bios_mtrrs) return; basek = resk(res->base); sizek = resk(res->size); @@ -341,7 +374,7 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res) /* Write the range mtrrs */ if (state->range_sizek != 0) { #if CONFIG_VAR_MTRR_HOLE - if (state->hole_sizek == 0) { + if (state->hole_sizek == 0 && state->above4gb != 2) { /* We need to put that on to hole */ unsigned long endk = basek + sizek; state->hole_startk = state->range_startk + state->range_sizek; @@ -424,6 +457,10 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) var_state.address_bits = address_bits; var_state.above4gb = above4gb; + /* Detect number of variable MTRRs */ + if (above4gb == 2) + detect_var_mtrrs(); + search_global_resources( IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, set_var_mtrr_resource, &var_state); @@ -435,7 +472,8 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) } else { #if CONFIG_VAR_MTRR_HOLE // Increase the base range and set up UMA as an UC hole instead - var_state.range_sizek += (uma_memory_size >> 10); + if (above4gb != 2) + var_state.range_sizek += (uma_memory_size >> 10); var_state.hole_startk = (uma_memory_base >> 10); var_state.hole_sizek = (uma_memory_size >> 10); @@ -454,7 +492,7 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) printk(BIOS_DEBUG, "DONE variable MTRRs\n"); printk(BIOS_DEBUG, "Clear out the extra MTRR's\n"); /* Clear out the extra MTRR's */ - while(var_state.reg < MTRRS) { + while(var_state.reg < total_mtrrs) { set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits); } @@ -463,7 +501,7 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) * complete ROM now that we actually have RAM. */ if (boot_cpu() && (acpi_slp_type != 3)) { - set_var_mtrr(7, (4096-4)*1024, 4*1024, + set_var_mtrr(total_mtrrs-1, (4096-4)*1024, 4*1024, MTRR_TYPE_WRPROT, address_bits); } #endif

1 0

Patch merged into filo/master: ba947af makefile: create directories on demand
by gerrit＠coreboot.org 07 Mar '12

07 Mar '12

the following patch was just integrated into master: commit ba947af8efc8d7d5b403150ed16a8c61cdd9750d Author: Mathias Krause <mathias.krause(a)secunet.com> Date: Tue Mar 6 09:31:38 2012 +0100 makefile: create directories on demand Use makefile dependencies to created needed directories instead of trying to recreate them on each make invocation. Change-Id: Ia06b1042f2a2c4905f5c8277a48ec4b8188f3079 Signed-off-by: Mathias Krause <mathias.krause(a)secunet.com> Build-Tested: build bot (Jenkins) at Tue Mar 6 16:47:07 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue Mar 6 21:53:30 2012, giving +2 See http://review.coreboot.org/742 for details. -gerrit

1 0

Patch merged into filo/master: df119be makefile: rebuild config.h when needed
by gerrit＠coreboot.org 07 Mar '12

07 Mar '12

the following patch was just integrated into master: commit df119bed3bad665af86209cb41111ccc8754f2f6 Author: Mathias Krause <mathias.krause(a)secunet.com> Date: Tue Mar 6 09:16:29 2012 +0100 makefile: rebuild config.h when needed The dependencies for filo are quite awkward. Fix this by moving them where they belong to be, namely: * object files (not filo) depend on config.h * config.h (not filo) depends on .config to fix build problems when build/ gets removed or .config gets manually edited Change-Id: Ic107ad4d37cb6ce128ee3ad62cb8d271b457f91a Signed-off-by: Mathias Krause <mathias.krause(a)secunet.com> Build-Tested: build bot (Jenkins) at Tue Mar 6 16:45:39 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue Mar 6 21:53:10 2012, giving +2 See http://review.coreboot.org/741 for details. -gerrit

1 0

Patch merged into filo/master: f1f9d46 makefile: don't evaluate empty input
by gerrit＠coreboot.org 07 Mar '12

07 Mar '12

the following patch was just integrated into master: commit f1f9d467747176421a793ed0302730ee4b6a4bd2 Author: Mathias Krause <mathias.krause(a)secunet.com> Date: Mon Mar 5 11:23:24 2012 +0100 makefile: don't evaluate empty input The output from util/xcompile/xcompile is redirected, so there is nothing left for make to $(eval)uate. Change-Id: I0f482c4b680ca3eded4664c0a57e8525c068feaf Signed-off-by: Mathias Krause <mathias.krause(a)secunet.com> Build-Tested: build bot (Jenkins) at Tue Mar 6 16:44:14 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue Mar 6 21:52:45 2012, giving +2 See http://review.coreboot.org/740 for details. -gerrit

1 0

New patch to review for coreboot: c40f6dd drop use of MAX_PHYSICAL_CPUS and MAX_CPUS where not needed
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/760 -gerrit commit c40f6dde3b7c1cdcd18f223fceeb39c05b8e2b73 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Dec 15 09:24:40 2011 -0800 drop use of MAX_PHYSICAL_CPUS and MAX_CPUS where not needed Change-Id: Idf875ddec417e627f1e72a6d834860e7fd324a50 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/x86/lapic/lapic_cpu_init.c | 6 ------ src/cpu/x86/pae/Makefile.inc | 2 +- 2 files changed, 1 insertions(+), 7 deletions(-) diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index fc22ea4..99c3c4e 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -363,9 +363,7 @@ void secondary_cpu_init(void) { atomic_inc(&active_cpus); #if CONFIG_SERIAL_CPU_INIT == 1 - #if CONFIG_MAX_CPUS>2 spin_lock(&start_cpu_lock); - #endif #endif #ifdef __SSE3__ @@ -380,9 +378,7 @@ void secondary_cpu_init(void) #endif cpu_initialize(); #if CONFIG_SERIAL_CPU_INIT == 1 - #if CONFIG_MAX_CPUS>2 spin_unlock(&start_cpu_lock); - #endif #endif atomic_dec(&active_cpus); @@ -419,9 +415,7 @@ static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu) cpu->path.apic.apic_id); } #if CONFIG_SERIAL_CPU_INIT == 1 - #if CONFIG_MAX_CPUS>2 udelay(10); - #endif #endif } diff --git a/src/cpu/x86/pae/Makefile.inc b/src/cpu/x86/pae/Makefile.inc index 0ecec47..060720c 100644 --- a/src/cpu/x86/pae/Makefile.inc +++ b/src/cpu/x86/pae/Makefile.inc @@ -1 +1 @@ -ramstage-y += pgtbl.c +ramstage-$(CONFIG_CPU_AMD_MODEL_FXX) += pgtbl.c

1 0

New patch to review for coreboot: 4a17211 Fix romcc to compile cleanly
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/759 -gerrit commit 4a17211d7305877119606e9cbef9239830ec031d Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Dec 6 22:14:57 2011 +0000 Fix romcc to compile cleanly There have been many unused variable assignments in the romcc source file. They cause multiple warning messages during build process which in turn make it harder to see the actual error message, when they are present. The fix is to remove dead code and to add -Werror to romcc compilation to avoid issues like this creeping in in the future. Change-Id: I6f42684f39a4135b0fe64219b8c7f058275c9fee Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- util/romcc/Makefile | 2 +- util/romcc/romcc.c | 3 +-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/util/romcc/Makefile b/util/romcc/Makefile index 6543fbb..8242eb5 100644 --- a/util/romcc/Makefile +++ b/util/romcc/Makefile @@ -1,7 +1,7 @@ # Move the configuration defines to makefile.conf CC=gcc CPPFLAGS= -CFLAGS= -g -Wall $(CPPFLAGS) +CFLAGS= -g -Wall -Werror $(CPPFLAGS) CPROF_FLAGS=-pg -fprofile-arcs all: romcc test diff --git a/util/romcc/romcc.c b/util/romcc/romcc.c index c7ef223..7eee439 100644 --- a/util/romcc/romcc.c +++ b/util/romcc/romcc.c @@ -9161,8 +9161,7 @@ static void decompose_compound_types(struct compile_state *state) { struct triple *ins, *next, *first; #if DEBUG_DECOMPOSE_HIRES - FILE *fp; - fp = state->dbgout; + FILE *fp = state->dbgout; #endif first = state->first; ins = first;

1 0

New patch to review for coreboot: 973a340 Make PCI CONF2 support a compile time option.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/758 -gerrit commit 973a3407658fd138e1f0d1c243b3525b2b9f9dc3 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Nov 17 13:05:31 2011 -0800 Make PCI CONF2 support a compile time option. It's not used on any board supported by coreboot but has been detected at run time since ages. No new boards (since 2000?) are using the CONF2 method, so it is unlikely we ever have to turn this on for a board. Change-Id: I17df94a8a77b9338fde10a6b114b44d393776e66 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/Kconfig | 4 ++++ src/arch/x86/lib/Makefile.inc | 4 +--- src/arch/x86/lib/pci_ops_auto.c | 9 ++++++++- 3 files changed, 13 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 078ae95..bc01c9c 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -96,4 +96,8 @@ config LITTLE_ENDIAN bool default !BIG_ENDIAN +config PCI_CONF2 + bool + default n + endmenu diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc index 3f4dc95..96fb9b0 100644 --- a/src/arch/x86/lib/Makefile.inc +++ b/src/arch/x86/lib/Makefile.inc @@ -1,10 +1,8 @@ ramstage-y += c_start.S ramstage-y += cpu.c ramstage-y += pci_ops_conf1.c -ramstage-y += pci_ops_conf2.c - +ramstage-$(CONFIG_PCI_CONF2) += pci_ops_conf2.c ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c - ramstage-y += pci_ops_auto.c ramstage-y += exception.c ramstage-$(CONFIG_IOAPIC) += ioapic.c diff --git a/src/arch/x86/lib/pci_ops_auto.c b/src/arch/x86/lib/pci_ops_auto.c index 92eedd3..58e098b 100644 --- a/src/arch/x86/lib/pci_ops_auto.c +++ b/src/arch/x86/lib/pci_ops_auto.c @@ -6,6 +6,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> +#if CONFIG_PCI_CONF2 /* * Before we decide to use direct hardware access mechanisms, we try to do some * trivial checks to ensure it at least _seems_ to be working -- we just test @@ -41,7 +42,7 @@ static int pci_sanity_check(const struct pci_bus_operations *o) return 0; } -struct pci_bus_operations *pci_bus_fallback_ops = NULL; +static struct pci_bus_operations *pci_bus_fallback_ops = NULL; static const struct pci_bus_operations *pci_check_direct(void) { @@ -89,6 +90,12 @@ const struct pci_bus_operations *pci_remember_direct(void) pci_bus_fallback_ops = (struct pci_bus_operations *)pci_check_direct(); return pci_bus_fallback_ops; } +#else +const struct pci_bus_operations *pci_remember_direct(void) +{ + return &pci_cf8_conf1; +} +#endif /** Set the method to be used for PCI, type I or type II */

1 0

New patch to review for coreboot: 35cd061 Add DEBUG_TPM option to Debugging menu
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/757 -gerrit commit 35cd0615e09f887036311b104c218d9743a3501b Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Nov 17 12:50:54 2011 -0800 Add DEBUG_TPM option to Debugging menu instead of having to edit the source code of tpm.c Change-Id: I519d9ada14dd383e668a2da4219e5373a24c7c3d Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/Kconfig | 7 +++++++ src/pc80/tpm.c | 9 +-------- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 26e6dde..41c5dbf 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -870,6 +870,13 @@ config X86EMU_DEBUG_IO If unsure, say N. +config DEBUG_TPM + bool "Output verbose TPM debug messages" + default n + depends on TPM + help + This option enables additional TPM related debug messages. + config LLSHELL bool "Built-in low-level shell" default n diff --git a/src/pc80/tpm.c b/src/pc80/tpm.c index 8e94303..17e1ed7 100644 --- a/src/pc80/tpm.c +++ b/src/pc80/tpm.c @@ -27,7 +27,6 @@ * Infineon slb9635), so this driver provides access to locality 0 only. */ -/* #define DEBUG */ #include <stdlib.h> #include <string.h> #include <delay.h> @@ -37,17 +36,11 @@ #include <pc80/tpm.h> #include <cpu/x86/car.h> -#ifdef DEBUG -#define TPM_DEBUG_ON 1 -#else -#define TPM_DEBUG_ON 0 -#endif - #define PREFIX "lpc_tpm: " /* coreboot wrapper for TPM driver (start) */ #define TPM_DEBUG(fmt, args...) \ - if (TPM_DEBUG_ON) { \ + if (CONFIG_DEBUG_TPM) { \ printk(BIOS_DEBUG, PREFIX); \ printk(BIOS_DEBUG, fmt , ##args); \ }

1 0

New patch to review for coreboot: 075dfb2 Don't unconditionally add support for cardbus and pci-x devices
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/756 -gerrit commit 075dfb2195058ea398d7b47adb7c0afec0818261 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Nov 30 12:45:14 2011 -0800 Don't unconditionally add support for cardbus and pci-x devices It's still on by default. Change-Id: I8b6539eaf2f8d6a4fa975deb14789a00f2090d34 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/devices/Makefile.inc | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/devices/Makefile.inc b/src/devices/Makefile.inc index 86b4d21..9ffc0bb 100644 --- a/src/devices/Makefile.inc +++ b/src/devices/Makefile.inc @@ -3,10 +3,10 @@ ramstage-y += root_device.c ramstage-y += device_util.c ramstage-y += pci_device.c ramstage-$(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT) += hypertransport.c -ramstage-y += pcix_device.c +ramstage-$(CONFIG_PCIX_PLUGIN_SUPPORT) += pcix_device.c ramstage-y += pciexp_device.c -ramstage-y += agp_device.c -ramstage-y += cardbus_device.c +ramstage-$(CONFIG_AGP_PLUGIN_SUPPORT) += agp_device.c +ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += cardbus_device.c ramstage-y += pnp_device.c ramstage-y += pci_ops.c ramstage-y += smbus_ops.c

1 0

← Newer
1
...
60
61
62
63
64
65
66
...
72
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot March 2012