coreboot March 2012

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Patch set updated for coreboot: 38c5140 Make PCI CONF2 support a compile time option.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/758 -gerrit commit 38c51408f7c7568f164b93988dd98fc2fbe86e23 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Nov 17 13:05:31 2011 -0800 Make PCI CONF2 support a compile time option. It's not used on any board supported by coreboot but has been detected at run time since ages. No new boards (since 2000?) are using the CONF2 method, so it is unlikely we ever have to turn this on for a board. Change-Id: I17df94a8a77b9338fde10a6b114b44d393776e66 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/Kconfig | 4 ++++ src/arch/x86/lib/Makefile.inc | 4 +--- src/arch/x86/lib/pci_ops_auto.c | 9 ++++++++- 3 files changed, 13 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 078ae95..bc01c9c 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -96,4 +96,8 @@ config LITTLE_ENDIAN bool default !BIG_ENDIAN +config PCI_CONF2 + bool + default n + endmenu diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc index 3f4dc95..96fb9b0 100644 --- a/src/arch/x86/lib/Makefile.inc +++ b/src/arch/x86/lib/Makefile.inc @@ -1,10 +1,8 @@ ramstage-y += c_start.S ramstage-y += cpu.c ramstage-y += pci_ops_conf1.c -ramstage-y += pci_ops_conf2.c - +ramstage-$(CONFIG_PCI_CONF2) += pci_ops_conf2.c ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c - ramstage-y += pci_ops_auto.c ramstage-y += exception.c ramstage-$(CONFIG_IOAPIC) += ioapic.c diff --git a/src/arch/x86/lib/pci_ops_auto.c b/src/arch/x86/lib/pci_ops_auto.c index 92eedd3..58e098b 100644 --- a/src/arch/x86/lib/pci_ops_auto.c +++ b/src/arch/x86/lib/pci_ops_auto.c @@ -6,6 +6,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> +#if CONFIG_PCI_CONF2 /* * Before we decide to use direct hardware access mechanisms, we try to do some * trivial checks to ensure it at least _seems_ to be working -- we just test @@ -41,7 +42,7 @@ static int pci_sanity_check(const struct pci_bus_operations *o) return 0; } -struct pci_bus_operations *pci_bus_fallback_ops = NULL; +static struct pci_bus_operations *pci_bus_fallback_ops = NULL; static const struct pci_bus_operations *pci_check_direct(void) { @@ -89,6 +90,12 @@ const struct pci_bus_operations *pci_remember_direct(void) pci_bus_fallback_ops = (struct pci_bus_operations *)pci_check_direct(); return pci_bus_fallback_ops; } +#else +const struct pci_bus_operations *pci_remember_direct(void) +{ + return &pci_cf8_conf1; +} +#endif /** Set the method to be used for PCI, type I or type II */

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Patch set updated for coreboot: 93c0132 vga_io.c is not needed unless CONFIG_VGA is set
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/753 -gerrit commit 93c01328938eafd9ef98414da4d709e75af5b6be Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Nov 17 11:13:36 2011 -0800 vga_io.c is not needed unless CONFIG_VGA is set hence disable it. Change-Id: I7b406251a2f3830748140a111f76f2792fe923ed Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/pc80/vga/Makefile.inc | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/pc80/vga/Makefile.inc b/src/pc80/vga/Makefile.inc index 0ca7896..d4b726a 100644 --- a/src/pc80/vga/Makefile.inc +++ b/src/pc80/vga/Makefile.inc @@ -1,4 +1,4 @@ -ramstage-y += vga_io.c +ramstage-$(CONFIG_VGA) += vga_io.c ramstage-$(CONFIG_VGA) += vga_palette.c ramstage-$(CONFIG_VGA) += vga_font_8x16.c ramstage-$(CONFIG_VGA) += vga.c

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Patch set updated for coreboot: d9f5a72 Fix warnings in coreboot utilities.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/752 -gerrit commit d9f5a7240b4f694d94afd64924f167d78a6f6b16 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Nov 14 12:40:34 2011 -0800 Fix warnings in coreboot utilities. Fix some poor programming practice (breaks of strict aliasing as well as not checking the return value of read) Change-Id: I08b2e8d1bbc908f6b1f26d25cb3a4b03d818e124 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- util/inteltool/cpu.c | 6 ++++-- util/inteltool/inteltool.c | 4 +++- util/nvramtool/cli/nvramtool.c | 3 ++- 3 files changed, 9 insertions(+), 4 deletions(-) diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c index 20748bd..3bffa4e 100644 --- a/util/inteltool/cpu.c +++ b/util/inteltool/cpu.c @@ -67,8 +67,10 @@ msr_t rdmsr(int addr) } if (read(fd_msr, buf, 8) == 8) { - msr.lo = *(uint32_t *)buf; - msr.hi = *(uint32_t *)(buf + 4); + msr.lo = buf[0] | (buf[1] << 8) | + (buf[2] << 16) | (buf[3] << 24); + msr.hi = buf[4] | (buf[5] << 8) | + (buf[6] << 16) | (buf[7] << 24); return msr; } diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 6b99605..e5c2b86 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -21,6 +21,7 @@ #include <stdio.h> #include <stdlib.h> +#include <inttypes.h> #include <getopt.h> #include <fcntl.h> #include <sys/mman.h> @@ -99,7 +100,8 @@ void *map_physical(uint64_t phys_addr, size_t len) fd_mem, (off_t) phys_addr); if (virt_addr == MAP_FAILED) { - printf("Error mapping physical memory 0x%08lx[0x%zx]\n", phys_addr, len); + printf("Error mapping physical memory 0x%08" PRIx64 "[0x%zx]\n", + phys_addr, len); return NULL; } diff --git a/util/nvramtool/cli/nvramtool.c b/util/nvramtool/cli/nvramtool.c index 11a1a70..20097b8 100644 --- a/util/nvramtool/cli/nvramtool.c +++ b/util/nvramtool/cli/nvramtool.c @@ -143,7 +143,8 @@ int main(int argc, char *argv[]) if (fd_stat.st_size < 128) { lseek(fd, 127, SEEK_SET); - write(fd, "\0", 1); + if (write(fd, "\0", 1) != 1) + fprintf(stderr, "Write failed.\n"); fsync(fd); }

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Patch set updated for coreboot: d202b26 use movsl for copying resume memory back
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/755 -gerrit commit d202b262c5d0bbc6bb22a9a7550b7f1b285c22f2 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Nov 17 13:03:38 2011 -0800 use movsl for copying resume memory back It's not significantly faster, but easier to read and smaller. Change-Id: Ibab0b478873912d67bf1f07743f628586353368a Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/boot/wakeup.S | 20 ++++---------------- 1 files changed, 4 insertions(+), 16 deletions(-) diff --git a/src/arch/x86/boot/wakeup.S b/src/arch/x86/boot/wakeup.S index a1df4d5..f12b176 100644 --- a/src/arch/x86/boot/wakeup.S +++ b/src/arch/x86/boot/wakeup.S @@ -38,23 +38,11 @@ __wakeup: movw %ax, (__wakeup_segment) /* Then overwrite coreboot with our backed up memory */ - movl 8(%esp), %esi - movl 12(%esp), %edi - movl 16(%esp), %ecx + movl 8(%esp), %esi + movl 12(%esp), %edi + movl 16(%esp), %ecx shrl $4, %ecx -1: - movl 0(%esi),%eax - movl 4(%esi),%edx - movl 8(%esi),%ebx - movl 12(%esi),%ebp - addl $16,%esi - subl $1,%ecx - movl %eax,0(%edi) - movl %edx,4(%edi) - movl %ebx,8(%edi) - movl %ebp,12(%edi) - leal 16(%edi),%edi - jne 1b + rep movsl /* Activate the right segment descriptor real mode. */ ljmp $0x28, $RELOCATED(1f)

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Patch set updated for coreboot: c9ea9ae labels should start at the beginning of the line
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/754 -gerrit commit c9ea9aed220ad8d0580040d1a29353c9b1566349 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Nov 17 12:52:30 2011 -0800 labels should start at the beginning of the line cosmetical fix Change-Id: I60d0fa90656f85ecb8acc357fe6518baa773505b Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/x86/lapic/secondary.S | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/cpu/x86/lapic/secondary.S b/src/cpu/x86/lapic/secondary.S index 5c1e760..dc00b08 100644 --- a/src/cpu/x86/lapic/secondary.S +++ b/src/cpu/x86/lapic/secondary.S @@ -47,7 +47,7 @@ _secondary_start: 1: hlt jmp 1b - gdtaddr: +gdtaddr: .word gdt_limit /* the table limit */ .long gdt /* we know the offset */

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Patch set updated for coreboot: 0077bb7 Make MTRR min hole alignment 64MB
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/765 -gerrit commit 0077bb72e00748699551856abef8645ca1652a67 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jan 9 22:05:18 2012 -0800 Make MTRR min hole alignment 64MB This affects the algorithm when determining when to transform a range into a larger range with a hole. It is needed when for when I switch on an 8MB TSEG and cause the memory maps to go crazy. Also add header defines for the SMRR. Change-Id: I1a06ccc28ef139cc79f655a8b19fd3533aca0401 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/cpu/x86/mtrr/mtrr.c | 9 ++++++--- src/include/cpu/x86/mtrr.h | 3 +++ 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 5f5e02b..ed7d93b 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -265,13 +265,16 @@ static unsigned int range_to_mtrr(unsigned int reg, return reg; } - if (above4gb == 2 && type == MTRR_TYPE_WRBACK && range_sizek % 0x4000) { +#define MIN_ALIGN 0x10000 /* 64MB */ + + if (above4gb == 2 && type == MTRR_TYPE_WRBACK && + range_sizek > MIN_ALIGN && range_sizek % MIN_ALIGN) { /* - * If this range is not divisible by 16MB then instead + * If this range is not divisible then instead * make a larger range and carve out an uncached hole. */ hole_startk = range_startk + range_sizek; - hole_sizek = 0x4000 - (range_sizek % 0x4000); + hole_sizek = MIN_ALIGN - (range_sizek % MIN_ALIGN); range_sizek += hole_sizek; } diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 62cb8b7..8b5cc28 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -17,6 +17,9 @@ #define MTRRdefTypeEn (1 << 11) #define MTRRdefTypeFixEn (1 << 10) +#define SMRRphysBase_MSR 0x1f2 +#define SMRRphysMask_MSR 0x1f3 + #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)

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Patch set updated for coreboot: 0abb86d Make cpuid functions usable when compiled with PIC
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/764 -gerrit commit 0abb86d60d69218872391e96a0587ed145f0ffdc Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jan 9 22:00:30 2012 -0800 Make cpuid functions usable when compiled with PIC This avoids using EBX and instead uses EDI where possible, and ESI when necessary to get the EBX value out. This allows me to enable -fpic for SMM TSEG code. Change-Id: I10dbded3f3ad98a39ba7b53da59af6ca3145e2e5 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/arch/x86/include/arch/cpu.h | 57 ++++++++++++++++++++++++++++++-------- 1 files changed, 45 insertions(+), 12 deletions(-) diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 85357d7..508b7d6 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -36,12 +36,36 @@ static inline struct cpuid_result cpuid(int op) { struct cpuid_result result; asm volatile( - "cpuid" + "mov %%ebx, %%edi;" + "cpuid;" + "mov %%ebx, %%esi;" + "mov %%edi, %%ebx;" : "=a" (result.eax), - "=b" (result.ebx), + "=S" (result.ebx), "=c" (result.ecx), "=d" (result.edx) - : "0" (op)); + : "0" (op) + : "edi"); + return result; +} + +/* + * Generic Extended CPUID function + */ +static inline struct cpuid_result cpuid_ext(int op, unsigned ecx) +{ + struct cpuid_result result; + asm volatile( + "mov %%ebx, %%edi;" + "cpuid;" + "mov %%ebx, %%esi;" + "mov %%edi, %%ebx;" + : "=a" (result.eax), + "=S" (result.ebx), + "=c" (result.ecx), + "=d" (result.edx) + : "0" (op), "2" (ecx) + : "edi"); return result; } @@ -52,10 +76,12 @@ static inline unsigned int cpuid_eax(unsigned int op) { unsigned int eax; - __asm__("cpuid" + __asm__("mov %%ebx, %%edi;" + "cpuid;" + "mov %%edi, %%ebx;" : "=a" (eax) : "0" (op) - : "ebx", "ecx", "edx"); + : "ecx", "edx", "edi"); return eax; } @@ -63,10 +89,13 @@ static inline unsigned int cpuid_ebx(unsigned int op) { unsigned int eax, ebx; - __asm__("cpuid" - : "=a" (eax), "=b" (ebx) + __asm__("mov %%ebx, %%edi;" + "cpuid;" + "mov %%edi, %%ebx;" + "mov %%edi, %%esi;" + : "=a" (eax), "=S" (ebx) : "0" (op) - : "ecx", "edx" ); + : "ecx", "edx", "edi"); return ebx; } @@ -74,10 +103,12 @@ static inline unsigned int cpuid_ecx(unsigned int op) { unsigned int eax, ecx; - __asm__("cpuid" + __asm__("mov %%ebx, %%edi;" + "cpuid;" + "mov %%edi, %%ebx;" : "=a" (eax), "=c" (ecx) : "0" (op) - : "ebx", "edx" ); + : "edx", "edi"); return ecx; } @@ -85,10 +116,12 @@ static inline unsigned int cpuid_edx(unsigned int op) { unsigned int eax, edx; - __asm__("cpuid" + __asm__("mov %%ebx, %%edi;" + "cpuid;" + "mov %%edi, %%ebx;" : "=a" (eax), "=d" (edx) : "0" (op) - : "ebx", "ecx"); + : "ecx", "edi"); return edx; }

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Patch set updated for coreboot: 15113e2 correctly mark code segments as code in SELF
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/767 -gerrit commit 15113e2ebca3657600bd9f682eafae3ba3f26575 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jan 11 12:40:14 2012 -0800 correctly mark code segments as code in SELF In bios_log, find that the first segment of the payload is shown as code rather than data. Change-Id: I82eaad23f08c02f4ed75744affa8835255cf5c17 Sample: Got a payload Loading segment from rom address 0xfff29378 code (compression=1) ... Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- util/cbfstool/cbfs-mkpayload.c | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-) diff --git a/util/cbfstool/cbfs-mkpayload.c b/util/cbfstool/cbfs-mkpayload.c index ff6479d..e4ef5c8 100644 --- a/util/cbfstool/cbfs-mkpayload.c +++ b/util/cbfstool/cbfs-mkpayload.c @@ -161,7 +161,10 @@ int parse_elf_to_payload(unsigned char *input, unsigned char **output, continue; } - segs[segments].type = PAYLOAD_SEGMENT_DATA; + if (phdr[i].p_flags & PF_X) + segs[segments].type = PAYLOAD_SEGMENT_CODE; + else + segs[segments].type = PAYLOAD_SEGMENT_DATA; segs[segments].load_addr = (uint64_t)htonll(phdr[i].p_paddr); segs[segments].mem_len = (uint32_t)htonl(phdr[i].p_memsz); segs[segments].compression = htonl(algo);

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Patch set updated for coreboot: d92bae9 Add Kconfig options to enable TSEG and set a size
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/766 -gerrit commit d92bae997cea9dcba57f7d5416ef8feddb55dd7c Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jan 9 22:11:25 2012 -0800 Add Kconfig options to enable TSEG and set a size Future CPUs will require TSEG use for SMM Change-Id: I1432569ece4371d6e12c997e90d66c175fa54c5c Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/cpu/x86/Kconfig | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index fdbd527..2033a0a 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -42,3 +42,11 @@ config LOGICAL_CPUS config CACHE_ROM bool default n + +config SMM_TSEG + bool + default n + +config SMM_TSEG_SIZE + hex + default 0

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Patch set updated for coreboot: 9059486 MTRR: add alternate allocation method for odd memory maps With >= 4GB memory installed we get a memory map split in the middle due to remap that has boundaries that are inconveniently aligned for MTRRs due to the various UMA regions.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/761 -gerrit commit 9059486ecb849c71626d41d8e4ef7a59d17b4b52 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Dec 22 10:59:40 2011 -0800 MTRR: add alternate allocation method for odd memory maps With >= 4GB memory installed we get a memory map split in the middle due to remap that has boundaries that are inconveniently aligned for MTRRs due to the various UMA regions. 0000MB-2780MB 2780MB RAM (writeback) 2780MB-2782MB 2MB TSEG (uncached/SMRR) 2782MB-2784MB 2MB GFX GTT (uncached) 2784MB-2816MB 32MB GFX UMA (uncached) 2816MB-4096MB 1280MB EMPTY (N/A) 4096MB-5368MB 1272MB RAM (writeback) 5368MB-5376MB 8MB ME UMA (uncached) The default MTRR allocation method of trying to cover everything with one MTRR and then carve out a single uncached region does not work for the GPU aperture which needs write-combining type, and it also has issues trying to cover the uneven boundaries in the avaiable variable MTRRs. My goal was to make a minimal set of changes and avoid modifying behavior on existing systems with an algorithm that is not always optimal for a typical memory layout. So the flag 'above4gb=2' will change these allocation behaviors: 1) Detect the number of available variable MTRRs rather than limiting to hardcoded value. We need every last MTRR. 2) Don't try to cover all RAM with one MTRR, instead let each RAM region get covered independently. 3) Don't assume uma_memory_base is part of the last region and increase the size of that region. In this case the UMA region is carved out from the lower memory region and it is already declared as part of the ram region. 4) If a memory region can't be covered with MTRRs >= 16MB then instead make a larger region and trim it with uncached MTRRs. Change-Id: I5a60a44ab6d3ae2f46ea6ffa9e3677aaad2485eb Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/cpu/x86/mtrr/mtrr.c | 52 ++++++++++++++++++++++++++++++++++++++++------ 1 files changed, 45 insertions(+), 7 deletions(-) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 9015ad4..8dccfef 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -179,6 +179,18 @@ static inline unsigned int fls(unsigned int x) #endif #define MTRRS (BIOS_MTRRS + OS_MTRRS) +static int total_mtrrs = MTRRS; +static int bios_mtrrs = BIOS_MTRRS; + +static void detect_var_mtrrs(void) +{ + msr_t msr; + + msr = rdmsr(MTRRcap_MSR); + + total_mtrrs = msr.lo & 0xff; + bios_mtrrs = total_mtrrs - 2; +} static void set_fixed_mtrrs(unsigned int first, unsigned int last, unsigned char type) { @@ -235,6 +247,8 @@ static unsigned int range_to_mtrr(unsigned int reg, unsigned long next_range_startk, unsigned char type, unsigned int address_bits, unsigned int above4gb) { + unsigned long hole_startk = 0, hole_sizek = 0; + if (!range_sizek) { /* If there's no MTRR hole, this function will bail out * here when called for the hole. @@ -243,7 +257,7 @@ static unsigned int range_to_mtrr(unsigned int reg, return reg; } - if (reg >= BIOS_MTRRS) { + if (reg >= bios_mtrrs) { printk(BIOS_ERR, "Warning: Out of MTRRs for base: %4ldMB, range: %ldMB, type %s\n", range_startk >>10, range_sizek >> 10, (type==MTRR_TYPE_UNCACHEABLE)?"UC": @@ -251,6 +265,16 @@ static unsigned int range_to_mtrr(unsigned int reg, return reg; } + if (above4gb == 2 && type == MTRR_TYPE_WRBACK && range_sizek % 0x4000) { + /* + * If this range is not divisible by 16MB then instead + * make a larger range and carve out an uncached hole. + */ + hole_startk = range_startk + range_sizek; + hole_sizek = 0x4000 - (range_sizek % 0x4000); + range_sizek += hole_sizek; + } + while(range_sizek) { unsigned long max_align, align; unsigned long sizek; @@ -274,11 +298,20 @@ static unsigned int range_to_mtrr(unsigned int reg, set_var_mtrr(reg++, range_startk, sizek, type, address_bits); range_startk += sizek; range_sizek -= sizek; - if (reg >= BIOS_MTRRS) { + if (reg >= bios_mtrrs) { printk(BIOS_ERR, "Running out of variable MTRRs!\n"); break; } } + + if (hole_sizek) { + printk(BIOS_DEBUG, "Adding hole at %ldMB-%ldMB\n", + hole_startk, hole_startk + hole_sizek); + reg = range_to_mtrr(reg, hole_startk, hole_sizek, + next_range_startk, MTRR_TYPE_UNCACHEABLE, + address_bits, above4gb); + } + return reg; } @@ -325,7 +358,7 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res) { struct var_mtrr_state *state = gp; unsigned long basek, sizek; - if (state->reg >= BIOS_MTRRS) + if (state->reg >= bios_mtrrs) return; basek = resk(res->base); sizek = resk(res->size); @@ -341,7 +374,7 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res) /* Write the range mtrrs */ if (state->range_sizek != 0) { #if CONFIG_VAR_MTRR_HOLE - if (state->hole_sizek == 0) { + if (state->hole_sizek == 0 && state->above4gb != 2) { /* We need to put that on to hole */ unsigned long endk = basek + sizek; state->hole_startk = state->range_startk + state->range_sizek; @@ -424,6 +457,10 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) var_state.address_bits = address_bits; var_state.above4gb = above4gb; + /* Detect number of variable MTRRs */ + if (above4gb == 2) + detect_var_mtrrs(); + search_global_resources( IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, set_var_mtrr_resource, &var_state); @@ -435,7 +472,8 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) } else { #if CONFIG_VAR_MTRR_HOLE // Increase the base range and set up UMA as an UC hole instead - var_state.range_sizek += (uma_memory_size >> 10); + if (above4gb != 2) + var_state.range_sizek += (uma_memory_size >> 10); var_state.hole_startk = (uma_memory_base >> 10); var_state.hole_sizek = (uma_memory_size >> 10); @@ -454,7 +492,7 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) printk(BIOS_DEBUG, "DONE variable MTRRs\n"); printk(BIOS_DEBUG, "Clear out the extra MTRR's\n"); /* Clear out the extra MTRR's */ - while(var_state.reg < MTRRS) { + while(var_state.reg < total_mtrrs) { set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits); } @@ -463,7 +501,7 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) * complete ROM now that we actually have RAM. */ if (boot_cpu() && (acpi_slp_type != 3)) { - set_var_mtrr(7, (4096-4)*1024, 4*1024, + set_var_mtrr(total_mtrrs-1, (4096-4)*1024, 4*1024, MTRR_TYPE_WRPROT, address_bits); } #endif

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coreboot March 2012