coreboot March 2012

coreboot@coreboot.org

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Patch set updated for coreboot: 1e073bf Fix typos in src/console/Kconfig
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/726 -gerrit commit 1e073bf8e1fe234169f0700af6d738b46d9d1246 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Oct 4 16:21:17 2011 -0700 Fix typos in src/console/Kconfig - cash -> Cache - make the new size of the cbmem console buffer the default Change-Id: Ia906077257e93622ad56bc54a42f8184ade78b29 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/console/Kconfig | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index fefbe2e..2cfc4db 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -201,7 +201,7 @@ config CONSOLE_CBMEM config CONSOLE_CBMEM_BUFFER_SIZE depends on CONSOLE_CBMEM hex "Room allocated for console output in CBMEM" - default 0xae00 + default 0x10000 help Space allocated for console output storage in CBMEM. The default value (almost 45K or 0xaeoo bytes) is large enough to accommodate @@ -209,7 +209,7 @@ config CONSOLE_CBMEM_BUFFER_SIZE config CONSOLE_CAR_BUFFER_SIZE depends on CONSOLE_CBMEM - hex "Room allocated for console output in cash as RAM" + hex "Room allocated for console output in Cache as RAM" default 0xc00 help Console is used before RAM is initialized. This is the room reserved

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Patch set updated for coreboot: 1121a0d Increase CBMEM to accommodate larger console.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/725 -gerrit commit 1121a0d8314e5d6021c92fa0dd3fccd6d8a0197c Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Oct 4 10:44:16 2011 -0700 Increase CBMEM to accommodate larger console. This change adds 128K to the memory amount set aside for CBMEM in case the CBMEM console is enabled (to keep the CBMEM 128K byte aligned). The console buffer size is being set to 64K, which is enough to accommodate the most verbose coreboot console and u-boot console. Change-Id: If583013dfb210de5028d69577675095c6fe2f3ab Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/include/cbmem.h | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index a19ec5a..6a48dd2 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -21,7 +21,12 @@ #define _CBMEM_H_ /* Reserve 128k for ACPI and other tables */ +#if CONFIG_CONSOLE_CBMEM +#define HIGH_MEMORY_DEF_SIZE ( 256 * 1024 ) +#else #define HIGH_MEMORY_DEF_SIZE ( 128 * 1024 ) +#endif + #ifndef __PRE_RAM__ extern uint64_t high_tables_base, high_tables_size; #endif

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Patch set updated for coreboot: 255707f Refactor publishing CBMEM addresses through coreboot table.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/724 -gerrit commit 255707f46e18ff3d563c95e6fc4f98c7b9c8438d Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Mon Oct 3 14:58:57 2011 -0700 Refactor publishing CBMEM addresses through coreboot table. We need to provide u-boot access to several different CBMEM sections. To do that, a common coreboot table structure is used, just different tags match different coreboot table sections. Also, the code is added to export CBMEM console and MRC cache addresses through the same mechanism. Change-Id: I63adb67093b8b50ee61b0deb0b56ebb2c4856895 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/arch/x86/boot/coreboot_table.c | 59 +++++++++++++++++++++++++++++------- src/include/boot/coreboot_tables.h | 6 ++- 2 files changed, 52 insertions(+), 13 deletions(-) diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c index f189e76..f29481b 100644 --- a/src/arch/x86/boot/coreboot_table.c +++ b/src/arch/x86/boot/coreboot_table.c @@ -175,22 +175,40 @@ static void lb_framebuffer(struct lb_header *header) #endif } -#if CONFIG_COLLECT_TIMESTAMPS -static void lb_tsamp(struct lb_header *header) +static void add_cbmem_pointers(struct lb_header *header) { - struct lb_tstamp *tstamp; - void *tstamp_table = cbmem_find(CBMEM_ID_TIMESTAMP); + /* + * These CBMEM sections' addresses are included in the coreboot table + * with the appropriate tags. + */ + const struct section_id { + int cbmem_id; + int table_tag; + } section_ids[] = { + {CBMEM_ID_TIMESTAMP, LB_TAG_TIMESTAMPS}, + {CBMEM_ID_MRCDATA, LB_TAG_MRC_CACHE}, + {CBMEM_ID_CONSOLE, LB_TAG_CBMEM_CONSOLE} + }; + int i; - if (!tstamp_table) - return; + for (i = 0; i < ARRAY_SIZE(section_ids); i++) { + const struct section_id *sid = section_ids + i; + struct lb_cbmem_ref *cbmem_ref; + void *cbmem_addr = cbmem_find(sid->cbmem_id); - tstamp = (struct lb_tstamp *)lb_new_record(header); - tstamp->tag = LB_TAG_TIMESTAMPS; - tstamp->size = sizeof(*tstamp); - tstamp->tstamp_tab = tstamp_table; + if (!cbmem_addr) + continue; /* This section is not present */ + cbmem_ref = (struct lb_cbmem_ref *)lb_new_record(header); + if (!cbmem_ref) { + printk(BIOS_ERR, "No more room in coreboot table!\n"); + break; + } + cbmem_ref->tag = sid->table_tag; + cbmem_ref->size = sizeof(*cbmem_ref); + cbmem_ref->cbmem_addr = cbmem_addr; + } } -#endif static struct lb_mainboard *lb_mainboard(struct lb_header *header) { @@ -633,9 +651,28 @@ unsigned long write_coreboot_table( /* Record our framebuffer */ lb_framebuffer(head); +<<<<<<< HEAD #if CONFIG_COLLECT_TIMESTAMPS lb_tsamp(head); #endif +======= +#if CONFIG_CHROMEOS + /* Record our GPIO settings (ChromeOS specific) */ + lb_gpios(head); + + /* pass along the VDAT buffer adress */ + lb_vdat(head); +#endif +#if CONFIG_ADD_FDT + /* + * Copy FDT from CBFS into the coreboot table possibly augmenting it + * along the way. + */ + lb_fdt(head, serial); +#endif + add_cbmem_pointers(head); + +>>>>>>> 3fc47a1... Refactor publishing CBMEM addresses through coreboot table. /* Remember where my valid memory ranges are */ return lb_table_fini(head, 1); diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index 46d6489..5535a38 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -196,11 +196,13 @@ struct lb_framebuffer { }; #define LB_TAG_TIMESTAMPS 0x0016 -struct lb_tstamp { +#define LB_TAG_CBMEM_CONSOLE 0x0017 +#define LB_TAG_MRC_CACHE 0x0018 +struct lb_cbmem_ref { uint32_t tag; uint32_t size; - void *tstamp_tab; + void *cbmem_addr; }; /* The following structures are for the cmos definitions table */

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Patch set updated for coreboot: 9c59105 Introduce utility for parsing CBMEM contents.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/723 -gerrit commit 9c591059993e49c5bbb841e8bcf47f2ff3987191 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri Sep 30 14:21:03 2011 -0700 Introduce utility for parsing CBMEM contents. This is a python script which is supposed to run on a target which is controlled by coreboot. The script examines top of memory looking for the CBMEM signature at addresses aligned at 128K boundary. Once the script finds the CBMEM, it iterates through the CBMEM table of contents and parses two entries: the timestamps and the console log. This submission is just a template to build upon to create a utility for displaying CBMEM information while running Linux on the target. BUG=chrome-os-partner:4200 TEST=manual See test description of d81e6b8c8d41f2d6 for test procedure. Change-Id: Id863a8598eaadc2d20d728f9186843e65cbe6f37 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Reviewed-on: https://gerrit-int.chromium.org/5942 Tested-by: Vadim Bendebury <vbendeb(a)google.com> Reviewed-by: Stefan Reinauer <reinauer(a)google.com> --- util/cbmem/cbmem.py | 204 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 204 insertions(+), 0 deletions(-) diff --git a/util/cbmem/cbmem.py b/util/cbmem/cbmem.py new file mode 100755 index 0000000..3e8476d --- /dev/null +++ b/util/cbmem/cbmem.py @@ -0,0 +1,204 @@ +#!/usr/bin/python +# +# cbmem.py - Linux space CBMEM contents parser +# +# Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +''' +Parse and display CBMEM contents. + +This module is meant to run on systems with coreboot based firmware. + +When started, it determines the amount of DRAM installed on the system, and +then scans the top area of DRAM (right above the available memory size) +looking for the CBMEM base signature at locations aligned at 0x20000 +boundaries. + +Once it finds the CBMEM signature, the utility parses the contents, reporting +the section IDs/sizes and also reporting the contents of the tiemstamp and +console sections. +''' + +import mmap +import re +import struct +import sys +import time + +# These definitions follow src/include/cbmem.h +CBMEM_MAGIC = 0x434f5245 +CBMEM_MAX_ENTRIES = 16 + +CBMEM_ENTRY_FORMAT = '@LLQQ' +CONSOLE_HEADER_FORMAT = '@LL' +TIMESTAMP_HEADER_FORMAT = '@QLL' +TIMESTAMP_ENTRY_FORMAT = '@LQ' + +mf_fileno = 0 # File number of the file providing access to memory. + +def align_up(base, alignment): + '''Increment to the alignment boundary. + + Return the next integer larger than 'base' and divisible by 'alignment'. + ''' + + return base + alignment - base % alignment + +def normalize_timer(value, freq): + '''Convert timer reading into microseconds. + + Get the free running clock counter value, divide it by the clock frequency + and multiply by 1 million to get reading in microseconds. + + Then convert the value into an ASCII string with groups of three digits + separated by commas. + + Inputs: + value: int, the clock reading + freq: float, the clock frequency + + Returns: + A string presenting 'value' in microseconds. + ''' + + result = [] + value = int(value * 1000000.0 / freq) + svalue = '%d' % value + vlength = len(svalue) + remainder = vlength % 3 + if remainder: + result.append(svalue[0:remainder]) + while remainder < vlength: + result.append(svalue[remainder:remainder+3]) + remainder = remainder + 3 + return ','.join(result) + +def get_cpu_freq(): + '''Retrieve CPU frequency from sysfs. + + Use /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq as the source. + ''' + freq_str = open('/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq' + ).read() + # Convert reading into Hertz + return float(freq_str) * 1000.0 + +def get_mem_size(): + '''Retrieve amount of memory available to the CPU from /proc/meminfo.''' + mult = { + 'kB': 1024 + } + meminfo = open('/proc/meminfo').read() + m = re.search('MemTotal:.*\n', meminfo) + mem_string = re.search('MemTotal:.*\n', meminfo).group(0) + (_, size, mult_name) = mem_string.split() + return int(size) * mult[mult_name] + +def parse_mem_at(addr, format): + '''Read and parse a memory location. + + This function reads memory at the passed in address, parses it according + to the passed in format specification and returns a list of values. + + The first value in the list is the size of data matching the format + expression, and the rest of the elements of the list are the actual values + retrieved using the format. + ''' + + size = struct.calcsize(format) + delta = addr % 4096 # mmap requires the offset to be page size aligned. + mm = mmap.mmap(mf_fileno, size + delta, + mmap.MAP_PRIVATE, offset=(addr - delta)) + buf = mm.read(size + delta) + mm.close() + rv = [size,] + list(struct.unpack(format, buf[delta:size + delta + 1])) + return rv + +def dprint(text): + '''Debug print function. + + Edit it to get the debug output. + ''' + + if False: + print text + +def process_timers(base): + '''Scan the array of timestamps found in CBMEM at address base. + + For each timestamp print the timer ID and the value in microseconds. + ''' + + (step, base_time, max_entr, entr) = parse_mem_at( + base, TIMESTAMP_HEADER_FORMAT) + + print('\ntime base %d, total entries %d' % (base_time, entr)) + clock_freq = get_cpu_freq() + base = base + step + for i in range(entr): + (step, timer_id, timer_value) = parse_mem_at( + base, TIMESTAMP_ENTRY_FORMAT) + print '%d:%s ' % (timer_id, normalize_timer(timer_value, clock_freq)), + base = base + step + print + +def process_console(base): + '''Dump the console log buffer contents found at address base.''' + + (step, size, cursor) = parse_mem_at(base, CONSOLE_HEADER_FORMAT) + print 'cursor at %d\n' % cursor + + cons_string_format = '%ds' % min(cursor, size) + (_, cons_text) = parse_mem_at(base + step, cons_string_format) + print cons_text + print '\n' + +mem_alignment = 1024 * 1024 * 1024 # 1 GBytes +table_alignment = 128 * 1024 + +mem_size = get_mem_size() + +# start at memory address aligned at 128K. +offset = align_up(mem_size, table_alignment) + +dprint('mem_size %x offset %x' %(mem_size, offset)) +mf = open("/dev/mem") +mf_fileno = mf.fileno() + +while offset % mem_alignment: # do not cross the 1G boundary while searching + (step, magic, mid, base, size) = parse_mem_at(offset, CBMEM_ENTRY_FORMAT) + if magic == CBMEM_MAGIC: + offset = offset + step + break + offset += table_alignment +else: + print 'Did not find the CBMEM' + sys.exit(0) + +for i in (range(1, CBMEM_MAX_ENTRIES)): + (_, magic, mid, base, size) = parse_mem_at(offset, CBMEM_ENTRY_FORMAT) + if mid == 0: + break + + print '%x, %x, %x' % (mid, base, size) + if mid == 0x54494d45: + process_timers(base) + if mid == 0x434f4e53: + process_console(base) + + offset = offset + step + +mf.close()

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Patch set updated for coreboot: 54747a4 CBMEM CONSOLE: Enable coreboot CBMEM console.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/722 -gerrit commit 54747a4361b36a6ea516116f7486ec1c8bd94669 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri Sep 30 12:02:18 2011 -0700 CBMEM CONSOLE: Enable coreboot CBMEM console. The appropriate Makefiles are modified to include the required source code in compilation. Change-Id: I91842b1ba0f89d611d3249b63c020a2713a9124f Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/console/Makefile.inc | 2 ++ src/lib/Makefile.inc | 2 ++ 2 files changed, 4 insertions(+), 0 deletions(-) diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index 4a30918..f3b8758 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -18,6 +18,8 @@ driver-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem_console.c driver-$(CONFIG_USBDEBUG) += usbdebug_console.c driver-$(CONFIG_CONSOLE_LOGBUF) += logbuf_console.c driver-$(CONFIG_CONSOLE_NE2K) += ne2k_console.c +driver-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c + $(obj)/console/console.ramstage.o : $(obj)/build.h $(obj)/console/console.romstage.o : $(obj)/build.h diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index db640dc..45cb788 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -11,6 +11,7 @@ romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c romstage-$(CONFIG_HAVE_ACPI_RESUME) += cbmem.c romstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c +romstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c romstage-$(CONFIG_CONSOLE_NE2K) += compute_ip_checksum.c romstage-$(CONFIG_USBDEBUG) += usbdebug.c @@ -34,6 +35,7 @@ ramstage-y += clog2.c ramstage-y += cbmem.c ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c +ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c ramstage-$(CONFIG_USBDEBUG) += usbdebug.c ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c ramstage-$(CONFIG_TRACE) += trace.c

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Patch set updated for coreboot: 3a3a281 CBMEM CONSOLE: Add code using the new console driver.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/721 -gerrit commit 3a3a28165b4c3e4d7e21326568646e8acefc96ad Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri Sep 30 11:16:49 2011 -0700 CBMEM CONSOLE: Add code using the new console driver. The new added code is compiled in when the CBMEM_CONSOLE config flag is enabled. Change-Id: Ifd1f492ce6321412a014333babbc5b3f14635988 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/arch/x86/lib/romcc_console.c | 3 +++ src/arch/x86/lib/romstage_console.c | 3 +++ src/boot/hardwaremain.c | 3 +++ src/console/console.c | 5 ++++- 4 files changed, 13 insertions(+), 1 deletions(-) diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c index 13ee1f0..0e1f4e6 100644 --- a/src/arch/x86/lib/romcc_console.c +++ b/src/arch/x86/lib/romcc_console.c @@ -46,6 +46,9 @@ static void __console_tx_byte(unsigned char byte) #if CONFIG_CONSOLE_NE2K ne2k_append_data_byte(byte, CONFIG_CONSOLE_NE2K_IO_PORT); #endif +#if CONFIG_CONSOLE_CBMEM + cbmemc_tx_byte(byte); +#endif } static void __console_tx_nibble(unsigned nibble) diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index 8adb3ba..0f22727 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -46,6 +46,9 @@ static void console_tx_byte(unsigned char byte) #if CONFIG_CONSOLE_NE2K ne2k_append_data(&byte, 1, CONFIG_CONSOLE_NE2K_IO_PORT); #endif +#if CONFIG_CONSOLE_CBMEM + cbmemc_tx_byte(byte); +#endif } static void console_tx_flush(void) diff --git a/src/boot/hardwaremain.c b/src/boot/hardwaremain.c index 3d15b55..9b293c0 100644 --- a/src/boot/hardwaremain.c +++ b/src/boot/hardwaremain.c @@ -92,6 +92,9 @@ void hardwaremain(int boot_complete) #if CONFIG_WRITE_HIGH_TABLES == 1 cbmem_initialize(); +#if CONFIG_CONSOLE_CBMEM + cbmemc_reinit(); +#endif #endif #if CONFIG_HAVE_ACPI_RESUME == 1 suspend_resume(); diff --git a/src/console/console.c b/src/console/console.c index d933668..8f60f04 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -87,7 +87,7 @@ int console_tst_byte(void) return 0; } -#else +#else // __PRE_RAM__ ^^^ NOT defined vvv defined void console_init(void) { @@ -104,6 +104,9 @@ void console_init(void) #if CONFIG_CONSOLE_NE2K ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT); #endif +#if CONFIG_CONSOLE_CBMEM + cbmemc_init(); +#endif static const char console_test[] = "\n\ncoreboot-" COREBOOT_VERSION

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Patch set updated for coreboot: 6992fdf CBMEM CONSOLE: Add CBMEM type for console buffer.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/720 -gerrit commit 6992fdf6d151541af2bdf246acf9ccc1d3a6ad45 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri Sep 30 11:13:06 2011 -0700 CBMEM CONSOLE: Add CBMEM type for console buffer. Add CBMEM type for the console buffer section. Change-Id: I02757c06d71e46af77b02b90b0e6018a37b62406 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/include/cbmem.h | 1 + src/lib/cbmem.c | 1 + 2 files changed, 2 insertions(+), 0 deletions(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index c3f10ef..a19ec5a 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -42,6 +42,7 @@ extern uint64_t high_tables_base, high_tables_size; #define CBMEM_ID_RESUME 0x5245534d #define CBMEM_ID_SMBIOS 0x534d4254 #define CBMEM_ID_TIMESTAMP 0x54494d45 +#define CBMEM_ID_CONSOLE 0x434f4e53 #define CBMEM_ID_NONE 0x00000000 int cbmem_initialize(void); diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index f800b04..b09b070 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -256,6 +256,7 @@ void cbmem_list(void) case CBMEM_ID_RESUME: printk(BIOS_DEBUG, "ACPI RESUME"); break; case CBMEM_ID_SMBIOS: printk(BIOS_DEBUG, "SMBIOS "); break; case CBMEM_ID_TIMESTAMP: printk(BIOS_DEBUG, "TIME STAMP "); break; + case CBMEM_ID_CONSOLE: printk(BIOS_DEBUG, "CONSOLE "); break; default: printk(BIOS_DEBUG, "%08x ", cbmem_toc[i].id); } printk(BIOS_DEBUG, "%08llx ", cbmem_toc[i].base);

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Patch set updated for coreboot: 2b1db7b Add support for enabling PCIe Common Clock and ASPM
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/735 -gerrit commit 2b1db7b02a9d12962a396e81dbe2d2828d8525a9 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Oct 25 14:15:11 2011 -0700 Add support for enabling PCIe Common Clock and ASPM These are guarded by individual Kconfig entries. The deprecated CONFIG_PCIE_TUNING defines have been removed in favor of using specific config options. This is the generic half, there is board-specific pieces still to come that tune before and after ASPM is enabled. Change-Id: I3fe46282eada67629e9eeeed07e487dff54f2729 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/devices/Kconfig | 14 +++ src/devices/pciexp_device.c | 188 +++++++++++++++++++++++++++++++++++++++--- src/include/device/pci_def.h | 7 ++ src/include/device/pciexp.h | 7 ++ 4 files changed, 205 insertions(+), 11 deletions(-) diff --git a/src/devices/Kconfig b/src/devices/Kconfig index 98e8d9f..7429bda 100644 --- a/src/devices/Kconfig +++ b/src/devices/Kconfig @@ -163,3 +163,17 @@ config AGP_PLUGIN_SUPPORT config CARDBUS_PLUGIN_SUPPORT bool default y + +config PCIEXP_COMMON_CLOCK + prompt "Enable PCIe Common Clock" + bool + default n + help + Detect and enable Common Clock on PCIe links. + +config PCIEXP_ASPM + prompt "Enable PCIe ASPM" + bool + default n + help + Detect and enable ASPM on PCIe links. diff --git a/src/devices/pciexp_device.c b/src/devices/pciexp_device.c index 5d33942..36f3e6a 100644 --- a/src/devices/pciexp_device.c +++ b/src/devices/pciexp_device.c @@ -19,31 +19,197 @@ */ #include <console/console.h> +#include <delay.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pciexp.h> +#if CONFIG_PCIEXP_COMMON_CLOCK +/* + * Re-train a PCIe link + */ +#define PCIE_TRAIN_RETRY 10000 +static int pciexp_retrain_link(device_t dev, unsigned cap) +{ + unsigned try = PCIE_TRAIN_RETRY; + u16 lnk; + + /* Start link retraining */ + lnk = pci_read_config16(dev, cap + PCI_EXP_LNKCTL); + lnk |= PCI_EXP_LNKCTL_RL; + pci_write_config16(dev, cap + PCI_EXP_LNKCTL, lnk); + + /* Wait for training to complete */ + while (try--) { + lnk = pci_read_config16(dev, cap + PCI_EXP_LNKSTA); + if (!(lnk & PCI_EXP_LNKSTA_LT)) + return 0; + udelay(100); + } + + printk(BIOS_ERR, "%s: Link Retrain timeout\n", dev_path(dev)); + return -1; +} + +/* + * Check the Slot Clock Configuration for root port and endpoint + * and enable Common Clock Configuration if possible. If CCC is + * enabled the link must be retrained. + */ +static void pciexp_enable_common_clock(device_t root, unsigned root_cap, + device_t endp, unsigned endp_cap) +{ + u16 root_scc, endp_scc, lnkctl; + + /* Get Slot Clock Configuration for root port */ + root_scc = pci_read_config16(root, root_cap + PCI_EXP_LNKSTA); + root_scc &= PCI_EXP_LNKSTA_SLC; + + /* Get Slot Clock Configuration for endpoint */ + endp_scc = pci_read_config16(endp, endp_cap + PCI_EXP_LNKSTA); + endp_scc &= PCI_EXP_LNKSTA_SLC; + + /* Enable Common Clock Configuration and retrain */ + if (root_scc && endp_scc) { + printk(BIOS_INFO, "Enabling Common Clock Configuration\n"); + + /* Set in endpoint */ + lnkctl = pci_read_config16(endp, endp_cap + PCI_EXP_LNKCTL); + lnkctl |= PCI_EXP_LNKCTL_CCC; + pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl); + + /* Set in root port */ + lnkctl = pci_read_config16(root, root_cap + PCI_EXP_LNKCTL); + lnkctl |= PCI_EXP_LNKCTL_CCC; + pci_write_config16(root, root_cap + PCI_EXP_LNKCTL, lnkctl); + + /* Retrain link if CCC was enabled */ + pciexp_retrain_link(root, root_cap); + } +} +#endif /* CONFIG_PCIEXP_COMMON_CLOCK */ + +#if CONFIG_PCIEXP_ASPM +/* + * Determine the ASPM L0s or L1 exit latency for a link + * by checking both root port and endpoint and returning + * the highest latency value. + */ +static int pciexp_aspm_latency(device_t root, unsigned root_cap, + device_t endp, unsigned endp_cap, + enum aspm_type type) +{ + int root_lat = 0, endp_lat = 0; + u32 root_lnkcap, endp_lnkcap; + + root_lnkcap = pci_read_config32(root, root_cap + PCI_EXP_LNKCAP); + endp_lnkcap = pci_read_config32(endp, endp_cap + PCI_EXP_LNKCAP); + + /* Make sure the link supports this ASPM type by checking + * capability bits 11:10 with aspm_type offset by 1 */ + if (!(root_lnkcap & (1 << (type + 9))) || + !(endp_lnkcap & (1 << (type + 9)))) + return -1; + + /* Find the one with higher latency */ + switch (type) { + case PCIE_ASPM_L0S: + root_lat = (root_lnkcap & PCI_EXP_LNKCAP_L0SEL) >> 12; + endp_lat = (endp_lnkcap & PCI_EXP_LNKCAP_L0SEL) >> 12; + break; + case PCIE_ASPM_L1: + root_lat = (root_lnkcap & PCI_EXP_LNKCAP_L1EL) >> 15; + endp_lat = (endp_lnkcap & PCI_EXP_LNKCAP_L1EL) >> 15; + break; + default: + return -1; + } + + return (endp_lat > root_lat) ? endp_lat : root_lat; +} + +/* + * Enable ASPM on PCIe root port and endpoint. + * + * Returns APMC value: + * -1 = Error + * 0 = no ASPM + * 1 = L0s Enabled + * 2 = L1 Enabled + * 3 = L0s and L1 Enabled + */ +static enum aspm_type pciexp_enable_aspm(device_t root, unsigned root_cap, + device_t endp, unsigned endp_cap) +{ + const char *aspm_type_str[] = { "None", "L0s", "L1", "L0s and L1" }; + enum aspm_type apmc = PCIE_ASPM_NONE; + int exit_latency, ok_latency; + u16 lnkctl; + u32 devcap; + + /* Get endpoint device capabilities for acceptable limits */ + devcap = pci_read_config32(endp, endp_cap + PCI_EXP_DEVCAP); + + /* Enable L0s if it is within endpoint acceptable limit */ + ok_latency = (devcap & PCI_EXP_DEVCAP_L0S) >> 6; + exit_latency = pciexp_aspm_latency(root, root_cap, endp, endp_cap, + PCIE_ASPM_L0S); + if (exit_latency >= 0 && exit_latency <= ok_latency) + apmc |= PCIE_ASPM_L0S; + + /* Enable L1 if it is within endpoint acceptable limit */ + ok_latency = (devcap & PCI_EXP_DEVCAP_L1) >> 9; + exit_latency = pciexp_aspm_latency(root, root_cap, endp, endp_cap, + PCIE_ASPM_L1); + if (exit_latency >= 0 && exit_latency <= ok_latency) + apmc |= PCIE_ASPM_L1; + + if (apmc != PCIE_ASPM_NONE) { + /* Set APMC in root port first */ + lnkctl = pci_read_config16(root, root_cap + PCI_EXP_LNKCTL); + lnkctl |= apmc; + pci_write_config16(root, root_cap + PCI_EXP_LNKCTL, lnkctl); + + /* Set APMC in endpoint device next */ + lnkctl = pci_read_config16(endp, endp_cap + PCI_EXP_LNKCTL); + lnkctl |= apmc; + pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl); + } + + printk(BIOS_INFO, "ASPM: Enabled %s\n", aspm_type_str[apmc]); + return apmc; +} +#endif /* CONFIG_PCIEXP_ASPM */ + static void pciexp_tune_dev(device_t dev) { - unsigned int cap; -#if CONFIG_PCIE_TUNING - u32 reg32; -#endif + device_t root = dev->bus->dev; + unsigned int root_cap, cap; cap = pci_find_capability(dev, PCI_CAP_ID_PCIE); if (!cap) return; -#if CONFIG_PCIE_TUNING - printk(BIOS_DEBUG, "PCIe: tuning %s\n", dev_path(dev)); + root_cap = pci_find_capability(root, PCI_CAP_ID_PCIE); + if (!root_cap) + return; + +#if CONFIG_PCIEXP_COMMON_CLOCK + /* Check for and enable Common Clock */ + pciexp_enable_common_clock(root, root_cap, dev, cap); +#endif - // TODO make this depending on ASPM. +#if CONFIG_PCIEXP_ASPM + /* Check for and enable ASPM */ + enum aspm_type apmc = pciexp_enable_aspm(root, root_cap, dev, cap); - /* Enable ASPM role based error reporting. */ - reg32 = pci_read_config32(dev, cap + PCI_EXP_DEVCAP); - reg32 |= PCI_EXP_DEVCAP_RBER; - pci_write_config32(dev, cap + PCI_EXP_DEVCAP, reg32); + if (apmc != PCIE_ASPM_NONE) { + /* Enable ASPM role based error reporting. */ + u32 reg32 = pci_read_config32(dev, cap + PCI_EXP_DEVCAP); + reg32 |= PCI_EXP_DEVCAP_RBER; + pci_write_config32(dev, cap + PCI_EXP_DEVCAP, reg32); + } #endif } diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index a5aa3a1..58a7321 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -371,8 +371,15 @@ #define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */ #define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */ #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ +#define PCI_EXP_LNKCAP_ASPMS 0xc00 /* ASPM Support */ +#define PCI_EXP_LNKCAP_L0SEL 0x7000 /* L0s Exit Latency */ +#define PCI_EXP_LNKCAP_L1EL 0x38000 /* L1 Exit Latency */ #define PCI_EXP_LNKCTL 16 /* Link Control */ +#define PCI_EXP_LNKCTL_RL 0x20 /* Retrain Link */ +#define PCI_EXP_LNKCTL_CCC 0x40 /* Common Clock COnfiguration */ #define PCI_EXP_LNKSTA 18 /* Link Status */ +#define PCI_EXP_LNKSTA_LT 0x800 /* Link Training */ +#define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */ #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ #define PCI_EXP_SLTCTL 24 /* Slot Control */ #define PCI_EXP_SLTSTA 26 /* Slot Status */ diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h index 409f211..87a5002 100644 --- a/src/include/device/pciexp.h +++ b/src/include/device/pciexp.h @@ -2,6 +2,13 @@ #define DEVICE_PCIEXP_H /* (c) 2005 Linux Networx GPL see COPYING for details */ +enum aspm_type { + PCIE_ASPM_NONE = 0, + PCIE_ASPM_L0S = 1, + PCIE_ASPM_L1 = 2, + PCIE_ASPM_BOTH = 3, +}; + unsigned int pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, unsigned int max_devfn, unsigned int max); unsigned int pciexp_scan_bridge(device_t dev, unsigned int max);

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Patch set updated for coreboot: 2c1ca17 tell superiotool about the ITE 8772
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/734 -gerrit commit 2c1ca1793b591e9b205259174e72f0658281eab0 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Oct 25 17:12:53 2011 +0000 tell superiotool about the ITE 8772 no dumping yet Change-Id: I4e687ca816c8d6d1c95255b0abf6a19513e23f86 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- util/superiotool/ite.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/util/superiotool/ite.c b/util/superiotool/ite.c index c83d788..e186e10 100644 --- a/util/superiotool/ite.c +++ b/util/superiotool/ite.c @@ -708,6 +708,8 @@ static const struct superio_registers reg_table[] = { {EOT}}}, {0x8761, "IT8761E", { {EOT}}}, + {0x8772, "IT8772F", { + {EOT}}}, {0x8780, "IT8780F", { {EOT}}}, {EOT}

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Patch set updated for coreboot: 395e6db Add timestamps for selfboot and acpi wake
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/733 -gerrit commit 395e6db059da6cbc0048ed9a082fe1906df43c11 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Oct 19 15:32:39 2011 -0700 Add timestamps for selfboot and acpi wake Change-Id: I28224867610b947739d940d25c98399d219f10f4 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/arch/x86/boot/acpi.c | 7 +++++++ src/boot/selfboot.c | 7 +++++++ src/include/timestamp.h | 2 ++ 3 files changed, 16 insertions(+), 0 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index eb2e4e1..d4d554c 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -31,6 +31,9 @@ #include <arch/acpigen.h> #include <device/pci.h> #include <cbmem.h> +#if CONFIG_COLLECT_TIMESTAMPS +#include <timestamp.h> +#endif #if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/chromeos.h> #endif @@ -611,6 +614,10 @@ void acpi_jump_to_wakeup(void *vector) /* Copy wakeup trampoline in place. */ memcpy((void *)WAKEUP_BASE, &__wakeup, (size_t)&__wakeup_size); +#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_ACPI_WAKE_JUMP); +#endif + acpi_do_wakeup((u32)vector, acpi_backup_memory, CONFIG_RAMBASE, HIGH_MEMORY_SAVE); } diff --git a/src/boot/selfboot.c b/src/boot/selfboot.c index bbf160e..d4ab8c8 100644 --- a/src/boot/selfboot.c +++ b/src/boot/selfboot.c @@ -29,6 +29,9 @@ #include <string.h> #include <cbfs.h> #include <lib.h> +#if CONFIG_COLLECT_TIMESTAMPS +#include <timestamp.h> +#endif /* Maximum physical address we can use for the coreboot bounce buffer. */ #ifndef MAX_ADDR @@ -529,6 +532,10 @@ static int selfboot(struct lb_memory *mem, struct cbfs_payload *payload) printk(BIOS_DEBUG, "Jumping to boot code at %x\n", entry); post_code(POST_ENTER_ELF_BOOT); +#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_SELFBOOT_JUMP); +#endif + /* Jump to kernel */ jmp_to_elf_entry((void*)entry, bounce_buffer, bounce_size); return 1; diff --git a/src/include/timestamp.h b/src/include/timestamp.h index cfa06e2..8b9a89a 100644 --- a/src/include/timestamp.h +++ b/src/include/timestamp.h @@ -37,6 +37,8 @@ struct timestamp_table { enum timestamp_id { TS_BEFORE_INITRAM = 1, TS_AFTER_INITRAM = 2, + TS_ACPI_WAKE_JUMP = 98, + TS_SELFBOOT_JUMP = 99, }; void timestamp_init(tsc_t base);

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coreboot March 2012