coreboot March 2012

coreboot@coreboot.org

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Patch set updated for coreboot: 3ce67ca Make TPM driver work in rom stage.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/738 -gerrit commit 3ce67caeb820b0e33cf791ea18d79218d4769318 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Oct 27 21:28:25 2011 +0000 Make TPM driver work in rom stage. Change-Id: Ifc827d0cd0159aa3f6752d395974f2812334f262 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/pc80/tpm.c | 7 ++++--- 1 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/pc80/tpm.c b/src/pc80/tpm.c index 1cbf800..8e94303 100644 --- a/src/pc80/tpm.c +++ b/src/pc80/tpm.c @@ -35,6 +35,7 @@ #include <arch/byteorder.h> #include <console/console.h> #include <pc80/tpm.h> +#include <cpu/x86/car.h> #ifdef DEBUG #define TPM_DEBUG_ON 1 @@ -130,10 +131,10 @@ struct device_name { struct vendor_name { u16 vendor_id; const char * vendor_name; - struct device_name* dev_names; + const struct device_name* dev_names; }; -static struct device_name infineon_devices[] = { +static const struct device_name infineon_devices[] = { {0xb, "SLB9635 TT 1.2"}, {0} }; @@ -146,7 +147,7 @@ static const struct vendor_name vendor_names[] = { * Cached vendor/device ID pair to indicate that the device has been already * discovered */ -static u32 vendor_dev_id; +static u32 vendor_dev_id CAR_GLOBAL; static int is_byte_reg(u32 reg) {

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Patch set updated for coreboot: cb46d2a Add an option to keep the ROM cached after romstage
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/739 -gerrit commit cb46d2aac3cbd2ae2a92ceacc7db527e43316c31 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Nov 2 16:12:34 2011 -0700 Add an option to keep the ROM cached after romstage Change-Id: I05f1cbd33f0cb7d80ec90c636d1607774b4a74ef Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/include/arch/acpi.h | 4 +++- src/cpu/x86/Kconfig | 4 +++- src/cpu/x86/lapic/Makefile.inc | 1 + src/cpu/x86/lapic/boot_cpu.c | 3 ++- src/cpu/x86/mtrr/mtrr.c | 14 +++++++++++++- src/include/cpu/x86/lapic.h | 4 ++++ 6 files changed, 26 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 030745d..504d71b 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -422,7 +422,8 @@ void *acpi_get_wakeup_rsdp(void); void acpi_jump_to_wakeup(void *wakeup_addr); int acpi_get_sleep_type(void); - +#else +#define acpi_slp_type 0 #endif /* northbridge/amd/amdfam10/amdfam10_acpi.c */ @@ -434,6 +435,7 @@ void generate_cpu_entries(void); #else // CONFIG_GENERATE_ACPI_TABLES #define write_acpi_tables(start) (start) +#define acpi_slp_type 0 #endif diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 348f0ef..fdbd527 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -39,4 +39,6 @@ config LOGICAL_CPUS bool default y - +config CACHE_ROM + bool + default n diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index af20956..f3fcadc 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -2,3 +2,4 @@ ramstage-y += lapic.c ramstage-y += lapic_cpu_init.c ramstage-y += secondary.S ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c +ramstage-y += boot_cpu.c diff --git a/src/cpu/x86/lapic/boot_cpu.c b/src/cpu/x86/lapic/boot_cpu.c index 87418d0..0fb9d5d 100644 --- a/src/cpu/x86/lapic/boot_cpu.c +++ b/src/cpu/x86/lapic/boot_cpu.c @@ -1,7 +1,8 @@ +#include <cpu/x86/lapic.h> #include <cpu/x86/msr.h> #if CONFIG_SMP -static int boot_cpu(void) +int boot_cpu(void) { int bsp; msr_t msr; diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 46d8e2d..9015ad4 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -36,7 +36,9 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> +#include <cpu/x86/lapic.h> #include <arch/cpu.h> +#include <arch/acpi.h> #if CONFIG_GFXUMA extern uint64_t uma_memory_base, uma_memory_size; @@ -48,7 +50,6 @@ static unsigned int mtrr_msr[] = { MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR, }; - void enable_fixed_mtrr(void) { msr_t msr; @@ -456,6 +457,17 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) while(var_state.reg < MTRRS) { set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits); } + +#if CONFIG_CACHE_ROM + /* Enable Caching and speculative Reads for the + * complete ROM now that we actually have RAM. + */ + if (boot_cpu() && (acpi_slp_type != 3)) { + set_var_mtrr(7, (4096-4)*1024, 4*1024, + MTRR_TYPE_WRPROT, address_bits); + } +#endif + printk(BIOS_SPEW, "call enable_var_mtrr()\n"); enable_var_mtrr(); printk(BIOS_SPEW, "Leave %s\n", __func__); diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 8b44a6c..016870d 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -1,6 +1,7 @@ #ifndef CPU_X86_LAPIC_H #define CPU_X86_LAPIC_H +#ifndef __ROMCC__ #include <cpu/x86/lapic_def.h> #include <cpu/x86/msr.h> #include <arch/hlt.h> @@ -156,4 +157,7 @@ int start_cpu(struct device *cpu); #endif /* !__PRE_RAM__ */ +int boot_cpu(void); +#endif + #endif /* CPU_X86_LAPIC_H */

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Patch set updated for coreboot: 33e6810 Add more timestamps in coreboot.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/749 -gerrit commit 33e681093f5ea71ef0acd3151c9ff3c9cb6291b1 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Nov 4 12:31:58 2011 -0700 Add more timestamps in coreboot. This adds a number of timestamps in ramstage and romstage so we can figure out where execution time goes. Change-Id: Iea17c08774e623fc1ca3fa4505b70523ba4cbf01 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/lib/cbfs_and_run.c | 3 +++ src/boot/hardwaremain.c | 21 +++++++++++++++++++++ src/include/timestamp.h | 22 ++++++++++++++++++++-- 3 files changed, 44 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/lib/cbfs_and_run.c b/src/arch/x86/lib/cbfs_and_run.c index ad36ddc..53f06ee 100644 --- a/src/arch/x86/lib/cbfs_and_run.c +++ b/src/arch/x86/lib/cbfs_and_run.c @@ -20,16 +20,19 @@ #include <console/console.h> #include <cbfs.h> #include <arch/stages.h> +#include <timestamp.h> static void cbfs_and_run_core(const char *filename, unsigned ebp) { u8 *dst; + timestamp_add_now(TS_START_COPYRAM); print_debug("Loading image.\n"); dst = cbfs_load_stage(filename); if ((void *)dst == (void *) -1) die("FATAL: Essential component is missing.\n"); + timestamp_add_now(TS_END_COPYRAM); print_debug("Jumping to image.\n"); __asm__ volatile ( "movl %%eax, %%ebp\n" diff --git a/src/boot/hardwaremain.c b/src/boot/hardwaremain.c index 9b293c0..489caa3 100644 --- a/src/boot/hardwaremain.c +++ b/src/boot/hardwaremain.c @@ -41,6 +41,7 @@ it with the version available from LANL. #if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> #endif +#include <timestamp.h> /** * @brief Main function of the RAM part of coreboot. @@ -56,7 +57,9 @@ void hardwaremain(int boot_complete); void hardwaremain(int boot_complete) { struct lb_memory *lb_mem; + tsc_t timestamps[6]; + timestamps[0] = rdtsc(); post_code(POST_ENTRY_RAMSTAGE); /* console_init() MUST PRECEDE ALL printk()! */ @@ -78,18 +81,26 @@ void hardwaremain(int boot_complete) /* FIXME: Is there a better way to handle this? */ init_timer(); + timestamps[1] = rdtsc(); /* Find the devices we don't have hard coded knowledge about. */ dev_enumerate(); post_code(POST_DEVICE_ENUMERATION_COMPLETE); + + timestamps[2] = rdtsc(); /* Now compute and assign the bus resources. */ dev_configure(); post_code(POST_DEVICE_CONFIGURATION_COMPLETE); + + timestamps[3] = rdtsc(); /* Now actually enable devices on the bus */ dev_enable(); + + timestamps[4] = rdtsc(); /* And of course initialize devices on the bus */ dev_initialize(); post_code(POST_DEVICES_ENABLED); + timestamps[5] = rdtsc(); #if CONFIG_WRITE_HIGH_TABLES == 1 cbmem_initialize(); #if CONFIG_CONSOLE_CBMEM @@ -101,10 +112,20 @@ void hardwaremain(int boot_complete) post_code(0x8a); #endif + timestamp_add(TS_START_RAMSTAGE, timestamps[0]); + timestamp_add(TS_DEVICE_ENUMERATE, timestamps[1]); + timestamp_add(TS_DEVICE_CONFIGURE, timestamps[2]); + timestamp_add(TS_DEVICE_ENABLE, timestamps[3]); + timestamp_add(TS_DEVICE_INITIALIZE, timestamps[4]); + timestamp_add(TS_DEVICE_DONE, timestamps[5]); + timestamp_add_now(TS_WRITE_TABLES); + /* Now that we have collected all of our information * write our configuration tables. */ lb_mem = write_tables(); + + timestamp_add_now(TS_LOAD_PAYLOAD); cbfs_load_payload(lb_mem, CONFIG_CBFS_PREFIX "/payload"); printk(BIOS_ERR, "Boot failed.\n"); } diff --git a/src/include/timestamp.h b/src/include/timestamp.h index 8b9a89a..0bb323c 100644 --- a/src/include/timestamp.h +++ b/src/include/timestamp.h @@ -35,14 +35,32 @@ struct timestamp_table { } __attribute__((packed)); enum timestamp_id { - TS_BEFORE_INITRAM = 1, - TS_AFTER_INITRAM = 2, + TS_START_ROMSTAGE = 1, + TS_BEFORE_INITRAM = 2, + TS_AFTER_INITRAM = 3, + TS_END_ROMSTAGE = 4, + TS_START_COPYRAM = 8, + TS_END_COPYRAM = 9, + TS_START_RAMSTAGE = 10, + TS_DEVICE_ENUMERATE = 30, + TS_DEVICE_CONFIGURE = 40, + TS_DEVICE_ENABLE = 50, + TS_DEVICE_INITIALIZE = 60, + TS_DEVICE_DONE = 70, + TS_WRITE_TABLES = 80, + TS_LOAD_PAYLOAD = 90, TS_ACPI_WAKE_JUMP = 98, TS_SELFBOOT_JUMP = 99, }; +#if CONFIG_COLLECT_TIMESTAMPS void timestamp_init(tsc_t base); void timestamp_add(enum timestamp_id id, tsc_t ts_time); void timestamp_add_now(enum timestamp_id id); +#else +#define timestamp_init(base) +#define timestamp_add(id, time) +#define timestamp_add_now(id) +#endif #endif

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Patch set updated for coreboot: ac302ea Fix coreboot makefiles not to produce half baked output.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/750 -gerrit commit ac302ea88301f29f982c0d6191cb07c687b2e09c Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Sat Nov 5 02:07:01 2011 +0000 Fix coreboot makefiles not to produce half baked output. It looks like the cbfstool utility generates the output file even when it fails to generate it properly. This causes make, if started second time in a row, after cbfstool failure, to continue beyond the point of failure (as the corrupted output file is present in the output tree, the second make invocation presumes that it is valid, as it is newer than the dependencies). The output file should be created only when successful, in an atomic operation. There could be other places in the make system which require a similar fix, this needs to be investigated further. Change-Id: I7c17f033ee5937eb712b1a594122430cee5c9146 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/arch/x86/Makefile.inc | 16 +++++++++------- 1 files changed, 9 insertions(+), 7 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index aeb4875..b2b9143 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -58,13 +58,15 @@ extract_nth=$(word $(1), $(subst |, ,$(2))) ifneq ($(CONFIG_UPDATE_IMAGE),y) prebuild-files = \ $(foreach file,$(cbfs-files), \ - $(CBFSTOOL) $@ add $(call extract_nth,1,$(file)) $(call extract_nth,2,$(file)) $(call extract_nth,3,$(file)) $(call extract_nth,4,$(file)); ) + $(CBFSTOOL) $@.tmp add $(call extract_nth,1,$(file)) \ + $(call extract_nth,2,$(file)) $(call extract_nth,3,$(file)) \ + $(call extract_nth,4,$(file)) &&) prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) $(obj)/coreboot.pre1: $(obj)/coreboot.bootblock $$(prebuilt-files) $(CBFSTOOL) - rm -f $@ - $(CBFSTOOL) $@ create $(CONFIG_COREBOOT_ROMSIZE_KB)K $(obj)/coreboot.bootblock - $(prebuild-files) + $(CBFSTOOL) $@.tmp create $(CONFIG_COREBOOT_ROMSIZE_KB)K $(obj)/coreboot.bootblock + $(prebuild-files) true + mv $@.tmp $@ else .PHONY: $(obj)/coreboot.pre1 $(obj)/coreboot.pre1: $(CBFSTOOL) @@ -269,10 +271,10 @@ endif $(obj)/coreboot.pre: $(obj)/coreboot.romstage $(obj)/coreboot.pre1 $(CBFSTOOL) @printf " CBFS $(subst $(obj)/,,$(@))\n" - rm -f $@ - cp $(obj)/coreboot.pre1 $@ - $(CBFSTOOL) $@ add-stage $(obj)/romstage.elf \ + cp $(obj)/coreboot.pre1 $@.tmp + $(CBFSTOOL) $@.tmp add-stage $(obj)/romstage.elf \ $(CONFIG_CBFS_PREFIX)/romstage x 0x$(shell cat $(obj)/location.txt) + mv $@.tmp $@ #FIXME: location.txt might require an offset of header size #######################################################################

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Patch set updated for coreboot: 349c6fa Allow components smaller than declared size.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/751 -gerrit commit 349c6faddb682c6c9932e3107cb02e9c0acdea36 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Nov 9 14:11:26 2011 -0800 Allow components smaller than declared size. idftool was failing to add the ME blobs into the output image in case the blob size does not exactly match the size allocated for it in the flashrom structure. It is difficult to set the field in the structure to exactly match the size (for some reason Intel flash tool fails to insert the correct size even when given the exact ME blob). On the other hand there is no harm in using am ME blob smaller than the allocated size, this change modifies the tool building the image to allow for smaller components. Change-Id: I1b04f90051b91157391943c9bad0eb06dd297431 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- util/ifdtool/ifdtool.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index eb91b2c..8c1077c 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -334,7 +334,7 @@ void inject_region(char *filename, char *image, int size, int region_type, printf("File %s is %d bytes\n", region_fname, region_size); if ( (region_size > region.size) || ((region_type != 1) && - (region_size != region.size))) { + (region_size > region.size))) { fprintf(stderr, "Region %s is %d(0x%x) bytes. File is %d(0x%x)" " bytes. Not injecting.\n", region_name(region_type), region.size,

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Re: [coreboot] Bug when I compiling coreboot with SeaBIOS
by Kevin O'Connor 07 Mar '12

07 Mar '12

On Mon, Mar 05, 2012 at 04:01:45PM -0800, ron minnich wrote: > I'm seeing the ld problem on all my linux systems. What distro do you have? This got fixed in Fedora updates at least. I would normally work around build tool defects (and have done so on many occasions). Unfortunately, this LD one is too severe. The issue is that SeaBIOS needs to have certain tables and code entry points at specific memory locations - this is a requirement for compatibility. The SeaBIOS build generates an LD script to locate the appropriate sections at the correct addresses. Unfortunately, the broken version of LD gets confused with alignment and refuses to place data at the locations they need to be. Not much that can be done - any solution would effectively require not using LD - might as well write our own LD (with the limited requirements of seabios) than try to work around it. -Kevin

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Patch merged into coreboot/master: f7a8b4e Move C labels to start-of-line
by gerrit＠coreboot.org 07 Mar '12

07 Mar '12

the following patch was just integrated into master: commit f7a8b4e8327349825c0c2e51d44e3dd323372cb1 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Wed Mar 7 15:55:47 2012 +0100 Move C labels to start-of-line Also mark the corresponding lint test stable. Change-Id: Ib7c9ed88c5254bf56e68c01cdbd5ab91cd7bfc2f Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Build-Tested: build bot (Jenkins) at Wed Mar 7 16:26:57 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Wed Mar 7 17:48:02 2012, giving +2 See http://review.coreboot.org/772 for details. -gerrit

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Patch merged into coreboot/master: cc2b317 lint: test that labels begin at start-of-line
by gerrit＠coreboot.org 07 Mar '12

07 Mar '12

the following patch was just integrated into master: commit cc2b3173570a49dae0c780c1e1b8d2e12a0f5975 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Wed Mar 7 15:49:07 2012 +0100 lint: test that labels begin at start-of-line Some attempt at enforcing style Change-Id: Ibbfb86402ecc57e8db6c3857c8e0193085ed4fc2 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Build-Tested: build bot (Jenkins) at Wed Mar 7 16:12:29 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Wed Mar 7 17:47:38 2012, giving +2 See http://review.coreboot.org/771 for details. -gerrit

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Patch merged into filo/master: dfc652a Fix some compiler warnings
by gerrit＠coreboot.org 07 Mar '12

07 Mar '12

the following patch was just integrated into master: commit dfc652ad783639baabc71e83b2ac76a583c08975 Author: Mathias Krause <mathias.krause(a)secunet.com> Date: Tue Mar 6 16:10:27 2012 +0100 Fix some compiler warnings The makefile cleanup brought up quite a few compiler warnings about unused functions and/or variables, undefined behaviour, missing return values and type mismatches. Fix those. Change-Id: I0e01b5fafd9d7594ec41c01d849f6ef9a2d56299 Signed-off-by: Mathias Krause <mathias.krause(a)secunet.com> Build-Tested: build bot (Jenkins) at Wed Mar 7 16:43:55 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Wed Mar 7 17:45:23 2012, giving +2 See http://review.coreboot.org/747 for details. -gerrit

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Patch merged into filo/master: baf1339 makefile: build system cleanup
by gerrit＠coreboot.org 07 Mar '12

07 Mar '12

the following patch was just integrated into master: commit baf1339a1334616c73cbbf9cd7743d54b4a86ff3 Author: Mathias Krause <mathias.krause(a)secunet.com> Date: Tue Mar 6 13:37:05 2012 +0100 makefile: build system cleanup This patch cleans up the include hierarchies for the Makefile system to decrease the knowledge of the main Makefile about every subdirectory. This allows us to add new drivers without the need to patch the main Makefile but, instead, just add a line to the appropriate Makefile.inc. Also all standard make variables are cleaned up (e.g. CFLAGS, CPPFLAGS,..). This, in turn, allows modifying them as needed in the included Makefile.inc to add flags or even library dependencies. It's no Linux Kbuild yet, but we're close ;) Change-Id: I67be4fcdd07d6960a7e46bfb6a3c0ea41f280e2b Signed-off-by: Mathias Krause <mathias.krause(a)secunet.com> Build-Tested: build bot (Jenkins) at Wed Mar 7 16:45:22 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Wed Mar 7 17:45:09 2012, giving +2 See http://review.coreboot.org/746 for details. -gerrit

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coreboot March 2012