coreboot March 2012

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Patch set updated for coreboot: 7861a33 Add support for enabling PCIe Common Clock and ASPM
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/735 -gerrit commit 7861a33f83e654439c3ba4e3c4191534264e28fc Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Oct 25 14:15:11 2011 -0700 Add support for enabling PCIe Common Clock and ASPM These are guarded by individual Kconfig entries. The deprecated CONFIG_PCIE_TUNING defines have been removed in favor of using specific config options. This is the generic half, there is board-specific pieces still to come that tune before and after ASPM is enabled. Change-Id: I3fe46282eada67629e9eeeed07e487dff54f2729 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/devices/Kconfig | 14 +++ src/devices/pciexp_device.c | 188 +++++++++++++++++++++++++++++++++++++++--- src/include/device/pci_def.h | 7 ++ src/include/device/pciexp.h | 7 ++ 4 files changed, 205 insertions(+), 11 deletions(-) diff --git a/src/devices/Kconfig b/src/devices/Kconfig index 98e8d9f..7429bda 100644 --- a/src/devices/Kconfig +++ b/src/devices/Kconfig @@ -163,3 +163,17 @@ config AGP_PLUGIN_SUPPORT config CARDBUS_PLUGIN_SUPPORT bool default y + +config PCIEXP_COMMON_CLOCK + prompt "Enable PCIe Common Clock" + bool + default n + help + Detect and enable Common Clock on PCIe links. + +config PCIEXP_ASPM + prompt "Enable PCIe ASPM" + bool + default n + help + Detect and enable ASPM on PCIe links. diff --git a/src/devices/pciexp_device.c b/src/devices/pciexp_device.c index 5d33942..36f3e6a 100644 --- a/src/devices/pciexp_device.c +++ b/src/devices/pciexp_device.c @@ -19,31 +19,197 @@ */ #include <console/console.h> +#include <delay.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pciexp.h> +#if CONFIG_PCIEXP_COMMON_CLOCK +/* + * Re-train a PCIe link + */ +#define PCIE_TRAIN_RETRY 10000 +static int pciexp_retrain_link(device_t dev, unsigned cap) +{ + unsigned try = PCIE_TRAIN_RETRY; + u16 lnk; + + /* Start link retraining */ + lnk = pci_read_config16(dev, cap + PCI_EXP_LNKCTL); + lnk |= PCI_EXP_LNKCTL_RL; + pci_write_config16(dev, cap + PCI_EXP_LNKCTL, lnk); + + /* Wait for training to complete */ + while (try--) { + lnk = pci_read_config16(dev, cap + PCI_EXP_LNKSTA); + if (!(lnk & PCI_EXP_LNKSTA_LT)) + return 0; + udelay(100); + } + + printk(BIOS_ERR, "%s: Link Retrain timeout\n", dev_path(dev)); + return -1; +} + +/* + * Check the Slot Clock Configuration for root port and endpoint + * and enable Common Clock Configuration if possible. If CCC is + * enabled the link must be retrained. + */ +static void pciexp_enable_common_clock(device_t root, unsigned root_cap, + device_t endp, unsigned endp_cap) +{ + u16 root_scc, endp_scc, lnkctl; + + /* Get Slot Clock Configuration for root port */ + root_scc = pci_read_config16(root, root_cap + PCI_EXP_LNKSTA); + root_scc &= PCI_EXP_LNKSTA_SLC; + + /* Get Slot Clock Configuration for endpoint */ + endp_scc = pci_read_config16(endp, endp_cap + PCI_EXP_LNKSTA); + endp_scc &= PCI_EXP_LNKSTA_SLC; + + /* Enable Common Clock Configuration and retrain */ + if (root_scc && endp_scc) { + printk(BIOS_INFO, "Enabling Common Clock Configuration\n"); + + /* Set in endpoint */ + lnkctl = pci_read_config16(endp, endp_cap + PCI_EXP_LNKCTL); + lnkctl |= PCI_EXP_LNKCTL_CCC; + pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl); + + /* Set in root port */ + lnkctl = pci_read_config16(root, root_cap + PCI_EXP_LNKCTL); + lnkctl |= PCI_EXP_LNKCTL_CCC; + pci_write_config16(root, root_cap + PCI_EXP_LNKCTL, lnkctl); + + /* Retrain link if CCC was enabled */ + pciexp_retrain_link(root, root_cap); + } +} +#endif /* CONFIG_PCIEXP_COMMON_CLOCK */ + +#if CONFIG_PCIEXP_ASPM +/* + * Determine the ASPM L0s or L1 exit latency for a link + * by checking both root port and endpoint and returning + * the highest latency value. + */ +static int pciexp_aspm_latency(device_t root, unsigned root_cap, + device_t endp, unsigned endp_cap, + enum aspm_type type) +{ + int root_lat = 0, endp_lat = 0; + u32 root_lnkcap, endp_lnkcap; + + root_lnkcap = pci_read_config32(root, root_cap + PCI_EXP_LNKCAP); + endp_lnkcap = pci_read_config32(endp, endp_cap + PCI_EXP_LNKCAP); + + /* Make sure the link supports this ASPM type by checking + * capability bits 11:10 with aspm_type offset by 1 */ + if (!(root_lnkcap & (1 << (type + 9))) || + !(endp_lnkcap & (1 << (type + 9)))) + return -1; + + /* Find the one with higher latency */ + switch (type) { + case PCIE_ASPM_L0S: + root_lat = (root_lnkcap & PCI_EXP_LNKCAP_L0SEL) >> 12; + endp_lat = (endp_lnkcap & PCI_EXP_LNKCAP_L0SEL) >> 12; + break; + case PCIE_ASPM_L1: + root_lat = (root_lnkcap & PCI_EXP_LNKCAP_L1EL) >> 15; + endp_lat = (endp_lnkcap & PCI_EXP_LNKCAP_L1EL) >> 15; + break; + default: + return -1; + } + + return (endp_lat > root_lat) ? endp_lat : root_lat; +} + +/* + * Enable ASPM on PCIe root port and endpoint. + * + * Returns APMC value: + * -1 = Error + * 0 = no ASPM + * 1 = L0s Enabled + * 2 = L1 Enabled + * 3 = L0s and L1 Enabled + */ +static enum aspm_type pciexp_enable_aspm(device_t root, unsigned root_cap, + device_t endp, unsigned endp_cap) +{ + const char *aspm_type_str[] = { "None", "L0s", "L1", "L0s and L1" }; + enum aspm_type apmc = PCIE_ASPM_NONE; + int exit_latency, ok_latency; + u16 lnkctl; + u32 devcap; + + /* Get endpoint device capabilities for acceptable limits */ + devcap = pci_read_config32(endp, endp_cap + PCI_EXP_DEVCAP); + + /* Enable L0s if it is within endpoint acceptable limit */ + ok_latency = (devcap & PCI_EXP_DEVCAP_L0S) >> 6; + exit_latency = pciexp_aspm_latency(root, root_cap, endp, endp_cap, + PCIE_ASPM_L0S); + if (exit_latency >= 0 && exit_latency <= ok_latency) + apmc |= PCIE_ASPM_L0S; + + /* Enable L1 if it is within endpoint acceptable limit */ + ok_latency = (devcap & PCI_EXP_DEVCAP_L1) >> 9; + exit_latency = pciexp_aspm_latency(root, root_cap, endp, endp_cap, + PCIE_ASPM_L1); + if (exit_latency >= 0 && exit_latency <= ok_latency) + apmc |= PCIE_ASPM_L1; + + if (apmc != PCIE_ASPM_NONE) { + /* Set APMC in root port first */ + lnkctl = pci_read_config16(root, root_cap + PCI_EXP_LNKCTL); + lnkctl |= apmc; + pci_write_config16(root, root_cap + PCI_EXP_LNKCTL, lnkctl); + + /* Set APMC in endpoint device next */ + lnkctl = pci_read_config16(endp, endp_cap + PCI_EXP_LNKCTL); + lnkctl |= apmc; + pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl); + } + + printk(BIOS_INFO, "ASPM: Enabled %s\n", aspm_type_str[apmc]); + return apmc; +} +#endif /* CONFIG_PCIEXP_ASPM */ + static void pciexp_tune_dev(device_t dev) { - unsigned int cap; -#if CONFIG_PCIE_TUNING - u32 reg32; -#endif + device_t root = dev->bus->dev; + unsigned int root_cap, cap; cap = pci_find_capability(dev, PCI_CAP_ID_PCIE); if (!cap) return; -#if CONFIG_PCIE_TUNING - printk(BIOS_DEBUG, "PCIe: tuning %s\n", dev_path(dev)); + root_cap = pci_find_capability(root, PCI_CAP_ID_PCIE); + if (!root_cap) + return; + +#if CONFIG_PCIEXP_COMMON_CLOCK + /* Check for and enable Common Clock */ + pciexp_enable_common_clock(root, root_cap, dev, cap); +#endif - // TODO make this depending on ASPM. +#if CONFIG_PCIEXP_ASPM + /* Check for and enable ASPM */ + enum aspm_type apmc = pciexp_enable_aspm(root, root_cap, dev, cap); - /* Enable ASPM role based error reporting. */ - reg32 = pci_read_config32(dev, cap + PCI_EXP_DEVCAP); - reg32 |= PCI_EXP_DEVCAP_RBER; - pci_write_config32(dev, cap + PCI_EXP_DEVCAP, reg32); + if (apmc != PCIE_ASPM_NONE) { + /* Enable ASPM role based error reporting. */ + u32 reg32 = pci_read_config32(dev, cap + PCI_EXP_DEVCAP); + reg32 |= PCI_EXP_DEVCAP_RBER; + pci_write_config32(dev, cap + PCI_EXP_DEVCAP, reg32); + } #endif } diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index a5aa3a1..58a7321 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -371,8 +371,15 @@ #define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */ #define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */ #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ +#define PCI_EXP_LNKCAP_ASPMS 0xc00 /* ASPM Support */ +#define PCI_EXP_LNKCAP_L0SEL 0x7000 /* L0s Exit Latency */ +#define PCI_EXP_LNKCAP_L1EL 0x38000 /* L1 Exit Latency */ #define PCI_EXP_LNKCTL 16 /* Link Control */ +#define PCI_EXP_LNKCTL_RL 0x20 /* Retrain Link */ +#define PCI_EXP_LNKCTL_CCC 0x40 /* Common Clock COnfiguration */ #define PCI_EXP_LNKSTA 18 /* Link Status */ +#define PCI_EXP_LNKSTA_LT 0x800 /* Link Training */ +#define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */ #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ #define PCI_EXP_SLTCTL 24 /* Slot Control */ #define PCI_EXP_SLTSTA 26 /* Slot Status */ diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h index 409f211..87a5002 100644 --- a/src/include/device/pciexp.h +++ b/src/include/device/pciexp.h @@ -2,6 +2,13 @@ #define DEVICE_PCIEXP_H /* (c) 2005 Linux Networx GPL see COPYING for details */ +enum aspm_type { + PCIE_ASPM_NONE = 0, + PCIE_ASPM_L0S = 1, + PCIE_ASPM_L1 = 2, + PCIE_ASPM_BOTH = 3, +}; + unsigned int pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, unsigned int max_devfn, unsigned int max); unsigned int pciexp_scan_bridge(device_t dev, unsigned int max);

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Patch set updated for coreboot: df4b21e tell superiotool about the ITE 8772
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/734 -gerrit commit df4b21edd01fae57bcb8ee5026693e8198100bb9 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Oct 25 17:12:53 2011 +0000 tell superiotool about the ITE 8772 no dumping yet Change-Id: I4e687ca816c8d6d1c95255b0abf6a19513e23f86 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- util/superiotool/ite.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/util/superiotool/ite.c b/util/superiotool/ite.c index c83d788..e186e10 100644 --- a/util/superiotool/ite.c +++ b/util/superiotool/ite.c @@ -708,6 +708,8 @@ static const struct superio_registers reg_table[] = { {EOT}}}, {0x8761, "IT8761E", { {EOT}}}, + {0x8772, "IT8772F", { + {EOT}}}, {0x8780, "IT8780F", { {EOT}}}, {EOT}

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Patch set updated for coreboot: b7fd05a Add timestamps for selfboot and acpi wake
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/733 -gerrit commit b7fd05a98d451fa9d98886025cc30cdcd8799551 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Oct 19 15:32:39 2011 -0700 Add timestamps for selfboot and acpi wake Change-Id: I28224867610b947739d940d25c98399d219f10f4 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/arch/x86/boot/acpi.c | 7 +++++++ src/boot/selfboot.c | 7 +++++++ src/include/timestamp.h | 2 ++ 3 files changed, 16 insertions(+), 0 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index eb2e4e1..d4d554c 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -31,6 +31,9 @@ #include <arch/acpigen.h> #include <device/pci.h> #include <cbmem.h> +#if CONFIG_COLLECT_TIMESTAMPS +#include <timestamp.h> +#endif #if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/chromeos.h> #endif @@ -611,6 +614,10 @@ void acpi_jump_to_wakeup(void *vector) /* Copy wakeup trampoline in place. */ memcpy((void *)WAKEUP_BASE, &__wakeup, (size_t)&__wakeup_size); +#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_ACPI_WAKE_JUMP); +#endif + acpi_do_wakeup((u32)vector, acpi_backup_memory, CONFIG_RAMBASE, HIGH_MEMORY_SAVE); } diff --git a/src/boot/selfboot.c b/src/boot/selfboot.c index bbf160e..d4ab8c8 100644 --- a/src/boot/selfboot.c +++ b/src/boot/selfboot.c @@ -29,6 +29,9 @@ #include <string.h> #include <cbfs.h> #include <lib.h> +#if CONFIG_COLLECT_TIMESTAMPS +#include <timestamp.h> +#endif /* Maximum physical address we can use for the coreboot bounce buffer. */ #ifndef MAX_ADDR @@ -529,6 +532,10 @@ static int selfboot(struct lb_memory *mem, struct cbfs_payload *payload) printk(BIOS_DEBUG, "Jumping to boot code at %x\n", entry); post_code(POST_ENTER_ELF_BOOT); +#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_SELFBOOT_JUMP); +#endif + /* Jump to kernel */ jmp_to_elf_entry((void*)entry, bounce_buffer, bounce_size); return 1; diff --git a/src/include/timestamp.h b/src/include/timestamp.h index cfa06e2..8b9a89a 100644 --- a/src/include/timestamp.h +++ b/src/include/timestamp.h @@ -37,6 +37,8 @@ struct timestamp_table { enum timestamp_id { TS_BEFORE_INITRAM = 1, TS_AFTER_INITRAM = 2, + TS_ACPI_WAKE_JUMP = 98, + TS_SELFBOOT_JUMP = 99, }; void timestamp_init(tsc_t base);

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Patch set updated for coreboot: b7e70b3 selfboot: Allow loading SeaBIOS into a reserved region in the lower 1MB This fixes loading SeaBIOS when lower memory is reserved.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/732 -gerrit commit b7e70b33f24510c3ec513def4ef210e2dbee6f5c Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Oct 18 15:11:04 2011 -0700 selfboot: Allow loading SeaBIOS into a reserved region in the lower 1MB This fixes loading SeaBIOS when lower memory is reserved. Change-Id: Idbdcaf95f3307f97307f304d6d677406d059927d Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/boot/selfboot.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/src/boot/selfboot.c b/src/boot/selfboot.c index fe56653..bbf160e 100644 --- a/src/boot/selfboot.c +++ b/src/boot/selfboot.c @@ -148,6 +148,11 @@ static int valid_area(struct lb_memory *mem, unsigned long buffer, } } if (i == mem_entries) { + if (start < (1024*1024) && end <=(1024*1024)) { + printk(BIOS_DEBUG, "Payload (probably SeaBIOS) loaded" + " into a reserved area in the lower 1MB\n"); + return 1; + } printk(BIOS_ERR, "No matching ram area found for range:\n"); printk(BIOS_ERR, " [0x%016lx, 0x%016lx)\n", start, end); printk(BIOS_ERR, "Ram areas\n");

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Patch set updated for coreboot: f91f4dc Add TPM support to coreboot
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/731 -gerrit commit f91f4dc2549767500e0f7d069f7c913767298ce8 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Oct 11 14:46:25 2011 -0700 Add TPM support to coreboot and initialize the TPM on S3 resume This patch integrates the TPM driver and runs TPM resume upon an ACPI S3 resume without including any other parts of vboot. We could link against vboot_fw.a but it is compiled with u-boot's CFLAGS (that are incompatible with coreboot's) and it does a lot more than we want it to do. Change-Id: I000d4322ef313e931e23c56defaa17e3a4d7f8cf Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/Kconfig | 4 + src/arch/x86/boot/acpi.c | 8 + src/include/pc80/tpm.h | 29 ++ src/pc80/Makefile.inc | 1 + src/pc80/tpm.c | 554 ++++++++++++++++++++++++++++++++ src/vendorcode/google/chromeos/vboot.c | 201 ++++++++++++ 6 files changed, 797 insertions(+), 0 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 573868f..26e6dde 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -262,6 +262,10 @@ config IOAPIC bool default n +config TPM + bool + default n + # TODO: Can probably be removed once all chipsets have kconfig options for it. config VIDEO_MB int diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index f1be034..eb2e4e1 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -31,6 +31,9 @@ #include <arch/acpigen.h> #include <device/pci.h> #include <cbmem.h> +#if CONFIG_CHROMEOS +#include <vendorcode/google/chromeos/chromeos.h> +#endif u8 acpi_checksum(u8 *table, u32 length) { @@ -525,6 +528,11 @@ void *acpi_find_wakeup_vector(void) if (!acpi_is_wakeup()) return NULL; +#ifdef CONFIG_CHROMEOS + printk(BIOS_DEBUG, "Verified boot TPM initialization.\n"); + init_vboot(); +#endif + printk(BIOS_DEBUG, "Trying to find the wakeup vector...\n"); /* Find RSDP. */ diff --git a/src/include/pc80/tpm.h b/src/include/pc80/tpm.h new file mode 100644 index 0000000..2eff15a --- /dev/null +++ b/src/include/pc80/tpm.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef TPM_H_ +#define TPM_H_ + +int tis_init(void); +int tis_open(void); +int tis_close(void); +int tis_sendrecv(const u8 *sendbuf, size_t send_size, u8 *recvbuf, + size_t *recv_len); + +#endif /* TPM_H_ */ diff --git a/src/pc80/Makefile.inc b/src/pc80/Makefile.inc index 2c8a80e..cd6ea33 100644 --- a/src/pc80/Makefile.inc +++ b/src/pc80/Makefile.inc @@ -4,6 +4,7 @@ ramstage-y += i8254.c ramstage-y += i8259.c ramstage-$(CONFIG_UDELAY_IO) += udelay_io.c ramstage-y += keyboard.c +ramstage-$(CONFIG_TPM) += tpm.c romstage-$(CONFIG_USE_OPTION_TABLE) += mc146818rtc_early.c subdirs-y += vga diff --git a/src/pc80/tpm.c b/src/pc80/tpm.c new file mode 100644 index 0000000..1cbf800 --- /dev/null +++ b/src/pc80/tpm.c @@ -0,0 +1,554 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * The code in this file has been heavily based on the article "Writing a TPM + * Device Driver" published on http://ptgmedia.pearsoncmg.com and the + * submission by Stefan Berger on Qemu-devel mailing list. + * + * One principal difference is that in the simplest config the other than 0 + * TPM localities do not get mapped by some devices (for instance, by + * Infineon slb9635), so this driver provides access to locality 0 only. + */ + +/* #define DEBUG */ +#include <stdlib.h> +#include <string.h> +#include <delay.h> +#include <arch/io.h> +#include <arch/byteorder.h> +#include <console/console.h> +#include <pc80/tpm.h> + +#ifdef DEBUG +#define TPM_DEBUG_ON 1 +#else +#define TPM_DEBUG_ON 0 +#endif + +#define PREFIX "lpc_tpm: " + +/* coreboot wrapper for TPM driver (start) */ +#define TPM_DEBUG(fmt, args...) \ + if (TPM_DEBUG_ON) { \ + printk(BIOS_DEBUG, PREFIX); \ + printk(BIOS_DEBUG, fmt , ##args); \ + } +#define printf(x...) printk(BIOS_ERR, x) + +#define min(a,b) MIN(a,b) +#define max(a,b) MAX(a,b) +#define readb(_a) (*(volatile unsigned char *) (_a)) +#define writeb(_v, _a) (*(volatile unsigned char *) (_a) = (_v)) +#define readl(_a) (*(volatile unsigned long *) (_a)) +#define writel(_v, _a) (*(volatile unsigned long *) (_a) = (_v)) +/* coreboot wrapper for TPM driver (end) */ + +#ifndef CONFIG_TPM_TIS_BASE_ADDRESS +/* Base TPM address standard for x86 systems */ +#define CONFIG_TPM_TIS_BASE_ADDRESS 0xfed40000 +#endif + +/* the macro accepts the locality value, but only locality 0 is operational */ +#define TIS_REG(LOCALITY, REG) \ + (void *)(CONFIG_TPM_TIS_BASE_ADDRESS + (LOCALITY << 12) + REG) + +/* hardware registers' offsets */ +#define TIS_REG_ACCESS 0x0 +#define TIS_REG_INT_ENABLE 0x8 +#define TIS_REG_INT_VECTOR 0xc +#define TIS_REG_INT_STATUS 0x10 +#define TIS_REG_INTF_CAPABILITY 0x14 +#define TIS_REG_STS 0x18 +#define TIS_REG_DATA_FIFO 0x24 +#define TIS_REG_DID_VID 0xf00 +#define TIS_REG_RID 0xf04 + +/* Some registers' bit field definitions */ +#define TIS_STS_VALID (1 << 7) /* 0x80 */ +#define TIS_STS_COMMAND_READY (1 << 6) /* 0x40 */ +#define TIS_STS_TPM_GO (1 << 5) /* 0x20 */ +#define TIS_STS_DATA_AVAILABLE (1 << 4) /* 0x10 */ +#define TIS_STS_EXPECT (1 << 3) /* 0x08 */ +#define TIS_STS_RESPONSE_RETRY (1 << 1) /* 0x02 */ + +#define TIS_ACCESS_TPM_REG_VALID_STS (1 << 7) /* 0x80 */ +#define TIS_ACCESS_ACTIVE_LOCALITY (1 << 5) /* 0x20 */ +#define TIS_ACCESS_BEEN_SEIZED (1 << 4) /* 0x10 */ +#define TIS_ACCESS_SEIZE (1 << 3) /* 0x08 */ +#define TIS_ACCESS_PENDING_REQUEST (1 << 2) /* 0x04 */ +#define TIS_ACCESS_REQUEST_USE (1 << 1) /* 0x02 */ +#define TIS_ACCESS_TPM_ESTABLISHMENT (1 << 0) /* 0x01 */ + +#define TIS_STS_BURST_COUNT_MASK (0xffff) +#define TIS_STS_BURST_COUNT_SHIFT (8) + +/* + * Error value returned if a tpm register does not enter the expected state + * after continuous polling. No actual TPM register reading ever returns ~0, + * so this value is a safe error indication to be mixed with possible status + * register values. + */ +#define TPM_TIMEOUT_ERR (~0) + +/* Error value returned on various TPM driver errors */ +#define TPM_DRIVER_ERR (~0) + + /* 1 second is plenty for anything TPM does.*/ +#define MAX_DELAY_US (1000 * 1000) + +/* Retrieve burst count value out of the status register contents. */ +#define BURST_COUNT(status) ((u16)(((status) >> TIS_STS_BURST_COUNT_SHIFT) & \ + TIS_STS_BURST_COUNT_MASK)) + +/* + * Structures defined below allow creating descriptions of TPM vendor/device + * ID information for run time discovery. The only device the system knows + * about at this time is Infineon slb9635 + */ +struct device_name { + u16 dev_id; + const char * const dev_name; +}; + +struct vendor_name { + u16 vendor_id; + const char * vendor_name; + struct device_name* dev_names; +}; + +static struct device_name infineon_devices[] = { + {0xb, "SLB9635 TT 1.2"}, + {0} +}; + +static const struct vendor_name vendor_names[] = { + {0x15d1, "Infineon", infineon_devices}, +}; + +/* + * Cached vendor/device ID pair to indicate that the device has been already + * discovered + */ +static u32 vendor_dev_id; + +static int is_byte_reg(u32 reg) +{ + /* + * These TPM registers are 8 bits wide and as such require byte access + * on writes and truncated value on reads. + */ + return ((reg == TIS_REG_ACCESS) || + (reg == TIS_REG_INT_VECTOR) || + (reg == TIS_REG_DATA_FIFO)); +} + +/* TPM access functions are carved out to make tracing easier. */ +static u32 tpm_read(int locality, u32 reg) +{ + u32 value; + /* + * Data FIFO register must be read and written in byte access mode, + * otherwise the FIFO values are returned 4 bytes at a time. + */ + if (is_byte_reg(reg)) + value = readb(TIS_REG(locality, reg)); + else + value = readl(TIS_REG(locality, reg)); + + TPM_DEBUG("Read reg 0x%x returns 0x%x\n", reg, value); + return value; +} + +static void tpm_write(u32 value, int locality, u32 reg) +{ + TPM_DEBUG("Write reg 0x%x with 0x%x\n", reg, value); + + if (is_byte_reg(reg)) + writeb(value & 0xff, TIS_REG(locality, reg)); + else + writel(value, TIS_REG(locality, reg)); +} + +/* + * tis_wait_reg() + * + * Wait for at least a second for a register to change its state to match the + * expected state. Normally the transition happens within microseconds. + * + * @reg - the TPM register offset + * @locality - locality + * @mask - bitmask for the bitfield(s) to watch + * @expected - value the field(s) are supposed to be set to + * + * Returns the register contents in case the expected value was found in the + * appropriate register bits, or TPM_TIMEOUT_ERR on timeout. + */ +static u32 tis_wait_reg(u8 reg, u8 locality, u8 mask, u8 expected) +{ + u32 time_us = MAX_DELAY_US; + while (time_us > 0) { + u32 value = tpm_read(locality, reg); + if ((value & mask) == expected) + return value; + udelay(1); /* 1 us */ + time_us--; + } + return TPM_TIMEOUT_ERR; +} + +/* + * Probe the TPM device and try determining its manufacturer/device name. + * + * Returns 0 on success (the device is found or was found during an earlier + * invocation) or TPM_DRIVER_ERR if the device is not found. + */ +static u32 tis_probe(void) +{ + u32 didvid = tpm_read(0, TIS_REG_DID_VID); + int i; + const char *device_name = "unknown"; + const char *vendor_name = device_name; + u16 vid, did; + + if (vendor_dev_id) + return 0; /* Already probed. */ + + if (!didvid || (didvid == 0xffffffff)) { + printf("%s: No TPM device found\n", __FUNCTION__); + return TPM_DRIVER_ERR; + } + + vendor_dev_id = didvid; + + vid = didvid & 0xffff; + did = (didvid >> 16) & 0xffff; + for (i = 0; i < ARRAY_SIZE(vendor_names); i++) { + int j = 0; + u16 known_did; + if (vid == vendor_names[i].vendor_id) { + vendor_name = vendor_names[i].vendor_name; + } + while ((known_did = vendor_names[i].dev_names[j].dev_id) != 0) { + if (known_did == did) { + device_name = + vendor_names[i].dev_names[j].dev_name; + break; + } + j++; + } + break; + } + /* this will have to be converted into debug printout */ + TPM_DEBUG("Found TPM %s by %s\n", device_name, vendor_name); + return 0; +} + +/* + * tis_senddata() + * + * send the passed in data to the TPM device. + * + * @data - address of the data to send, byte by byte + * @len - length of the data to send + * + * Returns 0 on success, TPM_DRIVER_ERR on error (in case the device does + * not accept the entire command). + */ +static u32 tis_senddata(const u8 * const data, u32 len) +{ + u32 offset = 0; + u16 burst = 0; + u32 max_cycles = 0; + u8 locality = 0; + u32 value; + + value = tis_wait_reg(TIS_REG_STS, locality, TIS_STS_COMMAND_READY, + TIS_STS_COMMAND_READY); + if (value == TPM_TIMEOUT_ERR) { + printf("%s:%d - failed to get 'command_ready' status\n", + __FILE__, __LINE__); + return TPM_DRIVER_ERR; + } + burst = BURST_COUNT(value); + + while (1) { + unsigned count; + + /* Wait till the device is ready to accept more data. */ + while (!burst) { + if (max_cycles++ == MAX_DELAY_US) { + printf("%s:%d failed to feed %d bytes of %d\n", + __FILE__, __LINE__, len - offset, len); + return TPM_DRIVER_ERR; + } + udelay(1); + burst = BURST_COUNT(tpm_read(locality, TIS_REG_STS)); + } + + max_cycles = 0; + + /* + * Calculate number of bytes the TPM is ready to accept in one + * shot. + * + * We want to send the last byte outside of the loop (hence + * the -1 below) to make sure that the 'expected' status bit + * changes to zero exactly after the last byte is fed into the + * FIFO. + */ + count = min(burst, len - offset - 1); + while (count--) + tpm_write(data[offset++], locality, TIS_REG_DATA_FIFO); + + value = tis_wait_reg(TIS_REG_STS, locality, + TIS_STS_VALID, TIS_STS_VALID); + + if ((value == TPM_TIMEOUT_ERR) || !(value & TIS_STS_EXPECT)) { + printf("%s:%d TPM command feed overflow\n", + __FILE__, __LINE__); + return TPM_DRIVER_ERR; + } + + burst = BURST_COUNT(value); + if ((offset == (len - 1)) && burst) + /* + * We need to be able to send the last byte to the + * device, so burst size must be nonzero before we + * break out. + */ + break; + } + + /* Send the last byte. */ + tpm_write(data[offset++], locality, TIS_REG_DATA_FIFO); + + /* + * Verify that TPM does not expect any more data as part of this + * command. + */ + value = tis_wait_reg(TIS_REG_STS, locality, + TIS_STS_VALID, TIS_STS_VALID); + if ((value == TPM_TIMEOUT_ERR) || (value & TIS_STS_EXPECT)) { + printf("%s:%d unexpected TPM status 0x%x\n", + __FILE__, __LINE__, value); + return TPM_DRIVER_ERR; + } + + /* OK, sitting pretty, let's start the command execution. */ + tpm_write(TIS_STS_TPM_GO, locality, TIS_REG_STS); + + return 0; +} + +/* + * tis_readresponse() + * + * read the TPM device response after a command was issued. + * + * @buffer - address where to read the response, byte by byte. + * @len - pointer to the size of buffer + * + * On success stores the number of received bytes to len and returns 0. On + * errors (misformatted TPM data or synchronization problems) returns + * TPM_DRIVER_ERR. + */ +static u32 tis_readresponse(u8 *buffer, size_t *len) +{ + u16 burst_count; + u32 status; + u32 offset = 0; + u8 locality = 0; + const u32 has_data = TIS_STS_DATA_AVAILABLE | TIS_STS_VALID; + u32 expected_count = *len; + int max_cycles = 0; + + /* Wait for the TPM to process the command */ + status = tis_wait_reg(TIS_REG_STS, locality, has_data, has_data); + if (status == TPM_TIMEOUT_ERR) { + printf("%s:%d failed processing command\n", + __FILE__, __LINE__); + return TPM_DRIVER_ERR; + } + + do { + while ((burst_count = BURST_COUNT(status)) == 0) { + if (max_cycles++ == MAX_DELAY_US) { + printf("%s:%d TPM stuck on read\n", + __FILE__, __LINE__); + return TPM_DRIVER_ERR; + } + udelay(1); + status = tpm_read(locality, TIS_REG_STS); + } + + max_cycles = 0; + + while (burst_count-- && (offset < expected_count)) { + buffer[offset++] = (u8) tpm_read(locality, + TIS_REG_DATA_FIFO); + if (offset == 6) { + /* + * We got the first six bytes of the reply, + * let's figure out how many bytes to expect + * total - it is stored as a 4 byte number in + * network order, starting with offset 2 into + * the body of the reply. + */ + u32 real_length; + memcpy(&real_length, + buffer + 2, + sizeof(real_length)); + expected_count = be32_to_cpu(real_length); + + if ((expected_count < offset) || + (expected_count > *len)) { + printf("%s:%d bad response size %d\n", + __FILE__, __LINE__, + expected_count); + return TPM_DRIVER_ERR; + } + } + } + + /* Wait for the next portion */ + status = tis_wait_reg(TIS_REG_STS, locality, + TIS_STS_VALID, TIS_STS_VALID); + if (status == TPM_TIMEOUT_ERR) { + printf("%s:%d failed to read response\n", + __FILE__, __LINE__); + return TPM_DRIVER_ERR; + } + + if (offset == expected_count) + break; /* We got all we need */ + + } while ((status & has_data) == has_data); + + /* + * Make sure we indeed read all there was. The TIS_STS_VALID bit is + * known to be set. + */ + if (status & TIS_STS_DATA_AVAILABLE) { + printf("%s:%d wrong receive status %x\n", + __FILE__, __LINE__, status); + return TPM_DRIVER_ERR; + } + + /* Tell the TPM that we are done. */ + tpm_write(TIS_STS_COMMAND_READY, locality, TIS_REG_STS); + + *len = offset; + return 0; +} + +/* + * tis_init() + * + * Initialize the TPM device. Returns 0 on success or TPM_DRIVER_ERR on + * failure (in case device probing did not succeed). + */ +int tis_init(void) +{ + if (tis_probe()) + return TPM_DRIVER_ERR; + return 0; +} + +/* + * tis_open() + * + * Requests access to locality 0 for the caller. After all commands have been + * completed the caller is supposed to call tis_close(). + * + * Returns 0 on success, TPM_DRIVER_ERR on failure. + */ +int tis_open(void) +{ + u8 locality = 0; /* we use locality zero for everything */ + + if (tis_close()) + return TPM_DRIVER_ERR; + + /* now request access to locality */ + tpm_write(TIS_ACCESS_REQUEST_USE, locality, TIS_REG_ACCESS); + + /* did we get a lock? */ + if (tis_wait_reg(TIS_REG_ACCESS, locality, + TIS_ACCESS_ACTIVE_LOCALITY, + TIS_ACCESS_ACTIVE_LOCALITY) == TPM_TIMEOUT_ERR) { + printf("%s:%d - failed to lock locality %d\n", + __FILE__, __LINE__, locality); + return TPM_DRIVER_ERR; + } + + tpm_write(TIS_STS_COMMAND_READY, locality, TIS_REG_STS); + + return 0; +} + +/* + * tis_close() + * + * terminate the currect session with the TPM by releasing the locked + * locality. Returns 0 on success of TPM_DRIVER_ERR on failure (in case lock + * removal did not succeed). + */ +int tis_close(void) +{ + u8 locality = 0; + if (tpm_read(locality, TIS_REG_ACCESS) & + TIS_ACCESS_ACTIVE_LOCALITY) { + tpm_write(TIS_ACCESS_ACTIVE_LOCALITY, locality, TIS_REG_ACCESS); + + if (tis_wait_reg(TIS_REG_ACCESS, locality, + TIS_ACCESS_ACTIVE_LOCALITY, 0) == + TPM_TIMEOUT_ERR) { + printf("%s:%d - failed to release locality %d\n", + __FILE__, __LINE__, locality); + return TPM_DRIVER_ERR; + } + } + return 0; +} + +/* + * tis_sendrecv() + * + * Send the requested data to the TPM and then try to get its response + * + * @sendbuf - buffer of the data to send + * @send_size size of the data to send + * @recvbuf - memory to save the response to + * @recv_len - pointer to the size of the response buffer + * + * Returns 0 on success (and places the number of response bytes at recv_len) + * or TPM_DRIVER_ERR on failure. + */ +int tis_sendrecv(const uint8_t *sendbuf, size_t send_size, + uint8_t *recvbuf, size_t *recv_len) +{ + if (tis_senddata(sendbuf, send_size)) { + printf("%s:%d failed sending data to TPM\n", + __FILE__, __LINE__); + return TPM_DRIVER_ERR; + } + + return tis_readresponse(recvbuf, recv_len); +} diff --git a/src/vendorcode/google/chromeos/vboot.c b/src/vendorcode/google/chromeos/vboot.c new file mode 100644 index 0000000..e0a8c9b --- /dev/null +++ b/src/vendorcode/google/chromeos/vboot.c @@ -0,0 +1,201 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <pc80/tpm.h> +#include "chromeos.h" + +//#define EXTRA_LOGGING + +#define TPM_LARGE_ENOUGH_COMMAND_SIZE 256 /* saves space in the firmware */ + +#define TPM_SUCCESS ((u32)0x00000000) + +#define TPM_E_IOERROR ((u32)0x0000001f) +#define TPM_E_COMMUNICATION_ERROR ((u32)0x00005004) +#define TPM_E_NON_FATAL ((u32)0x00000800) +#define TPM_E_INVALID_POSTINIT ((u32)0x00000026) + +#define TPM_E_NEEDS_SELFTEST ((u32)(TPM_E_NON_FATAL + 1)) +#define TPM_E_DOING_SELFTEST ((u32)(TPM_E_NON_FATAL + 2)) + +static const struct { + u8 buffer[12]; +} tpm_resume_cmd = { + { 0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x0, 0x99, 0x0, 0x2 } +}; + +static const struct { + u8 buffer[10]; +} tpm_continueselftest_cmd = { + { 0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x53 } +}; + +static inline void FromTpmUint32(const u8 * buffer, u32 * x) +{ + *x = ((buffer[0] << 24) | + (buffer[1] << 16) | (buffer[2] << 8) | buffer[3]); +} + +static inline int TpmCommandSize(const u8 * buffer) +{ + u32 size; + FromTpmUint32(buffer + sizeof(u16), &size); + return (int)size; +} + +/* Gets the code field of a TPM command. */ +static inline int TpmCommandCode(const u8 * buffer) +{ + u32 code; + FromTpmUint32(buffer + sizeof(u16) + sizeof(u32), &code); + return code; +} + +/* Gets the return code field of a TPM result. */ +static inline int TpmReturnCode(const u8 * buffer) +{ + return TpmCommandCode(buffer); +} + +/* Like TlclSendReceive below, but do not retry if NEEDS_SELFTEST or + * DOING_SELFTEST errors are returned. + */ +static u32 TlclSendReceiveNoRetry(const u8 * request, + u8 * response, int max_length) +{ + size_t response_length = max_length; + u32 result; + +#ifdef EXTRA_LOGGING + printk(BIOS_DEBUG, "TPM: command: %x%x %x%x%x%x %x%x%x%x\n", + request[0], request[1], + request[2], request[3], request[4], request[5], + request[6], request[7], request[8], request[9]); +#endif + + result = TPM_SUCCESS; + if (tis_sendrecv + (request, TpmCommandSize(request), response, &response_length)) + result = TPM_E_IOERROR; + + if (0 != result) { + /* Communication with TPM failed, so response is garbage */ + printk(BIOS_DEBUG, + "TPM: command 0x%x send/receive failed: 0x%x\n", + TpmCommandCode(request), result); + return TPM_E_COMMUNICATION_ERROR; + } + /* Otherwise, use the result code from the response */ + result = TpmReturnCode(response); + +/* TODO: add paranoia about returned response_length vs. max_length + * (and possibly expected length from the response header). See + * crosbug.com/17017 */ + +#ifdef EXTRA_LOGGING + printk(BIOS_DEBUG, "TPM: response: %x%x %x%x%x%x %x%x%x%x\n", + response[0], response[1], + response[2], response[3], response[4], response[5], + response[6], response[7], response[8], response[9]); +#endif + + printk(BIOS_DEBUG, "TPM: command 0x%x returned 0x%x\n", + TpmCommandCode(request), result); + + return result; +} + +static inline u32 TlclContinueSelfTest(void) +{ + u8 response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; + printk(BIOS_DEBUG, "TPM: Continue self test\n"); + /* Call the No Retry version of SendReceive to avoid recursion. */ + return TlclSendReceiveNoRetry(tpm_continueselftest_cmd.buffer, + response, sizeof(response)); +} + +/* Sends a TPM command and gets a response. Returns 0 if success or the TPM + * error code if error. In the firmware, waits for the self test to complete + * if needed. In the host, reports the first error without retries. */ +static u32 TlclSendReceive(const u8 * request, u8 * response, int max_length) +{ + u32 result = TlclSendReceiveNoRetry(request, response, max_length); + /* When compiling for the firmware, hide command failures due to the self + * test not having run or completed. */ + /* If the command fails because the self test has not completed, try it + * again after attempting to ensure that the self test has completed. */ + if (result == TPM_E_NEEDS_SELFTEST || result == TPM_E_DOING_SELFTEST) { + result = TlclContinueSelfTest(); + if (result != TPM_SUCCESS) { + return result; + } +#if defined(TPM_BLOCKING_CONTINUESELFTEST) || defined(VB_RECOVERY_MODE) + /* Retry only once */ + result = TlclSendReceiveNoRetry(request, response, max_length); +#else + /* This needs serious testing. The TPM specification says: + * "iii. The caller MUST wait for the actions of + * TPM_ContinueSelfTest to complete before reissuing the + * command C1." But, if ContinueSelfTest is non-blocking, how + * do we know that the actions have completed other than trying + * again? */ + do { + result = + TlclSendReceiveNoRetry(request, response, + max_length); + } while (result == TPM_E_DOING_SELFTEST); +#endif + } + + return result; +} + +void init_vboot(void) +{ + u32 result; + u8 response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; + + printk(BIOS_DEBUG, "TPM: Init\n"); + if (tis_init()) + return; + + printk(BIOS_DEBUG, "TPM: Open\n"); + if (tis_open()) + return; + + printk(BIOS_DEBUG, "TPM: Resume\n"); + + result = + TlclSendReceive(tpm_resume_cmd.buffer, response, sizeof(response)); + + if (result == TPM_E_INVALID_POSTINIT) { + /* We're on a platform where the TPM maintains power in S3, so + * it's already initialized. */ + printk(BIOS_DEBUG, "TPM: Already initialized.\n"); + return; + } + if (result == TPM_SUCCESS) { + printk(BIOS_DEBUG, "TPM: OK.\n"); + return; + } + // TODO(reinauer) hard reboot? +}

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Patch set updated for coreboot: bb711d3 Don't run any option roms stored outside of the system flash
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/730 -gerrit commit bb711d3f6dbde4db589fefb0cc10d49a62a944ba Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Oct 6 16:47:51 2011 -0700 Don't run any option roms stored outside of the system flash Right now coreboot only executes vga option roms. However, this is not good enough. For security reasons we want to execute only option roms stored in our RO CBFS. This patch adds a new option to disable execution of arbitrary option ROMs and enables it for all our boards. Change-Id: I485291c06ec5cd1f875357401831fe32ccfc5f2f Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/devices/Kconfig | 13 +++++++++++++ src/devices/pci_rom.c | 6 ++++++ 2 files changed, 19 insertions(+), 0 deletions(-) diff --git a/src/devices/Kconfig b/src/devices/Kconfig index 572addc..98e8d9f 100644 --- a/src/devices/Kconfig +++ b/src/devices/Kconfig @@ -49,6 +49,19 @@ config PCI_ROM_RUN Examples include IDE/SATA controller option ROMs and option ROMs for network cards (NICs). +config ON_DEVICE_ROM_RUN + bool "Run option ROMs on PCI devices" + default y + help + Execute option ROMs that are stored on PCI/PCIe/AGP devices. + + If disabled, only option ROMs stored in CBFS will be executed. If + you are concerned about security, you might want to disable this + option, but it might leave your system in a state of degraded + functionality. + + If unsure, say Y + choice prompt "Option ROM execution type" default PCI_OPTION_ROM_RUN_YABEL if !ARCH_X86 diff --git a/src/devices/pci_rom.c b/src/devices/pci_rom.c index 471c7e2..1b6f1da 100644 --- a/src/devices/pci_rom.c +++ b/src/devices/pci_rom.c @@ -71,9 +71,15 @@ struct rom_header *pci_rom_probe(struct device *dev) rom_address|PCI_ROM_ADDRESS_ENABLE); } +#if CONFIG_ON_DEVICE_ROM_RUN printk(BIOS_DEBUG, "On card, ROM address for %s = %lx\n", dev_path(dev), (unsigned long)rom_address); rom_header = (struct rom_header *)rom_address; +#else + printk(BIOS_DEBUG, "On card option ROM execution disabled " + "for %s\n", dev_path(dev)); + return NULL; +#endif } printk(BIOS_SPEW, "PCI expansion ROM, signature 0x%04x, "

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Patch set updated for coreboot: ce5ca60 If the memory mapped UART isn't present, leave it out of the cb tables.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/729 -gerrit commit ce5ca6042e1e71c331e9ef68e9fbabc60980e112 Author: Gabe Black <gabeblack(a)google.com> Date: Wed Oct 5 01:57:03 2011 -0700 If the memory mapped UART isn't present, leave it out of the cb tables. This way u-boot won't try to use a UART that isn't plugged in. Change-Id: I9a3a0d074dd03add8afbd4dad836c4c6a05abe6f Signed-off-by: Gabe Black <gabeblack(a)google.com> --- src/arch/x86/boot/coreboot_table.c | 24 ++++++++++++++---------- 1 files changed, 14 insertions(+), 10 deletions(-) diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c index f29481b..d24d7c4 100644 --- a/src/arch/x86/boot/coreboot_table.c +++ b/src/arch/x86/boot/coreboot_table.c @@ -118,16 +118,20 @@ static struct lb_serial *lb_serial(struct lb_header *header) serial->baud = CONFIG_TTYS0_BAUD; return serial; #elif CONFIG_CONSOLE_SERIAL8250MEM - struct lb_record *rec; - struct lb_serial *serial; - rec = lb_new_record(header); - serial = (struct lb_serial *)rec; - serial->tag = LB_TAG_SERIAL; - serial->size = sizeof(*serial); - serial->type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial->baseaddr = uartmem_getbaseaddr(); - serial->baud = CONFIG_TTYS0_BAUD; - return serial; + if (uartmem_getbaseaddr()) { + struct lb_record *rec; + struct lb_serial *serial; + rec = lb_new_record(header); + serial = (struct lb_serial *)rec; + serial->tag = LB_TAG_SERIAL; + serial->size = sizeof(*serial); + serial->type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial->baseaddr = uartmem_getbaseaddr(); + serial->baud = CONFIG_TTYS0_BAUD; + return serial; + } else { + return NULL; + } #else return NULL; #endif

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Patch set updated for coreboot: f39995e Detect whether the OXPCIE card is really present while in the ROM stage.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/728 -gerrit commit f39995ec5b90cc5c0fa7ad5247a68e3938f4fba1 Author: Gabe Black <gabeblack(a)google.com> Date: Wed Oct 5 01:52:08 2011 -0700 Detect whether the OXPCIE card is really present while in the ROM stage. Use an int in CAR global data to store whether or not the OXPCIE serial card is actually there. Also, time out if the card doesn't show up quickly enough, don't continue initialization if it's not there, and don't make the initialization routine default to a card if none is found. Change-Id: I9c72d3abc6ee2867b77ab2f2180e6f01f647af8c Signed-off-by: Gabe Black <gabeblack(a)google.com> --- src/arch/x86/lib/romstage_console.c | 5 ++++- src/drivers/oxford/oxpcie/oxpcie_early.c | 20 +++++++++++++++++--- src/include/uart8250.h | 5 +++++ 3 files changed, 26 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index 0f22727..25eda9b 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -35,7 +35,10 @@ static void console_tx_byte(unsigned char byte) console_tx_byte('\r'); #if CONFIG_CONSOLE_SERIAL8250MEM - uart8250_mem_tx_byte(CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte); + if (oxford_oxpcie_present) { + uart8250_mem_tx_byte( + CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte); + } #endif #if CONFIG_CONSOLE_SERIAL8250 uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c index 2c7767e..4f7a3cb 100644 --- a/src/drivers/oxford/oxpcie/oxpcie_early.c +++ b/src/drivers/oxford/oxpcie/oxpcie_early.c @@ -20,6 +20,8 @@ #include <stdint.h> #include <arch/io.h> #include <arch/romcc_io.h> +#include <cpu/x86/car.h> +#include <delay.h> #include <uart8250.h> #include <device/pci_def.h> @@ -34,9 +36,13 @@ #define OXPCIE_DEVICE_3 \ PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 3) +#if defined(__PRE_RAM__) +int oxford_oxpcie_present CAR_GLOBAL; + void oxford_init(void) { u16 reg16; + oxford_oxpcie_present = 1; /* First we reset the secondary bus */ reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL); @@ -69,11 +75,14 @@ void oxford_init(void) reg16 |= PCI_COMMAND_MEMORY; pci_write_config16(PCIE_BRIDGE, PCI_COMMAND, reg16); - // FIXME Add a timeout or this will hang forever if - // no device is in the slot. + u32 timeout = 20000; // Timeout in 10s of microseconds. u32 id = 0; - while ((id == 0) || (id == 0xffffffff)) + for (;;) { id = pci_read_config32(OXPCIE_DEVICE, PCI_VENDOR_ID); + if (!timeout-- || (id != 0 && id != 0xffffffff)) + break; + udelay(10); + } u32 device = OXPCIE_DEVICE; /* unknown default */ switch (id) { @@ -90,6 +99,10 @@ void oxford_init(void) case 0xc1581415: /* e.g. Startech MPEX2S952 */ device = OXPCIE_DEVICE; break; + default: + /* No UART here. */ + oxford_oxpcie_present = 0; + return; } /* Setup base address on device */ @@ -107,3 +120,4 @@ void oxford_init(void) uart8250_mem_init(uart0_base, (4000000 / CONFIG_TTYS0_BAUD)); } +#endif diff --git a/src/include/uart8250.h b/src/include/uart8250.h index aa510e5..71b9a5f 100644 --- a/src/include/uart8250.h +++ b/src/include/uart8250.h @@ -135,8 +135,13 @@ void uart8250_mem_init(unsigned base_port, unsigned divisor); u32 uart_mem_init(void); u32 uartmem_getbaseaddr(void); +#if defined(__PRE_RAM__) && CONFIG_DRIVERS_OXFORD_OXPCIE && \ + CONFIG_CONSOLE_SERIAL8250MEM /* and special init for OXPCIe based cards */ +extern int oxford_oxpcie_present; + void oxford_init(void); +#endif #endif /* __ROMCC__ */

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Patch set updated for coreboot: 05b3eee CBMEM CONSOLE: Add config option for CBMEM stored console log.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/718 -gerrit commit 05b3eeef8c098f761f4c7a61fbd27cc7b7175ec6 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Sep 28 13:51:30 2011 -0700 CBMEM CONSOLE: Add config option for CBMEM stored console log. Some experiments have demonstrated that total amount of text generated by coreboot console when BIOS_SPEW level is enabled exceeds 40KB. Console output generated before DRAM is initialized can exceed 2KB. This patch introduces the new configuration option and assigns adequate default values to cache based and DRAM based console buffers. BUG=chrome-os-partner:4200 TEST=manual . run the following commands in the root directory cp config.stumpy .config make menuconfig . enable the new option (Console->Send console output to a CBMEM buffer) . save the configuration Observe the following settings added to the config: +CONFIG_CONSOLE_CBMEM=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0xae00 +CONFIG_CONSOLE_CAR_BUFFER_SIZE=0xc00 Change-Id: I209603f516244ae136631e6281ba21ebc6fb1710 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Reviewed-on: https://gerrit-int.chromium.org/5855 Tested-by: Vadim Bendebury <vbendeb(a)google.com> Reviewed-by: Stefan Reinauer <reinauer(a)google.com> --- src/console/Kconfig | 27 +++++++++++++++++++++++++++ 1 files changed, 27 insertions(+), 0 deletions(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index dbd11f6..fefbe2e 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -190,6 +190,33 @@ config CONSOLE_NE2K_IO_PORT 32 bytes of IO spaces will be used (and align on 32 bytes boundary, qemu needs broader align) +config CONSOLE_CBMEM + depends on EARLY_CBMEM_INIT + bool "Send console output to a CBMEM buffer" + default n + help + Enable this to save the console output in a CBMEM buffer. This would + allow to see coreboot console output from Linux space. + +config CONSOLE_CBMEM_BUFFER_SIZE + depends on CONSOLE_CBMEM + hex "Room allocated for console output in CBMEM" + default 0xae00 + help + Space allocated for console output storage in CBMEM. The default + value (almost 45K or 0xaeoo bytes) is large enough to accommodate + even the BIOS_SPEW level. + +config CONSOLE_CAR_BUFFER_SIZE + depends on CONSOLE_CBMEM + hex "Room allocated for console output in cash as RAM" + default 0xc00 + help + Console is used before RAM is initialized. This is the room reserved + in the DCACHE based RAM to keep console output before it can be + saved in a CBMEM buffer. 3K bytes should be enough even for the + BIOS_SPEW level. + choice prompt "Maximum console log level"

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Patch set updated for coreboot: f24a9b9 CBMEM CONSOLE: Add CBMEM console driver implementation.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/719 -gerrit commit f24a9b904926af4039bc2530918d77a886f029b7 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu Sep 29 17:27:15 2011 -0700 CBMEM CONSOLE: Add CBMEM console driver implementation. The CBMEM console driver saves console output in a CBMEM area, which then is made available to Linux applications for perusing. There are some system limitations which need to be worked around to achieve this goal: - some console traffic is generated before DRAM is initialized, leave alone CBMEM initialized. - after the RAM based stage starts, a lot of traffic is generated before CBMEM is initialized. As a result, the console log lives in three different places - the bottom of the cache as RAM space, the CBMEM buffer (where it is expected to be) and a static buffer used early in the RAM stage. When execution starts (in the cache as RAM mode), the console buffer is allocated at the bottom of the cache as RAM memory address range. Once DRAM is initialized, the CBMEM structure is initialized, and then the console buffer contents are copied from the bottom of the cache as RAM space into the CBMEM area right before the cache as RAM mode is disabled. The src/lib/cbmem_console.c:cbmemc_reinit() takes care of the copying. At this point the cache as RAM memory is about to be disabled, but the ROM stage is still going generating console output. To make sure this output is not lost, cbmemc_reinit() saves the new buffer address at a fixed location (0x600 was chosen for this), and the actual "printing" function checks to see if the RAM is already initialized (the stack is in RAM), and if so, gets the console buffer pointer from this location instead of using the cache as RAM address. When the RAM stage starts, a static buffer is used to store the console output, as the CBMEM buffer location is not known. Then, when CBMEM is reinitialized, cbmemc_reinit() again takes care of the copying. In case the allocated buffers are not large enough, the excessive data is dropped, and the copying routine adds some text to the output buffer to indicate that there has been data lost and how many characters were dropped. Change-Id: I8c126e31db6cb2141f7f4f97c5047f39a8db44fc Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/console/cbmem_console.c | 35 ++++++ src/include/console/cbmem_console.h | 26 +++++ src/include/console/console.h | 3 + src/lib/cbmem_console.c | 195 +++++++++++++++++++++++++++++++++++ 4 files changed, 259 insertions(+), 0 deletions(-) diff --git a/src/console/cbmem_console.c b/src/console/cbmem_console.c new file mode 100644 index 0000000..2c43f5c --- /dev/null +++ b/src/console/cbmem_console.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#include <console/console.h> + +static void cbmemc_init_(void) +{ + cbmemc_init(); +} + +static void cbmemc_tx_byte_(unsigned char data) +{ + cbmemc_tx_byte(data); +} + +static const struct console_driver cbmem_console __console = { + .init = cbmemc_init_, + .tx_byte = cbmemc_tx_byte_, +}; diff --git a/src/include/console/cbmem_console.h b/src/include/console/cbmem_console.h new file mode 100644 index 0000000..37ea4d8 --- /dev/null +++ b/src/include/console/cbmem_console.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ +#ifndef _CONSOLE_CBMEM_CONSOLE_H_ +#define _CONSOLE_CBMEM_CONSOLE_H_ + +void cbmemc_init(void); +void cbmemc_reinit(void); +void cbmemc_tx_byte(unsigned char data); + +#endif diff --git a/src/include/console/console.h b/src/include/console/console.h index 54c825c..56e202d 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -33,6 +33,9 @@ #if CONFIG_CONSOLE_NE2K #include <console/ne2k.h> #endif +#if CONFIG_CONSOLE_CBMEM +#include <console/cbmem_console.h> +#endif #ifndef __PRE_RAM__ void console_tx_byte(unsigned char byte); diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c new file mode 100644 index 0000000..b58de48 --- /dev/null +++ b/src/lib/cbmem_console.c @@ -0,0 +1,195 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#include <console/console.h> +#include <cbmem.h> +#include <string.h> + +/* + * Structure describing console buffer. It is overlaid on a flat memory area, + * whith buffer_body covering the extent of the memory. Once the buffer is + * full, the cursor keeps going but the data is dropped on the floor. This + * allows to tell how much data was lost in the process. + */ +struct cbmem_console { + u32 buffer_size; + u32 buffer_cursor; + u8 buffer_body[0]; +} __attribute__ ((__packed__)); + +#ifdef __PRE_RAM__ +/* + * While running from ROM, before DRAM is initialized, some area in cache as + * ram space is used for the console buffer storage. The size and location of + * the area are defined in the config. + */ +#define cbmem_console_p ((struct cbmem_console *)CONFIG_DCACHE_RAM_BASE) + +/* + * Once DRAM is initialized and the cache as ram mode is disabled, while still + * running from ROM, the console buffer in the cache as RAM area becomes + * unavailable. + * + * By this time the console log buffer is already available in + * CBMEM. The location at 0x600 is used as the redirect pointer allowing to + * find out where the actual console log buffer is. + */ +#define CBMEM_CONSOLE_REDIRECT (*((struct cbmem_console **)0x600)) +#else + +/* + * When running from RAM, a lot of console output is generated before CBMEM is + * reinitialized. This static buffer is used to store that output temporarily, + * to be concatenated with the CBMEM console buffer contents accumulated + * during the ROM stage, once CBMEM becomes avaiklable at RAM stage. + */ +static u8 static_console[40000]; +static struct cbmem_console *cbmem_console_p; +#endif + +void cbmemc_init(void) +{ +#ifdef __PRE_RAM__ + cbmem_console_p->buffer_size = CONFIG_CONSOLE_CAR_BUFFER_SIZE - + sizeof(struct cbmem_console); +#else + /* + * Initializing before CBMEM is available, use static buffer to store + * the log. + */ + cbmem_console_p = (struct cbmem_console *) static_console; + cbmem_console_p->buffer_size = sizeof(static_console) - + sizeof(struct cbmem_console); +#endif + cbmem_console_p->buffer_cursor = 0; +} + +void cbmemc_tx_byte(unsigned char data) +{ + struct cbmem_console *cbm_cons_p = cbmem_console_p; + u32 cursor; +#ifdef __PRE_RAM__ + /* + * This check allows to tell if the cache as RAM mode has been exited + * or not. If it has been exited, the real memory is being used + * (resulting in the variable on the stack located below + * DCACHE_RAM_BASE), use the redirect pointer to find out where the + * actual console buffer is. + */ + if ((u32)&cursor < (u32)CONFIG_DCACHE_RAM_BASE) + cbm_cons_p = CBMEM_CONSOLE_REDIRECT; +#endif + if (!cbm_cons_p) + return; + + cursor = cbm_cons_p->buffer_cursor++; + if (cursor < cbm_cons_p->buffer_size) + cbm_cons_p->buffer_body[cursor] = data; +} + +/* + * Copy the current console buffer (either from the cache as RAM area, or from + * the static buffer, pointed at by cbmem_console_p) into the CBMEM console + * buffer space (pointed at by new_cons_p), concatenating the copied data with + * the CBMEM console buffer contents. + * + * If there is overflow - add to the destination area a string, reporting the + * overflow and the number of dropped charactes. + */ +static void copy_console_buffer(struct cbmem_console *new_cons_p) +{ + u32 copy_size; + u32 cursor = new_cons_p->buffer_cursor; + int overflow = cbmem_console_p->buffer_cursor > + cbmem_console_p->buffer_size; + + copy_size = overflow ? + cbmem_console_p->buffer_size : cbmem_console_p->buffer_cursor; + + memcpy(new_cons_p->buffer_body + cursor, + cbmem_console_p->buffer_body, + copy_size); + + cursor += copy_size; + + if (overflow) { + const char loss_str1[] = "\n\n*** Log truncated, "; + const char loss_str2[] = " characters dropped. ***\n\n"; + u32 dropped_chars = cbmem_console_p->buffer_cursor - copy_size; + + /* + * When running from ROM sprintf is not available, a simple + * itoa implementation is used instead. + */ + int got_first_digit = 0; + + /* Way more than possible number of dropped characters. */ + u32 mult = 100000; + + strcpy((char *)new_cons_p->buffer_body + cursor, loss_str1); + cursor += sizeof(loss_str1) - 1; + + while (mult) { + int digit = dropped_chars / mult; + if (got_first_digit || digit) { + new_cons_p->buffer_body[cursor++] = digit + '0'; + dropped_chars %= mult; + /* Excessive, but keeps it simple */ + got_first_digit = 1; + } + mult /= 10; + } + + strcpy((char *)new_cons_p->buffer_body + cursor, loss_str2); + cursor += sizeof(loss_str2) - 1; + } + new_cons_p->buffer_cursor = cursor; +} + +void cbmemc_reinit(void) +{ + struct cbmem_console *cbm_cons_p; + +#ifdef __PRE_RAM__ + cbm_cons_p = cbmem_add(CBMEM_ID_CONSOLE, + CONFIG_CONSOLE_CBMEM_BUFFER_SIZE); + if (!cbm_cons_p) { + CBMEM_CONSOLE_REDIRECT = NULL; + return; + } + + cbm_cons_p->buffer_size = CONFIG_CONSOLE_CBMEM_BUFFER_SIZE - + sizeof(struct cbmem_console); + + cbm_cons_p->buffer_cursor = 0; + + copy_console_buffer(cbm_cons_p); + + CBMEM_CONSOLE_REDIRECT = cbm_cons_p; +#else + cbm_cons_p = cbmem_find(CBMEM_ID_CONSOLE); + + if (!cbm_cons_p) + return; + + copy_console_buffer(cbm_cons_p); + + cbmem_console_p = cbm_cons_p; +#endif +}

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coreboot March 2012