coreboot March 2012

coreboot@coreboot.org

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Patch set updated for coreboot: c98f469 Add timestamp table pointer to the coreboot table.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/716 -gerrit commit c98f469e29f49887d16d94392e6888d5ca66ebd0 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri Sep 23 09:56:11 2011 -0700 Add timestamp table pointer to the coreboot table. This change exports the timestamp table pointer through coreboot table to make it possible for u-boot to add timestamps to the table. Inclusion of cbmem.h allows to drop external declarations in coreboot_table.c. Change-Id: Ia070198cee7a6ffdaeece03d9d15bd91e033b6d1 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/arch/x86/boot/coreboot_table.c | 25 +++++++++++++++++++++---- src/include/boot/coreboot_tables.h | 8 ++++++++ 2 files changed, 29 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c index b0dcc9e..f189e76 100644 --- a/src/arch/x86/boot/coreboot_table.c +++ b/src/arch/x86/boot/coreboot_table.c @@ -30,6 +30,7 @@ #include <device/device.h> #include <stdlib.h> #include <cbfs.h> +#include <cbmem.h> #if CONFIG_USE_OPTION_TABLE #include <option_table.h> #endif @@ -174,6 +175,23 @@ static void lb_framebuffer(struct lb_header *header) #endif } +#if CONFIG_COLLECT_TIMESTAMPS +static void lb_tsamp(struct lb_header *header) +{ + struct lb_tstamp *tstamp; + void *tstamp_table = cbmem_find(CBMEM_ID_TIMESTAMP); + + if (!tstamp_table) + return; + + tstamp = (struct lb_tstamp *)lb_new_record(header); + tstamp->tag = LB_TAG_TIMESTAMPS; + tstamp->size = sizeof(*tstamp); + tstamp->tstamp_tab = tstamp_table; + +} +#endif + static struct lb_mainboard *lb_mainboard(struct lb_header *header) { struct lb_record *rec; @@ -513,10 +531,6 @@ static void add_lb_reserved(struct lb_memory *mem) lb_add_rsvd_range, mem); } -#if CONFIG_WRITE_HIGH_TABLES -extern uint64_t high_tables_base, high_tables_size; -#endif - unsigned long write_coreboot_table( unsigned long low_table_start, unsigned long low_table_end, unsigned long rom_table_start, unsigned long rom_table_end) @@ -619,6 +633,9 @@ unsigned long write_coreboot_table( /* Record our framebuffer */ lb_framebuffer(head); +#if CONFIG_COLLECT_TIMESTAMPS + lb_tsamp(head); +#endif /* Remember where my valid memory ranges are */ return lb_table_fini(head, 1); diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index 45ba3af..46d6489 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -195,6 +195,14 @@ struct lb_framebuffer { uint8_t reserved_mask_size; }; +#define LB_TAG_TIMESTAMPS 0x0016 +struct lb_tstamp { + uint32_t tag; + uint32_t size; + + void *tstamp_tab; +}; + /* The following structures are for the cmos definitions table */ #define LB_TAG_CMOS_OPTION_TABLE 200 /* cmos header record */

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Patch set updated for coreboot: a6e3815 Add cmos helper functions for reading/writing a dword
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/717 -gerrit commit a6e3815e02d6e7eaf381fbf64ff8fe6f22dabf3a Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Sep 26 13:24:40 2011 -0700 Add cmos helper functions for reading/writing a dword These get used later for saving/restoring the MRC scrambler seed values on each boot. Change-Id: I6e23f17649bea6d22c4b279ed8d0e5cb6c0885e7 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/include/pc80/mc146818rtc.h | 16 ++++++++++++++++ 1 files changed, 16 insertions(+), 0 deletions(-) diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index 3e5a61a..24dac2c 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -104,6 +104,22 @@ static inline void cmos_write(unsigned char val, unsigned char addr) outb(addr, RTC_BASE_PORT + offs + 0); outb(val, RTC_BASE_PORT + offs + 1); } + +static inline u32 cmos_read32(u8 offset) +{ + u32 value = 0; + u8 i; + for (i = 0; i < sizeof(value); ++i) + value |= cmos_read(offset + i) << (i << 3); + return value; +} + +static inline void cmos_write32(u8 offset, u32 value) +{ + u8 i; + for (i = 0; i < sizeof(value); ++i) + cmos_write((value >> (i << 3)) & 0xff, offset + i); +} #endif #if !defined(__ROMCC__)

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Patch set updated for coreboot: e14abc7 Don't run VGA option ROMs on S3 resume.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/715 -gerrit commit e14abc76e6fb9f82436e3710959a5505f659d315 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Sep 23 10:33:58 2011 -0700 Don't run VGA option ROMs on S3 resume. This will save us a few 100 ms on resume. Change-Id: Iabf4c8ab88662ba41236162f0a6f5bd80d8c1255 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/devices/Kconfig | 7 +++++++ src/devices/pci_device.c | 11 +++++++++++ 2 files changed, 18 insertions(+), 0 deletions(-) diff --git a/src/devices/Kconfig b/src/devices/Kconfig index 9e5ea6e..572addc 100644 --- a/src/devices/Kconfig +++ b/src/devices/Kconfig @@ -33,6 +33,13 @@ config VGA_ROM_RUN Execute VGA option ROMs, if found. This is required to enable PCI/AGP/PCI-E video cards. +config S3_VGA_ROM_RUN + bool "Re-run VGA option ROMs on S3 resume" + default y + depends on VGA_ROM_RUN && HAVE_ACPI_RESUME + help + Execute VGA option ROMs when coming out of an S3 resume. + config PCI_ROM_RUN bool "Run non-VGA option ROMs" default y diff --git a/src/devices/pci_device.c b/src/devices/pci_device.c index 2ccb38a..0a870b8 100644 --- a/src/devices/pci_device.c +++ b/src/devices/pci_device.c @@ -51,6 +51,9 @@ #if CONFIG_PC80_SYSTEM == 1 #include <pc80/i8259.h> #endif +#if CONFIG_HAVE_ACPI_RESUME && !CONFIG_S3_VGA_ROM_RUN +#include <arch/acpi.h> +#endif u8 pci_moving_config8(struct device *dev, unsigned int reg) { @@ -672,6 +675,14 @@ void pci_dev_init(struct device *dev) if (ram == NULL) return; +#if CONFIG_HAVE_ACPI_RESUME && !CONFIG_S3_VGA_ROM_RUN + /* If S3_VGA_ROM_RUN is disabled, skip running VGA option + * ROMs when coming out of an S3 resume. + */ + if ((acpi_slp_type == 3) && + ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)) + return; +#endif run_bios(dev, (unsigned long)ram); #endif /* CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN */ }

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Patch set updated for coreboot: fe0b190 Add DEBUG_TPM option to Debugging menu
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/757 -gerrit commit fe0b190cb629fdb6884aa96c0ca01582680bb804 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Nov 17 12:50:54 2011 -0800 Add DEBUG_TPM option to Debugging menu instead of having to edit the source code of tpm.c Change-Id: I519d9ada14dd383e668a2da4219e5373a24c7c3d Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/Kconfig | 7 +++++++ src/pc80/tpm.c | 9 +-------- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 26e6dde..41c5dbf 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -870,6 +870,13 @@ config X86EMU_DEBUG_IO If unsure, say N. +config DEBUG_TPM + bool "Output verbose TPM debug messages" + default n + depends on TPM + help + This option enables additional TPM related debug messages. + config LLSHELL bool "Built-in low-level shell" default n diff --git a/src/pc80/tpm.c b/src/pc80/tpm.c index 8e94303..17e1ed7 100644 --- a/src/pc80/tpm.c +++ b/src/pc80/tpm.c @@ -27,7 +27,6 @@ * Infineon slb9635), so this driver provides access to locality 0 only. */ -/* #define DEBUG */ #include <stdlib.h> #include <string.h> #include <delay.h> @@ -37,17 +36,11 @@ #include <pc80/tpm.h> #include <cpu/x86/car.h> -#ifdef DEBUG -#define TPM_DEBUG_ON 1 -#else -#define TPM_DEBUG_ON 0 -#endif - #define PREFIX "lpc_tpm: " /* coreboot wrapper for TPM driver (start) */ #define TPM_DEBUG(fmt, args...) \ - if (TPM_DEBUG_ON) { \ + if (CONFIG_DEBUG_TPM) { \ printk(BIOS_DEBUG, PREFIX); \ printk(BIOS_DEBUG, fmt , ##args); \ }

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Patch set updated for coreboot: 7f7ba8b Don't unconditionally add support for cardbus and pci-x devices
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/756 -gerrit commit 7f7ba8b34c759012009f39d5929eec2125d42254 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Nov 30 12:45:14 2011 -0800 Don't unconditionally add support for cardbus and pci-x devices It's still on by default. Change-Id: I8b6539eaf2f8d6a4fa975deb14789a00f2090d34 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/devices/Makefile.inc | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/devices/Makefile.inc b/src/devices/Makefile.inc index 86b4d21..9ffc0bb 100644 --- a/src/devices/Makefile.inc +++ b/src/devices/Makefile.inc @@ -3,10 +3,10 @@ ramstage-y += root_device.c ramstage-y += device_util.c ramstage-y += pci_device.c ramstage-$(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT) += hypertransport.c -ramstage-y += pcix_device.c +ramstage-$(CONFIG_PCIX_PLUGIN_SUPPORT) += pcix_device.c ramstage-y += pciexp_device.c -ramstage-y += agp_device.c -ramstage-y += cardbus_device.c +ramstage-$(CONFIG_AGP_PLUGIN_SUPPORT) += agp_device.c +ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += cardbus_device.c ramstage-y += pnp_device.c ramstage-y += pci_ops.c ramstage-y += smbus_ops.c

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Patch set updated for coreboot: 484a702 Fix romcc to compile cleanly
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/759 -gerrit commit 484a7021d3876b265039c8e242c48b2e7bf98a68 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Dec 6 22:14:57 2011 +0000 Fix romcc to compile cleanly There have been many unused variable assignments in the romcc source file. They cause multiple warning messages during build process which in turn make it harder to see the actual error message, when they are present. The fix is to remove dead code and to add -Werror to romcc compilation to avoid issues like this creeping in in the future. Change-Id: I6f42684f39a4135b0fe64219b8c7f058275c9fee Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- util/romcc/Makefile | 2 +- util/romcc/romcc.c | 3 +-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/util/romcc/Makefile b/util/romcc/Makefile index 6543fbb..8242eb5 100644 --- a/util/romcc/Makefile +++ b/util/romcc/Makefile @@ -1,7 +1,7 @@ # Move the configuration defines to makefile.conf CC=gcc CPPFLAGS= -CFLAGS= -g -Wall $(CPPFLAGS) +CFLAGS= -g -Wall -Werror $(CPPFLAGS) CPROF_FLAGS=-pg -fprofile-arcs all: romcc test diff --git a/util/romcc/romcc.c b/util/romcc/romcc.c index c7ef223..7eee439 100644 --- a/util/romcc/romcc.c +++ b/util/romcc/romcc.c @@ -9161,8 +9161,7 @@ static void decompose_compound_types(struct compile_state *state) { struct triple *ins, *next, *first; #if DEBUG_DECOMPOSE_HIRES - FILE *fp; - fp = state->dbgout; + FILE *fp = state->dbgout; #endif first = state->first; ins = first;

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Patch set updated for coreboot: ef76c56 Make PCI CONF2 support a compile time option.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/758 -gerrit commit ef76c56da3a73f82cb284cd16a186bfb30afd07a Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Nov 17 13:05:31 2011 -0800 Make PCI CONF2 support a compile time option. It's not used on any board supported by coreboot but has been detected at run time since ages. No new boards (since 2000?) are using the CONF2 method, so it is unlikely we ever have to turn this on for a board. Change-Id: I17df94a8a77b9338fde10a6b114b44d393776e66 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/Kconfig | 4 ++++ src/arch/x86/lib/Makefile.inc | 4 +--- src/arch/x86/lib/pci_ops_auto.c | 9 ++++++++- 3 files changed, 13 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 078ae95..bc01c9c 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -96,4 +96,8 @@ config LITTLE_ENDIAN bool default !BIG_ENDIAN +config PCI_CONF2 + bool + default n + endmenu diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc index 3f4dc95..96fb9b0 100644 --- a/src/arch/x86/lib/Makefile.inc +++ b/src/arch/x86/lib/Makefile.inc @@ -1,10 +1,8 @@ ramstage-y += c_start.S ramstage-y += cpu.c ramstage-y += pci_ops_conf1.c -ramstage-y += pci_ops_conf2.c - +ramstage-$(CONFIG_PCI_CONF2) += pci_ops_conf2.c ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c - ramstage-y += pci_ops_auto.c ramstage-y += exception.c ramstage-$(CONFIG_IOAPIC) += ioapic.c diff --git a/src/arch/x86/lib/pci_ops_auto.c b/src/arch/x86/lib/pci_ops_auto.c index 92eedd3..58e098b 100644 --- a/src/arch/x86/lib/pci_ops_auto.c +++ b/src/arch/x86/lib/pci_ops_auto.c @@ -6,6 +6,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> +#if CONFIG_PCI_CONF2 /* * Before we decide to use direct hardware access mechanisms, we try to do some * trivial checks to ensure it at least _seems_ to be working -- we just test @@ -41,7 +42,7 @@ static int pci_sanity_check(const struct pci_bus_operations *o) return 0; } -struct pci_bus_operations *pci_bus_fallback_ops = NULL; +static struct pci_bus_operations *pci_bus_fallback_ops = NULL; static const struct pci_bus_operations *pci_check_direct(void) { @@ -89,6 +90,12 @@ const struct pci_bus_operations *pci_remember_direct(void) pci_bus_fallback_ops = (struct pci_bus_operations *)pci_check_direct(); return pci_bus_fallback_ops; } +#else +const struct pci_bus_operations *pci_remember_direct(void) +{ + return &pci_cf8_conf1; +} +#endif /** Set the method to be used for PCI, type I or type II */

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Patch set updated for coreboot: 3759c0a vga_io.c is not needed unless CONFIG_VGA is set
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/753 -gerrit commit 3759c0aade0964783da50516075c3caebb8e0ed4 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Nov 17 11:13:36 2011 -0800 vga_io.c is not needed unless CONFIG_VGA is set hence disable it. Change-Id: I7b406251a2f3830748140a111f76f2792fe923ed Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/pc80/vga/Makefile.inc | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/pc80/vga/Makefile.inc b/src/pc80/vga/Makefile.inc index 0ca7896..d4b726a 100644 --- a/src/pc80/vga/Makefile.inc +++ b/src/pc80/vga/Makefile.inc @@ -1,4 +1,4 @@ -ramstage-y += vga_io.c +ramstage-$(CONFIG_VGA) += vga_io.c ramstage-$(CONFIG_VGA) += vga_palette.c ramstage-$(CONFIG_VGA) += vga_font_8x16.c ramstage-$(CONFIG_VGA) += vga.c

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Patch set updated for coreboot: c4df5da Fix warnings in coreboot utilities.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/752 -gerrit commit c4df5da25f4e8f76c51e593306d94bf648ad4142 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Nov 14 12:40:34 2011 -0800 Fix warnings in coreboot utilities. Fix some poor programming practice (breaks of strict aliasing as well as not checking the return value of read) Change-Id: I08b2e8d1bbc908f6b1f26d25cb3a4b03d818e124 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- util/inteltool/cpu.c | 6 ++++-- util/inteltool/inteltool.c | 4 +++- util/nvramtool/cli/nvramtool.c | 3 ++- 3 files changed, 9 insertions(+), 4 deletions(-) diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c index 20748bd..3bffa4e 100644 --- a/util/inteltool/cpu.c +++ b/util/inteltool/cpu.c @@ -67,8 +67,10 @@ msr_t rdmsr(int addr) } if (read(fd_msr, buf, 8) == 8) { - msr.lo = *(uint32_t *)buf; - msr.hi = *(uint32_t *)(buf + 4); + msr.lo = buf[0] | (buf[1] << 8) | + (buf[2] << 16) | (buf[3] << 24); + msr.hi = buf[4] | (buf[5] << 8) | + (buf[6] << 16) | (buf[7] << 24); return msr; } diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 6b99605..e5c2b86 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -21,6 +21,7 @@ #include <stdio.h> #include <stdlib.h> +#include <inttypes.h> #include <getopt.h> #include <fcntl.h> #include <sys/mman.h> @@ -99,7 +100,8 @@ void *map_physical(uint64_t phys_addr, size_t len) fd_mem, (off_t) phys_addr); if (virt_addr == MAP_FAILED) { - printf("Error mapping physical memory 0x%08lx[0x%zx]\n", phys_addr, len); + printf("Error mapping physical memory 0x%08" PRIx64 "[0x%zx]\n", + phys_addr, len); return NULL; } diff --git a/util/nvramtool/cli/nvramtool.c b/util/nvramtool/cli/nvramtool.c index 11a1a70..20097b8 100644 --- a/util/nvramtool/cli/nvramtool.c +++ b/util/nvramtool/cli/nvramtool.c @@ -143,7 +143,8 @@ int main(int argc, char *argv[]) if (fd_stat.st_size < 128) { lseek(fd, 127, SEEK_SET); - write(fd, "\0", 1); + if (write(fd, "\0", 1) != 1) + fprintf(stderr, "Write failed.\n"); fsync(fd); }

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Patch set updated for coreboot: ea93a3c use movsl for copying resume memory back
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/755 -gerrit commit ea93a3c17ffcdf9e8cf08a189195a141af646cc7 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Nov 17 13:03:38 2011 -0800 use movsl for copying resume memory back It's not significantly faster, but easier to read and smaller. Change-Id: Ibab0b478873912d67bf1f07743f628586353368a Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/boot/wakeup.S | 20 ++++---------------- 1 files changed, 4 insertions(+), 16 deletions(-) diff --git a/src/arch/x86/boot/wakeup.S b/src/arch/x86/boot/wakeup.S index a1df4d5..f12b176 100644 --- a/src/arch/x86/boot/wakeup.S +++ b/src/arch/x86/boot/wakeup.S @@ -38,23 +38,11 @@ __wakeup: movw %ax, (__wakeup_segment) /* Then overwrite coreboot with our backed up memory */ - movl 8(%esp), %esi - movl 12(%esp), %edi - movl 16(%esp), %ecx + movl 8(%esp), %esi + movl 12(%esp), %edi + movl 16(%esp), %ecx shrl $4, %ecx -1: - movl 0(%esi),%eax - movl 4(%esi),%edx - movl 8(%esi),%ebx - movl 12(%esi),%ebp - addl $16,%esi - subl $1,%ecx - movl %eax,0(%edi) - movl %edx,4(%edi) - movl %ebx,8(%edi) - movl %ebp,12(%edi) - leal 16(%edi),%edi - jne 1b + rep movsl /* Activate the right segment descriptor real mode. */ ljmp $0x28, $RELOCATED(1f)

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coreboot March 2012