coreboot March 2012

coreboot@coreboot.org

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718 discussions

Re: [coreboot] Bug when I compiling coreboot with SeaBIOS
by Kevin O'Connor 08 Mar '12

08 Mar '12

On Wed, Mar 07, 2012 at 10:30:17AM -0800, ron minnich wrote: > The solution in other projects I have worked on is to have an > initialized struct and just copy it at runtime to the right place. > This gets around all the issues with ld (which have been issues in > various ways for 12 years now ... just different ones :) > > How big are the tables? If they're not that big then just copying them > to where they need to be at startup might be the best solution. LD is > going to continue to break, always has and always will. Just a > thought. > > This fails on recent arch and ubuntu. If you can find a way not to use > this kind of LD trick, life will be easier. It's not really a trick - we're just asking LD to put sections at specific addresses - it's real basic stuff. > Of course if this is going to mess up entry points then we're out of luck. It's code entry points as well. I can't think of an easy way to do that as things get real messy when relocating code due to relative offsets in the code. It's doable, but it quickly reaches the complexity of just implementing a poor-man's LD replacement. -Kevin

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New patch to review for coreboot: 55312ae Fix AMD Agesa leaking Kconfig
by Kyösti Mälkki 08 Mar '12

08 Mar '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/773 -gerrit commit 55312ae0554da57c7becaef099ef240b4904ee5b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Mar 7 23:21:35 2012 +0200 Fix AMD Agesa leaking Kconfig Kconfig leaked XIP_ROM_SIZE to other platforms and also defined obsolete option XIP_ROM_BASE. Rename AMD_AGESA to CPU_AMD_AGESA. Also alias CPU_AMD_AGESA as NORTHBRIDGE_AMD_AGESA. Change-Id: Ic7891012220e1bef758a5a39002b66971d5206e3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/init/bootblock.ld | 2 +- src/cpu/amd/Makefile.inc | 2 +- src/cpu/amd/agesa/Kconfig | 10 ++++++---- src/cpu/amd/agesa/family15/Kconfig | 5 ----- src/mainboard/advansus/a785e-i/Makefile.inc | 2 +- src/mainboard/amd/inagua/Kconfig | 5 +---- src/mainboard/amd/persimmon/Kconfig | 5 +---- src/mainboard/amd/south_station/Kconfig | 5 +---- src/mainboard/amd/torpedo/Kconfig | 5 +---- src/mainboard/amd/union_station/Kconfig | 5 +---- src/mainboard/asrock/e350m1/Kconfig | 5 +---- src/mainboard/asus/m5a88-v/Makefile.inc | 2 +- src/mainboard/avalue/eax-785e/Makefile.inc | 2 +- src/northbridge/amd/Makefile.inc | 2 +- src/northbridge/amd/agesa/Kconfig | 7 +++++++ 15 files changed, 25 insertions(+), 39 deletions(-) diff --git a/src/arch/x86/init/bootblock.ld b/src/arch/x86/init/bootblock.ld index bde0430..fd4d3db 100644 --- a/src/arch/x86/init/bootblock.ld +++ b/src/arch/x86/init/bootblock.ld @@ -51,5 +51,5 @@ SECTIONS *(.eh_frame); } - _bogus = ASSERT((SIZEOF(.bss) + SIZEOF(.data)) == 0 || CONFIG_AMD_AGESA, "Do not use global variables in romstage"); + _bogus = ASSERT((SIZEOF(.bss) + SIZEOF(.data)) == 0 || CONFIG_CPU_AMD_AGESA, "Do not use global variables in romstage"); } diff --git a/src/cpu/amd/Makefile.inc b/src/cpu/amd/Makefile.inc index 2ea376a..6663d14 100644 --- a/src/cpu/amd/Makefile.inc +++ b/src/cpu/amd/Makefile.inc @@ -14,4 +14,4 @@ subdirs-$(CONFIG_CPU_AMD_GEODE_LX) += geode_lx subdirs-$(CONFIG_CPU_AMD_SC520) += sc520 subdirs-$(CONFIG_CPU_AMD_SOCKET_S1G1) += socket_S1G1 -subdirs-$(CONFIG_AMD_AGESA) += agesa +subdirs-$(CONFIG_CPU_AMD_AGESA) += agesa diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 631724b..214aca3 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -17,13 +17,12 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -config AMD_AGESA +config CPU_AMD_AGESA bool + default y if CPU_AMD_AGESA_FAMILY15 default n -config XIP_ROM_BASE - hex - default 0xfff00000 +if CPU_AMD_AGESA config XIP_ROM_SIZE hex @@ -40,3 +39,6 @@ source src/cpu/amd/agesa/family10/Kconfig source src/cpu/amd/agesa/family12/Kconfig source src/cpu/amd/agesa/family14/Kconfig source src/cpu/amd/agesa/family15/Kconfig + +endif # CPU_AMD_AGESA + diff --git a/src/cpu/amd/agesa/family15/Kconfig b/src/cpu/amd/agesa/family15/Kconfig index 0f2f920..c1528f6 100644 --- a/src/cpu/amd/agesa/family15/Kconfig +++ b/src/cpu/amd/agesa/family15/Kconfig @@ -20,7 +20,6 @@ config CPU_AMD_AGESA_FAMILY15 bool select PCI_IO_CFG_EXT - select AMD_AGESA if CPU_AMD_AGESA_FAMILY15 @@ -58,10 +57,6 @@ config CDB hex default 0x18 -config XIP_ROM_BASE - hex - default 0xfff80000 - config XIP_ROM_SIZE hex default 0x80000 diff --git a/src/mainboard/advansus/a785e-i/Makefile.inc b/src/mainboard/advansus/a785e-i/Makefile.inc index 737bb1c..d69a9bf 100755 --- a/src/mainboard/advansus/a785e-i/Makefile.inc +++ b/src/mainboard/advansus/a785e-i/Makefile.inc @@ -3,7 +3,7 @@ ramstage-y += reset.c #SB800 CIMx share AGESA V5 lib code -ifneq ($(CONFIG_AMD_AGESA),y) +ifneq ($(CONFIG_CPU_AMD_AGESA),y) AGESA_ROOT ?= src/vendorcode/amd/agesa/f14 romstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c ramstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig index a5920af..acc9e45 100644 --- a/src/mainboard/amd/inagua/Kconfig +++ b/src/mainboard/amd/inagua/Kconfig @@ -42,10 +42,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_2048 select ENABLE_APIC_EXT_ID select GFXUMA - -config AMD_AGESA - bool - default y + select CPU_AMD_AGESA config MAINBOARD_DIR string diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig index e01e101..7cb5c16 100644 --- a/src/mainboard/amd/persimmon/Kconfig +++ b/src/mainboard/amd/persimmon/Kconfig @@ -41,10 +41,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 select GFXUMA - -config AMD_AGESA - bool - default y + select CPU_AMD_AGESA config MAINBOARD_DIR string diff --git a/src/mainboard/amd/south_station/Kconfig b/src/mainboard/amd/south_station/Kconfig index fb41cec..69c4874 100644 --- a/src/mainboard/amd/south_station/Kconfig +++ b/src/mainboard/amd/south_station/Kconfig @@ -42,10 +42,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_4096 select GFXUMA select UDELAY_LAPIC - -config AMD_AGESA - bool - default y + select CPU_AMD_AGESA config MAINBOARD_DIR string diff --git a/src/mainboard/amd/torpedo/Kconfig b/src/mainboard/amd/torpedo/Kconfig index f368279..1a45724 100755 --- a/src/mainboard/amd/torpedo/Kconfig +++ b/src/mainboard/amd/torpedo/Kconfig @@ -44,10 +44,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_2048 select ENABLE_APIC_EXT_ID select GFXUMA - -config AMD_AGESA - bool - default y + select CPU_AMD_AGESA config MAINBOARD_DIR string diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig index 194a39d..9c1a779 100644 --- a/src/mainboard/amd/union_station/Kconfig +++ b/src/mainboard/amd/union_station/Kconfig @@ -42,10 +42,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_2048 select GFXUMA select UDELAY_LAPIC - -config AMD_AGESA - bool - default y + select CPU_AMD_AGESA config MAINBOARD_DIR string diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig index 8324fa4..c8d5218 100644 --- a/src/mainboard/asrock/e350m1/Kconfig +++ b/src/mainboard/asrock/e350m1/Kconfig @@ -42,10 +42,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 select GFXUMA - -config AMD_AGESA - bool - default y + select CPU_AMD_AGESA config MAINBOARD_DIR string diff --git a/src/mainboard/asus/m5a88-v/Makefile.inc b/src/mainboard/asus/m5a88-v/Makefile.inc index b55a0c7..35b2043 100644 --- a/src/mainboard/asus/m5a88-v/Makefile.inc +++ b/src/mainboard/asus/m5a88-v/Makefile.inc @@ -1,7 +1,7 @@ ramstage-y += reset.c #SB800 CIMx share AGESA V5 lib code -ifneq ($(CONFIG_AMD_AGESA),y) +ifneq ($(CONFIG_CPU_AMD_AGESA),y) AGESA_ROOT ?= src/vendorcode/amd/agesa/f14 romstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c ramstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c diff --git a/src/mainboard/avalue/eax-785e/Makefile.inc b/src/mainboard/avalue/eax-785e/Makefile.inc index 737bb1c..d69a9bf 100644 --- a/src/mainboard/avalue/eax-785e/Makefile.inc +++ b/src/mainboard/avalue/eax-785e/Makefile.inc @@ -3,7 +3,7 @@ ramstage-y += reset.c #SB800 CIMx share AGESA V5 lib code -ifneq ($(CONFIG_AMD_AGESA),y) +ifneq ($(CONFIG_CPU_AMD_AGESA),y) AGESA_ROOT ?= src/vendorcode/amd/agesa/f14 romstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c ramstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c diff --git a/src/northbridge/amd/Makefile.inc b/src/northbridge/amd/Makefile.inc index c438473..7e85d08 100644 --- a/src/northbridge/amd/Makefile.inc +++ b/src/northbridge/amd/Makefile.inc @@ -3,6 +3,6 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_AMDK8) += amdk8 subdirs-$(CONFIG_NORTHBRIDGE_AMD_GX1) += gx1 subdirs-$(CONFIG_NORTHBRIDGE_AMD_GX2) += gx2 subdirs-$(CONFIG_NORTHBRIDGE_AMD_LX) += lx +subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA) += agesa -subdirs-$(CONFIG_AMD_AGESA) += agesa subdirs-$(CONFIG_AMD_NB_CIMX) += cimx diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig index 2ed9fd5..2ee921b 100644 --- a/src/northbridge/amd/agesa/Kconfig +++ b/src/northbridge/amd/agesa/Kconfig @@ -17,6 +17,12 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +config NORTHBRIDGE_AMD_AGESA + bool + default CPU_AMD_AGESA + +if NORTHBRIDGE_AMD_AGESA + config CONSOLE_VGA_MULTI bool default n @@ -26,3 +32,4 @@ source src/northbridge/amd/agesa/family12/Kconfig source src/northbridge/amd/agesa/family14/Kconfig source src/northbridge/amd/agesa/family15/Kconfig +endif # NORTHBRIDGE_AMD_AGESA

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Patch set updated for coreboot: 27f1d38 Add infrastructure for global data in the CAR phase of boot.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/727 -gerrit commit 27f1d389c5d3e80e402ff637a48f4f7f6a156998 Author: Gabe Black <gabeblack(a)google.com> Date: Sat Oct 1 04:27:32 2011 -0700 Add infrastructure for global data in the CAR phase of boot. The cbmem console structure and car global data are put in their own section, with the cbmem console coming after the global data. These areas are linked to be where CAR is available and at the very bottom of the stack. There is one shortcoming of this change: The section created by this change needs to be stripped out by the Makefile since leaving it in confuses cbfstool when it installs the stage in the image. I would like to make the tools link those symbols at the right location but leave allocation of that space out of the ELF. Change-Id: Iccfb99b128d59c5b7d6164796d21ba46d2a674e0 Signed-off-by: Gabe Black <gabeblack(a)google.com> --- src/arch/x86/Makefile.inc | 2 +- src/arch/x86/init/bootblock.ld | 7 +++++++ src/include/cpu/x86/car.h | 31 +++++++++++++++++++++++++++++++ src/lib/cbmem_console.c | 7 +++++-- 4 files changed, 44 insertions(+), 3 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 624b510..aeb4875 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -272,7 +272,7 @@ $(obj)/coreboot.pre: $(obj)/coreboot.romstage $(obj)/coreboot.pre1 $(CBFSTOOL) rm -f $@ cp $(obj)/coreboot.pre1 $@ $(CBFSTOOL) $@ add-stage $(obj)/romstage.elf \ - $(CONFIG_CBFS_PREFIX)/romstage x 0x$(shell cat $(obj)/location.txt) + $(CONFIG_CBFS_PREFIX)/romstage x 0x$(shell cat $(obj)/location.txt) #FIXME: location.txt might require an offset of header size ####################################################################### diff --git a/src/arch/x86/init/bootblock.ld b/src/arch/x86/init/bootblock.ld index bde0430..6f8ade8 100644 --- a/src/arch/x86/init/bootblock.ld +++ b/src/arch/x86/init/bootblock.ld @@ -51,5 +51,12 @@ SECTIONS *(.eh_frame); } + . = CONFIG_DCACHE_RAM_BASE; + .car.data . (NOLOAD) : { + *(.car.global_data); + *(.car.cbmem_console); + } + + _bogus = ASSERT((SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full"); _bogus = ASSERT((SIZEOF(.bss) + SIZEOF(.data)) == 0 || CONFIG_AMD_AGESA, "Do not use global variables in romstage"); } diff --git a/src/include/cpu/x86/car.h b/src/include/cpu/x86/car.h new file mode 100644 index 0000000..2d2af03 --- /dev/null +++ b/src/include/cpu/x86/car.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#ifndef CPU_X86_CAR_H +#define CPU_X86_CAR_H + +#ifdef __PRE_RAM__ +#define CAR_GLOBAL __attribute__((section(".car.global_data,\"w\",@nobits#"))) +#define CAR_CBMEM __attribute__((section(".car.cbmem_console,\"w\",@nobits#"))) +#else +#define CAR_GLOBAL +#define CAR_CBMEM +#endif + +#endif diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index b58de48..431ea1f 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -19,6 +19,7 @@ #include <console/console.h> #include <cbmem.h> +#include <cpu/x86/car.h> #include <string.h> /* @@ -39,7 +40,9 @@ struct cbmem_console { * ram space is used for the console buffer storage. The size and location of * the area are defined in the config. */ -#define cbmem_console_p ((struct cbmem_console *)CONFIG_DCACHE_RAM_BASE) + +static struct cbmem_console car_cbmem_console CAR_CBMEM; +#define cbmem_console_p (&car_cbmem_console) /* * Once DRAM is initialized and the cache as ram mode is disabled, while still @@ -92,7 +95,7 @@ void cbmemc_tx_byte(unsigned char data) * DCACHE_RAM_BASE), use the redirect pointer to find out where the * actual console buffer is. */ - if ((u32)&cursor < (u32)CONFIG_DCACHE_RAM_BASE) + if ((uintptr_t)&cursor < (uintptr_t)&car_cbmem_console) cbm_cons_p = CBMEM_CONSOLE_REDIRECT; #endif if (!cbm_cons_p)

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Patch set updated for coreboot: 9f8dda7 Fix typos in src/console/Kconfig
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/726 -gerrit commit 9f8dda7328a023fb7ad0bb2960db589714c69ff2 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Oct 4 16:21:17 2011 -0700 Fix typos in src/console/Kconfig - cash -> Cache - make the new size of the cbmem console buffer the default Change-Id: Ia906077257e93622ad56bc54a42f8184ade78b29 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/console/Kconfig | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index fefbe2e..2cfc4db 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -201,7 +201,7 @@ config CONSOLE_CBMEM config CONSOLE_CBMEM_BUFFER_SIZE depends on CONSOLE_CBMEM hex "Room allocated for console output in CBMEM" - default 0xae00 + default 0x10000 help Space allocated for console output storage in CBMEM. The default value (almost 45K or 0xaeoo bytes) is large enough to accommodate @@ -209,7 +209,7 @@ config CONSOLE_CBMEM_BUFFER_SIZE config CONSOLE_CAR_BUFFER_SIZE depends on CONSOLE_CBMEM - hex "Room allocated for console output in cash as RAM" + hex "Room allocated for console output in Cache as RAM" default 0xc00 help Console is used before RAM is initialized. This is the room reserved

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Patch set updated for coreboot: 3f5e2ae Increase CBMEM to accommodate larger console.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/725 -gerrit commit 3f5e2ae69ac3c76349d7d65e5d4d380b1ecfb1d2 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Oct 4 10:44:16 2011 -0700 Increase CBMEM to accommodate larger console. This change adds 128K to the memory amount set aside for CBMEM in case the CBMEM console is enabled (to keep the CBMEM 128K byte aligned). The console buffer size is being set to 64K, which is enough to accommodate the most verbose coreboot console and u-boot console. Change-Id: If583013dfb210de5028d69577675095c6fe2f3ab Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/include/cbmem.h | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index a19ec5a..6a48dd2 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -21,7 +21,12 @@ #define _CBMEM_H_ /* Reserve 128k for ACPI and other tables */ +#if CONFIG_CONSOLE_CBMEM +#define HIGH_MEMORY_DEF_SIZE ( 256 * 1024 ) +#else #define HIGH_MEMORY_DEF_SIZE ( 128 * 1024 ) +#endif + #ifndef __PRE_RAM__ extern uint64_t high_tables_base, high_tables_size; #endif

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Patch set updated for coreboot: 2b91139 Refactor publishing CBMEM addresses through coreboot table.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/724 -gerrit commit 2b91139bc6554adf37436bbe9cb3526aca3af587 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Mon Oct 3 14:58:57 2011 -0700 Refactor publishing CBMEM addresses through coreboot table. We need to provide u-boot access to several different CBMEM sections. To do that, a common coreboot table structure is used, just different tags match different coreboot table sections. Also, the code is added to export CBMEM console and MRC cache addresses through the same mechanism. Change-Id: I63adb67093b8b50ee61b0deb0b56ebb2c4856895 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/arch/x86/boot/coreboot_table.c | 59 +++++++++++++++++++++++++++++------- src/include/boot/coreboot_tables.h | 6 ++- 2 files changed, 52 insertions(+), 13 deletions(-) diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c index f189e76..f29481b 100644 --- a/src/arch/x86/boot/coreboot_table.c +++ b/src/arch/x86/boot/coreboot_table.c @@ -175,22 +175,40 @@ static void lb_framebuffer(struct lb_header *header) #endif } -#if CONFIG_COLLECT_TIMESTAMPS -static void lb_tsamp(struct lb_header *header) +static void add_cbmem_pointers(struct lb_header *header) { - struct lb_tstamp *tstamp; - void *tstamp_table = cbmem_find(CBMEM_ID_TIMESTAMP); + /* + * These CBMEM sections' addresses are included in the coreboot table + * with the appropriate tags. + */ + const struct section_id { + int cbmem_id; + int table_tag; + } section_ids[] = { + {CBMEM_ID_TIMESTAMP, LB_TAG_TIMESTAMPS}, + {CBMEM_ID_MRCDATA, LB_TAG_MRC_CACHE}, + {CBMEM_ID_CONSOLE, LB_TAG_CBMEM_CONSOLE} + }; + int i; - if (!tstamp_table) - return; + for (i = 0; i < ARRAY_SIZE(section_ids); i++) { + const struct section_id *sid = section_ids + i; + struct lb_cbmem_ref *cbmem_ref; + void *cbmem_addr = cbmem_find(sid->cbmem_id); - tstamp = (struct lb_tstamp *)lb_new_record(header); - tstamp->tag = LB_TAG_TIMESTAMPS; - tstamp->size = sizeof(*tstamp); - tstamp->tstamp_tab = tstamp_table; + if (!cbmem_addr) + continue; /* This section is not present */ + cbmem_ref = (struct lb_cbmem_ref *)lb_new_record(header); + if (!cbmem_ref) { + printk(BIOS_ERR, "No more room in coreboot table!\n"); + break; + } + cbmem_ref->tag = sid->table_tag; + cbmem_ref->size = sizeof(*cbmem_ref); + cbmem_ref->cbmem_addr = cbmem_addr; + } } -#endif static struct lb_mainboard *lb_mainboard(struct lb_header *header) { @@ -633,9 +651,28 @@ unsigned long write_coreboot_table( /* Record our framebuffer */ lb_framebuffer(head); +<<<<<<< HEAD #if CONFIG_COLLECT_TIMESTAMPS lb_tsamp(head); #endif +======= +#if CONFIG_CHROMEOS + /* Record our GPIO settings (ChromeOS specific) */ + lb_gpios(head); + + /* pass along the VDAT buffer adress */ + lb_vdat(head); +#endif +#if CONFIG_ADD_FDT + /* + * Copy FDT from CBFS into the coreboot table possibly augmenting it + * along the way. + */ + lb_fdt(head, serial); +#endif + add_cbmem_pointers(head); + +>>>>>>> 3fc47a1... Refactor publishing CBMEM addresses through coreboot table. /* Remember where my valid memory ranges are */ return lb_table_fini(head, 1); diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index 46d6489..5535a38 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -196,11 +196,13 @@ struct lb_framebuffer { }; #define LB_TAG_TIMESTAMPS 0x0016 -struct lb_tstamp { +#define LB_TAG_CBMEM_CONSOLE 0x0017 +#define LB_TAG_MRC_CACHE 0x0018 +struct lb_cbmem_ref { uint32_t tag; uint32_t size; - void *tstamp_tab; + void *cbmem_addr; }; /* The following structures are for the cmos definitions table */

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Patch set updated for coreboot: 149337f Introduce utility for parsing CBMEM contents.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/723 -gerrit commit 149337fe6571b33b248f05bd72a21e4c7f715e49 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri Sep 30 14:21:03 2011 -0700 Introduce utility for parsing CBMEM contents. This is a python script which is supposed to run on a target which is controlled by coreboot. The script examines top of memory looking for the CBMEM signature at addresses aligned at 128K boundary. Once the script finds the CBMEM, it iterates through the CBMEM table of contents and parses two entries: the timestamps and the console log. This submission is just a template to build upon to create a utility for displaying CBMEM information while running Linux on the target. BUG=chrome-os-partner:4200 TEST=manual See test description of d81e6b8c8d41f2d6 for test procedure. Change-Id: Id863a8598eaadc2d20d728f9186843e65cbe6f37 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Reviewed-on: https://gerrit-int.chromium.org/5942 Tested-by: Vadim Bendebury <vbendeb(a)google.com> Reviewed-by: Stefan Reinauer <reinauer(a)google.com> --- util/cbmem/cbmem.py | 204 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 204 insertions(+), 0 deletions(-) diff --git a/util/cbmem/cbmem.py b/util/cbmem/cbmem.py new file mode 100755 index 0000000..3e8476d --- /dev/null +++ b/util/cbmem/cbmem.py @@ -0,0 +1,204 @@ +#!/usr/bin/python +# +# cbmem.py - Linux space CBMEM contents parser +# +# Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +''' +Parse and display CBMEM contents. + +This module is meant to run on systems with coreboot based firmware. + +When started, it determines the amount of DRAM installed on the system, and +then scans the top area of DRAM (right above the available memory size) +looking for the CBMEM base signature at locations aligned at 0x20000 +boundaries. + +Once it finds the CBMEM signature, the utility parses the contents, reporting +the section IDs/sizes and also reporting the contents of the tiemstamp and +console sections. +''' + +import mmap +import re +import struct +import sys +import time + +# These definitions follow src/include/cbmem.h +CBMEM_MAGIC = 0x434f5245 +CBMEM_MAX_ENTRIES = 16 + +CBMEM_ENTRY_FORMAT = '@LLQQ' +CONSOLE_HEADER_FORMAT = '@LL' +TIMESTAMP_HEADER_FORMAT = '@QLL' +TIMESTAMP_ENTRY_FORMAT = '@LQ' + +mf_fileno = 0 # File number of the file providing access to memory. + +def align_up(base, alignment): + '''Increment to the alignment boundary. + + Return the next integer larger than 'base' and divisible by 'alignment'. + ''' + + return base + alignment - base % alignment + +def normalize_timer(value, freq): + '''Convert timer reading into microseconds. + + Get the free running clock counter value, divide it by the clock frequency + and multiply by 1 million to get reading in microseconds. + + Then convert the value into an ASCII string with groups of three digits + separated by commas. + + Inputs: + value: int, the clock reading + freq: float, the clock frequency + + Returns: + A string presenting 'value' in microseconds. + ''' + + result = [] + value = int(value * 1000000.0 / freq) + svalue = '%d' % value + vlength = len(svalue) + remainder = vlength % 3 + if remainder: + result.append(svalue[0:remainder]) + while remainder < vlength: + result.append(svalue[remainder:remainder+3]) + remainder = remainder + 3 + return ','.join(result) + +def get_cpu_freq(): + '''Retrieve CPU frequency from sysfs. + + Use /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq as the source. + ''' + freq_str = open('/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq' + ).read() + # Convert reading into Hertz + return float(freq_str) * 1000.0 + +def get_mem_size(): + '''Retrieve amount of memory available to the CPU from /proc/meminfo.''' + mult = { + 'kB': 1024 + } + meminfo = open('/proc/meminfo').read() + m = re.search('MemTotal:.*\n', meminfo) + mem_string = re.search('MemTotal:.*\n', meminfo).group(0) + (_, size, mult_name) = mem_string.split() + return int(size) * mult[mult_name] + +def parse_mem_at(addr, format): + '''Read and parse a memory location. + + This function reads memory at the passed in address, parses it according + to the passed in format specification and returns a list of values. + + The first value in the list is the size of data matching the format + expression, and the rest of the elements of the list are the actual values + retrieved using the format. + ''' + + size = struct.calcsize(format) + delta = addr % 4096 # mmap requires the offset to be page size aligned. + mm = mmap.mmap(mf_fileno, size + delta, + mmap.MAP_PRIVATE, offset=(addr - delta)) + buf = mm.read(size + delta) + mm.close() + rv = [size,] + list(struct.unpack(format, buf[delta:size + delta + 1])) + return rv + +def dprint(text): + '''Debug print function. + + Edit it to get the debug output. + ''' + + if False: + print text + +def process_timers(base): + '''Scan the array of timestamps found in CBMEM at address base. + + For each timestamp print the timer ID and the value in microseconds. + ''' + + (step, base_time, max_entr, entr) = parse_mem_at( + base, TIMESTAMP_HEADER_FORMAT) + + print('\ntime base %d, total entries %d' % (base_time, entr)) + clock_freq = get_cpu_freq() + base = base + step + for i in range(entr): + (step, timer_id, timer_value) = parse_mem_at( + base, TIMESTAMP_ENTRY_FORMAT) + print '%d:%s ' % (timer_id, normalize_timer(timer_value, clock_freq)), + base = base + step + print + +def process_console(base): + '''Dump the console log buffer contents found at address base.''' + + (step, size, cursor) = parse_mem_at(base, CONSOLE_HEADER_FORMAT) + print 'cursor at %d\n' % cursor + + cons_string_format = '%ds' % min(cursor, size) + (_, cons_text) = parse_mem_at(base + step, cons_string_format) + print cons_text + print '\n' + +mem_alignment = 1024 * 1024 * 1024 # 1 GBytes +table_alignment = 128 * 1024 + +mem_size = get_mem_size() + +# start at memory address aligned at 128K. +offset = align_up(mem_size, table_alignment) + +dprint('mem_size %x offset %x' %(mem_size, offset)) +mf = open("/dev/mem") +mf_fileno = mf.fileno() + +while offset % mem_alignment: # do not cross the 1G boundary while searching + (step, magic, mid, base, size) = parse_mem_at(offset, CBMEM_ENTRY_FORMAT) + if magic == CBMEM_MAGIC: + offset = offset + step + break + offset += table_alignment +else: + print 'Did not find the CBMEM' + sys.exit(0) + +for i in (range(1, CBMEM_MAX_ENTRIES)): + (_, magic, mid, base, size) = parse_mem_at(offset, CBMEM_ENTRY_FORMAT) + if mid == 0: + break + + print '%x, %x, %x' % (mid, base, size) + if mid == 0x54494d45: + process_timers(base) + if mid == 0x434f4e53: + process_console(base) + + offset = offset + step + +mf.close()

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Patch set updated for coreboot: be71426 CBMEM CONSOLE: Enable coreboot CBMEM console.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/722 -gerrit commit be714260ace953f3f5f438a14054030ddb8a0c2e Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri Sep 30 12:02:18 2011 -0700 CBMEM CONSOLE: Enable coreboot CBMEM console. The appropriate Makefiles are modified to include the required source code in compilation. Change-Id: I91842b1ba0f89d611d3249b63c020a2713a9124f Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/console/Makefile.inc | 2 ++ src/lib/Makefile.inc | 2 ++ 2 files changed, 4 insertions(+), 0 deletions(-) diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index 4a30918..f3b8758 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -18,6 +18,8 @@ driver-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem_console.c driver-$(CONFIG_USBDEBUG) += usbdebug_console.c driver-$(CONFIG_CONSOLE_LOGBUF) += logbuf_console.c driver-$(CONFIG_CONSOLE_NE2K) += ne2k_console.c +driver-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c + $(obj)/console/console.ramstage.o : $(obj)/build.h $(obj)/console/console.romstage.o : $(obj)/build.h diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index db640dc..45cb788 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -11,6 +11,7 @@ romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c romstage-$(CONFIG_HAVE_ACPI_RESUME) += cbmem.c romstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c +romstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c romstage-$(CONFIG_CONSOLE_NE2K) += compute_ip_checksum.c romstage-$(CONFIG_USBDEBUG) += usbdebug.c @@ -34,6 +35,7 @@ ramstage-y += clog2.c ramstage-y += cbmem.c ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c +ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c ramstage-$(CONFIG_USBDEBUG) += usbdebug.c ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c ramstage-$(CONFIG_TRACE) += trace.c

1 0

Patch set updated for coreboot: 91462b5 CBMEM CONSOLE: Add code using the new console driver.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/721 -gerrit commit 91462b57c5a5a6e8475241d028d58b4a84970ec8 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri Sep 30 11:16:49 2011 -0700 CBMEM CONSOLE: Add code using the new console driver. The new added code is compiled in when the CBMEM_CONSOLE config flag is enabled. Change-Id: Ifd1f492ce6321412a014333babbc5b3f14635988 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/arch/x86/lib/romcc_console.c | 3 +++ src/arch/x86/lib/romstage_console.c | 3 +++ src/boot/hardwaremain.c | 3 +++ src/console/console.c | 5 ++++- 4 files changed, 13 insertions(+), 1 deletions(-) diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c index 13ee1f0..0e1f4e6 100644 --- a/src/arch/x86/lib/romcc_console.c +++ b/src/arch/x86/lib/romcc_console.c @@ -46,6 +46,9 @@ static void __console_tx_byte(unsigned char byte) #if CONFIG_CONSOLE_NE2K ne2k_append_data_byte(byte, CONFIG_CONSOLE_NE2K_IO_PORT); #endif +#if CONFIG_CONSOLE_CBMEM + cbmemc_tx_byte(byte); +#endif } static void __console_tx_nibble(unsigned nibble) diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index 8adb3ba..0f22727 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -46,6 +46,9 @@ static void console_tx_byte(unsigned char byte) #if CONFIG_CONSOLE_NE2K ne2k_append_data(&byte, 1, CONFIG_CONSOLE_NE2K_IO_PORT); #endif +#if CONFIG_CONSOLE_CBMEM + cbmemc_tx_byte(byte); +#endif } static void console_tx_flush(void) diff --git a/src/boot/hardwaremain.c b/src/boot/hardwaremain.c index 3d15b55..9b293c0 100644 --- a/src/boot/hardwaremain.c +++ b/src/boot/hardwaremain.c @@ -92,6 +92,9 @@ void hardwaremain(int boot_complete) #if CONFIG_WRITE_HIGH_TABLES == 1 cbmem_initialize(); +#if CONFIG_CONSOLE_CBMEM + cbmemc_reinit(); +#endif #endif #if CONFIG_HAVE_ACPI_RESUME == 1 suspend_resume(); diff --git a/src/console/console.c b/src/console/console.c index d933668..8f60f04 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -87,7 +87,7 @@ int console_tst_byte(void) return 0; } -#else +#else // __PRE_RAM__ ^^^ NOT defined vvv defined void console_init(void) { @@ -104,6 +104,9 @@ void console_init(void) #if CONFIG_CONSOLE_NE2K ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT); #endif +#if CONFIG_CONSOLE_CBMEM + cbmemc_init(); +#endif static const char console_test[] = "\n\ncoreboot-" COREBOOT_VERSION

1 0

Patch set updated for coreboot: 1017143 CBMEM CONSOLE: Add CBMEM type for console buffer.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/720 -gerrit commit 1017143d7c8c2b58c11027279f7d0b9b62dbc55f Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri Sep 30 11:13:06 2011 -0700 CBMEM CONSOLE: Add CBMEM type for console buffer. Add CBMEM type for the console buffer section. Change-Id: I02757c06d71e46af77b02b90b0e6018a37b62406 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/include/cbmem.h | 1 + src/lib/cbmem.c | 1 + 2 files changed, 2 insertions(+), 0 deletions(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index c3f10ef..a19ec5a 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -42,6 +42,7 @@ extern uint64_t high_tables_base, high_tables_size; #define CBMEM_ID_RESUME 0x5245534d #define CBMEM_ID_SMBIOS 0x534d4254 #define CBMEM_ID_TIMESTAMP 0x54494d45 +#define CBMEM_ID_CONSOLE 0x434f4e53 #define CBMEM_ID_NONE 0x00000000 int cbmem_initialize(void); diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index f800b04..b09b070 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -256,6 +256,7 @@ void cbmem_list(void) case CBMEM_ID_RESUME: printk(BIOS_DEBUG, "ACPI RESUME"); break; case CBMEM_ID_SMBIOS: printk(BIOS_DEBUG, "SMBIOS "); break; case CBMEM_ID_TIMESTAMP: printk(BIOS_DEBUG, "TIME STAMP "); break; + case CBMEM_ID_CONSOLE: printk(BIOS_DEBUG, "CONSOLE "); break; default: printk(BIOS_DEBUG, "%08x ", cbmem_toc[i].id); } printk(BIOS_DEBUG, "%08llx ", cbmem_toc[i].base);

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coreboot March 2012