coreboot March 2012

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Patch set updated for coreboot: a9e4b1a Don't run any option roms stored outside of the system flash
by Stefan Reinauer 08 Mar '12

08 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/730 -gerrit commit a9e4b1ace0c54ef84e4aba8907bc2ea5c090f7e4 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Oct 6 16:47:51 2011 -0700 Don't run any option roms stored outside of the system flash Right now coreboot only executes vga option roms. However, this is not good enough. For security reasons we want to execute only option roms stored in our RO CBFS. This patch adds a new option to disable execution of arbitrary option ROMs and enables it for all our boards. Change-Id: I485291c06ec5cd1f875357401831fe32ccfc5f2f Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/devices/Kconfig | 13 +++++++++++++ src/devices/pci_rom.c | 6 ++++++ 2 files changed, 19 insertions(+), 0 deletions(-) diff --git a/src/devices/Kconfig b/src/devices/Kconfig index 572addc..98e8d9f 100644 --- a/src/devices/Kconfig +++ b/src/devices/Kconfig @@ -49,6 +49,19 @@ config PCI_ROM_RUN Examples include IDE/SATA controller option ROMs and option ROMs for network cards (NICs). +config ON_DEVICE_ROM_RUN + bool "Run option ROMs on PCI devices" + default y + help + Execute option ROMs that are stored on PCI/PCIe/AGP devices. + + If disabled, only option ROMs stored in CBFS will be executed. If + you are concerned about security, you might want to disable this + option, but it might leave your system in a state of degraded + functionality. + + If unsure, say Y + choice prompt "Option ROM execution type" default PCI_OPTION_ROM_RUN_YABEL if !ARCH_X86 diff --git a/src/devices/pci_rom.c b/src/devices/pci_rom.c index 471c7e2..1b6f1da 100644 --- a/src/devices/pci_rom.c +++ b/src/devices/pci_rom.c @@ -71,9 +71,15 @@ struct rom_header *pci_rom_probe(struct device *dev) rom_address|PCI_ROM_ADDRESS_ENABLE); } +#if CONFIG_ON_DEVICE_ROM_RUN printk(BIOS_DEBUG, "On card, ROM address for %s = %lx\n", dev_path(dev), (unsigned long)rom_address); rom_header = (struct rom_header *)rom_address; +#else + printk(BIOS_DEBUG, "On card option ROM execution disabled " + "for %s\n", dev_path(dev)); + return NULL; +#endif } printk(BIOS_SPEW, "PCI expansion ROM, signature 0x%04x, "

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Patch set updated for coreboot: 75f206f If the memory mapped UART isn't present, leave it out of the cb tables.
by Stefan Reinauer 08 Mar '12

08 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/729 -gerrit commit 75f206fd16c21602c62026d2c6ce0805713a66b7 Author: Gabe Black <gabeblack(a)google.com> Date: Wed Oct 5 01:57:03 2011 -0700 If the memory mapped UART isn't present, leave it out of the cb tables. This way u-boot won't try to use a UART that isn't plugged in. Change-Id: I9a3a0d074dd03add8afbd4dad836c4c6a05abe6f Signed-off-by: Gabe Black <gabeblack(a)google.com> --- src/arch/x86/boot/coreboot_table.c | 24 ++++++++++++++---------- 1 files changed, 14 insertions(+), 10 deletions(-) diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c index 59cf174..a9ff6f0 100644 --- a/src/arch/x86/boot/coreboot_table.c +++ b/src/arch/x86/boot/coreboot_table.c @@ -118,16 +118,20 @@ static struct lb_serial *lb_serial(struct lb_header *header) serial->baud = CONFIG_TTYS0_BAUD; return serial; #elif CONFIG_CONSOLE_SERIAL8250MEM - struct lb_record *rec; - struct lb_serial *serial; - rec = lb_new_record(header); - serial = (struct lb_serial *)rec; - serial->tag = LB_TAG_SERIAL; - serial->size = sizeof(*serial); - serial->type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial->baseaddr = uartmem_getbaseaddr(); - serial->baud = CONFIG_TTYS0_BAUD; - return serial; + if (uartmem_getbaseaddr()) { + struct lb_record *rec; + struct lb_serial *serial; + rec = lb_new_record(header); + serial = (struct lb_serial *)rec; + serial->tag = LB_TAG_SERIAL; + serial->size = sizeof(*serial); + serial->type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial->baseaddr = uartmem_getbaseaddr(); + serial->baud = CONFIG_TTYS0_BAUD; + return serial; + } else { + return NULL; + } #else return NULL; #endif

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Patch set updated for coreboot: 47ba453 Detect whether the OXPCIE card is really present while in the ROM stage.
by Stefan Reinauer 08 Mar '12

08 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/728 -gerrit commit 47ba453b31fe17ca4afb824d3001bd25ad7822ea Author: Gabe Black <gabeblack(a)google.com> Date: Wed Oct 5 01:52:08 2011 -0700 Detect whether the OXPCIE card is really present while in the ROM stage. Use an int in CAR global data to store whether or not the OXPCIE serial card is actually there. Also, time out if the card doesn't show up quickly enough, don't continue initialization if it's not there, and don't make the initialization routine default to a card if none is found. Change-Id: I9c72d3abc6ee2867b77ab2f2180e6f01f647af8c Signed-off-by: Gabe Black <gabeblack(a)google.com> --- src/arch/x86/lib/romstage_console.c | 5 ++++- src/drivers/oxford/oxpcie/oxpcie_early.c | 20 +++++++++++++++++--- src/include/uart8250.h | 5 +++++ 3 files changed, 26 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index 0f22727..25eda9b 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -35,7 +35,10 @@ static void console_tx_byte(unsigned char byte) console_tx_byte('\r'); #if CONFIG_CONSOLE_SERIAL8250MEM - uart8250_mem_tx_byte(CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte); + if (oxford_oxpcie_present) { + uart8250_mem_tx_byte( + CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte); + } #endif #if CONFIG_CONSOLE_SERIAL8250 uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c index 2c7767e..4f7a3cb 100644 --- a/src/drivers/oxford/oxpcie/oxpcie_early.c +++ b/src/drivers/oxford/oxpcie/oxpcie_early.c @@ -20,6 +20,8 @@ #include <stdint.h> #include <arch/io.h> #include <arch/romcc_io.h> +#include <cpu/x86/car.h> +#include <delay.h> #include <uart8250.h> #include <device/pci_def.h> @@ -34,9 +36,13 @@ #define OXPCIE_DEVICE_3 \ PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 3) +#if defined(__PRE_RAM__) +int oxford_oxpcie_present CAR_GLOBAL; + void oxford_init(void) { u16 reg16; + oxford_oxpcie_present = 1; /* First we reset the secondary bus */ reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL); @@ -69,11 +75,14 @@ void oxford_init(void) reg16 |= PCI_COMMAND_MEMORY; pci_write_config16(PCIE_BRIDGE, PCI_COMMAND, reg16); - // FIXME Add a timeout or this will hang forever if - // no device is in the slot. + u32 timeout = 20000; // Timeout in 10s of microseconds. u32 id = 0; - while ((id == 0) || (id == 0xffffffff)) + for (;;) { id = pci_read_config32(OXPCIE_DEVICE, PCI_VENDOR_ID); + if (!timeout-- || (id != 0 && id != 0xffffffff)) + break; + udelay(10); + } u32 device = OXPCIE_DEVICE; /* unknown default */ switch (id) { @@ -90,6 +99,10 @@ void oxford_init(void) case 0xc1581415: /* e.g. Startech MPEX2S952 */ device = OXPCIE_DEVICE; break; + default: + /* No UART here. */ + oxford_oxpcie_present = 0; + return; } /* Setup base address on device */ @@ -107,3 +120,4 @@ void oxford_init(void) uart8250_mem_init(uart0_base, (4000000 / CONFIG_TTYS0_BAUD)); } +#endif diff --git a/src/include/uart8250.h b/src/include/uart8250.h index aa510e5..71b9a5f 100644 --- a/src/include/uart8250.h +++ b/src/include/uart8250.h @@ -135,8 +135,13 @@ void uart8250_mem_init(unsigned base_port, unsigned divisor); u32 uart_mem_init(void); u32 uartmem_getbaseaddr(void); +#if defined(__PRE_RAM__) && CONFIG_DRIVERS_OXFORD_OXPCIE && \ + CONFIG_CONSOLE_SERIAL8250MEM /* and special init for OXPCIe based cards */ +extern int oxford_oxpcie_present; + void oxford_init(void); +#endif #endif /* __ROMCC__ */

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Patch set updated for coreboot: 8047e25 Add DEBUG_TPM option to Debugging menu
by Stefan Reinauer 08 Mar '12

08 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/757 -gerrit commit 8047e25c46f84c4ef3b7cf5332c93d37bc0980cf Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Nov 17 12:50:54 2011 -0800 Add DEBUG_TPM option to Debugging menu instead of having to edit the source code of tpm.c Change-Id: I519d9ada14dd383e668a2da4219e5373a24c7c3d Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/Kconfig | 7 +++++++ src/pc80/tpm.c | 9 +-------- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 26e6dde..41c5dbf 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -870,6 +870,13 @@ config X86EMU_DEBUG_IO If unsure, say N. +config DEBUG_TPM + bool "Output verbose TPM debug messages" + default n + depends on TPM + help + This option enables additional TPM related debug messages. + config LLSHELL bool "Built-in low-level shell" default n diff --git a/src/pc80/tpm.c b/src/pc80/tpm.c index 8e94303..17e1ed7 100644 --- a/src/pc80/tpm.c +++ b/src/pc80/tpm.c @@ -27,7 +27,6 @@ * Infineon slb9635), so this driver provides access to locality 0 only. */ -/* #define DEBUG */ #include <stdlib.h> #include <string.h> #include <delay.h> @@ -37,17 +36,11 @@ #include <pc80/tpm.h> #include <cpu/x86/car.h> -#ifdef DEBUG -#define TPM_DEBUG_ON 1 -#else -#define TPM_DEBUG_ON 0 -#endif - #define PREFIX "lpc_tpm: " /* coreboot wrapper for TPM driver (start) */ #define TPM_DEBUG(fmt, args...) \ - if (TPM_DEBUG_ON) { \ + if (CONFIG_DEBUG_TPM) { \ printk(BIOS_DEBUG, PREFIX); \ printk(BIOS_DEBUG, fmt , ##args); \ }

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Patch set updated for coreboot: 32efa9a Don't unconditionally add support for cardbus and pci-x devices
by Stefan Reinauer 08 Mar '12

08 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/756 -gerrit commit 32efa9a18e83c1862f77bb5a3176834a1571abad Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Nov 30 12:45:14 2011 -0800 Don't unconditionally add support for cardbus and pci-x devices It's still on by default. Change-Id: I8b6539eaf2f8d6a4fa975deb14789a00f2090d34 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/devices/Makefile.inc | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/devices/Makefile.inc b/src/devices/Makefile.inc index 86b4d21..9ffc0bb 100644 --- a/src/devices/Makefile.inc +++ b/src/devices/Makefile.inc @@ -3,10 +3,10 @@ ramstage-y += root_device.c ramstage-y += device_util.c ramstage-y += pci_device.c ramstage-$(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT) += hypertransport.c -ramstage-y += pcix_device.c +ramstage-$(CONFIG_PCIX_PLUGIN_SUPPORT) += pcix_device.c ramstage-y += pciexp_device.c -ramstage-y += agp_device.c -ramstage-y += cardbus_device.c +ramstage-$(CONFIG_AGP_PLUGIN_SUPPORT) += agp_device.c +ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += cardbus_device.c ramstage-y += pnp_device.c ramstage-y += pci_ops.c ramstage-y += smbus_ops.c

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Patch set updated for coreboot: a9e4699 Fix romcc to compile cleanly
by Stefan Reinauer 08 Mar '12

08 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/759 -gerrit commit a9e4699deb5cd361f3a9e6af51f7b66701623950 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Dec 6 22:14:57 2011 +0000 Fix romcc to compile cleanly There have been many unused variable assignments in the romcc source file. They cause multiple warning messages during build process which in turn make it harder to see the actual error message, when they are present. The fix is to remove dead code and to add -Werror to romcc compilation to avoid issues like this creeping in in the future. Change-Id: I6f42684f39a4135b0fe64219b8c7f058275c9fee Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- util/romcc/Makefile | 2 +- util/romcc/romcc.c | 3 +-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/util/romcc/Makefile b/util/romcc/Makefile index 6543fbb..8242eb5 100644 --- a/util/romcc/Makefile +++ b/util/romcc/Makefile @@ -1,7 +1,7 @@ # Move the configuration defines to makefile.conf CC=gcc CPPFLAGS= -CFLAGS= -g -Wall $(CPPFLAGS) +CFLAGS= -g -Wall -Werror $(CPPFLAGS) CPROF_FLAGS=-pg -fprofile-arcs all: romcc test diff --git a/util/romcc/romcc.c b/util/romcc/romcc.c index c7ef223..7eee439 100644 --- a/util/romcc/romcc.c +++ b/util/romcc/romcc.c @@ -9161,8 +9161,7 @@ static void decompose_compound_types(struct compile_state *state) { struct triple *ins, *next, *first; #if DEBUG_DECOMPOSE_HIRES - FILE *fp; - fp = state->dbgout; + FILE *fp = state->dbgout; #endif first = state->first; ins = first;

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Patch set updated for coreboot: 16d8070 Make PCI CONF2 support a compile time option.
by Stefan Reinauer 08 Mar '12

08 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/758 -gerrit commit 16d8070fe7dc4c12d7b19d91c88a8eeca0b10725 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Nov 17 13:05:31 2011 -0800 Make PCI CONF2 support a compile time option. It's not used on any board supported by coreboot but has been detected at run time since ages. No new boards (since 2000?) are using the CONF2 method, so it is unlikely we ever have to turn this on for a board. Change-Id: I17df94a8a77b9338fde10a6b114b44d393776e66 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/Kconfig | 4 ++++ src/arch/x86/lib/Makefile.inc | 4 +--- src/arch/x86/lib/pci_ops_auto.c | 9 ++++++++- 3 files changed, 13 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 078ae95..bc01c9c 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -96,4 +96,8 @@ config LITTLE_ENDIAN bool default !BIG_ENDIAN +config PCI_CONF2 + bool + default n + endmenu diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc index 3f4dc95..96fb9b0 100644 --- a/src/arch/x86/lib/Makefile.inc +++ b/src/arch/x86/lib/Makefile.inc @@ -1,10 +1,8 @@ ramstage-y += c_start.S ramstage-y += cpu.c ramstage-y += pci_ops_conf1.c -ramstage-y += pci_ops_conf2.c - +ramstage-$(CONFIG_PCI_CONF2) += pci_ops_conf2.c ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c - ramstage-y += pci_ops_auto.c ramstage-y += exception.c ramstage-$(CONFIG_IOAPIC) += ioapic.c diff --git a/src/arch/x86/lib/pci_ops_auto.c b/src/arch/x86/lib/pci_ops_auto.c index 92eedd3..58e098b 100644 --- a/src/arch/x86/lib/pci_ops_auto.c +++ b/src/arch/x86/lib/pci_ops_auto.c @@ -6,6 +6,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> +#if CONFIG_PCI_CONF2 /* * Before we decide to use direct hardware access mechanisms, we try to do some * trivial checks to ensure it at least _seems_ to be working -- we just test @@ -41,7 +42,7 @@ static int pci_sanity_check(const struct pci_bus_operations *o) return 0; } -struct pci_bus_operations *pci_bus_fallback_ops = NULL; +static struct pci_bus_operations *pci_bus_fallback_ops = NULL; static const struct pci_bus_operations *pci_check_direct(void) { @@ -89,6 +90,12 @@ const struct pci_bus_operations *pci_remember_direct(void) pci_bus_fallback_ops = (struct pci_bus_operations *)pci_check_direct(); return pci_bus_fallback_ops; } +#else +const struct pci_bus_operations *pci_remember_direct(void) +{ + return &pci_cf8_conf1; +} +#endif /** Set the method to be used for PCI, type I or type II */

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Patch set updated for coreboot: 63694cc vga_io.c is not needed unless CONFIG_VGA is set
by Stefan Reinauer 08 Mar '12

08 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/753 -gerrit commit 63694ccc1d77e104301f11260e12aeaea643c8e7 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Nov 17 11:13:36 2011 -0800 vga_io.c is not needed unless CONFIG_VGA is set hence disable it. Change-Id: I7b406251a2f3830748140a111f76f2792fe923ed Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/pc80/vga/Makefile.inc | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/pc80/vga/Makefile.inc b/src/pc80/vga/Makefile.inc index 0ca7896..d4b726a 100644 --- a/src/pc80/vga/Makefile.inc +++ b/src/pc80/vga/Makefile.inc @@ -1,4 +1,4 @@ -ramstage-y += vga_io.c +ramstage-$(CONFIG_VGA) += vga_io.c ramstage-$(CONFIG_VGA) += vga_palette.c ramstage-$(CONFIG_VGA) += vga_font_8x16.c ramstage-$(CONFIG_VGA) += vga.c

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Patch set updated for coreboot: 5a945ef Fix warnings in coreboot utilities.
by Stefan Reinauer 08 Mar '12

08 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/752 -gerrit commit 5a945efad929c596802a73a50e9174e3a49eceb7 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Nov 14 12:40:34 2011 -0800 Fix warnings in coreboot utilities. Fix some poor programming practice (breaks of strict aliasing as well as not checking the return value of read) Change-Id: I08b2e8d1bbc908f6b1f26d25cb3a4b03d818e124 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- util/inteltool/cpu.c | 6 ++++-- util/inteltool/inteltool.c | 4 +++- util/nvramtool/cli/nvramtool.c | 3 ++- 3 files changed, 9 insertions(+), 4 deletions(-) diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c index 20748bd..3bffa4e 100644 --- a/util/inteltool/cpu.c +++ b/util/inteltool/cpu.c @@ -67,8 +67,10 @@ msr_t rdmsr(int addr) } if (read(fd_msr, buf, 8) == 8) { - msr.lo = *(uint32_t *)buf; - msr.hi = *(uint32_t *)(buf + 4); + msr.lo = buf[0] | (buf[1] << 8) | + (buf[2] << 16) | (buf[3] << 24); + msr.hi = buf[4] | (buf[5] << 8) | + (buf[6] << 16) | (buf[7] << 24); return msr; } diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 6b99605..e5c2b86 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -21,6 +21,7 @@ #include <stdio.h> #include <stdlib.h> +#include <inttypes.h> #include <getopt.h> #include <fcntl.h> #include <sys/mman.h> @@ -99,7 +100,8 @@ void *map_physical(uint64_t phys_addr, size_t len) fd_mem, (off_t) phys_addr); if (virt_addr == MAP_FAILED) { - printf("Error mapping physical memory 0x%08lx[0x%zx]\n", phys_addr, len); + printf("Error mapping physical memory 0x%08" PRIx64 "[0x%zx]\n", + phys_addr, len); return NULL; } diff --git a/util/nvramtool/cli/nvramtool.c b/util/nvramtool/cli/nvramtool.c index 11a1a70..20097b8 100644 --- a/util/nvramtool/cli/nvramtool.c +++ b/util/nvramtool/cli/nvramtool.c @@ -143,7 +143,8 @@ int main(int argc, char *argv[]) if (fd_stat.st_size < 128) { lseek(fd, 127, SEEK_SET); - write(fd, "\0", 1); + if (write(fd, "\0", 1) != 1) + fprintf(stderr, "Write failed.\n"); fsync(fd); }

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Patch set updated for coreboot: 84d0936 use movsl for copying resume memory back
by Stefan Reinauer 08 Mar '12

08 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/755 -gerrit commit 84d093600296389e65e87f09dea0242ae837e5e2 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Nov 17 13:03:38 2011 -0800 use movsl for copying resume memory back It's not significantly faster, but easier to read and smaller. Change-Id: Ibab0b478873912d67bf1f07743f628586353368a Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/boot/wakeup.S | 20 ++++---------------- 1 files changed, 4 insertions(+), 16 deletions(-) diff --git a/src/arch/x86/boot/wakeup.S b/src/arch/x86/boot/wakeup.S index a1df4d5..f12b176 100644 --- a/src/arch/x86/boot/wakeup.S +++ b/src/arch/x86/boot/wakeup.S @@ -38,23 +38,11 @@ __wakeup: movw %ax, (__wakeup_segment) /* Then overwrite coreboot with our backed up memory */ - movl 8(%esp), %esi - movl 12(%esp), %edi - movl 16(%esp), %ecx + movl 8(%esp), %esi + movl 12(%esp), %edi + movl 16(%esp), %ecx shrl $4, %ecx -1: - movl 0(%esi),%eax - movl 4(%esi),%edx - movl 8(%esi),%ebx - movl 12(%esi),%ebp - addl $16,%esi - subl $1,%ecx - movl %eax,0(%edi) - movl %edx,4(%edi) - movl %ebx,8(%edi) - movl %ebp,12(%edi) - leal 16(%edi),%edi - jne 1b + rep movsl /* Activate the right segment descriptor real mode. */ ljmp $0x28, $RELOCATED(1f)

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coreboot March 2012