coreboot March 2012

coreboot@coreboot.org

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Patch set updated for coreboot: 243cdc7 Fix coreboot table size calculations.
by Stefan Reinauer 08 Mar '12

08 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/703 -gerrit commit 243cdc7b487ecf0356b8e1a64efb0552a2df5f8c Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Aug 16 11:44:35 2011 -0700 Fix coreboot table size calculations. The code when reporting the coreboot table size did not account for the last added table record. This change fixes the problem. . rebuild coreboot, program it on the target, restart it . look for 'Wrote coreboot table at:' in the console log . observe the adequate table size reported $ grep 'Wrote coreboot table:' /tmp/cb.log Wrote coreboot table at: 00000500, 0x10 bytes, checksum c06f Wrote coreboot table at: 7f6fc000, 0x1a73 bytes, checksum 3e45 $ Change-Id: Ic55501a4ae06fab2bcda9aea58e362325f2edccf Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/arch/x86/boot/coreboot_table.c | 7 ++++--- 1 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c index a001259..b0dcc9e 100644 --- a/src/arch/x86/boot/coreboot_table.c +++ b/src/arch/x86/boot/coreboot_table.c @@ -320,9 +320,10 @@ static unsigned long lb_table_fini(struct lb_header *head, int fixup) head->table_checksum = compute_ip_checksum(first_rec, head->table_bytes); head->header_checksum = 0; head->header_checksum = compute_ip_checksum(head, sizeof(*head)); - printk(BIOS_DEBUG, "Wrote coreboot table at: %p - %p checksum %x\n", - head, rec, head->table_checksum); - return (unsigned long)rec; + printk(BIOS_DEBUG, + "Wrote coreboot table at: %p, 0x%x bytes, checksum %x\n", + head, head->table_bytes, head->table_checksum); + return (unsigned long)rec + rec->size; } static void lb_cleanup_memory_ranges(struct lb_memory *mem)

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Patch set updated for coreboot: f61c4fa Fix compilation when USE_OPTION_TABLE is not defined.
by Stefan Reinauer 08 Mar '12

08 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/702 -gerrit commit f61c4fa336157f9e91a777062192ccf23466258a Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Aug 15 16:35:10 2011 -0700 Fix compilation when USE_OPTION_TABLE is not defined. Change-Id: Id622e4e96b6c8e87b00a96c324a0b4dbfac3391d Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/arch/x86/boot/coreboot_table.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c index 77a1126..a001259 100644 --- a/src/arch/x86/boot/coreboot_table.c +++ b/src/arch/x86/boot/coreboot_table.c @@ -29,9 +29,9 @@ #include <version.h> #include <device/device.h> #include <stdlib.h> +#include <cbfs.h> #if CONFIG_USE_OPTION_TABLE #include <option_table.h> -#include <cbfs.h> #endif static struct lb_header *lb_table_init(unsigned long addr)

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Patch set updated for coreboot: 67cbf9d Introduce config option to initialize CBMEM early.
by Stefan Reinauer 08 Mar '12

08 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/710 -gerrit commit 67cbf9dd64a323f7bae11e2a78a495fdd70461a7 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Sep 20 16:46:46 2011 -0700 Introduce config option to initialize CBMEM early. We want to be able to communicate information between rom and ram stages of coreboot. This configuration option will be used to compile such ability in. Change-Id: I6736fdc264ecd0b63369b28462d7bb96e4c2b012 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/Kconfig | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index c165d93..544b61b 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -112,6 +112,14 @@ config INCLUDE_CONFIG_FILE help Include in CBFS the coreboot config file that was used to compile the ROM image +config EARLY_CBMEM_INIT + bool "Initialize CBMEM while in ROM stage" + default n + help + Make coreboot initialize the cbmem structures while running in rom + stage. This could be useful when the rom stage wants to communicate + some, for instance, execution timestamps. + endmenu source src/mainboard/Kconfig

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Patch set updated for coreboot: 710fe3b Initialize CBMEM early.
by Stefan Reinauer 08 Mar '12

08 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/711 -gerrit commit 710fe3bd556cc9de1e7067a4ca22e19b97475b1b Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Sep 20 17:07:14 2011 -0700 Initialize CBMEM early. We want to be able to share data between different phases of firmware (rom stage/ram stage/payload). Coreboot CBMEM seems an appropriate location for this data, but normally it is not initialized until coreboot reaches the ram stage. This change initializes the CBMEM while still in rom stage in case CONFIG_EARLY_CBMEM_INIT is set. Note that there is a discrepancy in how coreboot determines the size of DRAM at rom and ram stages, get_top_of_ram() is used at rom stage and is not defined for all platforms. Those platforms will have to define this function should they enable the CONFIG_EARLY_CBMEM_INIT flag. Change-Id: I81691d45e28de59496fb227f2cca4e8c15ece717 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/include/cbmem.h | 4 +++- src/lib/cbmem.c | 39 +++++++++++++++++++++++---------------- 2 files changed, 26 insertions(+), 17 deletions(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 9806854..a681c36 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -22,7 +22,9 @@ /* Reserve 128k for ACPI and other tables */ #define HIGH_MEMORY_DEF_SIZE ( 128 * 1024 ) +#ifndef __PRE_RAM__ extern uint64_t high_tables_base, high_tables_size; +#endif #if CONFIG_HAVE_ACPI_RESUME #define HIGH_MEMORY_SIZE ((CONFIG_RAMTOP - CONFIG_RAMBASE) + HIGH_MEMORY_DEF_SIZE) @@ -41,7 +43,7 @@ extern uint64_t high_tables_base, high_tables_size; #define CBMEM_ID_SMBIOS 0x534d4254 #define CBMEM_ID_NONE 0x00000000 -void cbmem_initialize(void); +int cbmem_initialize(void); void cbmem_init(u64 baseaddr, u64 size); int cbmem_reinit(u64 baseaddr); diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 202f521..f5c3d3a 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -183,30 +183,38 @@ void *cbmem_find(u32 id) return (void *)NULL; } -#ifndef __PRE_RAM__ -#if CONFIG_HAVE_ACPI_RESUME +#if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) extern u8 acpi_slp_type; #endif -void cbmem_initialize(void) +#if CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__) +/* Returns True if it was not intialized before. */ +int cbmem_initialize(void) { -#if CONFIG_HAVE_ACPI_RESUME - printk(BIOS_DEBUG, "%s: acpi_slp_type=%d\n", __func__, acpi_slp_type); - if (acpi_slp_type == 3 || acpi_slp_type == 2) { - if (!cbmem_reinit(high_tables_base)) { - printk(BIOS_DEBUG, "cbmem_reinit failed\n"); - /* Something went wrong, our high memory area got wiped */ + int rv = 0; + +#ifdef __PRE_RAM__ + extern unsigned long get_top_of_ram(void); + uint64_t high_tables_base = get_top_of_ram() - HIGH_MEMORY_SIZE; + uint64_t high_tables_size = HIGH_MEMORY_SIZE; +#endif + + /* We expect the romstage to always initialize it. */ + if (!cbmem_reinit(high_tables_base)) { +#if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) + /* Something went wrong, our high memory area got wiped */ + if (acpi_slp_type == 3 || acpi_slp_type == 2) acpi_slp_type = 0; - cbmem_init(high_tables_base, high_tables_size); - } - } else { +#endif cbmem_init(high_tables_base, high_tables_size); + rv = 1; } -#else - cbmem_init(high_tables_base, high_tables_size); -#endif +#ifndef __PRE_RAM__ cbmem_arch_init(); +#endif + return rv; } +#endif #ifndef __PRE_RAM__ void cbmem_list(void) @@ -240,5 +248,4 @@ void cbmem_list(void) } #endif -#endif

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Patch set updated for coreboot: daf3d89 Add an implementation for the memchr library function
by Stefan Reinauer 08 Mar '12

08 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/708 -gerrit commit daf3d89987751a461bc8d1db86e13644acc46047 Author: Gabe Black <gabeblack(a)google.com> Date: Fri Sep 16 02:18:56 2011 -0700 Add an implementation for the memchr library function Change-Id: Icded479d246f7cce8a3d2154c69f75178fa513e1 Signed-off-by: Gabe Black <gabeblack(a)google.com> --- src/include/string.h | 1 + src/lib/Makefile.inc | 2 ++ src/lib/memchr.c | 11 +++++++++++ 3 files changed, 14 insertions(+), 0 deletions(-) diff --git a/src/include/string.h b/src/include/string.h index 2168947..708961b 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -8,6 +8,7 @@ void *memcpy(void *dest, const void *src, size_t n); void *memmove(void *dest, const void *src, size_t n); void *memset(void *s, int c, size_t n); int memcmp(const void *s1, const void *s2, size_t n); +void *memchr(const void *s, int c, size_t n); #if !defined(__PRE_RAM__) int sprintf(char * buf, const char *fmt, ...); #endif diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 906dfae..e0e5e75 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -1,6 +1,7 @@ romstage-y += memset.c +romstage-y += memchr.c romstage-y += memcpy.c romstage-y += memcmp.c romstage-y += cbfs.c @@ -15,6 +16,7 @@ romstage-$(CONFIG_CONSOLE_NE2K) += compute_ip_checksum.c romstage-$(CONFIG_USBDEBUG) += usbdebug.c ramstage-y += memset.c +ramstage-y += memchr.c ramstage-y += memcpy.c ramstage-y += memcmp.c ramstage-y += memmove.c diff --git a/src/lib/memchr.c b/src/lib/memchr.c new file mode 100644 index 0000000..a890dce --- /dev/null +++ b/src/lib/memchr.c @@ -0,0 +1,11 @@ +#include <string.h> +void *memchr(const void *s, int c, size_t n) +{ + const unsigned char *sc = s; + while (n--) { + if (*sc == (unsigned char)c) + return (void *)sc; + sc++; + } + return NULL; +}

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Patch set updated for coreboot: 8cc685b Since cbfs_core.h provides a macro that uses ntohl, make sure ntohl is available
by Stefan Reinauer 08 Mar '12

08 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/709 -gerrit commit 8cc685b2e006f3756dd26885b834fb198fa1f137 Author: Gabe Black <gabeblack(a)google.com> Date: Fri Sep 16 02:24:03 2011 -0700 Since cbfs_core.h provides a macro that uses ntohl, make sure ntohl is available Since cbfs_core.h provides a macro that uses ntohl, make sure ntohl is available by including byteorder.h Change-Id: I9ab8cb51bd680e861b28d5130d09547bb9ab3b1f Signed-off-by: Gabe Black <gabeblack(a)google.com> --- src/include/cbfs_core.h | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/src/include/cbfs_core.h b/src/include/cbfs_core.h index 70368f8..43e6b9b 100644 --- a/src/include/cbfs_core.h +++ b/src/include/cbfs_core.h @@ -49,6 +49,8 @@ #ifndef _CBFS_CORE_H_ #define _CBFS_CORE_H_ +#include <arch/byteorder.h> + /** These are standard values for the known compression alogrithms that coreboot knows about for stages and payloads. Of course, other CBFS users can use whatever

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Patch set updated for coreboot: 221274e Increase size of the coreboot table area
by Stefan Reinauer 08 Mar '12

08 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/704 -gerrit commit 221274e7533b5b7c0ca772eb899492129d7c23a0 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Sun Aug 14 13:52:03 2011 -0700 Increase size of the coreboot table area Packing a device tree into the coreboot table can easily make the table exceed the current limit of 8KB. However, right now there is no error handling in place to catch that case. Increase the maximum memory usable for all tables from 64KB to 128KB and increase the maximum coreboot table size from 8KB to 32KB. Change-Id: I2025bf070d0adb276c1cd610aa8402b50bdf2525 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/boot/tables.c | 2 +- src/include/cbmem.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index 29d2ec0..b7dc4fe 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -202,7 +202,7 @@ struct lb_memory *write_tables(void) } #endif -#define MAX_COREBOOT_TABLE_SIZE (8 * 1024) +#define MAX_COREBOOT_TABLE_SIZE (32 * 1024) post_code(0x9d); high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE, MAX_COREBOOT_TABLE_SIZE); diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 7c5ec07..9806854 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -20,8 +20,8 @@ #ifndef _CBMEM_H_ #define _CBMEM_H_ -/* Reserve 64k for ACPI and other tables */ -#define HIGH_MEMORY_DEF_SIZE ( 64 * 1024 ) +/* Reserve 128k for ACPI and other tables */ +#define HIGH_MEMORY_DEF_SIZE ( 128 * 1024 ) extern uint64_t high_tables_base, high_tables_size; #if CONFIG_HAVE_ACPI_RESUME

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Patch set updated for coreboot: 0a2f25b Include arch/acpi.h instead of manually adding acpi_slp_type.
by Stefan Reinauer 08 Mar '12

08 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/714 -gerrit commit 0a2f25bc436e6a554e44bf959f307f814701695c Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Sep 23 10:24:49 2011 -0700 Include arch/acpi.h instead of manually adding acpi_slp_type. acpi_slp_type is defined in arch/acpi.h, so let's use that instead of manually spreading extern u8 acpi_slp_type throughout the code. Change-Id: Ia5eb420364c15ab5a764bc328bbd201ca9cb7837 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/lib/cbmem.c | 7 +++---- 1 files changed, 3 insertions(+), 4 deletions(-) diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 6597840..f800b04 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -21,6 +21,9 @@ #include <string.h> #include <cbmem.h> #include <console/console.h> +#if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) +#include <arch/acpi.h> +#endif // The CBMEM TOC reserves 512 bytes to keep // the other entries somewhat aligned. @@ -199,10 +202,6 @@ void *cbmem_find(u32 id) return (void *)NULL; } -#if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) -extern u8 acpi_slp_type; -#endif - #if CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__) /* Returns True if it was not intialized before. */ int cbmem_initialize(void)

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Patch set updated for coreboot: 79308ae Add a config flag to enable time stamp collection.
by Stefan Reinauer 08 Mar '12

08 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/712 -gerrit commit 79308ae2348b5e61474e1be2dc48fd21640c8f27 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Sep 21 14:46:43 2011 -0700 Add a config flag to enable time stamp collection. Add a new flag, make it dependent on EARLY_CBMEM_INIT Change-Id: Idbebcaf298238f31a73e9eb4a9af7b03e857bc74 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/Kconfig | 15 +++++++++++++++ 1 files changed, 15 insertions(+), 0 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 544b61b..573868f 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -112,6 +112,14 @@ config INCLUDE_CONFIG_FILE help Include in CBFS the coreboot config file that was used to compile the ROM image +config FDT_FILE_NAME + depends on ADD_FDT + string "Name of the CBFS file containing the compiled FDT" + default "u-boot.dtb" + help + Name of the CBFS file containing the binary representation of the + device tree to be optionally modified and passed to the payload. + config EARLY_CBMEM_INIT bool "Initialize CBMEM while in ROM stage" default n @@ -120,6 +128,13 @@ config EARLY_CBMEM_INIT stage. This could be useful when the rom stage wants to communicate some, for instance, execution timestamps. +config COLLECT_TIMESTAMPS + bool "Create a table of timestamps collected during boot" + depends on EARLY_CBMEM_INIT + help + Make coreboot create a table of timer id/timer value pairs to + allow measuring time spent at different phases of the boot + process. endmenu source src/mainboard/Kconfig

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Patch set updated for coreboot: 554708b Add timestamp collecting to coreboot.
by Stefan Reinauer 08 Mar '12

08 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/713 -gerrit commit 554708b5b210a0fa6a9d6c552b5826c6533cfbad Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Sep 21 16:12:39 2011 -0700 Add timestamp collecting to coreboot. This patch adds code to initialize the time stamp collection facility in coreboot. It adds a table in the CBMEM section, which provides the base timer reading value (all other readings are offsets of this one) and an array of timestamp id/timestamp value pairs. Just two values are being added now, this will have to be used more extensively and also integrated into payloads to provide more comprehensive boot process time measurements. Also, since the CBMEM area could already contain a section (from the previous run, before reset), when processing a section addition request we should check if a section already exists and return its address, if so. Change-Id: I7ed9f5c400bc5432f228348b41fd19a67c36d533 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/include/cbmem.h | 1 + src/include/timestamp.h | 46 +++++++++++++++++++++++++++++ src/lib/Makefile.inc | 2 + src/lib/cbmem.c | 17 +++++++++++ src/lib/timestamp.c | 74 +++++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 140 insertions(+), 0 deletions(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index a681c36..c3f10ef 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -41,6 +41,7 @@ extern uint64_t high_tables_base, high_tables_size; #define CBMEM_ID_MPTABLE 0x534d5054 #define CBMEM_ID_RESUME 0x5245534d #define CBMEM_ID_SMBIOS 0x534d4254 +#define CBMEM_ID_TIMESTAMP 0x54494d45 #define CBMEM_ID_NONE 0x00000000 int cbmem_initialize(void); diff --git a/src/include/timestamp.h b/src/include/timestamp.h new file mode 100644 index 0000000..cfa06e2 --- /dev/null +++ b/src/include/timestamp.h @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#ifndef __TIMESTAMP_H__ +#define __TIMESTAMP_H__ + +#include <cpu/x86/tsc.h> + +struct timestamp_entry { + uint32_t entry_id; + uint64_t entry_stamp; +} __attribute__((packed)); + +struct timestamp_table { + uint64_t base_time; + uint32_t max_entries; + uint32_t num_entries; + struct timestamp_entry entries[0]; /* Variable number of entries */ +} __attribute__((packed)); + +enum timestamp_id { + TS_BEFORE_INITRAM = 1, + TS_AFTER_INITRAM = 2, +}; + +void timestamp_init(tsc_t base); +void timestamp_add(enum timestamp_id id, tsc_t ts_time); +void timestamp_add_now(enum timestamp_id id); + +#endif diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index e0e5e75..db640dc 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -14,6 +14,7 @@ romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c romstage-$(CONFIG_CONSOLE_NE2K) += compute_ip_checksum.c romstage-$(CONFIG_USBDEBUG) += usbdebug.c +romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c ramstage-y += memset.c ramstage-y += memchr.c @@ -36,6 +37,7 @@ ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c ramstage-$(CONFIG_USBDEBUG) += usbdebug.c ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c ramstage-$(CONFIG_TRACE) += trace.c +ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c driver-$(CONFIG_CONSOLE_NE2K) += ne2k.c diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index f5c3d3a..6597840 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -118,6 +118,22 @@ void *cbmem_add(u32 id, u64 size) { struct cbmem_entry *cbmem_toc; int i; + void *p; + + /* + * This could be a restart, check if the section is there already. It + * is remotely possible that the dram contents persisted over the + * bootloader upgrade AND the same section now needs more room, but + * this is quite a remote possibility and it is ignored here. + */ + p = cbmem_find(id); + if (p) { + printk(BIOS_NOTICE, + "CBMEM section %x: using existing location at %p.\n", + id, p); + return p; + } + cbmem_toc = get_cbmem_toc(); if (cbmem_toc == NULL) { @@ -240,6 +256,7 @@ void cbmem_list(void) case CBMEM_ID_MPTABLE: printk(BIOS_DEBUG, "SMP TABLE "); break; case CBMEM_ID_RESUME: printk(BIOS_DEBUG, "ACPI RESUME"); break; case CBMEM_ID_SMBIOS: printk(BIOS_DEBUG, "SMBIOS "); break; + case CBMEM_ID_TIMESTAMP: printk(BIOS_DEBUG, "TIME STAMP "); break; default: printk(BIOS_DEBUG, "%08x ", cbmem_toc[i].id); } printk(BIOS_DEBUG, "%08llx ", cbmem_toc[i].base); diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c new file mode 100644 index 0000000..bbb8197d --- /dev/null +++ b/src/lib/timestamp.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#include <stdint.h> +#include <console/console.h> +#include <cbmem.h> +#include <timestamp.h> + +#define MAX_TIMESTAMPS 30 + +#ifndef __PRE_RAM__ +static struct timestamp_table* ts_table; +#endif + +static uint64_t tsc_to_uint64(tsc_t tstamp) +{ + return (((uint64_t)tstamp.hi) << 32) + tstamp.lo; +} + +void timestamp_init(tsc_t base) +{ + struct timestamp_table* tst; + + tst = cbmem_add(CBMEM_ID_TIMESTAMP, + sizeof(struct timestamp_table) + + MAX_TIMESTAMPS * sizeof(struct timestamp_entry)); + + if (!tst) { + printk(BIOS_ERR, "ERROR: failed to allocate timstamp table\n"); + return; + } + + tst->base_time = tsc_to_uint64(base); + tst->max_entries = MAX_TIMESTAMPS; + tst->num_entries = 0; +} + +void timestamp_add(enum timestamp_id id, tsc_t ts_time) +{ + struct timestamp_entry *tse; +#ifdef __PRE_RAM__ + struct timestamp_table *ts_table = cbmem_find(CBMEM_ID_TIMESTAMP); +#else + if (!ts_table) + ts_table = cbmem_find(CBMEM_ID_TIMESTAMP); +#endif + if (!ts_table || (ts_table->num_entries == ts_table->max_entries)) + return; + + tse = &ts_table->entries[ts_table->num_entries++]; + tse->entry_id = id; + tse->entry_stamp = tsc_to_uint64(ts_time) - ts_table->base_time; +} + +void timestamp_add_now(enum timestamp_id id) +{ + timestamp_add(id, rdtsc()); +}

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coreboot March 2012