coreboot March 2012

coreboot@coreboot.org

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718 discussions

Patch set updated for coreboot: 1b0d000 Include arch/acpi.h instead of manually adding acpi_slp_type.
by Stefan Reinauer 08 Mar '12

08 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/714 -gerrit commit 1b0d000be7468923efade01d70aaed1e8b1ca0e3 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Sep 23 10:24:49 2011 -0700 Include arch/acpi.h instead of manually adding acpi_slp_type. acpi_slp_type is defined in arch/acpi.h, so let's use that instead of manually spreading extern u8 acpi_slp_type throughout the code. Change-Id: Ia5eb420364c15ab5a764bc328bbd201ca9cb7837 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/lib/cbmem.c | 7 +++---- 1 files changed, 3 insertions(+), 4 deletions(-) diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 6597840..f800b04 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -21,6 +21,9 @@ #include <string.h> #include <cbmem.h> #include <console/console.h> +#if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) +#include <arch/acpi.h> +#endif // The CBMEM TOC reserves 512 bytes to keep // the other entries somewhat aligned. @@ -199,10 +202,6 @@ void *cbmem_find(u32 id) return (void *)NULL; } -#if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) -extern u8 acpi_slp_type; -#endif - #if CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__) /* Returns True if it was not intialized before. */ int cbmem_initialize(void)

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Patch set updated for coreboot: 8254fd4 Add a config flag to enable time stamp collection
by Stefan Reinauer 08 Mar '12

08 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/712 -gerrit commit 8254fd40495371ad1475e03c92741366deed09f1 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Sep 21 14:46:43 2011 -0700 Add a config flag to enable time stamp collection Add a new flag, make it dependent on EARLY_CBMEM_INIT Change-Id: Idbebcaf298238f31a73e9eb4a9af7b03e857bc74 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/Kconfig | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 544b61b..a654cc3 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -120,6 +120,13 @@ config EARLY_CBMEM_INIT stage. This could be useful when the rom stage wants to communicate some, for instance, execution timestamps. +config COLLECT_TIMESTAMPS + bool "Create a table of timestamps collected during boot" + depends on EARLY_CBMEM_INIT + help + Make coreboot create a table of timer id/timer value pairs to + allow measuring time spent at different phases of the boot + process. endmenu source src/mainboard/Kconfig

1 0

Patch set updated for coreboot: 7a95abb Add timestamp collecting to coreboot.
by Stefan Reinauer 08 Mar '12

08 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/713 -gerrit commit 7a95abbb000a9088f65e19a78e2468dea8e5b740 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Sep 21 16:12:39 2011 -0700 Add timestamp collecting to coreboot. This patch adds code to initialize the time stamp collection facility in coreboot. It adds a table in the CBMEM section, which provides the base timer reading value (all other readings are offsets of this one) and an array of timestamp id/timestamp value pairs. Just two values are being added now, this will have to be used more extensively and also integrated into payloads to provide more comprehensive boot process time measurements. Also, since the CBMEM area could already contain a section (from the previous run, before reset), when processing a section addition request we should check if a section already exists and return its address, if so. Change-Id: I7ed9f5c400bc5432f228348b41fd19a67c36d533 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/include/cbmem.h | 1 + src/include/timestamp.h | 46 +++++++++++++++++++++++++++++ src/lib/Makefile.inc | 2 + src/lib/cbmem.c | 17 +++++++++++ src/lib/timestamp.c | 74 +++++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 140 insertions(+), 0 deletions(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index a681c36..c3f10ef 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -41,6 +41,7 @@ extern uint64_t high_tables_base, high_tables_size; #define CBMEM_ID_MPTABLE 0x534d5054 #define CBMEM_ID_RESUME 0x5245534d #define CBMEM_ID_SMBIOS 0x534d4254 +#define CBMEM_ID_TIMESTAMP 0x54494d45 #define CBMEM_ID_NONE 0x00000000 int cbmem_initialize(void); diff --git a/src/include/timestamp.h b/src/include/timestamp.h new file mode 100644 index 0000000..cfa06e2 --- /dev/null +++ b/src/include/timestamp.h @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#ifndef __TIMESTAMP_H__ +#define __TIMESTAMP_H__ + +#include <cpu/x86/tsc.h> + +struct timestamp_entry { + uint32_t entry_id; + uint64_t entry_stamp; +} __attribute__((packed)); + +struct timestamp_table { + uint64_t base_time; + uint32_t max_entries; + uint32_t num_entries; + struct timestamp_entry entries[0]; /* Variable number of entries */ +} __attribute__((packed)); + +enum timestamp_id { + TS_BEFORE_INITRAM = 1, + TS_AFTER_INITRAM = 2, +}; + +void timestamp_init(tsc_t base); +void timestamp_add(enum timestamp_id id, tsc_t ts_time); +void timestamp_add_now(enum timestamp_id id); + +#endif diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index e0e5e75..db640dc 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -14,6 +14,7 @@ romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c romstage-$(CONFIG_CONSOLE_NE2K) += compute_ip_checksum.c romstage-$(CONFIG_USBDEBUG) += usbdebug.c +romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c ramstage-y += memset.c ramstage-y += memchr.c @@ -36,6 +37,7 @@ ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c ramstage-$(CONFIG_USBDEBUG) += usbdebug.c ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c ramstage-$(CONFIG_TRACE) += trace.c +ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c driver-$(CONFIG_CONSOLE_NE2K) += ne2k.c diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index f5c3d3a..6597840 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -118,6 +118,22 @@ void *cbmem_add(u32 id, u64 size) { struct cbmem_entry *cbmem_toc; int i; + void *p; + + /* + * This could be a restart, check if the section is there already. It + * is remotely possible that the dram contents persisted over the + * bootloader upgrade AND the same section now needs more room, but + * this is quite a remote possibility and it is ignored here. + */ + p = cbmem_find(id); + if (p) { + printk(BIOS_NOTICE, + "CBMEM section %x: using existing location at %p.\n", + id, p); + return p; + } + cbmem_toc = get_cbmem_toc(); if (cbmem_toc == NULL) { @@ -240,6 +256,7 @@ void cbmem_list(void) case CBMEM_ID_MPTABLE: printk(BIOS_DEBUG, "SMP TABLE "); break; case CBMEM_ID_RESUME: printk(BIOS_DEBUG, "ACPI RESUME"); break; case CBMEM_ID_SMBIOS: printk(BIOS_DEBUG, "SMBIOS "); break; + case CBMEM_ID_TIMESTAMP: printk(BIOS_DEBUG, "TIME STAMP "); break; default: printk(BIOS_DEBUG, "%08x ", cbmem_toc[i].id); } printk(BIOS_DEBUG, "%08llx ", cbmem_toc[i].base); diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c new file mode 100644 index 0000000..bbb8197d --- /dev/null +++ b/src/lib/timestamp.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#include <stdint.h> +#include <console/console.h> +#include <cbmem.h> +#include <timestamp.h> + +#define MAX_TIMESTAMPS 30 + +#ifndef __PRE_RAM__ +static struct timestamp_table* ts_table; +#endif + +static uint64_t tsc_to_uint64(tsc_t tstamp) +{ + return (((uint64_t)tstamp.hi) << 32) + tstamp.lo; +} + +void timestamp_init(tsc_t base) +{ + struct timestamp_table* tst; + + tst = cbmem_add(CBMEM_ID_TIMESTAMP, + sizeof(struct timestamp_table) + + MAX_TIMESTAMPS * sizeof(struct timestamp_entry)); + + if (!tst) { + printk(BIOS_ERR, "ERROR: failed to allocate timstamp table\n"); + return; + } + + tst->base_time = tsc_to_uint64(base); + tst->max_entries = MAX_TIMESTAMPS; + tst->num_entries = 0; +} + +void timestamp_add(enum timestamp_id id, tsc_t ts_time) +{ + struct timestamp_entry *tse; +#ifdef __PRE_RAM__ + struct timestamp_table *ts_table = cbmem_find(CBMEM_ID_TIMESTAMP); +#else + if (!ts_table) + ts_table = cbmem_find(CBMEM_ID_TIMESTAMP); +#endif + if (!ts_table || (ts_table->num_entries == ts_table->max_entries)) + return; + + tse = &ts_table->entries[ts_table->num_entries++]; + tse->entry_id = id; + tse->entry_stamp = tsc_to_uint64(ts_time) - ts_table->base_time; +} + +void timestamp_add_now(enum timestamp_id id) +{ + timestamp_add(id, rdtsc()); +}

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VIA CN700 / VT8237R support in V4 broken?
by Christian 08 Mar '12

08 Mar '12

Hey list I currently working on a Igel Thin Client 3210. The board is very closer to bcom/winnetp680. CN700 northbridge VT8237R southbridge W83679HF SuperIO A try with this tree did not work. I'm not new to coreboot and think that the first debug message should apear on the serial-console, but nothing happens. I have compiled nearly all via boards to test the ROMs with qemu. And get always this message: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ qemu: fatal: Trying to execute code outside RAM or ROM at 0x000a0000 EAX=00000004 EBX=00000000 ECX=00000000 EDX=00000001 ESI=00000000 EDI=00000000 EBP=ffef7fe8 ESP=ffef7fb8 EIP=0009ff66 EFL=00000002 [-------] CPL=0 II=0 A20=1 SMM=0 HLT=0 ES =0010 00000000 ffffffff 00cf9300 DPL=0 DS [-WA] CS =0008 00000000 ffffffff 00cf9b00 DPL=0 CS32 [-RA] SS =0010 00000000 ffffffff 00cf9300 DPL=0 DS [-WA] DS =0010 00000000 ffffffff 00cf9300 DPL=0 DS [-WA] FS =0010 00000000 ffffffff 00cf9300 DPL=0 DS [-WA] GS =0010 00000000 ffffffff 00cf9300 DPL=0 DS [-WA] LDT=0000 00000000 0000ffff 00008200 DPL=0 LDT TR =0000 00000000 0000ffff 00008b00 DPL=0 TSS32-busy GDT= fff8df54 00000017 IDT= 00000000 00000000 CR0=00000011 CR2=00000000 CR3=00000000 CR4=00000000 DR0=00000000 DR1=00000000 DR2=00000000 DR3=00000000 DR6=ffff0ff0 DR7=00000400 CCS=00000004 CCD=000000c4 CCO=ADDB EFER=0000000000000000 FCW=037f FSW=0000 [ST=0] FTW=ff MXCSR=00001f80 FPR0=0000000000000000 0000 FPR1=0000000000000000 0000 FPR2=0000000000000000 0000 FPR3=0000000000000000 0000 FPR4=0000000000000000 0000 FPR5=0000000000000000 0000 FPR6=0000000000000000 0000 FPR7=0000000000000000 0000 XMM00=00000000000000000000000000000000 XMM01=00000000000000000000000000000000 XMM02=00000000000000000000000000000000 XMM03=00000000000000000000000000000000 XMM04=00000000000000000000000000000000 XMM05=00000000000000000000000000000000 XMM06=00000000000000000000000000000000 XMM07=00000000000000000000000000000000 Abgebrochen +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ nothing more ... There is no "Coreboot Starting bla, bla" message Amd or Intel boards break later. Is it a problem with Qemu and Via C7 CPUs or is their something wrong in the via tree. Is anybody working on a cn700 board for now. There are hints for Rev. 3566 code for the southbridge? Is this important. Does the current code not working? Thanks Chris

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Patch set updated for coreboot: 74cc92c Don't try to compute I/O for empty sub buses.
by Stefan Reinauer 08 Mar '12

08 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/693 -gerrit commit 74cc92c58451be4592219e5e70b894484a1f761e Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed May 11 15:57:07 2011 -0700 Don't try to compute I/O for empty sub buses. I am not sure if the sub bus being 0 is a problem, or if the assumption there has to be at least one non empty link is just wrong. It certainly does not hurt to add a small consistency check in either case. Change-Id: I098446deef96a8baae26a7ca1ddd96e626a06dc5 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/devices/device_util.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/src/devices/device_util.c b/src/devices/device_util.c index 9081a36..84fb115 100644 --- a/src/devices/device_util.c +++ b/src/devices/device_util.c @@ -583,6 +583,8 @@ void search_bus_resources(struct bus *bus, unsigned long type_mask, if (subbus->link_num == IOINDEX_SUBTRACTIVE_LINK(res->index)) break; + if (!subbus) /* Why can subbus be NULL? */ + break; search_bus_resources(subbus, type_mask, type, search, gp); continue;

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Patch set updated for coreboot: a2eaa4f OXPCIe: Reinitialize UART after pci_dev_set_resources()
by Stefan Reinauer 08 Mar '12

08 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/692 -gerrit commit a2eaa4fb7bb98f171d54523f9af06a0794f14013 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue May 10 12:54:56 2011 -0700 OXPCIe: Reinitialize UART after pci_dev_set_resources() ... and only pull in early init code if the OXPCIe is used for console. Change-Id: I01feca3b9e8376a75c17554ba1bd200d523dff8d Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/drivers/oxford/oxpcie/Makefile.inc | 2 ++ src/drivers/oxford/oxpcie/oxpcie.c | 14 ++++++++++++-- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/src/drivers/oxford/oxpcie/Makefile.inc b/src/drivers/oxford/oxpcie/Makefile.inc index 7d3a26f..7f4aa58 100644 --- a/src/drivers/oxford/oxpcie/Makefile.inc +++ b/src/drivers/oxford/oxpcie/Makefile.inc @@ -1,3 +1,5 @@ driver-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie.c +ifeq ($(CONFIG_CONSOLE_SERIAL8250MEM),y) romstage-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie_early.c +endif diff --git a/src/drivers/oxford/oxpcie/oxpcie.c b/src/drivers/oxford/oxpcie/oxpcie.c index e1fb65f..8afdd1f 100644 --- a/src/drivers/oxford/oxpcie/oxpcie.c +++ b/src/drivers/oxford/oxpcie/oxpcie.c @@ -23,7 +23,6 @@ #include <device/pci_ids.h> #include <console/console.h> #include <arch/io.h> -#include <uart8250.h> static void oxford_oxpcie_enable(device_t dev) { @@ -41,9 +40,20 @@ static void oxford_oxpcie_enable(device_t dev) (read32(res->base + 4) & 3)); } + +static void oxford_oxpcie_set_resources(struct device *dev) +{ + pci_dev_set_resources(dev); + +#if CONFIG_CONSOLE_SERIAL8250MEM + /* Re-initialize OXPCIe base address after set_resources */ + uartmem_init(); +#endif +} + static struct device_operations oxford_oxpcie_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = oxford_oxpcie_set_resources, .enable_resources = pci_dev_enable_resources, .init = oxford_oxpcie_enable, .scan_bus = 0,

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Patch set updated for coreboot: 7e4ae17 Add helper function to find a Local APIC by ID in the device tree.
by Stefan Reinauer 08 Mar '12

08 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/695 -gerrit commit 7e4ae17266e087e02ba9cdd4a3d909549b518a91 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jul 18 10:41:36 2011 -0700 Add helper function to find a Local APIC by ID in the device tree. Change-Id: Ie2d7d8e1f647a0c92d2de09e32454fbea688b1e7 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/devices/device_util.c | 20 ++++++++++++++++++++ src/include/device/device.h | 1 + 2 files changed, 21 insertions(+), 0 deletions(-) diff --git a/src/devices/device_util.c b/src/devices/device_util.c index 84fb115..5b182e1 100644 --- a/src/devices/device_util.c +++ b/src/devices/device_util.c @@ -110,6 +110,26 @@ struct device *dev_find_slot_on_smbus(unsigned int bus, unsigned int addr) } /** + * Given a Local APIC ID, find the device structure. + * + * @param apic_id The Local APIC ID number. + * @return Pointer to the device structure (if found), 0 otherwise. + */ +device_t dev_find_lapic(unsigned apic_id) +{ + device_t dev, result = NULL; + + for (dev = all_devices; dev; dev = dev->next) { + if (dev->path.type == DEVICE_PATH_APIC && + dev->path.apic.apic_id == apic_id) { + result = dev; + break; + } + } + return result; +} + +/** * Find a device of a given vendor and type. * * @param vendor A PCI vendor ID (e.g. 0x8086 for Intel). diff --git a/src/include/device/device.h b/src/include/device/device.h index a7de0c9..c097f57 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -132,6 +132,7 @@ device_t dev_find_device (u16 vendor, u16 device, device_t from); device_t dev_find_class (unsigned int class, device_t from); device_t dev_find_slot (unsigned int bus, unsigned int devfn); device_t dev_find_slot_on_smbus (unsigned int bus, unsigned int addr); +device_t dev_find_lapic(unsigned apic_id); /* Debug functions */ void print_resource_tree(struct device * root, int debug_level,

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Patch set updated for coreboot: 45899e3 Fix compilation with CONFIG_USE_OPTION_TABLE enabled
by Stefan Reinauer 08 Mar '12

08 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/696 -gerrit commit 45899e3e5bd9bccce3edcb68c84fda209b72168b Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Jul 29 15:34:14 2011 -0700 Fix compilation with CONFIG_USE_OPTION_TABLE enabled Change-Id: I6c5d973442bc1770702180a8964f1bf6ed6062ed Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/lib/Makefile.inc | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 432e24e..b930fcc 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -43,3 +43,11 @@ smm-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c smm-$(CONFIG_USBDEBUG) += usbdebug.c $(obj)/lib/version.ramstage.o : $(obj)/build.h + +OPTION_TABLE_H:= +ifeq ($(CONFIG_HAVE_OPTION_TABLE),y) +OPTION_TABLE_H:=$(obj)/option_table.h +endif + +$(obj)/lib/uart8250mem.smm.o : $(OPTION_TABLE_H) +

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Patch set updated for coreboot: 73ac02c Fix dependency problem for uart8250.c as well
by Stefan Reinauer 08 Mar '12

08 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/698 -gerrit commit 73ac02c0ba8fbecde36aa5cbaff4a92dd428b5ea Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Aug 11 14:51:31 2011 -0700 Fix dependency problem for uart8250.c as well If you build in parallel, option_table.h will occasionally not be there yet and the build will fail. Change-Id: I828956ab2e05c48d20c2f7c55616cc8fa19e1227 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/lib/Makefile.inc | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index b930fcc..906dfae 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -50,4 +50,5 @@ OPTION_TABLE_H:=$(obj)/option_table.h endif $(obj)/lib/uart8250mem.smm.o : $(OPTION_TABLE_H) +$(obj)/lib/uart8250.smm.o : $(OPTION_TABLE_H)

1 0

Patch set updated for coreboot: 1fe424a Clean up use of CONFIG_ variables in coreboot_table.c
by Stefan Reinauer 08 Mar '12

08 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/701 -gerrit commit 1fe424a1a1b1bb7da9392a1d9da598a55b8ae586 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Aug 15 11:26:35 2011 -0700 Clean up use of CONFIG_ variables in coreboot_table.c CONFIG_ variables are used inconsistently within the file src/arch/x86/boot/coreboot_table.c. #ifdef will do the wrong thing if the option is disabled. #if (CONFIG_FOO == 1) is not needed. Change-Id: Ifcac6ceac5fb34b931281beae500023597b3533b Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/boot/coreboot_table.c | 14 +++++++------- 1 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c index 78ff97d..77a1126 100644 --- a/src/arch/x86/boot/coreboot_table.c +++ b/src/arch/x86/boot/coreboot_table.c @@ -29,7 +29,7 @@ #include <version.h> #include <device/device.h> #include <stdlib.h> -#if (CONFIG_USE_OPTION_TABLE == 1) +#if CONFIG_USE_OPTION_TABLE #include <option_table.h> #include <cbfs.h> #endif @@ -198,7 +198,7 @@ static struct lb_mainboard *lb_mainboard(struct lb_header *header) return mainboard; } -#if (CONFIG_USE_OPTION_TABLE == 1) +#if CONFIG_USE_OPTION_TABLE static struct cmos_checksum *lb_cmos_checksum(struct lb_header *header) { struct lb_record *rec; @@ -512,7 +512,7 @@ static void add_lb_reserved(struct lb_memory *mem) lb_add_rsvd_range, mem); } -#if CONFIG_WRITE_HIGH_TABLES == 1 +#if CONFIG_WRITE_HIGH_TABLES extern uint64_t high_tables_base, high_tables_size; #endif @@ -523,7 +523,7 @@ unsigned long write_coreboot_table( struct lb_header *head; struct lb_memory *mem; -#if CONFIG_WRITE_HIGH_TABLES == 1 +#if CONFIG_WRITE_HIGH_TABLES printk(BIOS_DEBUG, "Writing high table forward entry at 0x%08lx\n", low_table_end); head = lb_table_init(low_table_end); @@ -559,7 +559,7 @@ unsigned long write_coreboot_table( rom_table_end &= ~0xffff; printk(BIOS_DEBUG, "0x%08lx \n", rom_table_end); -#if (CONFIG_USE_OPTION_TABLE == 1) +#if CONFIG_USE_OPTION_TABLE { struct cmos_option_table *option_table = cbfs_find_file("cmos_layout.bin", 0x1aa); if (option_table) { @@ -584,7 +584,7 @@ unsigned long write_coreboot_table( lb_add_memory_range(mem, LB_MEM_TABLE, rom_table_start, rom_table_end-rom_table_start); -#if CONFIG_WRITE_HIGH_TABLES == 1 +#if CONFIG_WRITE_HIGH_TABLES printk(BIOS_DEBUG, "Adding high table area\n"); // should this be LB_MEM_ACPI? lb_add_memory_range(mem, LB_MEM_TABLE, @@ -594,7 +594,7 @@ unsigned long write_coreboot_table( /* Add reserved regions */ add_lb_reserved(mem); -#if (CONFIG_HAVE_MAINBOARD_RESOURCES == 1) +#if CONFIG_HAVE_MAINBOARD_RESOURCES add_mainboard_resources(mem); #endif

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coreboot March 2012