coreboot March 2012

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Patch set updated for coreboot: 2266b2e drop use of MAX_PHYSICAL_CPUS and MAX_CPUS where not needed
by Stefan Reinauer 09 Mar '12

09 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/760 -gerrit commit 2266b2ebc3018ece54bf806c5ab6f0577a04c08c Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Dec 15 09:24:40 2011 -0800 drop use of MAX_PHYSICAL_CPUS and MAX_CPUS where not needed Change-Id: Idf875ddec417e627f1e72a6d834860e7fd324a50 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/x86/lapic/lapic_cpu_init.c | 6 ------ src/cpu/x86/pae/Makefile.inc | 2 +- 2 files changed, 1 insertions(+), 7 deletions(-) diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index fc22ea4..99c3c4e 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -363,9 +363,7 @@ void secondary_cpu_init(void) { atomic_inc(&active_cpus); #if CONFIG_SERIAL_CPU_INIT == 1 - #if CONFIG_MAX_CPUS>2 spin_lock(&start_cpu_lock); - #endif #endif #ifdef __SSE3__ @@ -380,9 +378,7 @@ void secondary_cpu_init(void) #endif cpu_initialize(); #if CONFIG_SERIAL_CPU_INIT == 1 - #if CONFIG_MAX_CPUS>2 spin_unlock(&start_cpu_lock); - #endif #endif atomic_dec(&active_cpus); @@ -419,9 +415,7 @@ static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu) cpu->path.apic.apic_id); } #if CONFIG_SERIAL_CPU_INIT == 1 - #if CONFIG_MAX_CPUS>2 udelay(10); - #endif #endif } diff --git a/src/cpu/x86/pae/Makefile.inc b/src/cpu/x86/pae/Makefile.inc index 0ecec47..060720c 100644 --- a/src/cpu/x86/pae/Makefile.inc +++ b/src/cpu/x86/pae/Makefile.inc @@ -1 +1 @@ -ramstage-y += pgtbl.c +ramstage-$(CONFIG_CPU_AMD_MODEL_FXX) += pgtbl.c

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Patch set updated for coreboot: 6c9772d Fix MB calculation in the reporting of the MTRR hole
by Stefan Reinauer 09 Mar '12

09 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/763 -gerrit commit 6c9772d5ea46b3c5af27079aed14255759febfac Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Jan 6 15:49:30 2012 -0800 Fix MB calculation in the reporting of the MTRR hole Change-Id: I34b5c4ffd2a3f3e895d2bffedce1c00ee9aea942 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/cpu/x86/mtrr/mtrr.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 8dccfef..5f5e02b 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -306,7 +306,7 @@ static unsigned int range_to_mtrr(unsigned int reg, if (hole_sizek) { printk(BIOS_DEBUG, "Adding hole at %ldMB-%ldMB\n", - hole_startk, hole_startk + hole_sizek); + hole_startk >> 10, (hole_startk + hole_sizek) >> 10); reg = range_to_mtrr(reg, hole_startk, hole_sizek, next_range_startk, MTRR_TYPE_UNCACHEABLE, address_bits, above4gb);

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Patch set updated for coreboot: 43e2c9d Revamp cbmem.py to use the coreboot tables.
by Stefan Reinauer 09 Mar '12

09 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/762 -gerrit commit 43e2c9d38effdf1fca0f70d7abcb1a874e28690f Author: Gabe Black <gabeblack(a)google.com> Date: Sat Jan 7 01:03:42 2012 -0800 Revamp cbmem.py to use the coreboot tables. This change makes significant changes to cbmem.py to make it use the coreboot tables to find the memory console and timestamp areas instead of looking for the in memory table TOC structure. That appears to be more robust and gets cbmem.py working again after some unrelated changes that affected memory layout. It also introduces some small infrastructure to make accessing C style structures in physical memory easier and more transparent. Change-Id: I51833055a50c2d76423520ba6e059bf8fc50adea Signed-off-by: Gabe Black <gabeblack(a)google.com> --- util/cbmem/cbmem.py | 267 ++++++++++++++++++++++++++++++--------------------- 1 files changed, 158 insertions(+), 109 deletions(-) diff --git a/util/cbmem/cbmem.py b/util/cbmem/cbmem.py index 3e8476d..f4f3e88 100755 --- a/util/cbmem/cbmem.py +++ b/util/cbmem/cbmem.py @@ -33,29 +33,46 @@ console sections. ''' import mmap -import re import struct import sys -import time -# These definitions follow src/include/cbmem.h -CBMEM_MAGIC = 0x434f5245 -CBMEM_MAX_ENTRIES = 16 +def get_phys_mem(addr, size): + '''Read size bytes from address addr by mmaping /dev/mem''' -CBMEM_ENTRY_FORMAT = '@LLQQ' -CONSOLE_HEADER_FORMAT = '@LL' -TIMESTAMP_HEADER_FORMAT = '@QLL' -TIMESTAMP_ENTRY_FORMAT = '@LQ' - -mf_fileno = 0 # File number of the file providing access to memory. - -def align_up(base, alignment): - '''Increment to the alignment boundary. - - Return the next integer larger than 'base' and divisible by 'alignment'. - ''' - - return base + alignment - base % alignment + mf = open("/dev/mem") + delta = addr % 4096 + mm = mmap.mmap(mf.fileno(), size + delta, + mmap.MAP_PRIVATE, offset=(addr - delta)) + buf = mm.read(size + delta) + mf.close() + return buf[delta:] + +# This class and metaclass make it easier to define and access structures +# which live in physical memory. To use them, inherit from CStruct and define +# a class member called struct_members which is a tuple of pairs. The first +# item in the pair is the type format specifier that should be used with +# struct.unpack to read that member from memory. The second item is the name +# that member should have in the resulting object. + +class MetaCStruct(type): + def __init__(cls, name, bases, dct): + struct_members = dct["struct_members"] + cls.struct_fmt = "@" + for char, name in struct_members: + cls.struct_fmt += char + cls.struct_len = struct.calcsize(cls.struct_fmt) + super(MetaCStruct, cls).__init__(name, bases, dct) + +class CStruct(object): + __metaclass__ = MetaCStruct + struct_members = () + + def __init__(self, addr): + self.raw_memory = get_phys_mem(addr, self.struct_len) + values = struct.unpack(self.struct_fmt, self.raw_memory) + names = (name for char, name in self.struct_members) + for name, value in zip(names, values): + setattr(self, name, value) def normalize_timer(value, freq): '''Convert timer reading into microseconds. @@ -96,109 +113,141 @@ def get_cpu_freq(): # Convert reading into Hertz return float(freq_str) * 1000.0 -def get_mem_size(): - '''Retrieve amount of memory available to the CPU from /proc/meminfo.''' - mult = { - 'kB': 1024 - } - meminfo = open('/proc/meminfo').read() - m = re.search('MemTotal:.*\n', meminfo) - mem_string = re.search('MemTotal:.*\n', meminfo).group(0) - (_, size, mult_name) = mem_string.split() - return int(size) * mult[mult_name] - -def parse_mem_at(addr, format): - '''Read and parse a memory location. - - This function reads memory at the passed in address, parses it according - to the passed in format specification and returns a list of values. - - The first value in the list is the size of data matching the format - expression, and the rest of the elements of the list are the actual values - retrieved using the format. - ''' - - size = struct.calcsize(format) - delta = addr % 4096 # mmap requires the offset to be page size aligned. - mm = mmap.mmap(mf_fileno, size + delta, - mmap.MAP_PRIVATE, offset=(addr - delta)) - buf = mm.read(size + delta) - mm.close() - rv = [size,] + list(struct.unpack(format, buf[delta:size + delta + 1])) - return rv - -def dprint(text): - '''Debug print function. - - Edit it to get the debug output. - ''' - - if False: - print text - def process_timers(base): '''Scan the array of timestamps found in CBMEM at address base. For each timestamp print the timer ID and the value in microseconds. ''' - (step, base_time, max_entr, entr) = parse_mem_at( - base, TIMESTAMP_HEADER_FORMAT) - - print('\ntime base %d, total entries %d' % (base_time, entr)) + class TimestampHeader(CStruct): + struct_members = ( + ("Q", "base_time"), + ("L", "max_entr"), + ("L", "entr") + ) + + class TimestampEntry(CStruct): + struct_members = ( + ("L", "timer_id"), + ("Q", "timer_value") + ) + + header = TimestampHeader(base) + print('\ntime base %d, total entries %d' % (header.base_time, header.entr)) clock_freq = get_cpu_freq() - base = base + step - for i in range(entr): - (step, timer_id, timer_value) = parse_mem_at( - base, TIMESTAMP_ENTRY_FORMAT) - print '%d:%s ' % (timer_id, normalize_timer(timer_value, clock_freq)), - base = base + step + base = base + header.struct_len + for i in range(header.entr): + timestamp = TimestampEntry(base) + print '%d:%s ' % (timestamp.timer_id, + normalize_timer(timestamp.timer_value, clock_freq)), + base = base + timestamp.struct_len print def process_console(base): '''Dump the console log buffer contents found at address base.''' - (step, size, cursor) = parse_mem_at(base, CONSOLE_HEADER_FORMAT) - print 'cursor at %d\n' % cursor + class ConsoleHeader(CStruct): + struct_members = ( + ("L", "size"), + ("L", "cursor") + ) - cons_string_format = '%ds' % min(cursor, size) - (_, cons_text) = parse_mem_at(base + step, cons_string_format) + header = ConsoleHeader(base) + print 'cursor at %d\n' % header.cursor + + cons_addr = base + header.struct_len + cons_length = min(header.cursor, header.size) + cons_text = get_phys_mem(cons_addr, cons_length) print cons_text print '\n' -mem_alignment = 1024 * 1024 * 1024 # 1 GBytes -table_alignment = 128 * 1024 - -mem_size = get_mem_size() - -# start at memory address aligned at 128K. -offset = align_up(mem_size, table_alignment) - -dprint('mem_size %x offset %x' %(mem_size, offset)) -mf = open("/dev/mem") -mf_fileno = mf.fileno() - -while offset % mem_alignment: # do not cross the 1G boundary while searching - (step, magic, mid, base, size) = parse_mem_at(offset, CBMEM_ENTRY_FORMAT) - if magic == CBMEM_MAGIC: - offset = offset + step - break - offset += table_alignment -else: - print 'Did not find the CBMEM' - sys.exit(0) - -for i in (range(1, CBMEM_MAX_ENTRIES)): - (_, magic, mid, base, size) = parse_mem_at(offset, CBMEM_ENTRY_FORMAT) - if mid == 0: - break - - print '%x, %x, %x' % (mid, base, size) - if mid == 0x54494d45: - process_timers(base) - if mid == 0x434f4e53: - process_console(base) - - offset = offset + step - -mf.close() +def ipchksum(buf): + '''Checksumming function used on the coreboot tables. The buffer being + checksummed is summed up as if it was an array of 16 bit unsigned + integers. If there are an odd number of bytes, the last element is zero + extended.''' + + size = len(buf) + odd = size % 2 + fmt = "<%dH" % ((size - odd) / 2) + if odd: + fmt += "B" + shorts = struct.unpack(fmt, buf) + checksum = sum(shorts) + checksum = (checksum >> 16) + (checksum & 0xffff) + checksum += (checksum >> 16) + checksum = ~checksum & 0xffff + return checksum + +def parse_tables(base, length): + '''Find the coreboot tables in memory and process whatever we can.''' + + class CBTableHeader(CStruct): + struct_members = ( + ("4s", "signature"), + ("I", "header_bytes"), + ("I", "header_checksum"), + ("I", "table_bytes"), + ("I", "table_checksum"), + ("I", "table_entries") + ) + + class CBTableEntry(CStruct): + struct_members = ( + ("I", "tag"), + ("I", "size") + ) + + class CBTableForward(CBTableEntry): + struct_members = CBTableEntry.struct_members + ( + ("Q", "forward"), + ) + + class CBMemTab(CBTableEntry): + struct_members = CBTableEntry.struct_members + ( + ("L", "cbmem_tab"), + ) + + for addr in range(base, base + length, 16): + header = CBTableHeader(addr) + if header.signature == "LBIO": + break + else: + return -1 + + if header.header_bytes == 0: + return -1 + + if ipchksum(header.raw_memory) != 0: + print "Bad header checksum" + return -1 + + addr += header.header_bytes + table = get_phys_mem(addr, header.table_bytes) + if ipchksum(table) != header.table_checksum: + print "Bad table checksum" + return -1 + + for i in range(header.table_entries): + entry = CBTableEntry(addr) + if entry.tag == 0x11: # Forwarding entry + return parse_tables(CBTableForward(addr).forward, length) + elif entry.tag == 0x16: # Timestamps + process_timers(CBMemTab(addr).cbmem_tab) + elif entry.tag == 0x17: # CBMEM console + process_console(CBMemTab(addr).cbmem_tab) + + addr += entry.size + + return 0 + +def main(): + for base, length in (0x00000000, 0x1000), (0x000f0000, 0x1000): + if parse_tables(base, length): + break + else: + print "Didn't find the coreboot tables" + return 0 + +if __name__ == "__main__": + sys.exit(main())

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Patch set updated for coreboot: 5aabcb4 Add faster, architecture dependent memcpy()
by Stefan Reinauer 09 Mar '12

09 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/736 -gerrit commit 5aabcb486c2ed4c014d3a1f9981c7b1d47e0f4f4 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Oct 25 23:43:34 2011 +0000 Add faster, architecture dependent memcpy() Change-Id: I38d15f3f1ec65f0cb7974d2dd4ae6356433bddd8 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-by: Duncan Laurie <dlaurie(a)google.com> --- src/arch/x86/Kconfig | 4 ++++ src/arch/x86/lib/Makefile.inc | 4 ++++ src/arch/x86/lib/memcpy.c | 13 +++++++++++++ src/lib/Makefile.inc | 9 ++++++++- 4 files changed, 29 insertions(+), 1 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index e71d0f3..74933af 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -80,6 +80,10 @@ config CMOS_DEFAULT_FILE config BOOTBLOCK_SOUTHBRIDGE_INIT string +config HAVE_ARCH_MEMCPY + bool + default y + config BIG_ENDIAN bool default n diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc index 3388a9d..f99e429 100644 --- a/src/arch/x86/lib/Makefile.inc +++ b/src/arch/x86/lib/Makefile.inc @@ -8,8 +8,12 @@ ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c ramstage-y += pci_ops_auto.c ramstage-y += exception.c ramstage-$(CONFIG_IOAPIC) += ioapic.c +ramstage-y += memcpy.c romstage-y += romstage_console.c romstage-y += cbfs_and_run.c +romstage-y += memcpy.c + +smm-y += memcpy.c $(obj)/arch/x86/lib/console.ramstage.o :: $(obj)/build.h diff --git a/src/arch/x86/lib/memcpy.c b/src/arch/x86/lib/memcpy.c new file mode 100644 index 0000000..de21092 --- /dev/null +++ b/src/arch/x86/lib/memcpy.c @@ -0,0 +1,13 @@ +#include <string.h> + +void *memcpy(void *__restrict __dest, + __const void *__restrict __src, size_t __n) +{ + asm("cld\n" + "rep\n" + "movsb" + : /* no input (?) */ + :"S"(__src), "D"(__dest), "c"(__n) + ); + return __dest; +} diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 45cb788..61b6451 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -2,7 +2,9 @@ romstage-y += memset.c romstage-y += memchr.c +ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y) romstage-y += memcpy.c +endif romstage-y += memcmp.c romstage-y += cbfs.c romstage-y += lzma.c @@ -19,7 +21,9 @@ romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c ramstage-y += memset.c ramstage-y += memchr.c +ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y) ramstage-y += memcpy.c +endif ramstage-y += memcmp.c ramstage-y += memmove.c ramstage-y += malloc.c @@ -43,7 +47,10 @@ ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c driver-$(CONFIG_CONSOLE_NE2K) += ne2k.c -smm-y += memcpy.c cbfs.c memset.c memcmp.c +ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y) +smm-y += memcpy.c +endif +smm-y += cbfs.c memset.c memcmp.c smm-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c smm-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c smm-$(CONFIG_USBDEBUG) += usbdebug.c

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Patch set updated for coreboot: 975b9b7 Add native memset() function on x86
by Stefan Reinauer 09 Mar '12

09 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/737 -gerrit commit 975b9b72d3c88649355358c27810d9ed8d6669e4 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Oct 26 22:11:52 2011 +0000 Add native memset() function on x86 Change-Id: Ia118ebe0a4b59bdcefd78895141a365170f6aed2 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/Kconfig | 4 ++ src/arch/x86/lib/Makefile.inc | 2 + src/arch/x86/lib/memset.c | 85 +++++++++++++++++++++++++++++++++++++++++ src/lib/Makefile.inc | 4 ++ 4 files changed, 95 insertions(+), 0 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 74933af..078ae95 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -80,6 +80,10 @@ config CMOS_DEFAULT_FILE config BOOTBLOCK_SOUTHBRIDGE_INIT string +config HAVE_ARCH_MEMSET + bool + default y + config HAVE_ARCH_MEMCPY bool default y diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc index f99e429..3f4dc95 100644 --- a/src/arch/x86/lib/Makefile.inc +++ b/src/arch/x86/lib/Makefile.inc @@ -8,10 +8,12 @@ ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c ramstage-y += pci_ops_auto.c ramstage-y += exception.c ramstage-$(CONFIG_IOAPIC) += ioapic.c +ramstage-y += memset.c ramstage-y += memcpy.c romstage-y += romstage_console.c romstage-y += cbfs_and_run.c +romstage-y += memset.c romstage-y += memcpy.c smm-y += memcpy.c diff --git a/src/arch/x86/lib/memset.c b/src/arch/x86/lib/memset.c new file mode 100644 index 0000000..7c8129a --- /dev/null +++ b/src/arch/x86/lib/memset.c @@ -0,0 +1,85 @@ +/* + * Copyright (C) 1991,1992,1993,1997,1998,2003, 2005 Free Software Foundation, Inc. + * This file is part of the GNU C Library. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* From glibc-2.14, sysdeps/i386/memset.c */ + +#include <string.h> +#include <stdint.h> + +typedef uint32_t op_t; + +void *memset(void *dstpp, int c, size_t len) +{ + int d0; + unsigned long int dstp = (unsigned long int) dstpp; + + /* This explicit register allocation improves code very much indeed. */ + register op_t x asm("ax"); + + x = (unsigned char) c; + + /* Clear the direction flag, so filling will move forward. */ + asm volatile("cld"); + + /* This threshold value is optimal. */ + if (len >= 12) { + /* Fill X with four copies of the char we want to fill with. */ + x |= (x << 8); + x |= (x << 16); + + /* Adjust LEN for the bytes handled in the first loop. */ + len -= (-dstp) % sizeof(op_t); + + /* + * There are at least some bytes to set. No need to test for + * LEN == 0 in this alignment loop. + */ + + /* Fill bytes until DSTP is aligned on a longword boundary. */ + asm volatile( + "rep\n" + "stosb" /* %0, %2, %3 */ : + "=D" (dstp), "=c" (d0) : + "0" (dstp), "1" ((-dstp) % sizeof(op_t)), "a" (x) : + "memory"); + + /* Fill longwords. */ + asm volatile( + "rep\n" + "stosl" /* %0, %2, %3 */ : + "=D" (dstp), "=c" (d0) : + "0" (dstp), "1" (len / sizeof(op_t)), "a" (x) : + "memory"); + len %= sizeof(op_t); + } + + /* Write the last few bytes. */ + asm volatile( + "rep\n" + "stosb" /* %0, %2, %3 */ : + "=D" (dstp), "=c" (d0) : + "0" (dstp), "1" (len), "a" (x) : + "memory"); + + return dstpp; +} diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 61b6451..8ce72b2 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -1,6 +1,8 @@ +ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y) romstage-y += memset.c +endif romstage-y += memchr.c ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y) romstage-y += memcpy.c @@ -19,7 +21,9 @@ romstage-$(CONFIG_CONSOLE_NE2K) += compute_ip_checksum.c romstage-$(CONFIG_USBDEBUG) += usbdebug.c romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c +ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y) ramstage-y += memset.c +endif ramstage-y += memchr.c ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y) ramstage-y += memcpy.c

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Patch set updated for coreboot: 14573b9 Make TPM driver work in rom stage.
by Stefan Reinauer 09 Mar '12

09 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/738 -gerrit commit 14573b9bad4dfcec293ceec918f7d16f81135584 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Oct 27 21:28:25 2011 +0000 Make TPM driver work in rom stage. Change-Id: Ifc827d0cd0159aa3f6752d395974f2812334f262 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/pc80/tpm.c | 7 ++++--- 1 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/pc80/tpm.c b/src/pc80/tpm.c index 1cbf800..8e94303 100644 --- a/src/pc80/tpm.c +++ b/src/pc80/tpm.c @@ -35,6 +35,7 @@ #include <arch/byteorder.h> #include <console/console.h> #include <pc80/tpm.h> +#include <cpu/x86/car.h> #ifdef DEBUG #define TPM_DEBUG_ON 1 @@ -130,10 +131,10 @@ struct device_name { struct vendor_name { u16 vendor_id; const char * vendor_name; - struct device_name* dev_names; + const struct device_name* dev_names; }; -static struct device_name infineon_devices[] = { +static const struct device_name infineon_devices[] = { {0xb, "SLB9635 TT 1.2"}, {0} }; @@ -146,7 +147,7 @@ static const struct vendor_name vendor_names[] = { * Cached vendor/device ID pair to indicate that the device has been already * discovered */ -static u32 vendor_dev_id; +static u32 vendor_dev_id CAR_GLOBAL; static int is_byte_reg(u32 reg) {

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Patch set updated for coreboot: 64f465a Add an option to keep the ROM cached after romstage
by Stefan Reinauer 09 Mar '12

09 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/739 -gerrit commit 64f465a0154da1e425c5ef09f93662eab746cf4d Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Nov 2 16:12:34 2011 -0700 Add an option to keep the ROM cached after romstage Change-Id: I05f1cbd33f0cb7d80ec90c636d1607774b4a74ef Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/include/arch/acpi.h | 4 +++- src/cpu/x86/Kconfig | 4 +++- src/cpu/x86/lapic/Makefile.inc | 1 + src/cpu/x86/lapic/boot_cpu.c | 3 ++- src/cpu/x86/mtrr/mtrr.c | 14 +++++++++++++- src/include/cpu/x86/lapic.h | 4 ++++ 6 files changed, 26 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 030745d..504d71b 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -422,7 +422,8 @@ void *acpi_get_wakeup_rsdp(void); void acpi_jump_to_wakeup(void *wakeup_addr); int acpi_get_sleep_type(void); - +#else +#define acpi_slp_type 0 #endif /* northbridge/amd/amdfam10/amdfam10_acpi.c */ @@ -434,6 +435,7 @@ void generate_cpu_entries(void); #else // CONFIG_GENERATE_ACPI_TABLES #define write_acpi_tables(start) (start) +#define acpi_slp_type 0 #endif diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 348f0ef..fdbd527 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -39,4 +39,6 @@ config LOGICAL_CPUS bool default y - +config CACHE_ROM + bool + default n diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index af20956..f3fcadc 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -2,3 +2,4 @@ ramstage-y += lapic.c ramstage-y += lapic_cpu_init.c ramstage-y += secondary.S ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c +ramstage-y += boot_cpu.c diff --git a/src/cpu/x86/lapic/boot_cpu.c b/src/cpu/x86/lapic/boot_cpu.c index 87418d0..0fb9d5d 100644 --- a/src/cpu/x86/lapic/boot_cpu.c +++ b/src/cpu/x86/lapic/boot_cpu.c @@ -1,7 +1,8 @@ +#include <cpu/x86/lapic.h> #include <cpu/x86/msr.h> #if CONFIG_SMP -static int boot_cpu(void) +int boot_cpu(void) { int bsp; msr_t msr; diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 46d8e2d..9015ad4 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -36,7 +36,9 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> +#include <cpu/x86/lapic.h> #include <arch/cpu.h> +#include <arch/acpi.h> #if CONFIG_GFXUMA extern uint64_t uma_memory_base, uma_memory_size; @@ -48,7 +50,6 @@ static unsigned int mtrr_msr[] = { MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR, }; - void enable_fixed_mtrr(void) { msr_t msr; @@ -456,6 +457,17 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) while(var_state.reg < MTRRS) { set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits); } + +#if CONFIG_CACHE_ROM + /* Enable Caching and speculative Reads for the + * complete ROM now that we actually have RAM. + */ + if (boot_cpu() && (acpi_slp_type != 3)) { + set_var_mtrr(7, (4096-4)*1024, 4*1024, + MTRR_TYPE_WRPROT, address_bits); + } +#endif + printk(BIOS_SPEW, "call enable_var_mtrr()\n"); enable_var_mtrr(); printk(BIOS_SPEW, "Leave %s\n", __func__); diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 8b44a6c..016870d 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -1,6 +1,7 @@ #ifndef CPU_X86_LAPIC_H #define CPU_X86_LAPIC_H +#ifndef __ROMCC__ #include <cpu/x86/lapic_def.h> #include <cpu/x86/msr.h> #include <arch/hlt.h> @@ -156,4 +157,7 @@ int start_cpu(struct device *cpu); #endif /* !__PRE_RAM__ */ +int boot_cpu(void); +#endif + #endif /* CPU_X86_LAPIC_H */

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Patch set updated for coreboot: 9889f84 Add more timestamps in coreboot.
by Stefan Reinauer 09 Mar '12

09 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/749 -gerrit commit 9889f845d13f0093456abc006d87ea0d36d05ae6 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Nov 4 12:31:58 2011 -0700 Add more timestamps in coreboot. This adds a number of timestamps in ramstage and romstage so we can figure out where execution time goes. Change-Id: Iea17c08774e623fc1ca3fa4505b70523ba4cbf01 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/lib/cbfs_and_run.c | 3 +++ src/boot/hardwaremain.c | 21 +++++++++++++++++++++ src/include/timestamp.h | 22 ++++++++++++++++++++-- 3 files changed, 44 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/lib/cbfs_and_run.c b/src/arch/x86/lib/cbfs_and_run.c index ad36ddc..53f06ee 100644 --- a/src/arch/x86/lib/cbfs_and_run.c +++ b/src/arch/x86/lib/cbfs_and_run.c @@ -20,16 +20,19 @@ #include <console/console.h> #include <cbfs.h> #include <arch/stages.h> +#include <timestamp.h> static void cbfs_and_run_core(const char *filename, unsigned ebp) { u8 *dst; + timestamp_add_now(TS_START_COPYRAM); print_debug("Loading image.\n"); dst = cbfs_load_stage(filename); if ((void *)dst == (void *) -1) die("FATAL: Essential component is missing.\n"); + timestamp_add_now(TS_END_COPYRAM); print_debug("Jumping to image.\n"); __asm__ volatile ( "movl %%eax, %%ebp\n" diff --git a/src/boot/hardwaremain.c b/src/boot/hardwaremain.c index 9b293c0..489caa3 100644 --- a/src/boot/hardwaremain.c +++ b/src/boot/hardwaremain.c @@ -41,6 +41,7 @@ it with the version available from LANL. #if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> #endif +#include <timestamp.h> /** * @brief Main function of the RAM part of coreboot. @@ -56,7 +57,9 @@ void hardwaremain(int boot_complete); void hardwaremain(int boot_complete) { struct lb_memory *lb_mem; + tsc_t timestamps[6]; + timestamps[0] = rdtsc(); post_code(POST_ENTRY_RAMSTAGE); /* console_init() MUST PRECEDE ALL printk()! */ @@ -78,18 +81,26 @@ void hardwaremain(int boot_complete) /* FIXME: Is there a better way to handle this? */ init_timer(); + timestamps[1] = rdtsc(); /* Find the devices we don't have hard coded knowledge about. */ dev_enumerate(); post_code(POST_DEVICE_ENUMERATION_COMPLETE); + + timestamps[2] = rdtsc(); /* Now compute and assign the bus resources. */ dev_configure(); post_code(POST_DEVICE_CONFIGURATION_COMPLETE); + + timestamps[3] = rdtsc(); /* Now actually enable devices on the bus */ dev_enable(); + + timestamps[4] = rdtsc(); /* And of course initialize devices on the bus */ dev_initialize(); post_code(POST_DEVICES_ENABLED); + timestamps[5] = rdtsc(); #if CONFIG_WRITE_HIGH_TABLES == 1 cbmem_initialize(); #if CONFIG_CONSOLE_CBMEM @@ -101,10 +112,20 @@ void hardwaremain(int boot_complete) post_code(0x8a); #endif + timestamp_add(TS_START_RAMSTAGE, timestamps[0]); + timestamp_add(TS_DEVICE_ENUMERATE, timestamps[1]); + timestamp_add(TS_DEVICE_CONFIGURE, timestamps[2]); + timestamp_add(TS_DEVICE_ENABLE, timestamps[3]); + timestamp_add(TS_DEVICE_INITIALIZE, timestamps[4]); + timestamp_add(TS_DEVICE_DONE, timestamps[5]); + timestamp_add_now(TS_WRITE_TABLES); + /* Now that we have collected all of our information * write our configuration tables. */ lb_mem = write_tables(); + + timestamp_add_now(TS_LOAD_PAYLOAD); cbfs_load_payload(lb_mem, CONFIG_CBFS_PREFIX "/payload"); printk(BIOS_ERR, "Boot failed.\n"); } diff --git a/src/include/timestamp.h b/src/include/timestamp.h index 8b9a89a..0bb323c 100644 --- a/src/include/timestamp.h +++ b/src/include/timestamp.h @@ -35,14 +35,32 @@ struct timestamp_table { } __attribute__((packed)); enum timestamp_id { - TS_BEFORE_INITRAM = 1, - TS_AFTER_INITRAM = 2, + TS_START_ROMSTAGE = 1, + TS_BEFORE_INITRAM = 2, + TS_AFTER_INITRAM = 3, + TS_END_ROMSTAGE = 4, + TS_START_COPYRAM = 8, + TS_END_COPYRAM = 9, + TS_START_RAMSTAGE = 10, + TS_DEVICE_ENUMERATE = 30, + TS_DEVICE_CONFIGURE = 40, + TS_DEVICE_ENABLE = 50, + TS_DEVICE_INITIALIZE = 60, + TS_DEVICE_DONE = 70, + TS_WRITE_TABLES = 80, + TS_LOAD_PAYLOAD = 90, TS_ACPI_WAKE_JUMP = 98, TS_SELFBOOT_JUMP = 99, }; +#if CONFIG_COLLECT_TIMESTAMPS void timestamp_init(tsc_t base); void timestamp_add(enum timestamp_id id, tsc_t ts_time); void timestamp_add_now(enum timestamp_id id); +#else +#define timestamp_init(base) +#define timestamp_add(id, time) +#define timestamp_add_now(id) +#endif #endif

1 0

Patch set updated for coreboot: 5d7e6c4 Fix coreboot makefiles not to produce half baked output.
by Stefan Reinauer 09 Mar '12

09 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/750 -gerrit commit 5d7e6c4b3df30416e89ce03a1c96cb5a097c7d9a Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Sat Nov 5 02:07:01 2011 +0000 Fix coreboot makefiles not to produce half baked output. It looks like the cbfstool utility generates the output file even when it fails to generate it properly. This causes make, if started second time in a row, after cbfstool failure, to continue beyond the point of failure (as the corrupted output file is present in the output tree, the second make invocation presumes that it is valid, as it is newer than the dependencies). The output file should be created only when successful, in an atomic operation. There could be other places in the make system which require a similar fix, this needs to be investigated further. Change-Id: I7c17f033ee5937eb712b1a594122430cee5c9146 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/arch/x86/Makefile.inc | 16 +++++++++------- 1 files changed, 9 insertions(+), 7 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index aeb4875..b2b9143 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -58,13 +58,15 @@ extract_nth=$(word $(1), $(subst |, ,$(2))) ifneq ($(CONFIG_UPDATE_IMAGE),y) prebuild-files = \ $(foreach file,$(cbfs-files), \ - $(CBFSTOOL) $@ add $(call extract_nth,1,$(file)) $(call extract_nth,2,$(file)) $(call extract_nth,3,$(file)) $(call extract_nth,4,$(file)); ) + $(CBFSTOOL) $@.tmp add $(call extract_nth,1,$(file)) \ + $(call extract_nth,2,$(file)) $(call extract_nth,3,$(file)) \ + $(call extract_nth,4,$(file)) &&) prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) $(obj)/coreboot.pre1: $(obj)/coreboot.bootblock $$(prebuilt-files) $(CBFSTOOL) - rm -f $@ - $(CBFSTOOL) $@ create $(CONFIG_COREBOOT_ROMSIZE_KB)K $(obj)/coreboot.bootblock - $(prebuild-files) + $(CBFSTOOL) $@.tmp create $(CONFIG_COREBOOT_ROMSIZE_KB)K $(obj)/coreboot.bootblock + $(prebuild-files) true + mv $@.tmp $@ else .PHONY: $(obj)/coreboot.pre1 $(obj)/coreboot.pre1: $(CBFSTOOL) @@ -269,10 +271,10 @@ endif $(obj)/coreboot.pre: $(obj)/coreboot.romstage $(obj)/coreboot.pre1 $(CBFSTOOL) @printf " CBFS $(subst $(obj)/,,$(@))\n" - rm -f $@ - cp $(obj)/coreboot.pre1 $@ - $(CBFSTOOL) $@ add-stage $(obj)/romstage.elf \ + cp $(obj)/coreboot.pre1 $@.tmp + $(CBFSTOOL) $@.tmp add-stage $(obj)/romstage.elf \ $(CONFIG_CBFS_PREFIX)/romstage x 0x$(shell cat $(obj)/location.txt) + mv $@.tmp $@ #FIXME: location.txt might require an offset of header size #######################################################################

1 0

Patch set updated for coreboot: b9227e3 Allow components smaller than declared size.
by Stefan Reinauer 09 Mar '12

09 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/751 -gerrit commit b9227e30a26be8c87b30fbf0c43a0be8833a1afd Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Nov 9 14:11:26 2011 -0800 Allow components smaller than declared size. idftool was failing to add the ME blobs into the output image in case the blob size does not exactly match the size allocated for it in the flashrom structure. It is difficult to set the field in the structure to exactly match the size (for some reason Intel flash tool fails to insert the correct size even when given the exact ME blob). On the other hand there is no harm in using am ME blob smaller than the allocated size, this change modifies the tool building the image to allow for smaller components. Change-Id: I1b04f90051b91157391943c9bad0eb06dd297431 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- util/ifdtool/ifdtool.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index eb91b2c..8c1077c 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -334,7 +334,7 @@ void inject_region(char *filename, char *image, int size, int region_type, printf("File %s is %d bytes\n", region_fname, region_size); if ( (region_size > region.size) || ((region_type != 1) && - (region_size != region.size))) { + (region_size > region.size))) { fprintf(stderr, "Region %s is %d(0x%x) bytes. File is %d(0x%x)" " bytes. Not injecting.\n", region_name(region_type), region.size,

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coreboot March 2012