coreboot March 2012

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Patch set updated for coreboot: efcb447 selfboot: Allow loading SeaBIOS into a reserved region in the lower 1MB This fixes loading SeaBIOS when lower memory is reserved.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/732 -gerrit commit efcb44797d8cb116926eb6876cbbf59b373da804 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Oct 18 15:11:04 2011 -0700 selfboot: Allow loading SeaBIOS into a reserved region in the lower 1MB This fixes loading SeaBIOS when lower memory is reserved. Change-Id: Idbdcaf95f3307f97307f304d6d677406d059927d Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/boot/selfboot.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/src/boot/selfboot.c b/src/boot/selfboot.c index fe56653..bbf160e 100644 --- a/src/boot/selfboot.c +++ b/src/boot/selfboot.c @@ -148,6 +148,11 @@ static int valid_area(struct lb_memory *mem, unsigned long buffer, } } if (i == mem_entries) { + if (start < (1024*1024) && end <=(1024*1024)) { + printk(BIOS_DEBUG, "Payload (probably SeaBIOS) loaded" + " into a reserved area in the lower 1MB\n"); + return 1; + } printk(BIOS_ERR, "No matching ram area found for range:\n"); printk(BIOS_ERR, " [0x%016lx, 0x%016lx)\n", start, end); printk(BIOS_ERR, "Ram areas\n");

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Patch set updated for coreboot: 4532872 Add TPM support to coreboot
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/731 -gerrit commit 4532872237d30da130d3a30551df3cd25a30f0f8 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Oct 11 14:46:25 2011 -0700 Add TPM support to coreboot and initialize the TPM on S3 resume This patch integrates the TPM driver and runs TPM resume upon an ACPI S3 resume without including any other parts of vboot. We could link against vboot_fw.a but it is compiled with u-boot's CFLAGS (that are incompatible with coreboot's) and it does a lot more than we want it to do. Change-Id: I000d4322ef313e931e23c56defaa17e3a4d7f8cf Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/Kconfig | 4 + src/arch/x86/boot/acpi.c | 8 + src/include/pc80/tpm.h | 29 ++ src/pc80/Makefile.inc | 1 + src/pc80/tpm.c | 554 ++++++++++++++++++++++++++++++++ src/vendorcode/google/chromeos/vboot.c | 201 ++++++++++++ 6 files changed, 797 insertions(+), 0 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 573868f..26e6dde 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -262,6 +262,10 @@ config IOAPIC bool default n +config TPM + bool + default n + # TODO: Can probably be removed once all chipsets have kconfig options for it. config VIDEO_MB int diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index f1be034..eb2e4e1 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -31,6 +31,9 @@ #include <arch/acpigen.h> #include <device/pci.h> #include <cbmem.h> +#if CONFIG_CHROMEOS +#include <vendorcode/google/chromeos/chromeos.h> +#endif u8 acpi_checksum(u8 *table, u32 length) { @@ -525,6 +528,11 @@ void *acpi_find_wakeup_vector(void) if (!acpi_is_wakeup()) return NULL; +#ifdef CONFIG_CHROMEOS + printk(BIOS_DEBUG, "Verified boot TPM initialization.\n"); + init_vboot(); +#endif + printk(BIOS_DEBUG, "Trying to find the wakeup vector...\n"); /* Find RSDP. */ diff --git a/src/include/pc80/tpm.h b/src/include/pc80/tpm.h new file mode 100644 index 0000000..2eff15a --- /dev/null +++ b/src/include/pc80/tpm.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef TPM_H_ +#define TPM_H_ + +int tis_init(void); +int tis_open(void); +int tis_close(void); +int tis_sendrecv(const u8 *sendbuf, size_t send_size, u8 *recvbuf, + size_t *recv_len); + +#endif /* TPM_H_ */ diff --git a/src/pc80/Makefile.inc b/src/pc80/Makefile.inc index 2c8a80e..cd6ea33 100644 --- a/src/pc80/Makefile.inc +++ b/src/pc80/Makefile.inc @@ -4,6 +4,7 @@ ramstage-y += i8254.c ramstage-y += i8259.c ramstage-$(CONFIG_UDELAY_IO) += udelay_io.c ramstage-y += keyboard.c +ramstage-$(CONFIG_TPM) += tpm.c romstage-$(CONFIG_USE_OPTION_TABLE) += mc146818rtc_early.c subdirs-y += vga diff --git a/src/pc80/tpm.c b/src/pc80/tpm.c new file mode 100644 index 0000000..1cbf800 --- /dev/null +++ b/src/pc80/tpm.c @@ -0,0 +1,554 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * The code in this file has been heavily based on the article "Writing a TPM + * Device Driver" published on http://ptgmedia.pearsoncmg.com and the + * submission by Stefan Berger on Qemu-devel mailing list. + * + * One principal difference is that in the simplest config the other than 0 + * TPM localities do not get mapped by some devices (for instance, by + * Infineon slb9635), so this driver provides access to locality 0 only. + */ + +/* #define DEBUG */ +#include <stdlib.h> +#include <string.h> +#include <delay.h> +#include <arch/io.h> +#include <arch/byteorder.h> +#include <console/console.h> +#include <pc80/tpm.h> + +#ifdef DEBUG +#define TPM_DEBUG_ON 1 +#else +#define TPM_DEBUG_ON 0 +#endif + +#define PREFIX "lpc_tpm: " + +/* coreboot wrapper for TPM driver (start) */ +#define TPM_DEBUG(fmt, args...) \ + if (TPM_DEBUG_ON) { \ + printk(BIOS_DEBUG, PREFIX); \ + printk(BIOS_DEBUG, fmt , ##args); \ + } +#define printf(x...) printk(BIOS_ERR, x) + +#define min(a,b) MIN(a,b) +#define max(a,b) MAX(a,b) +#define readb(_a) (*(volatile unsigned char *) (_a)) +#define writeb(_v, _a) (*(volatile unsigned char *) (_a) = (_v)) +#define readl(_a) (*(volatile unsigned long *) (_a)) +#define writel(_v, _a) (*(volatile unsigned long *) (_a) = (_v)) +/* coreboot wrapper for TPM driver (end) */ + +#ifndef CONFIG_TPM_TIS_BASE_ADDRESS +/* Base TPM address standard for x86 systems */ +#define CONFIG_TPM_TIS_BASE_ADDRESS 0xfed40000 +#endif + +/* the macro accepts the locality value, but only locality 0 is operational */ +#define TIS_REG(LOCALITY, REG) \ + (void *)(CONFIG_TPM_TIS_BASE_ADDRESS + (LOCALITY << 12) + REG) + +/* hardware registers' offsets */ +#define TIS_REG_ACCESS 0x0 +#define TIS_REG_INT_ENABLE 0x8 +#define TIS_REG_INT_VECTOR 0xc +#define TIS_REG_INT_STATUS 0x10 +#define TIS_REG_INTF_CAPABILITY 0x14 +#define TIS_REG_STS 0x18 +#define TIS_REG_DATA_FIFO 0x24 +#define TIS_REG_DID_VID 0xf00 +#define TIS_REG_RID 0xf04 + +/* Some registers' bit field definitions */ +#define TIS_STS_VALID (1 << 7) /* 0x80 */ +#define TIS_STS_COMMAND_READY (1 << 6) /* 0x40 */ +#define TIS_STS_TPM_GO (1 << 5) /* 0x20 */ +#define TIS_STS_DATA_AVAILABLE (1 << 4) /* 0x10 */ +#define TIS_STS_EXPECT (1 << 3) /* 0x08 */ +#define TIS_STS_RESPONSE_RETRY (1 << 1) /* 0x02 */ + +#define TIS_ACCESS_TPM_REG_VALID_STS (1 << 7) /* 0x80 */ +#define TIS_ACCESS_ACTIVE_LOCALITY (1 << 5) /* 0x20 */ +#define TIS_ACCESS_BEEN_SEIZED (1 << 4) /* 0x10 */ +#define TIS_ACCESS_SEIZE (1 << 3) /* 0x08 */ +#define TIS_ACCESS_PENDING_REQUEST (1 << 2) /* 0x04 */ +#define TIS_ACCESS_REQUEST_USE (1 << 1) /* 0x02 */ +#define TIS_ACCESS_TPM_ESTABLISHMENT (1 << 0) /* 0x01 */ + +#define TIS_STS_BURST_COUNT_MASK (0xffff) +#define TIS_STS_BURST_COUNT_SHIFT (8) + +/* + * Error value returned if a tpm register does not enter the expected state + * after continuous polling. No actual TPM register reading ever returns ~0, + * so this value is a safe error indication to be mixed with possible status + * register values. + */ +#define TPM_TIMEOUT_ERR (~0) + +/* Error value returned on various TPM driver errors */ +#define TPM_DRIVER_ERR (~0) + + /* 1 second is plenty for anything TPM does.*/ +#define MAX_DELAY_US (1000 * 1000) + +/* Retrieve burst count value out of the status register contents. */ +#define BURST_COUNT(status) ((u16)(((status) >> TIS_STS_BURST_COUNT_SHIFT) & \ + TIS_STS_BURST_COUNT_MASK)) + +/* + * Structures defined below allow creating descriptions of TPM vendor/device + * ID information for run time discovery. The only device the system knows + * about at this time is Infineon slb9635 + */ +struct device_name { + u16 dev_id; + const char * const dev_name; +}; + +struct vendor_name { + u16 vendor_id; + const char * vendor_name; + struct device_name* dev_names; +}; + +static struct device_name infineon_devices[] = { + {0xb, "SLB9635 TT 1.2"}, + {0} +}; + +static const struct vendor_name vendor_names[] = { + {0x15d1, "Infineon", infineon_devices}, +}; + +/* + * Cached vendor/device ID pair to indicate that the device has been already + * discovered + */ +static u32 vendor_dev_id; + +static int is_byte_reg(u32 reg) +{ + /* + * These TPM registers are 8 bits wide and as such require byte access + * on writes and truncated value on reads. + */ + return ((reg == TIS_REG_ACCESS) || + (reg == TIS_REG_INT_VECTOR) || + (reg == TIS_REG_DATA_FIFO)); +} + +/* TPM access functions are carved out to make tracing easier. */ +static u32 tpm_read(int locality, u32 reg) +{ + u32 value; + /* + * Data FIFO register must be read and written in byte access mode, + * otherwise the FIFO values are returned 4 bytes at a time. + */ + if (is_byte_reg(reg)) + value = readb(TIS_REG(locality, reg)); + else + value = readl(TIS_REG(locality, reg)); + + TPM_DEBUG("Read reg 0x%x returns 0x%x\n", reg, value); + return value; +} + +static void tpm_write(u32 value, int locality, u32 reg) +{ + TPM_DEBUG("Write reg 0x%x with 0x%x\n", reg, value); + + if (is_byte_reg(reg)) + writeb(value & 0xff, TIS_REG(locality, reg)); + else + writel(value, TIS_REG(locality, reg)); +} + +/* + * tis_wait_reg() + * + * Wait for at least a second for a register to change its state to match the + * expected state. Normally the transition happens within microseconds. + * + * @reg - the TPM register offset + * @locality - locality + * @mask - bitmask for the bitfield(s) to watch + * @expected - value the field(s) are supposed to be set to + * + * Returns the register contents in case the expected value was found in the + * appropriate register bits, or TPM_TIMEOUT_ERR on timeout. + */ +static u32 tis_wait_reg(u8 reg, u8 locality, u8 mask, u8 expected) +{ + u32 time_us = MAX_DELAY_US; + while (time_us > 0) { + u32 value = tpm_read(locality, reg); + if ((value & mask) == expected) + return value; + udelay(1); /* 1 us */ + time_us--; + } + return TPM_TIMEOUT_ERR; +} + +/* + * Probe the TPM device and try determining its manufacturer/device name. + * + * Returns 0 on success (the device is found or was found during an earlier + * invocation) or TPM_DRIVER_ERR if the device is not found. + */ +static u32 tis_probe(void) +{ + u32 didvid = tpm_read(0, TIS_REG_DID_VID); + int i; + const char *device_name = "unknown"; + const char *vendor_name = device_name; + u16 vid, did; + + if (vendor_dev_id) + return 0; /* Already probed. */ + + if (!didvid || (didvid == 0xffffffff)) { + printf("%s: No TPM device found\n", __FUNCTION__); + return TPM_DRIVER_ERR; + } + + vendor_dev_id = didvid; + + vid = didvid & 0xffff; + did = (didvid >> 16) & 0xffff; + for (i = 0; i < ARRAY_SIZE(vendor_names); i++) { + int j = 0; + u16 known_did; + if (vid == vendor_names[i].vendor_id) { + vendor_name = vendor_names[i].vendor_name; + } + while ((known_did = vendor_names[i].dev_names[j].dev_id) != 0) { + if (known_did == did) { + device_name = + vendor_names[i].dev_names[j].dev_name; + break; + } + j++; + } + break; + } + /* this will have to be converted into debug printout */ + TPM_DEBUG("Found TPM %s by %s\n", device_name, vendor_name); + return 0; +} + +/* + * tis_senddata() + * + * send the passed in data to the TPM device. + * + * @data - address of the data to send, byte by byte + * @len - length of the data to send + * + * Returns 0 on success, TPM_DRIVER_ERR on error (in case the device does + * not accept the entire command). + */ +static u32 tis_senddata(const u8 * const data, u32 len) +{ + u32 offset = 0; + u16 burst = 0; + u32 max_cycles = 0; + u8 locality = 0; + u32 value; + + value = tis_wait_reg(TIS_REG_STS, locality, TIS_STS_COMMAND_READY, + TIS_STS_COMMAND_READY); + if (value == TPM_TIMEOUT_ERR) { + printf("%s:%d - failed to get 'command_ready' status\n", + __FILE__, __LINE__); + return TPM_DRIVER_ERR; + } + burst = BURST_COUNT(value); + + while (1) { + unsigned count; + + /* Wait till the device is ready to accept more data. */ + while (!burst) { + if (max_cycles++ == MAX_DELAY_US) { + printf("%s:%d failed to feed %d bytes of %d\n", + __FILE__, __LINE__, len - offset, len); + return TPM_DRIVER_ERR; + } + udelay(1); + burst = BURST_COUNT(tpm_read(locality, TIS_REG_STS)); + } + + max_cycles = 0; + + /* + * Calculate number of bytes the TPM is ready to accept in one + * shot. + * + * We want to send the last byte outside of the loop (hence + * the -1 below) to make sure that the 'expected' status bit + * changes to zero exactly after the last byte is fed into the + * FIFO. + */ + count = min(burst, len - offset - 1); + while (count--) + tpm_write(data[offset++], locality, TIS_REG_DATA_FIFO); + + value = tis_wait_reg(TIS_REG_STS, locality, + TIS_STS_VALID, TIS_STS_VALID); + + if ((value == TPM_TIMEOUT_ERR) || !(value & TIS_STS_EXPECT)) { + printf("%s:%d TPM command feed overflow\n", + __FILE__, __LINE__); + return TPM_DRIVER_ERR; + } + + burst = BURST_COUNT(value); + if ((offset == (len - 1)) && burst) + /* + * We need to be able to send the last byte to the + * device, so burst size must be nonzero before we + * break out. + */ + break; + } + + /* Send the last byte. */ + tpm_write(data[offset++], locality, TIS_REG_DATA_FIFO); + + /* + * Verify that TPM does not expect any more data as part of this + * command. + */ + value = tis_wait_reg(TIS_REG_STS, locality, + TIS_STS_VALID, TIS_STS_VALID); + if ((value == TPM_TIMEOUT_ERR) || (value & TIS_STS_EXPECT)) { + printf("%s:%d unexpected TPM status 0x%x\n", + __FILE__, __LINE__, value); + return TPM_DRIVER_ERR; + } + + /* OK, sitting pretty, let's start the command execution. */ + tpm_write(TIS_STS_TPM_GO, locality, TIS_REG_STS); + + return 0; +} + +/* + * tis_readresponse() + * + * read the TPM device response after a command was issued. + * + * @buffer - address where to read the response, byte by byte. + * @len - pointer to the size of buffer + * + * On success stores the number of received bytes to len and returns 0. On + * errors (misformatted TPM data or synchronization problems) returns + * TPM_DRIVER_ERR. + */ +static u32 tis_readresponse(u8 *buffer, size_t *len) +{ + u16 burst_count; + u32 status; + u32 offset = 0; + u8 locality = 0; + const u32 has_data = TIS_STS_DATA_AVAILABLE | TIS_STS_VALID; + u32 expected_count = *len; + int max_cycles = 0; + + /* Wait for the TPM to process the command */ + status = tis_wait_reg(TIS_REG_STS, locality, has_data, has_data); + if (status == TPM_TIMEOUT_ERR) { + printf("%s:%d failed processing command\n", + __FILE__, __LINE__); + return TPM_DRIVER_ERR; + } + + do { + while ((burst_count = BURST_COUNT(status)) == 0) { + if (max_cycles++ == MAX_DELAY_US) { + printf("%s:%d TPM stuck on read\n", + __FILE__, __LINE__); + return TPM_DRIVER_ERR; + } + udelay(1); + status = tpm_read(locality, TIS_REG_STS); + } + + max_cycles = 0; + + while (burst_count-- && (offset < expected_count)) { + buffer[offset++] = (u8) tpm_read(locality, + TIS_REG_DATA_FIFO); + if (offset == 6) { + /* + * We got the first six bytes of the reply, + * let's figure out how many bytes to expect + * total - it is stored as a 4 byte number in + * network order, starting with offset 2 into + * the body of the reply. + */ + u32 real_length; + memcpy(&real_length, + buffer + 2, + sizeof(real_length)); + expected_count = be32_to_cpu(real_length); + + if ((expected_count < offset) || + (expected_count > *len)) { + printf("%s:%d bad response size %d\n", + __FILE__, __LINE__, + expected_count); + return TPM_DRIVER_ERR; + } + } + } + + /* Wait for the next portion */ + status = tis_wait_reg(TIS_REG_STS, locality, + TIS_STS_VALID, TIS_STS_VALID); + if (status == TPM_TIMEOUT_ERR) { + printf("%s:%d failed to read response\n", + __FILE__, __LINE__); + return TPM_DRIVER_ERR; + } + + if (offset == expected_count) + break; /* We got all we need */ + + } while ((status & has_data) == has_data); + + /* + * Make sure we indeed read all there was. The TIS_STS_VALID bit is + * known to be set. + */ + if (status & TIS_STS_DATA_AVAILABLE) { + printf("%s:%d wrong receive status %x\n", + __FILE__, __LINE__, status); + return TPM_DRIVER_ERR; + } + + /* Tell the TPM that we are done. */ + tpm_write(TIS_STS_COMMAND_READY, locality, TIS_REG_STS); + + *len = offset; + return 0; +} + +/* + * tis_init() + * + * Initialize the TPM device. Returns 0 on success or TPM_DRIVER_ERR on + * failure (in case device probing did not succeed). + */ +int tis_init(void) +{ + if (tis_probe()) + return TPM_DRIVER_ERR; + return 0; +} + +/* + * tis_open() + * + * Requests access to locality 0 for the caller. After all commands have been + * completed the caller is supposed to call tis_close(). + * + * Returns 0 on success, TPM_DRIVER_ERR on failure. + */ +int tis_open(void) +{ + u8 locality = 0; /* we use locality zero for everything */ + + if (tis_close()) + return TPM_DRIVER_ERR; + + /* now request access to locality */ + tpm_write(TIS_ACCESS_REQUEST_USE, locality, TIS_REG_ACCESS); + + /* did we get a lock? */ + if (tis_wait_reg(TIS_REG_ACCESS, locality, + TIS_ACCESS_ACTIVE_LOCALITY, + TIS_ACCESS_ACTIVE_LOCALITY) == TPM_TIMEOUT_ERR) { + printf("%s:%d - failed to lock locality %d\n", + __FILE__, __LINE__, locality); + return TPM_DRIVER_ERR; + } + + tpm_write(TIS_STS_COMMAND_READY, locality, TIS_REG_STS); + + return 0; +} + +/* + * tis_close() + * + * terminate the currect session with the TPM by releasing the locked + * locality. Returns 0 on success of TPM_DRIVER_ERR on failure (in case lock + * removal did not succeed). + */ +int tis_close(void) +{ + u8 locality = 0; + if (tpm_read(locality, TIS_REG_ACCESS) & + TIS_ACCESS_ACTIVE_LOCALITY) { + tpm_write(TIS_ACCESS_ACTIVE_LOCALITY, locality, TIS_REG_ACCESS); + + if (tis_wait_reg(TIS_REG_ACCESS, locality, + TIS_ACCESS_ACTIVE_LOCALITY, 0) == + TPM_TIMEOUT_ERR) { + printf("%s:%d - failed to release locality %d\n", + __FILE__, __LINE__, locality); + return TPM_DRIVER_ERR; + } + } + return 0; +} + +/* + * tis_sendrecv() + * + * Send the requested data to the TPM and then try to get its response + * + * @sendbuf - buffer of the data to send + * @send_size size of the data to send + * @recvbuf - memory to save the response to + * @recv_len - pointer to the size of the response buffer + * + * Returns 0 on success (and places the number of response bytes at recv_len) + * or TPM_DRIVER_ERR on failure. + */ +int tis_sendrecv(const uint8_t *sendbuf, size_t send_size, + uint8_t *recvbuf, size_t *recv_len) +{ + if (tis_senddata(sendbuf, send_size)) { + printf("%s:%d failed sending data to TPM\n", + __FILE__, __LINE__); + return TPM_DRIVER_ERR; + } + + return tis_readresponse(recvbuf, recv_len); +} diff --git a/src/vendorcode/google/chromeos/vboot.c b/src/vendorcode/google/chromeos/vboot.c new file mode 100644 index 0000000..e0a8c9b --- /dev/null +++ b/src/vendorcode/google/chromeos/vboot.c @@ -0,0 +1,201 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <pc80/tpm.h> +#include "chromeos.h" + +//#define EXTRA_LOGGING + +#define TPM_LARGE_ENOUGH_COMMAND_SIZE 256 /* saves space in the firmware */ + +#define TPM_SUCCESS ((u32)0x00000000) + +#define TPM_E_IOERROR ((u32)0x0000001f) +#define TPM_E_COMMUNICATION_ERROR ((u32)0x00005004) +#define TPM_E_NON_FATAL ((u32)0x00000800) +#define TPM_E_INVALID_POSTINIT ((u32)0x00000026) + +#define TPM_E_NEEDS_SELFTEST ((u32)(TPM_E_NON_FATAL + 1)) +#define TPM_E_DOING_SELFTEST ((u32)(TPM_E_NON_FATAL + 2)) + +static const struct { + u8 buffer[12]; +} tpm_resume_cmd = { + { 0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x0, 0x99, 0x0, 0x2 } +}; + +static const struct { + u8 buffer[10]; +} tpm_continueselftest_cmd = { + { 0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x53 } +}; + +static inline void FromTpmUint32(const u8 * buffer, u32 * x) +{ + *x = ((buffer[0] << 24) | + (buffer[1] << 16) | (buffer[2] << 8) | buffer[3]); +} + +static inline int TpmCommandSize(const u8 * buffer) +{ + u32 size; + FromTpmUint32(buffer + sizeof(u16), &size); + return (int)size; +} + +/* Gets the code field of a TPM command. */ +static inline int TpmCommandCode(const u8 * buffer) +{ + u32 code; + FromTpmUint32(buffer + sizeof(u16) + sizeof(u32), &code); + return code; +} + +/* Gets the return code field of a TPM result. */ +static inline int TpmReturnCode(const u8 * buffer) +{ + return TpmCommandCode(buffer); +} + +/* Like TlclSendReceive below, but do not retry if NEEDS_SELFTEST or + * DOING_SELFTEST errors are returned. + */ +static u32 TlclSendReceiveNoRetry(const u8 * request, + u8 * response, int max_length) +{ + size_t response_length = max_length; + u32 result; + +#ifdef EXTRA_LOGGING + printk(BIOS_DEBUG, "TPM: command: %x%x %x%x%x%x %x%x%x%x\n", + request[0], request[1], + request[2], request[3], request[4], request[5], + request[6], request[7], request[8], request[9]); +#endif + + result = TPM_SUCCESS; + if (tis_sendrecv + (request, TpmCommandSize(request), response, &response_length)) + result = TPM_E_IOERROR; + + if (0 != result) { + /* Communication with TPM failed, so response is garbage */ + printk(BIOS_DEBUG, + "TPM: command 0x%x send/receive failed: 0x%x\n", + TpmCommandCode(request), result); + return TPM_E_COMMUNICATION_ERROR; + } + /* Otherwise, use the result code from the response */ + result = TpmReturnCode(response); + +/* TODO: add paranoia about returned response_length vs. max_length + * (and possibly expected length from the response header). See + * crosbug.com/17017 */ + +#ifdef EXTRA_LOGGING + printk(BIOS_DEBUG, "TPM: response: %x%x %x%x%x%x %x%x%x%x\n", + response[0], response[1], + response[2], response[3], response[4], response[5], + response[6], response[7], response[8], response[9]); +#endif + + printk(BIOS_DEBUG, "TPM: command 0x%x returned 0x%x\n", + TpmCommandCode(request), result); + + return result; +} + +static inline u32 TlclContinueSelfTest(void) +{ + u8 response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; + printk(BIOS_DEBUG, "TPM: Continue self test\n"); + /* Call the No Retry version of SendReceive to avoid recursion. */ + return TlclSendReceiveNoRetry(tpm_continueselftest_cmd.buffer, + response, sizeof(response)); +} + +/* Sends a TPM command and gets a response. Returns 0 if success or the TPM + * error code if error. In the firmware, waits for the self test to complete + * if needed. In the host, reports the first error without retries. */ +static u32 TlclSendReceive(const u8 * request, u8 * response, int max_length) +{ + u32 result = TlclSendReceiveNoRetry(request, response, max_length); + /* When compiling for the firmware, hide command failures due to the self + * test not having run or completed. */ + /* If the command fails because the self test has not completed, try it + * again after attempting to ensure that the self test has completed. */ + if (result == TPM_E_NEEDS_SELFTEST || result == TPM_E_DOING_SELFTEST) { + result = TlclContinueSelfTest(); + if (result != TPM_SUCCESS) { + return result; + } +#if defined(TPM_BLOCKING_CONTINUESELFTEST) || defined(VB_RECOVERY_MODE) + /* Retry only once */ + result = TlclSendReceiveNoRetry(request, response, max_length); +#else + /* This needs serious testing. The TPM specification says: + * "iii. The caller MUST wait for the actions of + * TPM_ContinueSelfTest to complete before reissuing the + * command C1." But, if ContinueSelfTest is non-blocking, how + * do we know that the actions have completed other than trying + * again? */ + do { + result = + TlclSendReceiveNoRetry(request, response, + max_length); + } while (result == TPM_E_DOING_SELFTEST); +#endif + } + + return result; +} + +void init_vboot(void) +{ + u32 result; + u8 response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; + + printk(BIOS_DEBUG, "TPM: Init\n"); + if (tis_init()) + return; + + printk(BIOS_DEBUG, "TPM: Open\n"); + if (tis_open()) + return; + + printk(BIOS_DEBUG, "TPM: Resume\n"); + + result = + TlclSendReceive(tpm_resume_cmd.buffer, response, sizeof(response)); + + if (result == TPM_E_INVALID_POSTINIT) { + /* We're on a platform where the TPM maintains power in S3, so + * it's already initialized. */ + printk(BIOS_DEBUG, "TPM: Already initialized.\n"); + return; + } + if (result == TPM_SUCCESS) { + printk(BIOS_DEBUG, "TPM: OK.\n"); + return; + } + // TODO(reinauer) hard reboot? +}

1 0

Patch set updated for coreboot: b213a6d Don't run any option roms stored outside of the system flash
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/730 -gerrit commit b213a6d254dd2a9a9ebdca982576e7072a89db04 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Oct 6 16:47:51 2011 -0700 Don't run any option roms stored outside of the system flash Right now coreboot only executes vga option roms. However, this is not good enough. For security reasons we want to execute only option roms stored in our RO CBFS. This patch adds a new option to disable execution of arbitrary option ROMs and enables it for all our boards. Change-Id: I485291c06ec5cd1f875357401831fe32ccfc5f2f Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/devices/Kconfig | 13 +++++++++++++ src/devices/pci_rom.c | 6 ++++++ 2 files changed, 19 insertions(+), 0 deletions(-) diff --git a/src/devices/Kconfig b/src/devices/Kconfig index 572addc..98e8d9f 100644 --- a/src/devices/Kconfig +++ b/src/devices/Kconfig @@ -49,6 +49,19 @@ config PCI_ROM_RUN Examples include IDE/SATA controller option ROMs and option ROMs for network cards (NICs). +config ON_DEVICE_ROM_RUN + bool "Run option ROMs on PCI devices" + default y + help + Execute option ROMs that are stored on PCI/PCIe/AGP devices. + + If disabled, only option ROMs stored in CBFS will be executed. If + you are concerned about security, you might want to disable this + option, but it might leave your system in a state of degraded + functionality. + + If unsure, say Y + choice prompt "Option ROM execution type" default PCI_OPTION_ROM_RUN_YABEL if !ARCH_X86 diff --git a/src/devices/pci_rom.c b/src/devices/pci_rom.c index 471c7e2..1b6f1da 100644 --- a/src/devices/pci_rom.c +++ b/src/devices/pci_rom.c @@ -71,9 +71,15 @@ struct rom_header *pci_rom_probe(struct device *dev) rom_address|PCI_ROM_ADDRESS_ENABLE); } +#if CONFIG_ON_DEVICE_ROM_RUN printk(BIOS_DEBUG, "On card, ROM address for %s = %lx\n", dev_path(dev), (unsigned long)rom_address); rom_header = (struct rom_header *)rom_address; +#else + printk(BIOS_DEBUG, "On card option ROM execution disabled " + "for %s\n", dev_path(dev)); + return NULL; +#endif } printk(BIOS_SPEW, "PCI expansion ROM, signature 0x%04x, "

1 0

Patch set updated for coreboot: 8e35db0 If the memory mapped UART isn't present, leave it out of the cb tables.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/729 -gerrit commit 8e35db00aa4fa92ead0a286d9b8ebe691d232a53 Author: Gabe Black <gabeblack(a)google.com> Date: Wed Oct 5 01:57:03 2011 -0700 If the memory mapped UART isn't present, leave it out of the cb tables. This way u-boot won't try to use a UART that isn't plugged in. Change-Id: I9a3a0d074dd03add8afbd4dad836c4c6a05abe6f Signed-off-by: Gabe Black <gabeblack(a)google.com> --- src/arch/x86/boot/coreboot_table.c | 24 ++++++++++++++---------- 1 files changed, 14 insertions(+), 10 deletions(-) diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c index f29481b..d24d7c4 100644 --- a/src/arch/x86/boot/coreboot_table.c +++ b/src/arch/x86/boot/coreboot_table.c @@ -118,16 +118,20 @@ static struct lb_serial *lb_serial(struct lb_header *header) serial->baud = CONFIG_TTYS0_BAUD; return serial; #elif CONFIG_CONSOLE_SERIAL8250MEM - struct lb_record *rec; - struct lb_serial *serial; - rec = lb_new_record(header); - serial = (struct lb_serial *)rec; - serial->tag = LB_TAG_SERIAL; - serial->size = sizeof(*serial); - serial->type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial->baseaddr = uartmem_getbaseaddr(); - serial->baud = CONFIG_TTYS0_BAUD; - return serial; + if (uartmem_getbaseaddr()) { + struct lb_record *rec; + struct lb_serial *serial; + rec = lb_new_record(header); + serial = (struct lb_serial *)rec; + serial->tag = LB_TAG_SERIAL; + serial->size = sizeof(*serial); + serial->type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial->baseaddr = uartmem_getbaseaddr(); + serial->baud = CONFIG_TTYS0_BAUD; + return serial; + } else { + return NULL; + } #else return NULL; #endif

1 0

Patch set updated for coreboot: 4d2426c Detect whether the OXPCIE card is really present while in the ROM stage.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/728 -gerrit commit 4d2426cf9e0ad1353aadbc49b96ecdb4a0e771cb Author: Gabe Black <gabeblack(a)google.com> Date: Wed Oct 5 01:52:08 2011 -0700 Detect whether the OXPCIE card is really present while in the ROM stage. Use an int in CAR global data to store whether or not the OXPCIE serial card is actually there. Also, time out if the card doesn't show up quickly enough, don't continue initialization if it's not there, and don't make the initialization routine default to a card if none is found. Change-Id: I9c72d3abc6ee2867b77ab2f2180e6f01f647af8c Signed-off-by: Gabe Black <gabeblack(a)google.com> --- src/arch/x86/lib/romstage_console.c | 5 ++++- src/drivers/oxford/oxpcie/oxpcie_early.c | 20 +++++++++++++++++--- src/include/uart8250.h | 5 +++++ 3 files changed, 26 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index 0f22727..25eda9b 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -35,7 +35,10 @@ static void console_tx_byte(unsigned char byte) console_tx_byte('\r'); #if CONFIG_CONSOLE_SERIAL8250MEM - uart8250_mem_tx_byte(CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte); + if (oxford_oxpcie_present) { + uart8250_mem_tx_byte( + CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte); + } #endif #if CONFIG_CONSOLE_SERIAL8250 uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c index 2c7767e..4f7a3cb 100644 --- a/src/drivers/oxford/oxpcie/oxpcie_early.c +++ b/src/drivers/oxford/oxpcie/oxpcie_early.c @@ -20,6 +20,8 @@ #include <stdint.h> #include <arch/io.h> #include <arch/romcc_io.h> +#include <cpu/x86/car.h> +#include <delay.h> #include <uart8250.h> #include <device/pci_def.h> @@ -34,9 +36,13 @@ #define OXPCIE_DEVICE_3 \ PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 3) +#if defined(__PRE_RAM__) +int oxford_oxpcie_present CAR_GLOBAL; + void oxford_init(void) { u16 reg16; + oxford_oxpcie_present = 1; /* First we reset the secondary bus */ reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL); @@ -69,11 +75,14 @@ void oxford_init(void) reg16 |= PCI_COMMAND_MEMORY; pci_write_config16(PCIE_BRIDGE, PCI_COMMAND, reg16); - // FIXME Add a timeout or this will hang forever if - // no device is in the slot. + u32 timeout = 20000; // Timeout in 10s of microseconds. u32 id = 0; - while ((id == 0) || (id == 0xffffffff)) + for (;;) { id = pci_read_config32(OXPCIE_DEVICE, PCI_VENDOR_ID); + if (!timeout-- || (id != 0 && id != 0xffffffff)) + break; + udelay(10); + } u32 device = OXPCIE_DEVICE; /* unknown default */ switch (id) { @@ -90,6 +99,10 @@ void oxford_init(void) case 0xc1581415: /* e.g. Startech MPEX2S952 */ device = OXPCIE_DEVICE; break; + default: + /* No UART here. */ + oxford_oxpcie_present = 0; + return; } /* Setup base address on device */ @@ -107,3 +120,4 @@ void oxford_init(void) uart8250_mem_init(uart0_base, (4000000 / CONFIG_TTYS0_BAUD)); } +#endif diff --git a/src/include/uart8250.h b/src/include/uart8250.h index aa510e5..71b9a5f 100644 --- a/src/include/uart8250.h +++ b/src/include/uart8250.h @@ -135,8 +135,13 @@ void uart8250_mem_init(unsigned base_port, unsigned divisor); u32 uart_mem_init(void); u32 uartmem_getbaseaddr(void); +#if defined(__PRE_RAM__) && CONFIG_DRIVERS_OXFORD_OXPCIE && \ + CONFIG_CONSOLE_SERIAL8250MEM /* and special init for OXPCIe based cards */ +extern int oxford_oxpcie_present; + void oxford_init(void); +#endif #endif /* __ROMCC__ */

1 0

Patch set updated for coreboot: 380481b Introduce config option to initialize CBMEM early.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/710 -gerrit commit 380481bf48bd5f9e5b9c0251f0162f5ccbd04b26 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Sep 20 16:46:46 2011 -0700 Introduce config option to initialize CBMEM early. We want to be able to communicate information between rom and ram stages of coreboot. This configuration option will be used to compile such ability in. Change-Id: I6736fdc264ecd0b63369b28462d7bb96e4c2b012 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/Kconfig | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index c165d93..544b61b 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -112,6 +112,14 @@ config INCLUDE_CONFIG_FILE help Include in CBFS the coreboot config file that was used to compile the ROM image +config EARLY_CBMEM_INIT + bool "Initialize CBMEM while in ROM stage" + default n + help + Make coreboot initialize the cbmem structures while running in rom + stage. This could be useful when the rom stage wants to communicate + some, for instance, execution timestamps. + endmenu source src/mainboard/Kconfig

1 0

Patch set updated for coreboot: 804886b Initialize CBMEM early.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/711 -gerrit commit 804886b2a737261e85e5b5dd0e43bc5c3a4fd096 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Sep 20 17:07:14 2011 -0700 Initialize CBMEM early. We want to be able to share data between different phases of firmware (rom stage/ram stage/payload). Coreboot CBMEM seems an appropriate location for this data, but normally it is not initialized until coreboot reaches the ram stage. This change initializes the CBMEM while still in rom stage in case CONFIG_EARLY_CBMEM_INIT is set. Note that there is a discrepancy in how coreboot determines the size of DRAM at rom and ram stages, get_top_of_ram() is used at rom stage and is not defined for all platforms. Those platforms will have to define this function should they enable the CONFIG_EARLY_CBMEM_INIT flag. Change-Id: I81691d45e28de59496fb227f2cca4e8c15ece717 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/include/cbmem.h | 4 +++- src/lib/cbmem.c | 39 +++++++++++++++++++++++---------------- 2 files changed, 26 insertions(+), 17 deletions(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 9806854..a681c36 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -22,7 +22,9 @@ /* Reserve 128k for ACPI and other tables */ #define HIGH_MEMORY_DEF_SIZE ( 128 * 1024 ) +#ifndef __PRE_RAM__ extern uint64_t high_tables_base, high_tables_size; +#endif #if CONFIG_HAVE_ACPI_RESUME #define HIGH_MEMORY_SIZE ((CONFIG_RAMTOP - CONFIG_RAMBASE) + HIGH_MEMORY_DEF_SIZE) @@ -41,7 +43,7 @@ extern uint64_t high_tables_base, high_tables_size; #define CBMEM_ID_SMBIOS 0x534d4254 #define CBMEM_ID_NONE 0x00000000 -void cbmem_initialize(void); +int cbmem_initialize(void); void cbmem_init(u64 baseaddr, u64 size); int cbmem_reinit(u64 baseaddr); diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 202f521..f5c3d3a 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -183,30 +183,38 @@ void *cbmem_find(u32 id) return (void *)NULL; } -#ifndef __PRE_RAM__ -#if CONFIG_HAVE_ACPI_RESUME +#if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) extern u8 acpi_slp_type; #endif -void cbmem_initialize(void) +#if CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__) +/* Returns True if it was not intialized before. */ +int cbmem_initialize(void) { -#if CONFIG_HAVE_ACPI_RESUME - printk(BIOS_DEBUG, "%s: acpi_slp_type=%d\n", __func__, acpi_slp_type); - if (acpi_slp_type == 3 || acpi_slp_type == 2) { - if (!cbmem_reinit(high_tables_base)) { - printk(BIOS_DEBUG, "cbmem_reinit failed\n"); - /* Something went wrong, our high memory area got wiped */ + int rv = 0; + +#ifdef __PRE_RAM__ + extern unsigned long get_top_of_ram(void); + uint64_t high_tables_base = get_top_of_ram() - HIGH_MEMORY_SIZE; + uint64_t high_tables_size = HIGH_MEMORY_SIZE; +#endif + + /* We expect the romstage to always initialize it. */ + if (!cbmem_reinit(high_tables_base)) { +#if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) + /* Something went wrong, our high memory area got wiped */ + if (acpi_slp_type == 3 || acpi_slp_type == 2) acpi_slp_type = 0; - cbmem_init(high_tables_base, high_tables_size); - } - } else { +#endif cbmem_init(high_tables_base, high_tables_size); + rv = 1; } -#else - cbmem_init(high_tables_base, high_tables_size); -#endif +#ifndef __PRE_RAM__ cbmem_arch_init(); +#endif + return rv; } +#endif #ifndef __PRE_RAM__ void cbmem_list(void) @@ -240,5 +248,4 @@ void cbmem_list(void) } #endif -#endif

1 0

Patch set updated for coreboot: 47697f1 Add an implementation for the memchr library function
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/708 -gerrit commit 47697f1d75a2f22e828e672ad6da6786e82b9361 Author: Gabe Black <gabeblack(a)google.com> Date: Fri Sep 16 02:18:56 2011 -0700 Add an implementation for the memchr library function Change-Id: Icded479d246f7cce8a3d2154c69f75178fa513e1 Signed-off-by: Gabe Black <gabeblack(a)google.com> --- src/include/string.h | 1 + src/lib/Makefile.inc | 2 ++ src/lib/memchr.c | 11 +++++++++++ 3 files changed, 14 insertions(+), 0 deletions(-) diff --git a/src/include/string.h b/src/include/string.h index 2168947..708961b 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -8,6 +8,7 @@ void *memcpy(void *dest, const void *src, size_t n); void *memmove(void *dest, const void *src, size_t n); void *memset(void *s, int c, size_t n); int memcmp(const void *s1, const void *s2, size_t n); +void *memchr(const void *s, int c, size_t n); #if !defined(__PRE_RAM__) int sprintf(char * buf, const char *fmt, ...); #endif diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 906dfae..e0e5e75 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -1,6 +1,7 @@ romstage-y += memset.c +romstage-y += memchr.c romstage-y += memcpy.c romstage-y += memcmp.c romstage-y += cbfs.c @@ -15,6 +16,7 @@ romstage-$(CONFIG_CONSOLE_NE2K) += compute_ip_checksum.c romstage-$(CONFIG_USBDEBUG) += usbdebug.c ramstage-y += memset.c +ramstage-y += memchr.c ramstage-y += memcpy.c ramstage-y += memcmp.c ramstage-y += memmove.c diff --git a/src/lib/memchr.c b/src/lib/memchr.c new file mode 100644 index 0000000..a890dce --- /dev/null +++ b/src/lib/memchr.c @@ -0,0 +1,11 @@ +#include <string.h> +void *memchr(const void *s, int c, size_t n) +{ + const unsigned char *sc = s; + while (n--) { + if (*sc == (unsigned char)c) + return (void *)sc; + sc++; + } + return NULL; +}

1 0

Patch set updated for coreboot: 356ee5f Since cbfs_core.h provides a macro that uses ntohl, make sure ntohl is available
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/709 -gerrit commit 356ee5f62fec68644dba49951ebc97cc3412befb Author: Gabe Black <gabeblack(a)google.com> Date: Fri Sep 16 02:24:03 2011 -0700 Since cbfs_core.h provides a macro that uses ntohl, make sure ntohl is available Since cbfs_core.h provides a macro that uses ntohl, make sure ntohl is available by including byteorder.h Change-Id: I9ab8cb51bd680e861b28d5130d09547bb9ab3b1f Signed-off-by: Gabe Black <gabeblack(a)google.com> --- src/include/cbfs_core.h | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/src/include/cbfs_core.h b/src/include/cbfs_core.h index 70368f8..43e6b9b 100644 --- a/src/include/cbfs_core.h +++ b/src/include/cbfs_core.h @@ -49,6 +49,8 @@ #ifndef _CBFS_CORE_H_ #define _CBFS_CORE_H_ +#include <arch/byteorder.h> + /** These are standard values for the known compression alogrithms that coreboot knows about for stages and payloads. Of course, other CBFS users can use whatever

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Patch set updated for coreboot: 0297308 CBMEM CONSOLE: Add config option for CBMEM stored console log.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/718 -gerrit commit 0297308be444a7128f227c2784d6c8addf1cb176 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Sep 28 13:51:30 2011 -0700 CBMEM CONSOLE: Add config option for CBMEM stored console log. Some experiments have demonstrated that total amount of text generated by coreboot console when BIOS_SPEW level is enabled exceeds 40KB. Console output generated before DRAM is initialized can exceed 2KB. This patch introduces the new configuration option and assigns adequate default values to cache based and DRAM based console buffers. BUG=chrome-os-partner:4200 TEST=manual . run the following commands in the root directory cp config.stumpy .config make menuconfig . enable the new option (Console->Send console output to a CBMEM buffer) . save the configuration Observe the following settings added to the config: +CONFIG_CONSOLE_CBMEM=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0xae00 +CONFIG_CONSOLE_CAR_BUFFER_SIZE=0xc00 Change-Id: I209603f516244ae136631e6281ba21ebc6fb1710 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Reviewed-on: https://gerrit-int.chromium.org/5855 Tested-by: Vadim Bendebury <vbendeb(a)google.com> Reviewed-by: Stefan Reinauer <reinauer(a)google.com> --- src/console/Kconfig | 27 +++++++++++++++++++++++++++ 1 files changed, 27 insertions(+), 0 deletions(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index dbd11f6..fefbe2e 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -190,6 +190,33 @@ config CONSOLE_NE2K_IO_PORT 32 bytes of IO spaces will be used (and align on 32 bytes boundary, qemu needs broader align) +config CONSOLE_CBMEM + depends on EARLY_CBMEM_INIT + bool "Send console output to a CBMEM buffer" + default n + help + Enable this to save the console output in a CBMEM buffer. This would + allow to see coreboot console output from Linux space. + +config CONSOLE_CBMEM_BUFFER_SIZE + depends on CONSOLE_CBMEM + hex "Room allocated for console output in CBMEM" + default 0xae00 + help + Space allocated for console output storage in CBMEM. The default + value (almost 45K or 0xaeoo bytes) is large enough to accommodate + even the BIOS_SPEW level. + +config CONSOLE_CAR_BUFFER_SIZE + depends on CONSOLE_CBMEM + hex "Room allocated for console output in cash as RAM" + default 0xc00 + help + Console is used before RAM is initialized. This is the room reserved + in the DCACHE based RAM to keep console output before it can be + saved in a CBMEM buffer. 3K bytes should be enough even for the + BIOS_SPEW level. + choice prompt "Maximum console log level"

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coreboot March 2012