coreboot March 2012

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Patch set updated for coreboot: a8d94d6 Prepare the BIOS data areas before device init.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/769 -gerrit commit a8d94d6de75a653c0f58a4dbb2522bab6ce56c52 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jan 17 09:03:11 2012 -0800 Prepare the BIOS data areas before device init. Since we do not run option roms in normal mode nothing was initializing the BDA/EBDA and yet Linux depends very much on it having sane values here. For the most part the kernel tries to work around this not being initialized, but every once in awhile (1/300 boots or so) it would end up reading something that looked sane from BDA but was not and then it would panic. In this change the EBDA is unconditionally setup before devices are initialized. I'm not set on the location in dev_initialize() but there does not seem to be another place to hook it in so that it runs just once for ALL platforms regardless of whether they use option roms or not. (possibly hardwaremain?) The EBDA setup code has been moved into its own location in arch/x86/lib/ebda.c so it can be compiled in even if the option rom code is not. The low memory size is still set to 1MB which is enough to make linux happy without having to hook into each mainboard to get a more appropriate value. The setup_ebda() function takes inputs so it could be changed for a mainboard if needed. OLD/BROKEN would read garbage. Examples from different boots: ebda_addr=0x75e80 lowmem=0x1553400 ebda_addr=0x5e080 lowmem=0x3e51400 ebda_addr=0x7aa80 lowmem=0x2f8a800 NEW/FIXED now reads consistent values: ebda_addr=0xf6000 lowmem=0x100000 Change-Id: I6cb79f0e3e43cc65f7e5fe98b6cad1a557ccd949 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/arch/x86/include/arch/ebda.h | 37 +++++++++++++++++++++++++++++ src/arch/x86/lib/Makefile.inc | 1 + src/arch/x86/lib/ebda.c | 48 ++++++++++++++++++++++++++++++++++++++ src/devices/device.c | 8 ++++++ src/devices/oprom/x86.c | 16 ------------ 5 files changed, 94 insertions(+), 16 deletions(-) diff --git a/src/arch/x86/include/arch/ebda.h b/src/arch/x86/include/arch/ebda.h new file mode 100644 index 0000000..1de6097 --- /dev/null +++ b/src/arch/x86/include/arch/ebda.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __ARCH_EBDA_H +#define __ARCH_EBDA_H + +#define X86_BDA_SIZE 0x200 +#define X86_BDA_BASE 0x400 +#define X86_EBDA_SEGMENT 0x40e +#define X86_EBDA_LOWMEM 0x413 + +#define DEFAULT_EBDA_LOWMEM (1024 << 10) +#define DEFAULT_EBDA_SEGMENT 0xF600 +#define DEFAULT_EBDA_SIZE 0x400 + +void setup_ebda(u32 low_memory_size, u16 ebda_segment, u16 ebda_size); +void setup_default_ebda(void); + +#endif diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc index 96fb9b0..8f5fd5f 100644 --- a/src/arch/x86/lib/Makefile.inc +++ b/src/arch/x86/lib/Makefile.inc @@ -8,6 +8,7 @@ ramstage-y += exception.c ramstage-$(CONFIG_IOAPIC) += ioapic.c ramstage-y += memset.c ramstage-y += memcpy.c +ramstage-y += ebda.c romstage-y += romstage_console.c romstage-y += cbfs_and_run.c diff --git a/src/arch/x86/lib/ebda.c b/src/arch/x86/lib/ebda.c new file mode 100644 index 0000000..faf1451 --- /dev/null +++ b/src/arch/x86/lib/ebda.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <arch/io.h> +#include <arch/ebda.h> + +void setup_ebda(u32 low_memory_size, u16 ebda_segment, u16 ebda_size) +{ + if (!low_memory_size || !ebda_segment || !ebda_size) + return; + + /* clear BIOS DATA AREA */ + memset((void *)X86_BDA_BASE, 0, X86_BDA_SIZE); + + write16(X86_EBDA_LOWMEM, (low_memory_size >> 10)); + write16(X86_EBDA_SEGMENT, ebda_segment); + + /* Set up EBDA */ + memset((void *)(ebda_segment << 4), 0, ebda_size); + write16((ebda_segment << 4), (ebda_size >> 10)); +} + +void setup_default_ebda(void) +{ + setup_ebda(DEFAULT_EBDA_LOWMEM, + DEFAULT_EBDA_SEGMENT, + DEFAULT_EBDA_SIZE); +} diff --git a/src/devices/device.c b/src/devices/device.c index a2619bf..f559da5 100644 --- a/src/devices/device.c +++ b/src/devices/device.c @@ -41,6 +41,9 @@ #include <stdlib.h> #include <string.h> #include <smp/spinlock.h> +#if CONFIG_ARCH_X86 +#include <arch/ebda.h> +#endif /** Linked list of ALL devices */ struct device *all_devices = &dev_root; @@ -1102,6 +1105,11 @@ void dev_initialize(void) printk(BIOS_INFO, "Initializing devices...\n"); +#if CONFIG_ARCH_X86 + /* Ensure EBDA is prepared before Option ROMs. */ + setup_default_ebda(); +#endif + /* First call the mainboard init. */ init_dev(&dev_root); diff --git a/src/devices/oprom/x86.c b/src/devices/oprom/x86.c index 0c15b15..564017d 100644 --- a/src/devices/oprom/x86.c +++ b/src/devices/oprom/x86.c @@ -40,19 +40,6 @@ void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx, u32 esi, u32 edi) __attribute__((regparm(0))) = (void *)&__realmode_interrupt; -static void setup_bda(void) -{ - /* clear BIOS DATA AREA */ - memset((void *)0x400, 0, 0x200); - - write16(0x413, FAKE_MEMORY_SIZE / 1024); - write16(0x40e, INITIAL_EBDA_SEGMENT); - - /* Set up EBDA */ - memset((void *)(INITIAL_EBDA_SEGMENT << 4), 0, INITIAL_EBDA_SIZE); - write16((INITIAL_EBDA_SEGMENT << 4) + 0x0, INITIAL_EBDA_SIZE / 1024); -} - static void setup_rombios(void) { const char date[] = "06/11/99"; @@ -272,9 +259,6 @@ void run_bios(struct device *dev, unsigned long addr) */ setup_i8259(); - /* Set up BIOS Data Area */ - setup_bda(); - /* Set up some legacy information in the F segment */ setup_rombios();

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Patch set updated for coreboot: 0196d91 selfboot: drop dead code As a left over from elfboot times, selfboot keeps the segments to load in the order in which they appeared in the original file as well as in the order they will later appear in memory. This is not needed in selfboot, so drop the code and structure members that handle the in-file order.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/768 -gerrit commit 0196d911dfa20c442c0b52a667a30c5922ec1710 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jan 11 14:07:39 2012 -0800 selfboot: drop dead code As a left over from elfboot times, selfboot keeps the segments to load in the order in which they appeared in the original file as well as in the order they will later appear in memory. This is not needed in selfboot, so drop the code and structure members that handle the in-file order. Change-Id: I6be7a3a1bdf717fec1ee8e5b3227c63150580b41 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/boot/selfboot.c | 25 ++++--------------------- 1 files changed, 4 insertions(+), 21 deletions(-) diff --git a/src/boot/selfboot.c b/src/boot/selfboot.c index d4ab8c8..1675474 100644 --- a/src/boot/selfboot.c +++ b/src/boot/selfboot.c @@ -48,8 +48,6 @@ static const unsigned long lb_end = (unsigned long)&_eram_seg; struct segment { struct segment *next; struct segment *prev; - struct segment *phdr_next; - struct segment *phdr_prev; unsigned long s_dstaddr; unsigned long s_srcaddr; unsigned long s_memsz; @@ -234,11 +232,6 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) new->prev = seg->prev; seg->prev->next = new; seg->prev = new; - /* Order by original program header order */ - new->phdr_next = seg; - new->phdr_prev = seg->phdr_prev; - seg->phdr_prev->phdr_next = new; - seg->phdr_prev = new; /* compute the new value of start */ start = seg->s_dstaddr; @@ -274,11 +267,6 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) new->prev = seg; seg->next->prev = new; seg->next = new; - /* Order by original program header order */ - new->phdr_next = seg->phdr_next; - new->phdr_prev = seg; - seg->phdr_next->phdr_prev = new; - seg->phdr_next = new; printk(BIOS_SPEW, " late: [0x%016lx, 0x%016lx, 0x%016lx)\n", new->s_dstaddr, @@ -312,7 +300,6 @@ static int build_self_segment_list( struct segment *ptr; struct cbfs_payload_segment *segment, *first_segment; memset(head, 0, sizeof(*head)); - head->phdr_next = head->phdr_prev = head; head->next = head->prev = head; first_segment = segment = &payload->segments; @@ -375,9 +362,10 @@ static int build_self_segment_list( return -1; } + /* We have found another CODE, DATA or BSS segment */ segment++; - // FIXME: Explain what this is + /* Find place where to insert our segment */ for(ptr = head->next; ptr != head; ptr = ptr->next) { if (new->s_srcaddr < ntohll(segment->load_addr)) break; @@ -388,12 +376,6 @@ static int build_self_segment_list( new->prev = ptr->prev; ptr->prev->next = new; ptr->prev = new; - - /* Order by original program header order */ - new->phdr_next = head; - new->phdr_prev = head->phdr_prev; - head->phdr_prev->phdr_next = new; - head->phdr_prev = new; } return 1; @@ -408,7 +390,8 @@ static int load_self_segments( unsigned long bounce_high = lb_end; for(ptr = head->next; ptr != head; ptr = ptr->next) { - if (!overlaps_coreboot(ptr)) continue; + if (!overlaps_coreboot(ptr)) + continue; if (ptr->s_dstaddr + ptr->s_memsz > bounce_high) bounce_high = ptr->s_dstaddr + ptr->s_memsz; }

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Patch set updated for coreboot: 2c403e4 Don't re-init EBDA in S3 resume path.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/770 -gerrit commit 2c403e49c56e818e669e4c095c3f7a2124e0032c Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Jan 18 10:05:18 2012 -0800 Don't re-init EBDA in S3 resume path. I forgot to implement this the first time around. It does not seem to cause noticeable problems but in heavy suspend/resume testing I saw a suspicious crash in the kernel when trying to bring one of the CPUs back online. Change-Id: I950ac260f251e2683693d9bd20a0dd5e041aa26e Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/arch/x86/lib/ebda.c | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/src/arch/x86/lib/ebda.c b/src/arch/x86/lib/ebda.c index faf1451..fb407b6 100644 --- a/src/arch/x86/lib/ebda.c +++ b/src/arch/x86/lib/ebda.c @@ -23,9 +23,18 @@ #include <string.h> #include <arch/io.h> #include <arch/ebda.h> +#if CONFIG_HAVE_ACPI_RESUME +#include <arch/acpi.h> +#endif void setup_ebda(u32 low_memory_size, u16 ebda_segment, u16 ebda_size) { +#if CONFIG_HAVE_ACPI_RESUME + /* Skip in S3 resume path */ + if (acpi_slp_type == 3) + return; +#endif + if (!low_memory_size || !ebda_segment || !ebda_size) return;

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New patch to review for coreboot: 8963535 Don't re-init EBDA in S3 resume path.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/770 -gerrit commit 8963535f0da1e1e464c48b200fab3288fe3db75b Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Jan 18 10:05:18 2012 -0800 Don't re-init EBDA in S3 resume path. I forgot to implement this the first time around. It does not seem to cause noticeable problems but in heavy suspend/resume testing I saw a suspicious crash in the kernel when trying to bring one of the CPUs back online. Change-Id: I950ac260f251e2683693d9bd20a0dd5e041aa26e Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/arch/x86/lib/ebda.c | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/src/arch/x86/lib/ebda.c b/src/arch/x86/lib/ebda.c index faf1451..fb407b6 100644 --- a/src/arch/x86/lib/ebda.c +++ b/src/arch/x86/lib/ebda.c @@ -23,9 +23,18 @@ #include <string.h> #include <arch/io.h> #include <arch/ebda.h> +#if CONFIG_HAVE_ACPI_RESUME +#include <arch/acpi.h> +#endif void setup_ebda(u32 low_memory_size, u16 ebda_segment, u16 ebda_size) { +#if CONFIG_HAVE_ACPI_RESUME + /* Skip in S3 resume path */ + if (acpi_slp_type == 3) + return; +#endif + if (!low_memory_size || !ebda_segment || !ebda_size) return;

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New patch to review for coreboot: f1424d7 selfboot: drop dead code As a left over from elfboot times, selfboot keeps the segments to load in the order in which they appeared in the original file as well as in the order they will later appear in memory. This is not needed in selfboot, so drop the code and structure members that handle the in-file order.
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/768 -gerrit commit f1424d7b0eabbc2fc6c320469ad25a57cbb8e0b6 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jan 11 14:07:39 2012 -0800 selfboot: drop dead code As a left over from elfboot times, selfboot keeps the segments to load in the order in which they appeared in the original file as well as in the order they will later appear in memory. This is not needed in selfboot, so drop the code and structure members that handle the in-file order. Change-Id: I6be7a3a1bdf717fec1ee8e5b3227c63150580b41 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/boot/selfboot.c | 25 ++++--------------------- 1 files changed, 4 insertions(+), 21 deletions(-) diff --git a/src/boot/selfboot.c b/src/boot/selfboot.c index d4ab8c8..1675474 100644 --- a/src/boot/selfboot.c +++ b/src/boot/selfboot.c @@ -48,8 +48,6 @@ static const unsigned long lb_end = (unsigned long)&_eram_seg; struct segment { struct segment *next; struct segment *prev; - struct segment *phdr_next; - struct segment *phdr_prev; unsigned long s_dstaddr; unsigned long s_srcaddr; unsigned long s_memsz; @@ -234,11 +232,6 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) new->prev = seg->prev; seg->prev->next = new; seg->prev = new; - /* Order by original program header order */ - new->phdr_next = seg; - new->phdr_prev = seg->phdr_prev; - seg->phdr_prev->phdr_next = new; - seg->phdr_prev = new; /* compute the new value of start */ start = seg->s_dstaddr; @@ -274,11 +267,6 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) new->prev = seg; seg->next->prev = new; seg->next = new; - /* Order by original program header order */ - new->phdr_next = seg->phdr_next; - new->phdr_prev = seg; - seg->phdr_next->phdr_prev = new; - seg->phdr_next = new; printk(BIOS_SPEW, " late: [0x%016lx, 0x%016lx, 0x%016lx)\n", new->s_dstaddr, @@ -312,7 +300,6 @@ static int build_self_segment_list( struct segment *ptr; struct cbfs_payload_segment *segment, *first_segment; memset(head, 0, sizeof(*head)); - head->phdr_next = head->phdr_prev = head; head->next = head->prev = head; first_segment = segment = &payload->segments; @@ -375,9 +362,10 @@ static int build_self_segment_list( return -1; } + /* We have found another CODE, DATA or BSS segment */ segment++; - // FIXME: Explain what this is + /* Find place where to insert our segment */ for(ptr = head->next; ptr != head; ptr = ptr->next) { if (new->s_srcaddr < ntohll(segment->load_addr)) break; @@ -388,12 +376,6 @@ static int build_self_segment_list( new->prev = ptr->prev; ptr->prev->next = new; ptr->prev = new; - - /* Order by original program header order */ - new->phdr_next = head; - new->phdr_prev = head->phdr_prev; - head->phdr_prev->phdr_next = new; - head->phdr_prev = new; } return 1; @@ -408,7 +390,8 @@ static int load_self_segments( unsigned long bounce_high = lb_end; for(ptr = head->next; ptr != head; ptr = ptr->next) { - if (!overlaps_coreboot(ptr)) continue; + if (!overlaps_coreboot(ptr)) + continue; if (ptr->s_dstaddr + ptr->s_memsz > bounce_high) bounce_high = ptr->s_dstaddr + ptr->s_memsz; }

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New patch to review for coreboot: 990fa2a correctly mark code segments as code in SELF
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/767 -gerrit commit 990fa2ac2da79f8dbbdd3d1ad3abd7c2a749a5df Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jan 11 12:40:14 2012 -0800 correctly mark code segments as code in SELF In bios_log, find that the first segment of the payload is shown as code rather than data. Change-Id: I82eaad23f08c02f4ed75744affa8835255cf5c17 Sample: Got a payload Loading segment from rom address 0xfff29378 code (compression=1) ... Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- util/cbfstool/cbfs-mkpayload.c | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-) diff --git a/util/cbfstool/cbfs-mkpayload.c b/util/cbfstool/cbfs-mkpayload.c index ff6479d..e4ef5c8 100644 --- a/util/cbfstool/cbfs-mkpayload.c +++ b/util/cbfstool/cbfs-mkpayload.c @@ -161,7 +161,10 @@ int parse_elf_to_payload(unsigned char *input, unsigned char **output, continue; } - segs[segments].type = PAYLOAD_SEGMENT_DATA; + if (phdr[i].p_flags & PF_X) + segs[segments].type = PAYLOAD_SEGMENT_CODE; + else + segs[segments].type = PAYLOAD_SEGMENT_DATA; segs[segments].load_addr = (uint64_t)htonll(phdr[i].p_paddr); segs[segments].mem_len = (uint32_t)htonl(phdr[i].p_memsz); segs[segments].compression = htonl(algo);

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New patch to review for coreboot: b0ba5e3 Add Kconfig options to enable TSEG and set a size
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/766 -gerrit commit b0ba5e3a291611e2389755c6037ea289207b74fe Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jan 9 22:11:25 2012 -0800 Add Kconfig options to enable TSEG and set a size Future CPUs will require TSEG use for SMM Change-Id: I1432569ece4371d6e12c997e90d66c175fa54c5c Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/cpu/x86/Kconfig | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index fdbd527..2033a0a 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -42,3 +42,11 @@ config LOGICAL_CPUS config CACHE_ROM bool default n + +config SMM_TSEG + bool + default n + +config SMM_TSEG_SIZE + hex + default 0

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New patch to review for coreboot: 8819294 Make MTRR min hole alignment 64MB
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/765 -gerrit commit 8819294696d2d2aa89bf760a9b8529991255f6fd Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jan 9 22:05:18 2012 -0800 Make MTRR min hole alignment 64MB This affects the algorithm when determining when to transform a range into a larger range with a hole. It is needed when for when I switch on an 8MB TSEG and cause the memory maps to go crazy. Also add header defines for the SMRR. Change-Id: I1a06ccc28ef139cc79f655a8b19fd3533aca0401 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/cpu/x86/mtrr/mtrr.c | 9 ++++++--- src/include/cpu/x86/mtrr.h | 3 +++ 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 5f5e02b..ed7d93b 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -265,13 +265,16 @@ static unsigned int range_to_mtrr(unsigned int reg, return reg; } - if (above4gb == 2 && type == MTRR_TYPE_WRBACK && range_sizek % 0x4000) { +#define MIN_ALIGN 0x10000 /* 64MB */ + + if (above4gb == 2 && type == MTRR_TYPE_WRBACK && + range_sizek > MIN_ALIGN && range_sizek % MIN_ALIGN) { /* - * If this range is not divisible by 16MB then instead + * If this range is not divisible then instead * make a larger range and carve out an uncached hole. */ hole_startk = range_startk + range_sizek; - hole_sizek = 0x4000 - (range_sizek % 0x4000); + hole_sizek = MIN_ALIGN - (range_sizek % MIN_ALIGN); range_sizek += hole_sizek; } diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 62cb8b7..8b5cc28 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -17,6 +17,9 @@ #define MTRRdefTypeEn (1 << 11) #define MTRRdefTypeFixEn (1 << 10) +#define SMRRphysBase_MSR 0x1f2 +#define SMRRphysMask_MSR 0x1f3 + #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)

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New patch to review for coreboot: 3b05660 Make cpuid functions usable when compiled with PIC
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/764 -gerrit commit 3b0566044cdf94f37e3227b4423dd4d84735d064 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jan 9 22:00:30 2012 -0800 Make cpuid functions usable when compiled with PIC This avoids using EBX and instead uses EDI where possible, and ESI when necessary to get the EBX value out. This allows me to enable -fpic for SMM TSEG code. Change-Id: I10dbded3f3ad98a39ba7b53da59af6ca3145e2e5 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/arch/x86/include/arch/cpu.h | 57 ++++++++++++++++++++++++++++++-------- 1 files changed, 45 insertions(+), 12 deletions(-) diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 85357d7..508b7d6 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -36,12 +36,36 @@ static inline struct cpuid_result cpuid(int op) { struct cpuid_result result; asm volatile( - "cpuid" + "mov %%ebx, %%edi;" + "cpuid;" + "mov %%ebx, %%esi;" + "mov %%edi, %%ebx;" : "=a" (result.eax), - "=b" (result.ebx), + "=S" (result.ebx), "=c" (result.ecx), "=d" (result.edx) - : "0" (op)); + : "0" (op) + : "edi"); + return result; +} + +/* + * Generic Extended CPUID function + */ +static inline struct cpuid_result cpuid_ext(int op, unsigned ecx) +{ + struct cpuid_result result; + asm volatile( + "mov %%ebx, %%edi;" + "cpuid;" + "mov %%ebx, %%esi;" + "mov %%edi, %%ebx;" + : "=a" (result.eax), + "=S" (result.ebx), + "=c" (result.ecx), + "=d" (result.edx) + : "0" (op), "2" (ecx) + : "edi"); return result; } @@ -52,10 +76,12 @@ static inline unsigned int cpuid_eax(unsigned int op) { unsigned int eax; - __asm__("cpuid" + __asm__("mov %%ebx, %%edi;" + "cpuid;" + "mov %%edi, %%ebx;" : "=a" (eax) : "0" (op) - : "ebx", "ecx", "edx"); + : "ecx", "edx", "edi"); return eax; } @@ -63,10 +89,13 @@ static inline unsigned int cpuid_ebx(unsigned int op) { unsigned int eax, ebx; - __asm__("cpuid" - : "=a" (eax), "=b" (ebx) + __asm__("mov %%ebx, %%edi;" + "cpuid;" + "mov %%edi, %%ebx;" + "mov %%edi, %%esi;" + : "=a" (eax), "=S" (ebx) : "0" (op) - : "ecx", "edx" ); + : "ecx", "edx", "edi"); return ebx; } @@ -74,10 +103,12 @@ static inline unsigned int cpuid_ecx(unsigned int op) { unsigned int eax, ecx; - __asm__("cpuid" + __asm__("mov %%ebx, %%edi;" + "cpuid;" + "mov %%edi, %%ebx;" : "=a" (eax), "=c" (ecx) : "0" (op) - : "ebx", "edx" ); + : "edx", "edi"); return ecx; } @@ -85,10 +116,12 @@ static inline unsigned int cpuid_edx(unsigned int op) { unsigned int eax, edx; - __asm__("cpuid" + __asm__("mov %%ebx, %%edi;" + "cpuid;" + "mov %%edi, %%ebx;" : "=a" (eax), "=d" (edx) : "0" (op) - : "ebx", "ecx"); + : "ecx", "edi"); return edx; }

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New patch to review for coreboot: 748e349 Fix MB calculation in the reporting of the MTRR hole
by Stefan Reinauer 07 Mar '12

07 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/763 -gerrit commit 748e349a427ffe71324173a80c1d1a6e9762f06c Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Jan 6 15:49:30 2012 -0800 Fix MB calculation in the reporting of the MTRR hole Change-Id: I34b5c4ffd2a3f3e895d2bffedce1c00ee9aea942 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/cpu/x86/mtrr/mtrr.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 8dccfef..5f5e02b 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -306,7 +306,7 @@ static unsigned int range_to_mtrr(unsigned int reg, if (hole_sizek) { printk(BIOS_DEBUG, "Adding hole at %ldMB-%ldMB\n", - hole_startk, hole_startk + hole_sizek); + hole_startk >> 10, (hole_startk + hole_sizek) >> 10); reg = range_to_mtrr(reg, hole_startk, hole_sizek, next_range_startk, MTRR_TYPE_UNCACHEABLE, address_bits, above4gb);

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coreboot March 2012