coreboot March 2012

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Bug when I compiling coreboot with SeaBIOS
by Денис 06 Mar '12

06 Mar '12

Ok, I've downloaded coreboot, did it /make menuconfig /and saved configuration. Then I wrote $ make /Cloning SeaBIOS from Git Cloning into /home/denis/Загрузки/coreboot/build/seabios... remote: Counting objects: 7460, done. remote: Compressing objects: 100% (2358/2358), done. remote: Total 7460 (delta 5915), reused 6374 (delta 5096) Receiving objects: 100% (7460/7460), 1.77 MiB | 269 KiB/s, done. Resolving deltas: 100% (5915/5915), done. Checking out SeaBIOS revision e66fb31eac3e6be6aaab548c229af9bb1ba55c33 Already on 'master' Switched to a new branch 'coreboot' CONFIG SeaBIOS e66fb31eac3e6be6aaab548c229af9bb1ba55c33 The version of LD on this system does not properly handle alignments. As a result, this project can not be built. The problem may be the result of this LD bug report: http://sourceware.org/bugzilla/show_bug.cgi?id=12726 Please update to a working version of binutils and retry. Makefile:75: *** "Please upgrade GCC and/or binutils". Останов. make[1]: *** [config] Error 2 make: *** [seabios] Error 2 /Then, I tried /$ make crossgcc/ Thereafter /$ make/ /`IntelDisplayType' referenced in section `.text.handle_15' of /home/denis/Загрузки/coreboot/build/seabios/out/code16.o: defined in discarded section `.data16./home/denis/Загрузки/coreboot/build/seabios/out/../src/vgahooks.c.170' of /home/denis/Загрузки/coreboot/build/seabios/out/code16.o `IntelDisplayId' referenced in section `.text.handle_15' of /home/denis/Загрузки/coreboot/build/seabios/out/code16.o: defined in discarded section `.data16./home/denis/Загрузки/coreboot/build/seabios/out/../src/vgahooks.c.170' of /home/denis/Загрузки/coreboot/build/seabios/out/code16.o `pmode_IDT_info' referenced in section `.text.handle_15' of /home/denis/Загрузки/coreboot/build/seabios/out/code16.o: defined in discarded section `.data16./home/denis/Загрузки/coreboot/build/seabios/out/../src/misc.c.142' of /home/denis/Загрузки/coreboot/build/seabios/out/code16.o `rmode_IDT_info' referenced in section `.text.handle_15' of /home/denis/Загрузки/coreboot/build/seabios/out/code16.o: defined in discarded section `.data16./home/denis/Загрузки/coreboot/build/seabios/out/../src/misc.c.132' of /home/denis/Загрузки/coreboot/build/seabios/out/code16.o `RamSize' referenced in section `.text.handle_15' of /home/denis/Загрузки/coreboot/build/seabios/out/code16.o: defined in discarded section `.data16./home/denis/Загрузки/coreboot/build/seabios/out/../src/misc.c.14' of /home/denis/Загрузки/coreboot/build/seabios/out/code16.o `.data16./home/denis/Загрузки/coreboot/build/seabios/out/../src/mouse.c.104' referenced in section `.text.handle_15' of /home/denis/Загрузки/coreboot/build/seabios/out/code16.o: defined in discarded section `.data16./home/denis/Загрузки/coreboot/build/seabios/out/../src/mouse.c.104' of /home/denis/Загрузки/coreboot/build/seabios/out/code16.o `RamSize' referenced in section `.text.handle_15' of /home/denis/Загрузки/coreboot/build/seabios/out/code16.o: defined in discarded section `.data16./home/denis/Загрузки/coreboot/build/seabios/out/../src/misc.c.14' of /home/denis/Загрузки/coreboot/build/seabios/out/code16.o `e820_count' referenced in section `.text.handle_15' of /home/denis/Загрузки/coreboot/build/seabios/out/code16.o: defined in discarded section `.data16./home/denis/Загрузки/coreboot/build/seabios/out/../src/system.c.295' of /home/denis/Загрузки/coreboot/build/seabios/out/code16.o `e820_list' referenced in section `.text.handle_15' of /home/denis/Загрузки/coreboot/build/seabios/out/code16.o: defined in discarded section `.data16./home/denis/Загрузки/coreboot/build/seabios/out/../src/system.c.294' of /home/denis/Загрузки/coreboot/build/seabios/out/code16.o `cdemu_drive_gf' referenced in section `.text.handle_13' of /home/denis/Загрузки/coreboot/build/seabios/out/code16.o: defined in discarded section `.data16./home/denis/Загрузки/coreboot/build/seabios/out/../src/cdrom.c.20' of /home/denis/Загрузки/coreboot/build/seabios/out/code16.o `pmode_IDT_info' referenced in section `.text.asm.transition32' of /home/denis/Загрузки/coreboot/build/seabios/out/code16.o: defined in discarded section `.data16./home/denis/Загрузки/coreboot/build/seabios/out/../src/misc.c.142' of /home/denis/Загрузки/coreboot/build/seabios/out/code16.o `rombios32_gdt_48' referenced in section `.text.asm.transition32' of /home/denis/Загрузки/coreboot/build/seabios/out/code16.o: defined in discarded section `.data16./home/denis/Загрузки/coreboot/build/seabios/out/../src/misc.c.166' of /home/denis/Загрузки/coreboot/build/seabios/out/code16.o `rmode_IDT_info' referenced in section `.text.asm.transition16' of /home/denis/Загрузки/coreboot/build/seabios/out/code16.o: defined in discarded section `.data16./home/denis/Загрузки/coreboot/build/seabios/out/../src/misc.c.132' of /home/denis/Загрузки/coreboot/build/seabios/out/code16.o `pmode_IDT_info' referenced in section `.text.asm.export.entry_elf' of /home/denis/Загрузки/coreboot/build/seabios/out/code16.o: defined in discarded section `.data16./home/denis/Загрузки/coreboot/build/seabios/out/../src/misc.c.142' of /home/denis/Загрузки/coreboot/build/seabios/out/code16.o `rombios32_gdt_48' referenced in section `.text.asm.export.entry_elf' of /home/denis/Загрузки/coreboot/build/seabios/out/code16.o: defined in discarded section `.data16./home/denis/Загрузки/coreboot/build/seabios/out/../src/misc.c.166' of /home/denis/Загрузки/coreboot/build/seabios/out/code16.o `HaveRunPost' referenced in section `.fixedaddr.0xe05b' of /home/denis/Загрузки/coreboot/build/seabios/out/code16.o: defined in discarded section `.data16./home/denis/Загрузки/coreboot/build/seabios/out/../src/resume.c.18' of /home/denis/Загрузки/coreboot/build/seabios/out/code16.o make[2]: *** [/home/denis/Загрузки/coreboot/build/seabios/out/rom16.o] Ошибка 1 make[1]: *** [build] Error 2 make: *** [seabios] Error 2/ Please, help me fixed this problem. Best Regards, *Denis* / /

4 4

New patch to review for coreboot: c927439 Add an option to keep the ROM cached after romstage
by Stefan Reinauer 06 Mar '12

06 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/739 -gerrit commit c927439853e094f4e687f5069c4a577104c7ac56 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Nov 2 16:12:34 2011 -0700 Add an option to keep the ROM cached after romstage Change-Id: I05f1cbd33f0cb7d80ec90c636d1607774b4a74ef Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/include/arch/acpi.h | 4 +++- src/cpu/x86/Kconfig | 4 +++- src/cpu/x86/lapic/Makefile.inc | 1 + src/cpu/x86/lapic/boot_cpu.c | 3 ++- src/cpu/x86/mtrr/mtrr.c | 14 +++++++++++++- src/include/cpu/x86/lapic.h | 4 ++++ 6 files changed, 26 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 030745d..504d71b 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -422,7 +422,8 @@ void *acpi_get_wakeup_rsdp(void); void acpi_jump_to_wakeup(void *wakeup_addr); int acpi_get_sleep_type(void); - +#else +#define acpi_slp_type 0 #endif /* northbridge/amd/amdfam10/amdfam10_acpi.c */ @@ -434,6 +435,7 @@ void generate_cpu_entries(void); #else // CONFIG_GENERATE_ACPI_TABLES #define write_acpi_tables(start) (start) +#define acpi_slp_type 0 #endif diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 348f0ef..fdbd527 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -39,4 +39,6 @@ config LOGICAL_CPUS bool default y - +config CACHE_ROM + bool + default n diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index af20956..f3fcadc 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -2,3 +2,4 @@ ramstage-y += lapic.c ramstage-y += lapic_cpu_init.c ramstage-y += secondary.S ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c +ramstage-y += boot_cpu.c diff --git a/src/cpu/x86/lapic/boot_cpu.c b/src/cpu/x86/lapic/boot_cpu.c index 87418d0..0fb9d5d 100644 --- a/src/cpu/x86/lapic/boot_cpu.c +++ b/src/cpu/x86/lapic/boot_cpu.c @@ -1,7 +1,8 @@ +#include <cpu/x86/lapic.h> #include <cpu/x86/msr.h> #if CONFIG_SMP -static int boot_cpu(void) +int boot_cpu(void) { int bsp; msr_t msr; diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 46d8e2d..9015ad4 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -36,7 +36,9 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> +#include <cpu/x86/lapic.h> #include <arch/cpu.h> +#include <arch/acpi.h> #if CONFIG_GFXUMA extern uint64_t uma_memory_base, uma_memory_size; @@ -48,7 +50,6 @@ static unsigned int mtrr_msr[] = { MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR, }; - void enable_fixed_mtrr(void) { msr_t msr; @@ -456,6 +457,17 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) while(var_state.reg < MTRRS) { set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits); } + +#if CONFIG_CACHE_ROM + /* Enable Caching and speculative Reads for the + * complete ROM now that we actually have RAM. + */ + if (boot_cpu() && (acpi_slp_type != 3)) { + set_var_mtrr(7, (4096-4)*1024, 4*1024, + MTRR_TYPE_WRPROT, address_bits); + } +#endif + printk(BIOS_SPEW, "call enable_var_mtrr()\n"); enable_var_mtrr(); printk(BIOS_SPEW, "Leave %s\n", __func__); diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 8b44a6c..016870d 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -1,6 +1,7 @@ #ifndef CPU_X86_LAPIC_H #define CPU_X86_LAPIC_H +#ifndef __ROMCC__ #include <cpu/x86/lapic_def.h> #include <cpu/x86/msr.h> #include <arch/hlt.h> @@ -156,4 +157,7 @@ int start_cpu(struct device *cpu); #endif /* !__PRE_RAM__ */ +int boot_cpu(void); +#endif + #endif /* CPU_X86_LAPIC_H */

1 0

New patch to review for coreboot: cbc6faa Make TPM driver work in rom stage.
by Stefan Reinauer 06 Mar '12

06 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/738 -gerrit commit cbc6faa6960ec494785b24688c3872e2a74721ff Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Oct 27 21:28:25 2011 +0000 Make TPM driver work in rom stage. Change-Id: Ifc827d0cd0159aa3f6752d395974f2812334f262 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/pc80/tpm.c | 7 ++++--- 1 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/pc80/tpm.c b/src/pc80/tpm.c index 1cbf800..8e94303 100644 --- a/src/pc80/tpm.c +++ b/src/pc80/tpm.c @@ -35,6 +35,7 @@ #include <arch/byteorder.h> #include <console/console.h> #include <pc80/tpm.h> +#include <cpu/x86/car.h> #ifdef DEBUG #define TPM_DEBUG_ON 1 @@ -130,10 +131,10 @@ struct device_name { struct vendor_name { u16 vendor_id; const char * vendor_name; - struct device_name* dev_names; + const struct device_name* dev_names; }; -static struct device_name infineon_devices[] = { +static const struct device_name infineon_devices[] = { {0xb, "SLB9635 TT 1.2"}, {0} }; @@ -146,7 +147,7 @@ static const struct vendor_name vendor_names[] = { * Cached vendor/device ID pair to indicate that the device has been already * discovered */ -static u32 vendor_dev_id; +static u32 vendor_dev_id CAR_GLOBAL; static int is_byte_reg(u32 reg) {

1 0

New patch to review for coreboot: 02adb9a add native memset() function on x86.
by Stefan Reinauer 06 Mar '12

06 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/737 -gerrit commit 02adb9a045c12eda0797fbe1b7e832cd742b3de7 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Oct 26 22:11:52 2011 +0000 add native memset() function on x86. Change-Id: Ia118ebe0a4b59bdcefd78895141a365170f6aed2 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/Kconfig | 4 ++ src/arch/x86/lib/Makefile.inc | 2 + src/arch/x86/lib/memset.c | 86 +++++++++++++++++++++++++++++++++++++++++ src/lib/Makefile.inc | 4 ++ 4 files changed, 96 insertions(+), 0 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 74933af..078ae95 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -80,6 +80,10 @@ config CMOS_DEFAULT_FILE config BOOTBLOCK_SOUTHBRIDGE_INIT string +config HAVE_ARCH_MEMSET + bool + default y + config HAVE_ARCH_MEMCPY bool default y diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc index f99e429..3f4dc95 100644 --- a/src/arch/x86/lib/Makefile.inc +++ b/src/arch/x86/lib/Makefile.inc @@ -8,10 +8,12 @@ ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c ramstage-y += pci_ops_auto.c ramstage-y += exception.c ramstage-$(CONFIG_IOAPIC) += ioapic.c +ramstage-y += memset.c ramstage-y += memcpy.c romstage-y += romstage_console.c romstage-y += cbfs_and_run.c +romstage-y += memset.c romstage-y += memcpy.c smm-y += memcpy.c diff --git a/src/arch/x86/lib/memset.c b/src/arch/x86/lib/memset.c new file mode 100644 index 0000000..e850726 --- /dev/null +++ b/src/arch/x86/lib/memset.c @@ -0,0 +1,86 @@ +/* + * Copyright (C) 1991,1992,1993,1997,1998,2003, 2005 Free Software Foundation, Inc. + * This file is part of the GNU C Library. + * Copyright (c) 2011 The Chromium OS Authors. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* From glibc-2.14, sysdeps/i386/memset.c */ + +#include <string.h> +#include <stdint.h> + +typedef uint32_t op_t; + +void *memset(void *dstpp, int c, size_t len) +{ + int d0; + unsigned long int dstp = (unsigned long int) dstpp; + + /* This explicit register allocation improves code very much indeed. */ + register op_t x asm("ax"); + + x = (unsigned char) c; + + /* Clear the direction flag, so filling will move forward. */ + asm volatile("cld"); + + /* This threshold value is optimal. */ + if (len >= 12) { + /* Fill X with four copies of the char we want to fill with. */ + x |= (x << 8); + x |= (x << 16); + + /* Adjust LEN for the bytes handled in the first loop. */ + len -= (-dstp) % sizeof(op_t); + + /* + * There are at least some bytes to set. No need to test for + * LEN == 0 in this alignment loop. + */ + + /* Fill bytes until DSTP is aligned on a longword boundary. */ + asm volatile( + "rep\n" + "stosb" /* %0, %2, %3 */ : + "=D" (dstp), "=c" (d0) : + "0" (dstp), "1" ((-dstp) % sizeof(op_t)), "a" (x) : + "memory"); + + /* Fill longwords. */ + asm volatile( + "rep\n" + "stosl" /* %0, %2, %3 */ : + "=D" (dstp), "=c" (d0) : + "0" (dstp), "1" (len / sizeof(op_t)), "a" (x) : + "memory"); + len %= sizeof(op_t); + } + + /* Write the last few bytes. */ + asm volatile( + "rep\n" + "stosb" /* %0, %2, %3 */ : + "=D" (dstp), "=c" (d0) : + "0" (dstp), "1" (len), "a" (x) : + "memory"); + + return dstpp; +} diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 61b6451..8ce72b2 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -1,6 +1,8 @@ +ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y) romstage-y += memset.c +endif romstage-y += memchr.c ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y) romstage-y += memcpy.c @@ -19,7 +21,9 @@ romstage-$(CONFIG_CONSOLE_NE2K) += compute_ip_checksum.c romstage-$(CONFIG_USBDEBUG) += usbdebug.c romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c +ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y) ramstage-y += memset.c +endif ramstage-y += memchr.c ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y) ramstage-y += memcpy.c

1 0

New patch to review for coreboot: 6c49581 Add faster, architecture dependent memcpy()
by Stefan Reinauer 06 Mar '12

06 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/736 -gerrit commit 6c495814c7da47fff7db57267915f5290ab1d560 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Oct 25 23:43:34 2011 +0000 Add faster, architecture dependent memcpy() Change-Id: I38d15f3f1ec65f0cb7974d2dd4ae6356433bddd8 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-by: Duncan Laurie <dlaurie(a)google.com> --- src/arch/x86/Kconfig | 4 ++++ src/arch/x86/lib/Makefile.inc | 4 ++++ src/arch/x86/lib/memcpy.c | 13 +++++++++++++ src/lib/Makefile.inc | 9 ++++++++- 4 files changed, 29 insertions(+), 1 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index e71d0f3..74933af 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -80,6 +80,10 @@ config CMOS_DEFAULT_FILE config BOOTBLOCK_SOUTHBRIDGE_INIT string +config HAVE_ARCH_MEMCPY + bool + default y + config BIG_ENDIAN bool default n diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc index 3388a9d..f99e429 100644 --- a/src/arch/x86/lib/Makefile.inc +++ b/src/arch/x86/lib/Makefile.inc @@ -8,8 +8,12 @@ ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c ramstage-y += pci_ops_auto.c ramstage-y += exception.c ramstage-$(CONFIG_IOAPIC) += ioapic.c +ramstage-y += memcpy.c romstage-y += romstage_console.c romstage-y += cbfs_and_run.c +romstage-y += memcpy.c + +smm-y += memcpy.c $(obj)/arch/x86/lib/console.ramstage.o :: $(obj)/build.h diff --git a/src/arch/x86/lib/memcpy.c b/src/arch/x86/lib/memcpy.c new file mode 100644 index 0000000..de21092 --- /dev/null +++ b/src/arch/x86/lib/memcpy.c @@ -0,0 +1,13 @@ +#include <string.h> + +void *memcpy(void *__restrict __dest, + __const void *__restrict __src, size_t __n) +{ + asm("cld\n" + "rep\n" + "movsb" + : /* no input (?) */ + :"S"(__src), "D"(__dest), "c"(__n) + ); + return __dest; +} diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 45cb788..61b6451 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -2,7 +2,9 @@ romstage-y += memset.c romstage-y += memchr.c +ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y) romstage-y += memcpy.c +endif romstage-y += memcmp.c romstage-y += cbfs.c romstage-y += lzma.c @@ -19,7 +21,9 @@ romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c ramstage-y += memset.c ramstage-y += memchr.c +ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y) ramstage-y += memcpy.c +endif ramstage-y += memcmp.c ramstage-y += memmove.c ramstage-y += malloc.c @@ -43,7 +47,10 @@ ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c driver-$(CONFIG_CONSOLE_NE2K) += ne2k.c -smm-y += memcpy.c cbfs.c memset.c memcmp.c +ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y) +smm-y += memcpy.c +endif +smm-y += cbfs.c memset.c memcmp.c smm-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c smm-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c smm-$(CONFIG_USBDEBUG) += usbdebug.c

1 0

New patch to review for coreboot: 6e237f3 Add support for enabling PCIe Common Clock and ASPM
by Stefan Reinauer 06 Mar '12

06 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/735 -gerrit commit 6e237f330edcfee3ec6ca0202e919ab9e2441966 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Oct 25 14:15:11 2011 -0700 Add support for enabling PCIe Common Clock and ASPM These are guarded by individual Kconfig entries. The deprecated CONFIG_PCIE_TUNING defines have been removed in favor of using specific config options. This is the generic half, there is board-specific pieces still to come that tune before and after ASPM is enabled. Change-Id: I3fe46282eada67629e9eeeed07e487dff54f2729 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/devices/Kconfig | 14 +++ src/devices/pciexp_device.c | 188 +++++++++++++++++++++++++++++++++++++++--- src/include/device/pci_def.h | 7 ++ src/include/device/pciexp.h | 7 ++ 4 files changed, 205 insertions(+), 11 deletions(-) diff --git a/src/devices/Kconfig b/src/devices/Kconfig index 98e8d9f..7429bda 100644 --- a/src/devices/Kconfig +++ b/src/devices/Kconfig @@ -163,3 +163,17 @@ config AGP_PLUGIN_SUPPORT config CARDBUS_PLUGIN_SUPPORT bool default y + +config PCIEXP_COMMON_CLOCK + prompt "Enable PCIe Common Clock" + bool + default n + help + Detect and enable Common Clock on PCIe links. + +config PCIEXP_ASPM + prompt "Enable PCIe ASPM" + bool + default n + help + Detect and enable ASPM on PCIe links. diff --git a/src/devices/pciexp_device.c b/src/devices/pciexp_device.c index 5d33942..36f3e6a 100644 --- a/src/devices/pciexp_device.c +++ b/src/devices/pciexp_device.c @@ -19,31 +19,197 @@ */ #include <console/console.h> +#include <delay.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pciexp.h> +#if CONFIG_PCIEXP_COMMON_CLOCK +/* + * Re-train a PCIe link + */ +#define PCIE_TRAIN_RETRY 10000 +static int pciexp_retrain_link(device_t dev, unsigned cap) +{ + unsigned try = PCIE_TRAIN_RETRY; + u16 lnk; + + /* Start link retraining */ + lnk = pci_read_config16(dev, cap + PCI_EXP_LNKCTL); + lnk |= PCI_EXP_LNKCTL_RL; + pci_write_config16(dev, cap + PCI_EXP_LNKCTL, lnk); + + /* Wait for training to complete */ + while (try--) { + lnk = pci_read_config16(dev, cap + PCI_EXP_LNKSTA); + if (!(lnk & PCI_EXP_LNKSTA_LT)) + return 0; + udelay(100); + } + + printk(BIOS_ERR, "%s: Link Retrain timeout\n", dev_path(dev)); + return -1; +} + +/* + * Check the Slot Clock Configuration for root port and endpoint + * and enable Common Clock Configuration if possible. If CCC is + * enabled the link must be retrained. + */ +static void pciexp_enable_common_clock(device_t root, unsigned root_cap, + device_t endp, unsigned endp_cap) +{ + u16 root_scc, endp_scc, lnkctl; + + /* Get Slot Clock Configuration for root port */ + root_scc = pci_read_config16(root, root_cap + PCI_EXP_LNKSTA); + root_scc &= PCI_EXP_LNKSTA_SLC; + + /* Get Slot Clock Configuration for endpoint */ + endp_scc = pci_read_config16(endp, endp_cap + PCI_EXP_LNKSTA); + endp_scc &= PCI_EXP_LNKSTA_SLC; + + /* Enable Common Clock Configuration and retrain */ + if (root_scc && endp_scc) { + printk(BIOS_INFO, "Enabling Common Clock Configuration\n"); + + /* Set in endpoint */ + lnkctl = pci_read_config16(endp, endp_cap + PCI_EXP_LNKCTL); + lnkctl |= PCI_EXP_LNKCTL_CCC; + pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl); + + /* Set in root port */ + lnkctl = pci_read_config16(root, root_cap + PCI_EXP_LNKCTL); + lnkctl |= PCI_EXP_LNKCTL_CCC; + pci_write_config16(root, root_cap + PCI_EXP_LNKCTL, lnkctl); + + /* Retrain link if CCC was enabled */ + pciexp_retrain_link(root, root_cap); + } +} +#endif /* CONFIG_PCIEXP_COMMON_CLOCK */ + +#if CONFIG_PCIEXP_ASPM +/* + * Determine the ASPM L0s or L1 exit latency for a link + * by checking both root port and endpoint and returning + * the highest latency value. + */ +static int pciexp_aspm_latency(device_t root, unsigned root_cap, + device_t endp, unsigned endp_cap, + enum aspm_type type) +{ + int root_lat = 0, endp_lat = 0; + u32 root_lnkcap, endp_lnkcap; + + root_lnkcap = pci_read_config32(root, root_cap + PCI_EXP_LNKCAP); + endp_lnkcap = pci_read_config32(endp, endp_cap + PCI_EXP_LNKCAP); + + /* Make sure the link supports this ASPM type by checking + * capability bits 11:10 with aspm_type offset by 1 */ + if (!(root_lnkcap & (1 << (type + 9))) || + !(endp_lnkcap & (1 << (type + 9)))) + return -1; + + /* Find the one with higher latency */ + switch (type) { + case PCIE_ASPM_L0S: + root_lat = (root_lnkcap & PCI_EXP_LNKCAP_L0SEL) >> 12; + endp_lat = (endp_lnkcap & PCI_EXP_LNKCAP_L0SEL) >> 12; + break; + case PCIE_ASPM_L1: + root_lat = (root_lnkcap & PCI_EXP_LNKCAP_L1EL) >> 15; + endp_lat = (endp_lnkcap & PCI_EXP_LNKCAP_L1EL) >> 15; + break; + default: + return -1; + } + + return (endp_lat > root_lat) ? endp_lat : root_lat; +} + +/* + * Enable ASPM on PCIe root port and endpoint. + * + * Returns APMC value: + * -1 = Error + * 0 = no ASPM + * 1 = L0s Enabled + * 2 = L1 Enabled + * 3 = L0s and L1 Enabled + */ +static enum aspm_type pciexp_enable_aspm(device_t root, unsigned root_cap, + device_t endp, unsigned endp_cap) +{ + const char *aspm_type_str[] = { "None", "L0s", "L1", "L0s and L1" }; + enum aspm_type apmc = PCIE_ASPM_NONE; + int exit_latency, ok_latency; + u16 lnkctl; + u32 devcap; + + /* Get endpoint device capabilities for acceptable limits */ + devcap = pci_read_config32(endp, endp_cap + PCI_EXP_DEVCAP); + + /* Enable L0s if it is within endpoint acceptable limit */ + ok_latency = (devcap & PCI_EXP_DEVCAP_L0S) >> 6; + exit_latency = pciexp_aspm_latency(root, root_cap, endp, endp_cap, + PCIE_ASPM_L0S); + if (exit_latency >= 0 && exit_latency <= ok_latency) + apmc |= PCIE_ASPM_L0S; + + /* Enable L1 if it is within endpoint acceptable limit */ + ok_latency = (devcap & PCI_EXP_DEVCAP_L1) >> 9; + exit_latency = pciexp_aspm_latency(root, root_cap, endp, endp_cap, + PCIE_ASPM_L1); + if (exit_latency >= 0 && exit_latency <= ok_latency) + apmc |= PCIE_ASPM_L1; + + if (apmc != PCIE_ASPM_NONE) { + /* Set APMC in root port first */ + lnkctl = pci_read_config16(root, root_cap + PCI_EXP_LNKCTL); + lnkctl |= apmc; + pci_write_config16(root, root_cap + PCI_EXP_LNKCTL, lnkctl); + + /* Set APMC in endpoint device next */ + lnkctl = pci_read_config16(endp, endp_cap + PCI_EXP_LNKCTL); + lnkctl |= apmc; + pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl); + } + + printk(BIOS_INFO, "ASPM: Enabled %s\n", aspm_type_str[apmc]); + return apmc; +} +#endif /* CONFIG_PCIEXP_ASPM */ + static void pciexp_tune_dev(device_t dev) { - unsigned int cap; -#if CONFIG_PCIE_TUNING - u32 reg32; -#endif + device_t root = dev->bus->dev; + unsigned int root_cap, cap; cap = pci_find_capability(dev, PCI_CAP_ID_PCIE); if (!cap) return; -#if CONFIG_PCIE_TUNING - printk(BIOS_DEBUG, "PCIe: tuning %s\n", dev_path(dev)); + root_cap = pci_find_capability(root, PCI_CAP_ID_PCIE); + if (!root_cap) + return; + +#if CONFIG_PCIEXP_COMMON_CLOCK + /* Check for and enable Common Clock */ + pciexp_enable_common_clock(root, root_cap, dev, cap); +#endif - // TODO make this depending on ASPM. +#if CONFIG_PCIEXP_ASPM + /* Check for and enable ASPM */ + enum aspm_type apmc = pciexp_enable_aspm(root, root_cap, dev, cap); - /* Enable ASPM role based error reporting. */ - reg32 = pci_read_config32(dev, cap + PCI_EXP_DEVCAP); - reg32 |= PCI_EXP_DEVCAP_RBER; - pci_write_config32(dev, cap + PCI_EXP_DEVCAP, reg32); + if (apmc != PCIE_ASPM_NONE) { + /* Enable ASPM role based error reporting. */ + u32 reg32 = pci_read_config32(dev, cap + PCI_EXP_DEVCAP); + reg32 |= PCI_EXP_DEVCAP_RBER; + pci_write_config32(dev, cap + PCI_EXP_DEVCAP, reg32); + } #endif } diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index a5aa3a1..58a7321 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -371,8 +371,15 @@ #define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */ #define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */ #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ +#define PCI_EXP_LNKCAP_ASPMS 0xc00 /* ASPM Support */ +#define PCI_EXP_LNKCAP_L0SEL 0x7000 /* L0s Exit Latency */ +#define PCI_EXP_LNKCAP_L1EL 0x38000 /* L1 Exit Latency */ #define PCI_EXP_LNKCTL 16 /* Link Control */ +#define PCI_EXP_LNKCTL_RL 0x20 /* Retrain Link */ +#define PCI_EXP_LNKCTL_CCC 0x40 /* Common Clock COnfiguration */ #define PCI_EXP_LNKSTA 18 /* Link Status */ +#define PCI_EXP_LNKSTA_LT 0x800 /* Link Training */ +#define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */ #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ #define PCI_EXP_SLTCTL 24 /* Slot Control */ #define PCI_EXP_SLTSTA 26 /* Slot Status */ diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h index 409f211..87a5002 100644 --- a/src/include/device/pciexp.h +++ b/src/include/device/pciexp.h @@ -2,6 +2,13 @@ #define DEVICE_PCIEXP_H /* (c) 2005 Linux Networx GPL see COPYING for details */ +enum aspm_type { + PCIE_ASPM_NONE = 0, + PCIE_ASPM_L0S = 1, + PCIE_ASPM_L1 = 2, + PCIE_ASPM_BOTH = 3, +}; + unsigned int pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, unsigned int max_devfn, unsigned int max); unsigned int pciexp_scan_bridge(device_t dev, unsigned int max);

1 0

New patch to review for coreboot: 311ab73 tell superiotool about the ITE 8772
by Stefan Reinauer 06 Mar '12

06 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/734 -gerrit commit 311ab730491b4846a499a4a2694176bec93070ae Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Oct 25 17:12:53 2011 +0000 tell superiotool about the ITE 8772 no dumping yet Change-Id: I4e687ca816c8d6d1c95255b0abf6a19513e23f86 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- util/superiotool/ite.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/util/superiotool/ite.c b/util/superiotool/ite.c index c83d788..e186e10 100644 --- a/util/superiotool/ite.c +++ b/util/superiotool/ite.c @@ -708,6 +708,8 @@ static const struct superio_registers reg_table[] = { {EOT}}}, {0x8761, "IT8761E", { {EOT}}}, + {0x8772, "IT8772F", { + {EOT}}}, {0x8780, "IT8780F", { {EOT}}}, {EOT}

1 0

New patch to review for coreboot: a58c8a3 Add timestamps for selfboot and acpi wake
by Stefan Reinauer 06 Mar '12

06 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/733 -gerrit commit a58c8a3e3a4226a9eadd63f65e0f262ac1e74c57 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Oct 19 15:32:39 2011 -0700 Add timestamps for selfboot and acpi wake Change-Id: I28224867610b947739d940d25c98399d219f10f4 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/arch/x86/boot/acpi.c | 7 +++++++ src/boot/selfboot.c | 7 +++++++ src/include/timestamp.h | 2 ++ 3 files changed, 16 insertions(+), 0 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index eb2e4e1..d4d554c 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -31,6 +31,9 @@ #include <arch/acpigen.h> #include <device/pci.h> #include <cbmem.h> +#if CONFIG_COLLECT_TIMESTAMPS +#include <timestamp.h> +#endif #if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/chromeos.h> #endif @@ -611,6 +614,10 @@ void acpi_jump_to_wakeup(void *vector) /* Copy wakeup trampoline in place. */ memcpy((void *)WAKEUP_BASE, &__wakeup, (size_t)&__wakeup_size); +#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_ACPI_WAKE_JUMP); +#endif + acpi_do_wakeup((u32)vector, acpi_backup_memory, CONFIG_RAMBASE, HIGH_MEMORY_SAVE); } diff --git a/src/boot/selfboot.c b/src/boot/selfboot.c index bbf160e..d4ab8c8 100644 --- a/src/boot/selfboot.c +++ b/src/boot/selfboot.c @@ -29,6 +29,9 @@ #include <string.h> #include <cbfs.h> #include <lib.h> +#if CONFIG_COLLECT_TIMESTAMPS +#include <timestamp.h> +#endif /* Maximum physical address we can use for the coreboot bounce buffer. */ #ifndef MAX_ADDR @@ -529,6 +532,10 @@ static int selfboot(struct lb_memory *mem, struct cbfs_payload *payload) printk(BIOS_DEBUG, "Jumping to boot code at %x\n", entry); post_code(POST_ENTER_ELF_BOOT); +#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_SELFBOOT_JUMP); +#endif + /* Jump to kernel */ jmp_to_elf_entry((void*)entry, bounce_buffer, bounce_size); return 1; diff --git a/src/include/timestamp.h b/src/include/timestamp.h index cfa06e2..8b9a89a 100644 --- a/src/include/timestamp.h +++ b/src/include/timestamp.h @@ -37,6 +37,8 @@ struct timestamp_table { enum timestamp_id { TS_BEFORE_INITRAM = 1, TS_AFTER_INITRAM = 2, + TS_ACPI_WAKE_JUMP = 98, + TS_SELFBOOT_JUMP = 99, }; void timestamp_init(tsc_t base);

1 0

New patch to review for coreboot: 3cf8407 selfboot: Allow loading SeaBIOS into a reserved region in the lower 1MB This fixes loading SeaBIOS when lower memory is reserved.
by Stefan Reinauer 06 Mar '12

06 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/732 -gerrit commit 3cf8407dff32d39a8e6365f17bd4455b2f009964 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Oct 18 15:11:04 2011 -0700 selfboot: Allow loading SeaBIOS into a reserved region in the lower 1MB This fixes loading SeaBIOS when lower memory is reserved. Change-Id: Idbdcaf95f3307f97307f304d6d677406d059927d Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/boot/selfboot.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/src/boot/selfboot.c b/src/boot/selfboot.c index fe56653..bbf160e 100644 --- a/src/boot/selfboot.c +++ b/src/boot/selfboot.c @@ -148,6 +148,11 @@ static int valid_area(struct lb_memory *mem, unsigned long buffer, } } if (i == mem_entries) { + if (start < (1024*1024) && end <=(1024*1024)) { + printk(BIOS_DEBUG, "Payload (probably SeaBIOS) loaded" + " into a reserved area in the lower 1MB\n"); + return 1; + } printk(BIOS_ERR, "No matching ram area found for range:\n"); printk(BIOS_ERR, " [0x%016lx, 0x%016lx)\n", start, end); printk(BIOS_ERR, "Ram areas\n");

1 0

New patch to review for coreboot: e6e259b Add TPM support to coreboot
by Stefan Reinauer 06 Mar '12

06 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/731 -gerrit commit e6e259bc37761ddaaf6c1644bf23724bf561b827 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Oct 11 14:46:25 2011 -0700 Add TPM support to coreboot and initialize the TPM on S3 resume This patch integrates the TPM driver and runs TPM resume upon an ACPI S3 resume without including any other parts of vboot. We could link against vboot_fw.a but it is compiled with u-boot's CFLAGS (that are incompatible with coreboot's) and it does a lot more than we want it to do. Change-Id: I000d4322ef313e931e23c56defaa17e3a4d7f8cf Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/Kconfig | 4 + src/arch/x86/boot/acpi.c | 8 + src/include/pc80/tpm.h | 29 ++ src/pc80/Makefile.inc | 1 + src/pc80/tpm.c | 554 ++++++++++++++++++++++++++++++++ src/vendorcode/google/chromeos/vboot.c | 201 ++++++++++++ 6 files changed, 797 insertions(+), 0 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 573868f..26e6dde 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -262,6 +262,10 @@ config IOAPIC bool default n +config TPM + bool + default n + # TODO: Can probably be removed once all chipsets have kconfig options for it. config VIDEO_MB int diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index f1be034..eb2e4e1 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -31,6 +31,9 @@ #include <arch/acpigen.h> #include <device/pci.h> #include <cbmem.h> +#if CONFIG_CHROMEOS +#include <vendorcode/google/chromeos/chromeos.h> +#endif u8 acpi_checksum(u8 *table, u32 length) { @@ -525,6 +528,11 @@ void *acpi_find_wakeup_vector(void) if (!acpi_is_wakeup()) return NULL; +#ifdef CONFIG_CHROMEOS + printk(BIOS_DEBUG, "Verified boot TPM initialization.\n"); + init_vboot(); +#endif + printk(BIOS_DEBUG, "Trying to find the wakeup vector...\n"); /* Find RSDP. */ diff --git a/src/include/pc80/tpm.h b/src/include/pc80/tpm.h new file mode 100644 index 0000000..2eff15a --- /dev/null +++ b/src/include/pc80/tpm.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef TPM_H_ +#define TPM_H_ + +int tis_init(void); +int tis_open(void); +int tis_close(void); +int tis_sendrecv(const u8 *sendbuf, size_t send_size, u8 *recvbuf, + size_t *recv_len); + +#endif /* TPM_H_ */ diff --git a/src/pc80/Makefile.inc b/src/pc80/Makefile.inc index 2c8a80e..cd6ea33 100644 --- a/src/pc80/Makefile.inc +++ b/src/pc80/Makefile.inc @@ -4,6 +4,7 @@ ramstage-y += i8254.c ramstage-y += i8259.c ramstage-$(CONFIG_UDELAY_IO) += udelay_io.c ramstage-y += keyboard.c +ramstage-$(CONFIG_TPM) += tpm.c romstage-$(CONFIG_USE_OPTION_TABLE) += mc146818rtc_early.c subdirs-y += vga diff --git a/src/pc80/tpm.c b/src/pc80/tpm.c new file mode 100644 index 0000000..1cbf800 --- /dev/null +++ b/src/pc80/tpm.c @@ -0,0 +1,554 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * The code in this file has been heavily based on the article "Writing a TPM + * Device Driver" published on http://ptgmedia.pearsoncmg.com and the + * submission by Stefan Berger on Qemu-devel mailing list. + * + * One principal difference is that in the simplest config the other than 0 + * TPM localities do not get mapped by some devices (for instance, by + * Infineon slb9635), so this driver provides access to locality 0 only. + */ + +/* #define DEBUG */ +#include <stdlib.h> +#include <string.h> +#include <delay.h> +#include <arch/io.h> +#include <arch/byteorder.h> +#include <console/console.h> +#include <pc80/tpm.h> + +#ifdef DEBUG +#define TPM_DEBUG_ON 1 +#else +#define TPM_DEBUG_ON 0 +#endif + +#define PREFIX "lpc_tpm: " + +/* coreboot wrapper for TPM driver (start) */ +#define TPM_DEBUG(fmt, args...) \ + if (TPM_DEBUG_ON) { \ + printk(BIOS_DEBUG, PREFIX); \ + printk(BIOS_DEBUG, fmt , ##args); \ + } +#define printf(x...) printk(BIOS_ERR, x) + +#define min(a,b) MIN(a,b) +#define max(a,b) MAX(a,b) +#define readb(_a) (*(volatile unsigned char *) (_a)) +#define writeb(_v, _a) (*(volatile unsigned char *) (_a) = (_v)) +#define readl(_a) (*(volatile unsigned long *) (_a)) +#define writel(_v, _a) (*(volatile unsigned long *) (_a) = (_v)) +/* coreboot wrapper for TPM driver (end) */ + +#ifndef CONFIG_TPM_TIS_BASE_ADDRESS +/* Base TPM address standard for x86 systems */ +#define CONFIG_TPM_TIS_BASE_ADDRESS 0xfed40000 +#endif + +/* the macro accepts the locality value, but only locality 0 is operational */ +#define TIS_REG(LOCALITY, REG) \ + (void *)(CONFIG_TPM_TIS_BASE_ADDRESS + (LOCALITY << 12) + REG) + +/* hardware registers' offsets */ +#define TIS_REG_ACCESS 0x0 +#define TIS_REG_INT_ENABLE 0x8 +#define TIS_REG_INT_VECTOR 0xc +#define TIS_REG_INT_STATUS 0x10 +#define TIS_REG_INTF_CAPABILITY 0x14 +#define TIS_REG_STS 0x18 +#define TIS_REG_DATA_FIFO 0x24 +#define TIS_REG_DID_VID 0xf00 +#define TIS_REG_RID 0xf04 + +/* Some registers' bit field definitions */ +#define TIS_STS_VALID (1 << 7) /* 0x80 */ +#define TIS_STS_COMMAND_READY (1 << 6) /* 0x40 */ +#define TIS_STS_TPM_GO (1 << 5) /* 0x20 */ +#define TIS_STS_DATA_AVAILABLE (1 << 4) /* 0x10 */ +#define TIS_STS_EXPECT (1 << 3) /* 0x08 */ +#define TIS_STS_RESPONSE_RETRY (1 << 1) /* 0x02 */ + +#define TIS_ACCESS_TPM_REG_VALID_STS (1 << 7) /* 0x80 */ +#define TIS_ACCESS_ACTIVE_LOCALITY (1 << 5) /* 0x20 */ +#define TIS_ACCESS_BEEN_SEIZED (1 << 4) /* 0x10 */ +#define TIS_ACCESS_SEIZE (1 << 3) /* 0x08 */ +#define TIS_ACCESS_PENDING_REQUEST (1 << 2) /* 0x04 */ +#define TIS_ACCESS_REQUEST_USE (1 << 1) /* 0x02 */ +#define TIS_ACCESS_TPM_ESTABLISHMENT (1 << 0) /* 0x01 */ + +#define TIS_STS_BURST_COUNT_MASK (0xffff) +#define TIS_STS_BURST_COUNT_SHIFT (8) + +/* + * Error value returned if a tpm register does not enter the expected state + * after continuous polling. No actual TPM register reading ever returns ~0, + * so this value is a safe error indication to be mixed with possible status + * register values. + */ +#define TPM_TIMEOUT_ERR (~0) + +/* Error value returned on various TPM driver errors */ +#define TPM_DRIVER_ERR (~0) + + /* 1 second is plenty for anything TPM does.*/ +#define MAX_DELAY_US (1000 * 1000) + +/* Retrieve burst count value out of the status register contents. */ +#define BURST_COUNT(status) ((u16)(((status) >> TIS_STS_BURST_COUNT_SHIFT) & \ + TIS_STS_BURST_COUNT_MASK)) + +/* + * Structures defined below allow creating descriptions of TPM vendor/device + * ID information for run time discovery. The only device the system knows + * about at this time is Infineon slb9635 + */ +struct device_name { + u16 dev_id; + const char * const dev_name; +}; + +struct vendor_name { + u16 vendor_id; + const char * vendor_name; + struct device_name* dev_names; +}; + +static struct device_name infineon_devices[] = { + {0xb, "SLB9635 TT 1.2"}, + {0} +}; + +static const struct vendor_name vendor_names[] = { + {0x15d1, "Infineon", infineon_devices}, +}; + +/* + * Cached vendor/device ID pair to indicate that the device has been already + * discovered + */ +static u32 vendor_dev_id; + +static int is_byte_reg(u32 reg) +{ + /* + * These TPM registers are 8 bits wide and as such require byte access + * on writes and truncated value on reads. + */ + return ((reg == TIS_REG_ACCESS) || + (reg == TIS_REG_INT_VECTOR) || + (reg == TIS_REG_DATA_FIFO)); +} + +/* TPM access functions are carved out to make tracing easier. */ +static u32 tpm_read(int locality, u32 reg) +{ + u32 value; + /* + * Data FIFO register must be read and written in byte access mode, + * otherwise the FIFO values are returned 4 bytes at a time. + */ + if (is_byte_reg(reg)) + value = readb(TIS_REG(locality, reg)); + else + value = readl(TIS_REG(locality, reg)); + + TPM_DEBUG("Read reg 0x%x returns 0x%x\n", reg, value); + return value; +} + +static void tpm_write(u32 value, int locality, u32 reg) +{ + TPM_DEBUG("Write reg 0x%x with 0x%x\n", reg, value); + + if (is_byte_reg(reg)) + writeb(value & 0xff, TIS_REG(locality, reg)); + else + writel(value, TIS_REG(locality, reg)); +} + +/* + * tis_wait_reg() + * + * Wait for at least a second for a register to change its state to match the + * expected state. Normally the transition happens within microseconds. + * + * @reg - the TPM register offset + * @locality - locality + * @mask - bitmask for the bitfield(s) to watch + * @expected - value the field(s) are supposed to be set to + * + * Returns the register contents in case the expected value was found in the + * appropriate register bits, or TPM_TIMEOUT_ERR on timeout. + */ +static u32 tis_wait_reg(u8 reg, u8 locality, u8 mask, u8 expected) +{ + u32 time_us = MAX_DELAY_US; + while (time_us > 0) { + u32 value = tpm_read(locality, reg); + if ((value & mask) == expected) + return value; + udelay(1); /* 1 us */ + time_us--; + } + return TPM_TIMEOUT_ERR; +} + +/* + * Probe the TPM device and try determining its manufacturer/device name. + * + * Returns 0 on success (the device is found or was found during an earlier + * invocation) or TPM_DRIVER_ERR if the device is not found. + */ +static u32 tis_probe(void) +{ + u32 didvid = tpm_read(0, TIS_REG_DID_VID); + int i; + const char *device_name = "unknown"; + const char *vendor_name = device_name; + u16 vid, did; + + if (vendor_dev_id) + return 0; /* Already probed. */ + + if (!didvid || (didvid == 0xffffffff)) { + printf("%s: No TPM device found\n", __FUNCTION__); + return TPM_DRIVER_ERR; + } + + vendor_dev_id = didvid; + + vid = didvid & 0xffff; + did = (didvid >> 16) & 0xffff; + for (i = 0; i < ARRAY_SIZE(vendor_names); i++) { + int j = 0; + u16 known_did; + if (vid == vendor_names[i].vendor_id) { + vendor_name = vendor_names[i].vendor_name; + } + while ((known_did = vendor_names[i].dev_names[j].dev_id) != 0) { + if (known_did == did) { + device_name = + vendor_names[i].dev_names[j].dev_name; + break; + } + j++; + } + break; + } + /* this will have to be converted into debug printout */ + TPM_DEBUG("Found TPM %s by %s\n", device_name, vendor_name); + return 0; +} + +/* + * tis_senddata() + * + * send the passed in data to the TPM device. + * + * @data - address of the data to send, byte by byte + * @len - length of the data to send + * + * Returns 0 on success, TPM_DRIVER_ERR on error (in case the device does + * not accept the entire command). + */ +static u32 tis_senddata(const u8 * const data, u32 len) +{ + u32 offset = 0; + u16 burst = 0; + u32 max_cycles = 0; + u8 locality = 0; + u32 value; + + value = tis_wait_reg(TIS_REG_STS, locality, TIS_STS_COMMAND_READY, + TIS_STS_COMMAND_READY); + if (value == TPM_TIMEOUT_ERR) { + printf("%s:%d - failed to get 'command_ready' status\n", + __FILE__, __LINE__); + return TPM_DRIVER_ERR; + } + burst = BURST_COUNT(value); + + while (1) { + unsigned count; + + /* Wait till the device is ready to accept more data. */ + while (!burst) { + if (max_cycles++ == MAX_DELAY_US) { + printf("%s:%d failed to feed %d bytes of %d\n", + __FILE__, __LINE__, len - offset, len); + return TPM_DRIVER_ERR; + } + udelay(1); + burst = BURST_COUNT(tpm_read(locality, TIS_REG_STS)); + } + + max_cycles = 0; + + /* + * Calculate number of bytes the TPM is ready to accept in one + * shot. + * + * We want to send the last byte outside of the loop (hence + * the -1 below) to make sure that the 'expected' status bit + * changes to zero exactly after the last byte is fed into the + * FIFO. + */ + count = min(burst, len - offset - 1); + while (count--) + tpm_write(data[offset++], locality, TIS_REG_DATA_FIFO); + + value = tis_wait_reg(TIS_REG_STS, locality, + TIS_STS_VALID, TIS_STS_VALID); + + if ((value == TPM_TIMEOUT_ERR) || !(value & TIS_STS_EXPECT)) { + printf("%s:%d TPM command feed overflow\n", + __FILE__, __LINE__); + return TPM_DRIVER_ERR; + } + + burst = BURST_COUNT(value); + if ((offset == (len - 1)) && burst) + /* + * We need to be able to send the last byte to the + * device, so burst size must be nonzero before we + * break out. + */ + break; + } + + /* Send the last byte. */ + tpm_write(data[offset++], locality, TIS_REG_DATA_FIFO); + + /* + * Verify that TPM does not expect any more data as part of this + * command. + */ + value = tis_wait_reg(TIS_REG_STS, locality, + TIS_STS_VALID, TIS_STS_VALID); + if ((value == TPM_TIMEOUT_ERR) || (value & TIS_STS_EXPECT)) { + printf("%s:%d unexpected TPM status 0x%x\n", + __FILE__, __LINE__, value); + return TPM_DRIVER_ERR; + } + + /* OK, sitting pretty, let's start the command execution. */ + tpm_write(TIS_STS_TPM_GO, locality, TIS_REG_STS); + + return 0; +} + +/* + * tis_readresponse() + * + * read the TPM device response after a command was issued. + * + * @buffer - address where to read the response, byte by byte. + * @len - pointer to the size of buffer + * + * On success stores the number of received bytes to len and returns 0. On + * errors (misformatted TPM data or synchronization problems) returns + * TPM_DRIVER_ERR. + */ +static u32 tis_readresponse(u8 *buffer, size_t *len) +{ + u16 burst_count; + u32 status; + u32 offset = 0; + u8 locality = 0; + const u32 has_data = TIS_STS_DATA_AVAILABLE | TIS_STS_VALID; + u32 expected_count = *len; + int max_cycles = 0; + + /* Wait for the TPM to process the command */ + status = tis_wait_reg(TIS_REG_STS, locality, has_data, has_data); + if (status == TPM_TIMEOUT_ERR) { + printf("%s:%d failed processing command\n", + __FILE__, __LINE__); + return TPM_DRIVER_ERR; + } + + do { + while ((burst_count = BURST_COUNT(status)) == 0) { + if (max_cycles++ == MAX_DELAY_US) { + printf("%s:%d TPM stuck on read\n", + __FILE__, __LINE__); + return TPM_DRIVER_ERR; + } + udelay(1); + status = tpm_read(locality, TIS_REG_STS); + } + + max_cycles = 0; + + while (burst_count-- && (offset < expected_count)) { + buffer[offset++] = (u8) tpm_read(locality, + TIS_REG_DATA_FIFO); + if (offset == 6) { + /* + * We got the first six bytes of the reply, + * let's figure out how many bytes to expect + * total - it is stored as a 4 byte number in + * network order, starting with offset 2 into + * the body of the reply. + */ + u32 real_length; + memcpy(&real_length, + buffer + 2, + sizeof(real_length)); + expected_count = be32_to_cpu(real_length); + + if ((expected_count < offset) || + (expected_count > *len)) { + printf("%s:%d bad response size %d\n", + __FILE__, __LINE__, + expected_count); + return TPM_DRIVER_ERR; + } + } + } + + /* Wait for the next portion */ + status = tis_wait_reg(TIS_REG_STS, locality, + TIS_STS_VALID, TIS_STS_VALID); + if (status == TPM_TIMEOUT_ERR) { + printf("%s:%d failed to read response\n", + __FILE__, __LINE__); + return TPM_DRIVER_ERR; + } + + if (offset == expected_count) + break; /* We got all we need */ + + } while ((status & has_data) == has_data); + + /* + * Make sure we indeed read all there was. The TIS_STS_VALID bit is + * known to be set. + */ + if (status & TIS_STS_DATA_AVAILABLE) { + printf("%s:%d wrong receive status %x\n", + __FILE__, __LINE__, status); + return TPM_DRIVER_ERR; + } + + /* Tell the TPM that we are done. */ + tpm_write(TIS_STS_COMMAND_READY, locality, TIS_REG_STS); + + *len = offset; + return 0; +} + +/* + * tis_init() + * + * Initialize the TPM device. Returns 0 on success or TPM_DRIVER_ERR on + * failure (in case device probing did not succeed). + */ +int tis_init(void) +{ + if (tis_probe()) + return TPM_DRIVER_ERR; + return 0; +} + +/* + * tis_open() + * + * Requests access to locality 0 for the caller. After all commands have been + * completed the caller is supposed to call tis_close(). + * + * Returns 0 on success, TPM_DRIVER_ERR on failure. + */ +int tis_open(void) +{ + u8 locality = 0; /* we use locality zero for everything */ + + if (tis_close()) + return TPM_DRIVER_ERR; + + /* now request access to locality */ + tpm_write(TIS_ACCESS_REQUEST_USE, locality, TIS_REG_ACCESS); + + /* did we get a lock? */ + if (tis_wait_reg(TIS_REG_ACCESS, locality, + TIS_ACCESS_ACTIVE_LOCALITY, + TIS_ACCESS_ACTIVE_LOCALITY) == TPM_TIMEOUT_ERR) { + printf("%s:%d - failed to lock locality %d\n", + __FILE__, __LINE__, locality); + return TPM_DRIVER_ERR; + } + + tpm_write(TIS_STS_COMMAND_READY, locality, TIS_REG_STS); + + return 0; +} + +/* + * tis_close() + * + * terminate the currect session with the TPM by releasing the locked + * locality. Returns 0 on success of TPM_DRIVER_ERR on failure (in case lock + * removal did not succeed). + */ +int tis_close(void) +{ + u8 locality = 0; + if (tpm_read(locality, TIS_REG_ACCESS) & + TIS_ACCESS_ACTIVE_LOCALITY) { + tpm_write(TIS_ACCESS_ACTIVE_LOCALITY, locality, TIS_REG_ACCESS); + + if (tis_wait_reg(TIS_REG_ACCESS, locality, + TIS_ACCESS_ACTIVE_LOCALITY, 0) == + TPM_TIMEOUT_ERR) { + printf("%s:%d - failed to release locality %d\n", + __FILE__, __LINE__, locality); + return TPM_DRIVER_ERR; + } + } + return 0; +} + +/* + * tis_sendrecv() + * + * Send the requested data to the TPM and then try to get its response + * + * @sendbuf - buffer of the data to send + * @send_size size of the data to send + * @recvbuf - memory to save the response to + * @recv_len - pointer to the size of the response buffer + * + * Returns 0 on success (and places the number of response bytes at recv_len) + * or TPM_DRIVER_ERR on failure. + */ +int tis_sendrecv(const uint8_t *sendbuf, size_t send_size, + uint8_t *recvbuf, size_t *recv_len) +{ + if (tis_senddata(sendbuf, send_size)) { + printf("%s:%d failed sending data to TPM\n", + __FILE__, __LINE__); + return TPM_DRIVER_ERR; + } + + return tis_readresponse(recvbuf, recv_len); +} diff --git a/src/vendorcode/google/chromeos/vboot.c b/src/vendorcode/google/chromeos/vboot.c new file mode 100644 index 0000000..e0a8c9b --- /dev/null +++ b/src/vendorcode/google/chromeos/vboot.c @@ -0,0 +1,201 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <pc80/tpm.h> +#include "chromeos.h" + +//#define EXTRA_LOGGING + +#define TPM_LARGE_ENOUGH_COMMAND_SIZE 256 /* saves space in the firmware */ + +#define TPM_SUCCESS ((u32)0x00000000) + +#define TPM_E_IOERROR ((u32)0x0000001f) +#define TPM_E_COMMUNICATION_ERROR ((u32)0x00005004) +#define TPM_E_NON_FATAL ((u32)0x00000800) +#define TPM_E_INVALID_POSTINIT ((u32)0x00000026) + +#define TPM_E_NEEDS_SELFTEST ((u32)(TPM_E_NON_FATAL + 1)) +#define TPM_E_DOING_SELFTEST ((u32)(TPM_E_NON_FATAL + 2)) + +static const struct { + u8 buffer[12]; +} tpm_resume_cmd = { + { 0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x0, 0x99, 0x0, 0x2 } +}; + +static const struct { + u8 buffer[10]; +} tpm_continueselftest_cmd = { + { 0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x53 } +}; + +static inline void FromTpmUint32(const u8 * buffer, u32 * x) +{ + *x = ((buffer[0] << 24) | + (buffer[1] << 16) | (buffer[2] << 8) | buffer[3]); +} + +static inline int TpmCommandSize(const u8 * buffer) +{ + u32 size; + FromTpmUint32(buffer + sizeof(u16), &size); + return (int)size; +} + +/* Gets the code field of a TPM command. */ +static inline int TpmCommandCode(const u8 * buffer) +{ + u32 code; + FromTpmUint32(buffer + sizeof(u16) + sizeof(u32), &code); + return code; +} + +/* Gets the return code field of a TPM result. */ +static inline int TpmReturnCode(const u8 * buffer) +{ + return TpmCommandCode(buffer); +} + +/* Like TlclSendReceive below, but do not retry if NEEDS_SELFTEST or + * DOING_SELFTEST errors are returned. + */ +static u32 TlclSendReceiveNoRetry(const u8 * request, + u8 * response, int max_length) +{ + size_t response_length = max_length; + u32 result; + +#ifdef EXTRA_LOGGING + printk(BIOS_DEBUG, "TPM: command: %x%x %x%x%x%x %x%x%x%x\n", + request[0], request[1], + request[2], request[3], request[4], request[5], + request[6], request[7], request[8], request[9]); +#endif + + result = TPM_SUCCESS; + if (tis_sendrecv + (request, TpmCommandSize(request), response, &response_length)) + result = TPM_E_IOERROR; + + if (0 != result) { + /* Communication with TPM failed, so response is garbage */ + printk(BIOS_DEBUG, + "TPM: command 0x%x send/receive failed: 0x%x\n", + TpmCommandCode(request), result); + return TPM_E_COMMUNICATION_ERROR; + } + /* Otherwise, use the result code from the response */ + result = TpmReturnCode(response); + +/* TODO: add paranoia about returned response_length vs. max_length + * (and possibly expected length from the response header). See + * crosbug.com/17017 */ + +#ifdef EXTRA_LOGGING + printk(BIOS_DEBUG, "TPM: response: %x%x %x%x%x%x %x%x%x%x\n", + response[0], response[1], + response[2], response[3], response[4], response[5], + response[6], response[7], response[8], response[9]); +#endif + + printk(BIOS_DEBUG, "TPM: command 0x%x returned 0x%x\n", + TpmCommandCode(request), result); + + return result; +} + +static inline u32 TlclContinueSelfTest(void) +{ + u8 response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; + printk(BIOS_DEBUG, "TPM: Continue self test\n"); + /* Call the No Retry version of SendReceive to avoid recursion. */ + return TlclSendReceiveNoRetry(tpm_continueselftest_cmd.buffer, + response, sizeof(response)); +} + +/* Sends a TPM command and gets a response. Returns 0 if success or the TPM + * error code if error. In the firmware, waits for the self test to complete + * if needed. In the host, reports the first error without retries. */ +static u32 TlclSendReceive(const u8 * request, u8 * response, int max_length) +{ + u32 result = TlclSendReceiveNoRetry(request, response, max_length); + /* When compiling for the firmware, hide command failures due to the self + * test not having run or completed. */ + /* If the command fails because the self test has not completed, try it + * again after attempting to ensure that the self test has completed. */ + if (result == TPM_E_NEEDS_SELFTEST || result == TPM_E_DOING_SELFTEST) { + result = TlclContinueSelfTest(); + if (result != TPM_SUCCESS) { + return result; + } +#if defined(TPM_BLOCKING_CONTINUESELFTEST) || defined(VB_RECOVERY_MODE) + /* Retry only once */ + result = TlclSendReceiveNoRetry(request, response, max_length); +#else + /* This needs serious testing. The TPM specification says: + * "iii. The caller MUST wait for the actions of + * TPM_ContinueSelfTest to complete before reissuing the + * command C1." But, if ContinueSelfTest is non-blocking, how + * do we know that the actions have completed other than trying + * again? */ + do { + result = + TlclSendReceiveNoRetry(request, response, + max_length); + } while (result == TPM_E_DOING_SELFTEST); +#endif + } + + return result; +} + +void init_vboot(void) +{ + u32 result; + u8 response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; + + printk(BIOS_DEBUG, "TPM: Init\n"); + if (tis_init()) + return; + + printk(BIOS_DEBUG, "TPM: Open\n"); + if (tis_open()) + return; + + printk(BIOS_DEBUG, "TPM: Resume\n"); + + result = + TlclSendReceive(tpm_resume_cmd.buffer, response, sizeof(response)); + + if (result == TPM_E_INVALID_POSTINIT) { + /* We're on a platform where the TPM maintains power in S3, so + * it's already initialized. */ + printk(BIOS_DEBUG, "TPM: Already initialized.\n"); + return; + } + if (result == TPM_SUCCESS) { + printk(BIOS_DEBUG, "TPM: OK.\n"); + return; + } + // TODO(reinauer) hard reboot? +}

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coreboot March 2012