March 2012 - coreboot - mail.coreboot.org

New patch to review for coreboot: 48ce747 CBMEM CONSOLE: Add CBMEM type for console buffer.
by Stefan Reinauer March 6, 2012

March 6, 2012

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/720 -gerrit commit 48ce747d48a0cc6c633e290fb1e66ada7c4142fd Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri Sep 30 11:13:06 2011 -0700 CBMEM CONSOLE: Add CBMEM type for console buffer. Add CBMEM type for the console buffer section. Change-Id: I02757c06d71e46af77b02b90b0e6018a37b62406 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/include/cbmem.h | 1 + src/lib/cbmem.c | 1 + 2 files changed, 2 insertions(+), 0 deletions(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index c3f10ef..a19ec5a 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -42,6 +42,7 @@ extern uint64_t high_tables_base, high_tables_size; #define CBMEM_ID_RESUME 0x5245534d #define CBMEM_ID_SMBIOS 0x534d4254 #define CBMEM_ID_TIMESTAMP 0x54494d45 +#define CBMEM_ID_CONSOLE 0x434f4e53 #define CBMEM_ID_NONE 0x00000000 int cbmem_initialize(void); diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index f800b04..b09b070 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -256,6 +256,7 @@ void cbmem_list(void) case CBMEM_ID_RESUME: printk(BIOS_DEBUG, "ACPI RESUME"); break; case CBMEM_ID_SMBIOS: printk(BIOS_DEBUG, "SMBIOS "); break; case CBMEM_ID_TIMESTAMP: printk(BIOS_DEBUG, "TIME STAMP "); break; + case CBMEM_ID_CONSOLE: printk(BIOS_DEBUG, "CONSOLE "); break; default: printk(BIOS_DEBUG, "%08x ", cbmem_toc[i].id); } printk(BIOS_DEBUG, "%08llx ", cbmem_toc[i].base);

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New patch to review for coreboot: a14055f CBMEM CONSOLE: Add CBMEM console driver implementation.
by Stefan Reinauer March 6, 2012

March 6, 2012

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/719 -gerrit commit a14055f63ad05cc8e69e0a1999d1ea90f6889185 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu Sep 29 17:27:15 2011 -0700 CBMEM CONSOLE: Add CBMEM console driver implementation. The CBMEM console driver saves console output in a CBMEM area, which then is made available to Linux applications for perusing. There are some system limitations which need to be worked around to achieve this goal: - some console traffic is generated before DRAM is initialized, leave alone CBMEM initialized. - after the RAM based stage starts, a lot of traffic is generated before CBMEM is initialized. As a result, the console log lives in three different places - the bottom of the cache as RAM space, the CBMEM buffer (where it is expected to be) and a static buffer used early in the RAM stage. When execution starts (in the cache as RAM mode), the console buffer is allocated at the bottom of the cache as RAM memory address range. Once DRAM is initialized, the CBMEM structure is initialized, and then the console buffer contents are copied from the bottom of the cache as RAM space into the CBMEM area right before the cache as RAM mode is disabled. The src/lib/cbmem_console.c:cbmemc_reinit() takes care of the copying. At this point the cache as RAM memory is about to be disabled, but the ROM stage is still going generating console output. To make sure this output is not lost, cbmemc_reinit() saves the new buffer address at a fixed location (0x600 was chosen for this), and the actual "printing" function checks to see if the RAM is already initialized (the stack is in RAM), and if so, gets the console buffer pointer from this location instead of using the cache as RAM address. When the RAM stage starts, a static buffer is used to store the console output, as the CBMEM buffer location is not known. Then, when CBMEM is reinitialized, cbmemc_reinit() again takes care of the copying. In case the allocated buffers are not large enough, the excessive data is dropped, and the copying routine adds some text to the output buffer to indicate that there has been data lost and how many characters were dropped. Change-Id: I8c126e31db6cb2141f7f4f97c5047f39a8db44fc Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/console/cbmem_console.c | 35 ++++++ src/include/console/cbmem_console.h | 26 +++++ src/include/console/console.h | 3 + src/lib/cbmem_console.c | 195 +++++++++++++++++++++++++++++++++++ 4 files changed, 259 insertions(+), 0 deletions(-) diff --git a/src/console/cbmem_console.c b/src/console/cbmem_console.c new file mode 100644 index 0000000..2c43f5c --- /dev/null +++ b/src/console/cbmem_console.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#include <console/console.h> + +static void cbmemc_init_(void) +{ + cbmemc_init(); +} + +static void cbmemc_tx_byte_(unsigned char data) +{ + cbmemc_tx_byte(data); +} + +static const struct console_driver cbmem_console __console = { + .init = cbmemc_init_, + .tx_byte = cbmemc_tx_byte_, +}; diff --git a/src/include/console/cbmem_console.h b/src/include/console/cbmem_console.h new file mode 100644 index 0000000..37ea4d8 --- /dev/null +++ b/src/include/console/cbmem_console.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ +#ifndef _CONSOLE_CBMEM_CONSOLE_H_ +#define _CONSOLE_CBMEM_CONSOLE_H_ + +void cbmemc_init(void); +void cbmemc_reinit(void); +void cbmemc_tx_byte(unsigned char data); + +#endif diff --git a/src/include/console/console.h b/src/include/console/console.h index 54c825c..56e202d 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -33,6 +33,9 @@ #if CONFIG_CONSOLE_NE2K #include <console/ne2k.h> #endif +#if CONFIG_CONSOLE_CBMEM +#include <console/cbmem_console.h> +#endif #ifndef __PRE_RAM__ void console_tx_byte(unsigned char byte); diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c new file mode 100644 index 0000000..b58de48 --- /dev/null +++ b/src/lib/cbmem_console.c @@ -0,0 +1,195 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#include <console/console.h> +#include <cbmem.h> +#include <string.h> + +/* + * Structure describing console buffer. It is overlaid on a flat memory area, + * whith buffer_body covering the extent of the memory. Once the buffer is + * full, the cursor keeps going but the data is dropped on the floor. This + * allows to tell how much data was lost in the process. + */ +struct cbmem_console { + u32 buffer_size; + u32 buffer_cursor; + u8 buffer_body[0]; +} __attribute__ ((__packed__)); + +#ifdef __PRE_RAM__ +/* + * While running from ROM, before DRAM is initialized, some area in cache as + * ram space is used for the console buffer storage. The size and location of + * the area are defined in the config. + */ +#define cbmem_console_p ((struct cbmem_console *)CONFIG_DCACHE_RAM_BASE) + +/* + * Once DRAM is initialized and the cache as ram mode is disabled, while still + * running from ROM, the console buffer in the cache as RAM area becomes + * unavailable. + * + * By this time the console log buffer is already available in + * CBMEM. The location at 0x600 is used as the redirect pointer allowing to + * find out where the actual console log buffer is. + */ +#define CBMEM_CONSOLE_REDIRECT (*((struct cbmem_console **)0x600)) +#else + +/* + * When running from RAM, a lot of console output is generated before CBMEM is + * reinitialized. This static buffer is used to store that output temporarily, + * to be concatenated with the CBMEM console buffer contents accumulated + * during the ROM stage, once CBMEM becomes avaiklable at RAM stage. + */ +static u8 static_console[40000]; +static struct cbmem_console *cbmem_console_p; +#endif + +void cbmemc_init(void) +{ +#ifdef __PRE_RAM__ + cbmem_console_p->buffer_size = CONFIG_CONSOLE_CAR_BUFFER_SIZE - + sizeof(struct cbmem_console); +#else + /* + * Initializing before CBMEM is available, use static buffer to store + * the log. + */ + cbmem_console_p = (struct cbmem_console *) static_console; + cbmem_console_p->buffer_size = sizeof(static_console) - + sizeof(struct cbmem_console); +#endif + cbmem_console_p->buffer_cursor = 0; +} + +void cbmemc_tx_byte(unsigned char data) +{ + struct cbmem_console *cbm_cons_p = cbmem_console_p; + u32 cursor; +#ifdef __PRE_RAM__ + /* + * This check allows to tell if the cache as RAM mode has been exited + * or not. If it has been exited, the real memory is being used + * (resulting in the variable on the stack located below + * DCACHE_RAM_BASE), use the redirect pointer to find out where the + * actual console buffer is. + */ + if ((u32)&cursor < (u32)CONFIG_DCACHE_RAM_BASE) + cbm_cons_p = CBMEM_CONSOLE_REDIRECT; +#endif + if (!cbm_cons_p) + return; + + cursor = cbm_cons_p->buffer_cursor++; + if (cursor < cbm_cons_p->buffer_size) + cbm_cons_p->buffer_body[cursor] = data; +} + +/* + * Copy the current console buffer (either from the cache as RAM area, or from + * the static buffer, pointed at by cbmem_console_p) into the CBMEM console + * buffer space (pointed at by new_cons_p), concatenating the copied data with + * the CBMEM console buffer contents. + * + * If there is overflow - add to the destination area a string, reporting the + * overflow and the number of dropped charactes. + */ +static void copy_console_buffer(struct cbmem_console *new_cons_p) +{ + u32 copy_size; + u32 cursor = new_cons_p->buffer_cursor; + int overflow = cbmem_console_p->buffer_cursor > + cbmem_console_p->buffer_size; + + copy_size = overflow ? + cbmem_console_p->buffer_size : cbmem_console_p->buffer_cursor; + + memcpy(new_cons_p->buffer_body + cursor, + cbmem_console_p->buffer_body, + copy_size); + + cursor += copy_size; + + if (overflow) { + const char loss_str1[] = "\n\n*** Log truncated, "; + const char loss_str2[] = " characters dropped. ***\n\n"; + u32 dropped_chars = cbmem_console_p->buffer_cursor - copy_size; + + /* + * When running from ROM sprintf is not available, a simple + * itoa implementation is used instead. + */ + int got_first_digit = 0; + + /* Way more than possible number of dropped characters. */ + u32 mult = 100000; + + strcpy((char *)new_cons_p->buffer_body + cursor, loss_str1); + cursor += sizeof(loss_str1) - 1; + + while (mult) { + int digit = dropped_chars / mult; + if (got_first_digit || digit) { + new_cons_p->buffer_body[cursor++] = digit + '0'; + dropped_chars %= mult; + /* Excessive, but keeps it simple */ + got_first_digit = 1; + } + mult /= 10; + } + + strcpy((char *)new_cons_p->buffer_body + cursor, loss_str2); + cursor += sizeof(loss_str2) - 1; + } + new_cons_p->buffer_cursor = cursor; +} + +void cbmemc_reinit(void) +{ + struct cbmem_console *cbm_cons_p; + +#ifdef __PRE_RAM__ + cbm_cons_p = cbmem_add(CBMEM_ID_CONSOLE, + CONFIG_CONSOLE_CBMEM_BUFFER_SIZE); + if (!cbm_cons_p) { + CBMEM_CONSOLE_REDIRECT = NULL; + return; + } + + cbm_cons_p->buffer_size = CONFIG_CONSOLE_CBMEM_BUFFER_SIZE - + sizeof(struct cbmem_console); + + cbm_cons_p->buffer_cursor = 0; + + copy_console_buffer(cbm_cons_p); + + CBMEM_CONSOLE_REDIRECT = cbm_cons_p; +#else + cbm_cons_p = cbmem_find(CBMEM_ID_CONSOLE); + + if (!cbm_cons_p) + return; + + copy_console_buffer(cbm_cons_p); + + cbmem_console_p = cbm_cons_p; +#endif +}

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New patch to review for coreboot: b26c9b0 CBMEM CONSOLE: Add config option for CBMEM stored console log.
by Stefan Reinauer March 6, 2012

March 6, 2012

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/718 -gerrit commit b26c9b0c087f14a84b08b62f6f0c2796ac9253d1 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Sep 28 13:51:30 2011 -0700 CBMEM CONSOLE: Add config option for CBMEM stored console log. Some experiments have demonstrated that total amount of text generated by coreboot console when BIOS_SPEW level is enabled exceeds 40KB. Console output generated before DRAM is initialized can exceed 2KB. This patch introduces the new configuration option and assigns adequate default values to cache based and DRAM based console buffers. BUG=chrome-os-partner:4200 TEST=manual . run the following commands in the root directory cp config.stumpy .config make menuconfig . enable the new option (Console->Send console output to a CBMEM buffer) . save the configuration Observe the following settings added to the config: +CONFIG_CONSOLE_CBMEM=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0xae00 +CONFIG_CONSOLE_CAR_BUFFER_SIZE=0xc00 Change-Id: I209603f516244ae136631e6281ba21ebc6fb1710 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Reviewed-on: https://gerrit-int.chromium.org/5855 Tested-by: Vadim Bendebury <vbendeb(a)google.com> Reviewed-by: Stefan Reinauer <reinauer(a)google.com> --- src/console/Kconfig | 27 +++++++++++++++++++++++++++ 1 files changed, 27 insertions(+), 0 deletions(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index dbd11f6..fefbe2e 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -190,6 +190,33 @@ config CONSOLE_NE2K_IO_PORT 32 bytes of IO spaces will be used (and align on 32 bytes boundary, qemu needs broader align) +config CONSOLE_CBMEM + depends on EARLY_CBMEM_INIT + bool "Send console output to a CBMEM buffer" + default n + help + Enable this to save the console output in a CBMEM buffer. This would + allow to see coreboot console output from Linux space. + +config CONSOLE_CBMEM_BUFFER_SIZE + depends on CONSOLE_CBMEM + hex "Room allocated for console output in CBMEM" + default 0xae00 + help + Space allocated for console output storage in CBMEM. The default + value (almost 45K or 0xaeoo bytes) is large enough to accommodate + even the BIOS_SPEW level. + +config CONSOLE_CAR_BUFFER_SIZE + depends on CONSOLE_CBMEM + hex "Room allocated for console output in cash as RAM" + default 0xc00 + help + Console is used before RAM is initialized. This is the room reserved + in the DCACHE based RAM to keep console output before it can be + saved in a CBMEM buffer. 3K bytes should be enough even for the + BIOS_SPEW level. + choice prompt "Maximum console log level"

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New patch to review for coreboot: 56c20fc Add timestamp table pointer to the coreboot table.
by Stefan Reinauer March 6, 2012

March 6, 2012

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/716 -gerrit commit 56c20fcc646838e17e44f2a90c14996315698643 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri Sep 23 09:56:11 2011 -0700 Add timestamp table pointer to the coreboot table. This change exports the timestamp table pointer through coreboot table to make it possible for u-boot to add timestamps to the table. Inclusion of cbmem.h allows to drop external declarations in coreboot_table.c. Change-Id: Ia070198cee7a6ffdaeece03d9d15bd91e033b6d1 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/arch/x86/boot/coreboot_table.c | 25 +++++++++++++++++++++---- src/include/boot/coreboot_tables.h | 8 ++++++++ 2 files changed, 29 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c index b0dcc9e..f189e76 100644 --- a/src/arch/x86/boot/coreboot_table.c +++ b/src/arch/x86/boot/coreboot_table.c @@ -30,6 +30,7 @@ #include <device/device.h> #include <stdlib.h> #include <cbfs.h> +#include <cbmem.h> #if CONFIG_USE_OPTION_TABLE #include <option_table.h> #endif @@ -174,6 +175,23 @@ static void lb_framebuffer(struct lb_header *header) #endif } +#if CONFIG_COLLECT_TIMESTAMPS +static void lb_tsamp(struct lb_header *header) +{ + struct lb_tstamp *tstamp; + void *tstamp_table = cbmem_find(CBMEM_ID_TIMESTAMP); + + if (!tstamp_table) + return; + + tstamp = (struct lb_tstamp *)lb_new_record(header); + tstamp->tag = LB_TAG_TIMESTAMPS; + tstamp->size = sizeof(*tstamp); + tstamp->tstamp_tab = tstamp_table; + +} +#endif + static struct lb_mainboard *lb_mainboard(struct lb_header *header) { struct lb_record *rec; @@ -513,10 +531,6 @@ static void add_lb_reserved(struct lb_memory *mem) lb_add_rsvd_range, mem); } -#if CONFIG_WRITE_HIGH_TABLES -extern uint64_t high_tables_base, high_tables_size; -#endif - unsigned long write_coreboot_table( unsigned long low_table_start, unsigned long low_table_end, unsigned long rom_table_start, unsigned long rom_table_end) @@ -619,6 +633,9 @@ unsigned long write_coreboot_table( /* Record our framebuffer */ lb_framebuffer(head); +#if CONFIG_COLLECT_TIMESTAMPS + lb_tsamp(head); +#endif /* Remember where my valid memory ranges are */ return lb_table_fini(head, 1); diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index 45ba3af..46d6489 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -195,6 +195,14 @@ struct lb_framebuffer { uint8_t reserved_mask_size; }; +#define LB_TAG_TIMESTAMPS 0x0016 +struct lb_tstamp { + uint32_t tag; + uint32_t size; + + void *tstamp_tab; +}; + /* The following structures are for the cmos definitions table */ #define LB_TAG_CMOS_OPTION_TABLE 200 /* cmos header record */

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New patch to review for coreboot: 0739dfa Add cmos helper functions for reading/writing a dword
by Stefan Reinauer March 6, 2012

March 6, 2012

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/717 -gerrit commit 0739dfa33e71e00d87ba9fd107a73d9758c9ebb9 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Sep 26 13:24:40 2011 -0700 Add cmos helper functions for reading/writing a dword These get used later for saving/restoring the MRC scrambler seed values on each boot. Change-Id: I6e23f17649bea6d22c4b279ed8d0e5cb6c0885e7 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/include/pc80/mc146818rtc.h | 16 ++++++++++++++++ 1 files changed, 16 insertions(+), 0 deletions(-) diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index 3e5a61a..24dac2c 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -104,6 +104,22 @@ static inline void cmos_write(unsigned char val, unsigned char addr) outb(addr, RTC_BASE_PORT + offs + 0); outb(val, RTC_BASE_PORT + offs + 1); } + +static inline u32 cmos_read32(u8 offset) +{ + u32 value = 0; + u8 i; + for (i = 0; i < sizeof(value); ++i) + value |= cmos_read(offset + i) << (i << 3); + return value; +} + +static inline void cmos_write32(u8 offset, u32 value) +{ + u8 i; + for (i = 0; i < sizeof(value); ++i) + cmos_write((value >> (i << 3)) & 0xff, offset + i); +} #endif #if !defined(__ROMCC__)

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New patch to review for coreboot: 2d9ed13 Don't run VGA option ROMs on S3 resume.
by Stefan Reinauer March 6, 2012

March 6, 2012

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/715 -gerrit commit 2d9ed13c22a4a37b4ef9f30c9e9b1136dff2a9ee Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Sep 23 10:33:58 2011 -0700 Don't run VGA option ROMs on S3 resume. This will save us a few 100 ms on resume. Change-Id: Iabf4c8ab88662ba41236162f0a6f5bd80d8c1255 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/devices/Kconfig | 7 +++++++ src/devices/pci_device.c | 11 +++++++++++ 2 files changed, 18 insertions(+), 0 deletions(-) diff --git a/src/devices/Kconfig b/src/devices/Kconfig index 9e5ea6e..572addc 100644 --- a/src/devices/Kconfig +++ b/src/devices/Kconfig @@ -33,6 +33,13 @@ config VGA_ROM_RUN Execute VGA option ROMs, if found. This is required to enable PCI/AGP/PCI-E video cards. +config S3_VGA_ROM_RUN + bool "Re-run VGA option ROMs on S3 resume" + default y + depends on VGA_ROM_RUN && HAVE_ACPI_RESUME + help + Execute VGA option ROMs when coming out of an S3 resume. + config PCI_ROM_RUN bool "Run non-VGA option ROMs" default y diff --git a/src/devices/pci_device.c b/src/devices/pci_device.c index 2ccb38a..1f36679 100644 --- a/src/devices/pci_device.c +++ b/src/devices/pci_device.c @@ -51,6 +51,9 @@ #if CONFIG_PC80_SYSTEM == 1 #include <pc80/i8259.h> #endif +#if CONFIG_HAVE_ACPI_RESUME && !CONFIG_S3_VGA_ROM_RUN +#include <arch/acpi.h> +#endif u8 pci_moving_config8(struct device *dev, unsigned int reg) { @@ -672,6 +675,14 @@ void pci_dev_init(struct device *dev) if (ram == NULL) return; +#if !CONFIG_S3_VGA_ROM_RUN + /* If S3_VGA_ROM_RUN is disabled, skip running VGA option + * ROMs when coming out of an S3 resume. + */ + if ((acpi_slp_type == 3) && + ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)) + return; +#endif run_bios(dev, (unsigned long)ram); #endif /* CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN */ }

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New patch to review for coreboot: 6135be8 Add a config flag to enable time stamp collection.
by Stefan Reinauer March 6, 2012

March 6, 2012

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/712 -gerrit commit 6135be8c41d82ee84c6417c901f42b60ec6bec59 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Sep 21 14:46:43 2011 -0700 Add a config flag to enable time stamp collection. Add a new flag, make it dependent on EARLY_CBMEM_INIT Change-Id: Idbebcaf298238f31a73e9eb4a9af7b03e857bc74 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/Kconfig | 15 +++++++++++++++ 1 files changed, 15 insertions(+), 0 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 544b61b..573868f 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -112,6 +112,14 @@ config INCLUDE_CONFIG_FILE help Include in CBFS the coreboot config file that was used to compile the ROM image +config FDT_FILE_NAME + depends on ADD_FDT + string "Name of the CBFS file containing the compiled FDT" + default "u-boot.dtb" + help + Name of the CBFS file containing the binary representation of the + device tree to be optionally modified and passed to the payload. + config EARLY_CBMEM_INIT bool "Initialize CBMEM while in ROM stage" default n @@ -120,6 +128,13 @@ config EARLY_CBMEM_INIT stage. This could be useful when the rom stage wants to communicate some, for instance, execution timestamps. +config COLLECT_TIMESTAMPS + bool "Create a table of timestamps collected during boot" + depends on EARLY_CBMEM_INIT + help + Make coreboot create a table of timer id/timer value pairs to + allow measuring time spent at different phases of the boot + process. endmenu source src/mainboard/Kconfig

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New patch to review for coreboot: 4030efb Add timestamp collecting to coreboot.
by Stefan Reinauer March 6, 2012

March 6, 2012

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/713 -gerrit commit 4030efb3234d9f40543fea820d19c76438aad0c2 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Sep 21 16:12:39 2011 -0700 Add timestamp collecting to coreboot. This patch adds code to initialize the time stamp collection facility in coreboot. It adds a table in the CBMEM section, which provides the base timer reading value (all other readings are offsets of this one) and an array of timestamp id/timestamp value pairs. Just two values are being added now, this will have to be used more extensively and also integrated into payloads to provide more comprehensive boot process time measurements. Also, since the CBMEM area could already contain a section (from the previous run, before reset), when processing a section addition request we should check if a section already exists and return its address, if so. Change-Id: I7ed9f5c400bc5432f228348b41fd19a67c36d533 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/include/cbmem.h | 1 + src/include/timestamp.h | 46 +++++++++++++++++++++++++++++ src/lib/Makefile.inc | 2 + src/lib/cbmem.c | 17 +++++++++++ src/lib/timestamp.c | 74 +++++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 140 insertions(+), 0 deletions(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index a681c36..c3f10ef 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -41,6 +41,7 @@ extern uint64_t high_tables_base, high_tables_size; #define CBMEM_ID_MPTABLE 0x534d5054 #define CBMEM_ID_RESUME 0x5245534d #define CBMEM_ID_SMBIOS 0x534d4254 +#define CBMEM_ID_TIMESTAMP 0x54494d45 #define CBMEM_ID_NONE 0x00000000 int cbmem_initialize(void); diff --git a/src/include/timestamp.h b/src/include/timestamp.h new file mode 100644 index 0000000..cfa06e2 --- /dev/null +++ b/src/include/timestamp.h @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#ifndef __TIMESTAMP_H__ +#define __TIMESTAMP_H__ + +#include <cpu/x86/tsc.h> + +struct timestamp_entry { + uint32_t entry_id; + uint64_t entry_stamp; +} __attribute__((packed)); + +struct timestamp_table { + uint64_t base_time; + uint32_t max_entries; + uint32_t num_entries; + struct timestamp_entry entries[0]; /* Variable number of entries */ +} __attribute__((packed)); + +enum timestamp_id { + TS_BEFORE_INITRAM = 1, + TS_AFTER_INITRAM = 2, +}; + +void timestamp_init(tsc_t base); +void timestamp_add(enum timestamp_id id, tsc_t ts_time); +void timestamp_add_now(enum timestamp_id id); + +#endif diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index e0e5e75..db640dc 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -14,6 +14,7 @@ romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c romstage-$(CONFIG_CONSOLE_NE2K) += compute_ip_checksum.c romstage-$(CONFIG_USBDEBUG) += usbdebug.c +romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c ramstage-y += memset.c ramstage-y += memchr.c @@ -36,6 +37,7 @@ ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c ramstage-$(CONFIG_USBDEBUG) += usbdebug.c ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c ramstage-$(CONFIG_TRACE) += trace.c +ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c driver-$(CONFIG_CONSOLE_NE2K) += ne2k.c diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index f5c3d3a..6597840 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -118,6 +118,22 @@ void *cbmem_add(u32 id, u64 size) { struct cbmem_entry *cbmem_toc; int i; + void *p; + + /* + * This could be a restart, check if the section is there already. It + * is remotely possible that the dram contents persisted over the + * bootloader upgrade AND the same section now needs more room, but + * this is quite a remote possibility and it is ignored here. + */ + p = cbmem_find(id); + if (p) { + printk(BIOS_NOTICE, + "CBMEM section %x: using existing location at %p.\n", + id, p); + return p; + } + cbmem_toc = get_cbmem_toc(); if (cbmem_toc == NULL) { @@ -240,6 +256,7 @@ void cbmem_list(void) case CBMEM_ID_MPTABLE: printk(BIOS_DEBUG, "SMP TABLE "); break; case CBMEM_ID_RESUME: printk(BIOS_DEBUG, "ACPI RESUME"); break; case CBMEM_ID_SMBIOS: printk(BIOS_DEBUG, "SMBIOS "); break; + case CBMEM_ID_TIMESTAMP: printk(BIOS_DEBUG, "TIME STAMP "); break; default: printk(BIOS_DEBUG, "%08x ", cbmem_toc[i].id); } printk(BIOS_DEBUG, "%08llx ", cbmem_toc[i].base); diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c new file mode 100644 index 0000000..bbb8197d --- /dev/null +++ b/src/lib/timestamp.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#include <stdint.h> +#include <console/console.h> +#include <cbmem.h> +#include <timestamp.h> + +#define MAX_TIMESTAMPS 30 + +#ifndef __PRE_RAM__ +static struct timestamp_table* ts_table; +#endif + +static uint64_t tsc_to_uint64(tsc_t tstamp) +{ + return (((uint64_t)tstamp.hi) << 32) + tstamp.lo; +} + +void timestamp_init(tsc_t base) +{ + struct timestamp_table* tst; + + tst = cbmem_add(CBMEM_ID_TIMESTAMP, + sizeof(struct timestamp_table) + + MAX_TIMESTAMPS * sizeof(struct timestamp_entry)); + + if (!tst) { + printk(BIOS_ERR, "ERROR: failed to allocate timstamp table\n"); + return; + } + + tst->base_time = tsc_to_uint64(base); + tst->max_entries = MAX_TIMESTAMPS; + tst->num_entries = 0; +} + +void timestamp_add(enum timestamp_id id, tsc_t ts_time) +{ + struct timestamp_entry *tse; +#ifdef __PRE_RAM__ + struct timestamp_table *ts_table = cbmem_find(CBMEM_ID_TIMESTAMP); +#else + if (!ts_table) + ts_table = cbmem_find(CBMEM_ID_TIMESTAMP); +#endif + if (!ts_table || (ts_table->num_entries == ts_table->max_entries)) + return; + + tse = &ts_table->entries[ts_table->num_entries++]; + tse->entry_id = id; + tse->entry_stamp = tsc_to_uint64(ts_time) - ts_table->base_time; +} + +void timestamp_add_now(enum timestamp_id id) +{ + timestamp_add(id, rdtsc()); +}

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New patch to review for coreboot: 484acec Include arch/acpi.h instead of manually adding acpi_slp_type.
by Stefan Reinauer March 6, 2012

March 6, 2012

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/714 -gerrit commit 484acec01d2b55a648cf810ae37a8f405b529ba6 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Sep 23 10:24:49 2011 -0700 Include arch/acpi.h instead of manually adding acpi_slp_type. acpi_slp_type is defined in arch/acpi.h, so let's use that instead of manually spreading extern u8 acpi_slp_type throughout the code. Change-Id: Ia5eb420364c15ab5a764bc328bbd201ca9cb7837 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/lib/cbmem.c | 7 +++---- 1 files changed, 3 insertions(+), 4 deletions(-) diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 6597840..f800b04 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -21,6 +21,9 @@ #include <string.h> #include <cbmem.h> #include <console/console.h> +#if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) +#include <arch/acpi.h> +#endif // The CBMEM TOC reserves 512 bytes to keep // the other entries somewhat aligned. @@ -199,10 +202,6 @@ void *cbmem_find(u32 id) return (void *)NULL; } -#if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) -extern u8 acpi_slp_type; -#endif - #if CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__) /* Returns True if it was not intialized before. */ int cbmem_initialize(void)

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Patch set updated for coreboot: 8689912 Add helper function to find a Local APIC by ID in the device tree.
by Stefan Reinauer March 5, 2012

March 5, 2012

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/695 -gerrit commit 86899127de3f98718453192a15bd0344d90063f6 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jul 18 10:41:36 2011 -0700 Add helper function to find a Local APIC by ID in the device tree. Change-Id: Ie2d7d8e1f647a0c92d2de09e32454fbea688b1e7 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/devices/device_util.c | 20 ++++++++++++++++++++ src/include/device/device.h | 1 + 2 files changed, 21 insertions(+), 0 deletions(-) diff --git a/src/devices/device_util.c b/src/devices/device_util.c index 84fb115..5b182e1 100644 --- a/src/devices/device_util.c +++ b/src/devices/device_util.c @@ -110,6 +110,26 @@ struct device *dev_find_slot_on_smbus(unsigned int bus, unsigned int addr) } /** + * Given a Local APIC ID, find the device structure. + * + * @param apic_id The Local APIC ID number. + * @return Pointer to the device structure (if found), 0 otherwise. + */ +device_t dev_find_lapic(unsigned apic_id) +{ + device_t dev, result = NULL; + + for (dev = all_devices; dev; dev = dev->next) { + if (dev->path.type == DEVICE_PATH_APIC && + dev->path.apic.apic_id == apic_id) { + result = dev; + break; + } + } + return result; +} + +/** * Find a device of a given vendor and type. * * @param vendor A PCI vendor ID (e.g. 0x8086 for Intel). diff --git a/src/include/device/device.h b/src/include/device/device.h index a7de0c9..c097f57 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -132,6 +132,7 @@ device_t dev_find_device (u16 vendor, u16 device, device_t from); device_t dev_find_class (unsigned int class, device_t from); device_t dev_find_slot (unsigned int bus, unsigned int devfn); device_t dev_find_slot_on_smbus (unsigned int bus, unsigned int addr); +device_t dev_find_lapic(unsigned apic_id); /* Debug functions */ void print_resource_tree(struct device * root, int debug_level,

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