coreboot March 2012

coreboot@coreboot.org

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718 discussions

Patch set updated for coreboot: 5405656 Don't try to compute I/O for empty sub buses.
by Stefan Reinauer 05 Mar '12

05 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/693 -gerrit commit 540565641844bdc3e6fae44a73ce05b9bd0e9d07 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed May 11 15:57:07 2011 -0700 Don't try to compute I/O for empty sub buses. I am not sure if the sub bus being 0 is a problem, or if the assumption there has to be at least one non empty link is just wrong. It certainly does not hurt to add a small consistency check in either case. Change-Id: I098446deef96a8baae26a7ca1ddd96e626a06dc5 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/devices/device_util.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/src/devices/device_util.c b/src/devices/device_util.c index 9081a36..84fb115 100644 --- a/src/devices/device_util.c +++ b/src/devices/device_util.c @@ -583,6 +583,8 @@ void search_bus_resources(struct bus *bus, unsigned long type_mask, if (subbus->link_num == IOINDEX_SUBTRACTIVE_LINK(res->index)) break; + if (!subbus) /* Why can subbus be NULL? */ + break; search_bus_resources(subbus, type_mask, type, search, gp); continue;

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Trac reminder: list of new ticket(s)
by coreboot tracker 05 Mar '12

05 Mar '12

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Linux-ready Firmware Kit
by Fred . 03 Mar '12

03 Mar '12

# yum install pmtools # acpidump > acpi.dump # acpixtract -l acpi.dump # dmidecode Intel provides a Linux-ready Firmware Kit, available on a LiveCD (79 MB) ( http://linuxfirmwarekit.org/download/firmwarekit-r3.iso ). You only have to launch it, wait 1 or 2 minutes, and there is a summary of the results based on different topics (memory handling, PCI resources, HPET, ACPI tables, and more). The results is a number of "Fail", "Warn" and "Pass" flags. This Linux-ready Firmware Kit seems to not be developed anymore, but I guess it can give us a idea of the quality of the BIOS.

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New patch to review for coreboot: 7c48e07 Revert "Use -mno-sse to prevent overzealous gcc optimizations"
by Patrick Georgi 03 Mar '12

03 Mar '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/706 -gerrit commit 7c48e07a261eafda2119354d282bd05eac5a14b6 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Mar 3 10:46:26 2012 +0100 Revert "Use -mno-sse to prevent overzealous gcc optimizations" AGESA uses SSE intrinsics :-( This reverts commit 05f4b03fb64999ba373fe61256f358e5371bf8ae --- util/xcompile/xcompile | 4 ---- 1 files changed, 0 insertions(+), 4 deletions(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index f5d43d0..4926394 100644 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -84,10 +84,6 @@ testcc "$CC" "$CFLAGS-Wl,--build-id=none " && CFLAGS="$CFLAGS-Wl,--build-id=none # now: testcc "$CC" "$CFLAGS-Wno-unused-but-set-variable " && \ CFLAGS="$CFLAGS-Wno-unused-but-set-variable " -# Use bfd linker instead of gold if available: -testcc "$CC" "$CFLAGS-fuse-ld=bfd " && CFLAGS="$CFLAGS-fuse-ld=bfd " && LINKER_SUFFIX='.bfd' -# Prevent SSE instructions sneaking in: -testcc "$CC" "$CFLAGS-mno-sse " && CFLAGS="$CFLAGS-mno-sse " if which gcc 2>/dev/null >/dev/null; then HOSTCC=gcc

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Patch merged into coreboot/master: 05f4b03 Use -mno-sse to prevent overzealous gcc optimizations
by gerrit＠coreboot.org 03 Mar '12

03 Mar '12

the following patch was just integrated into master: commit 05f4b03fb64999ba373fe61256f358e5371bf8ae Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jun 23 17:12:08 2011 -0700 Use -mno-sse to prevent overzealous gcc optimizations The offending part that made coreboot crash with some toolchains was that gcc emits SSE instructions but coreboot did not enable SSE at that point. Since the gain for coreboot using SSE instructions is not measurable, let's not use SSE instructions rather than enabling SSE early on. One rationale behind this is that other parts of coreboot, like the SMM handler would need fixing because the XMM registers are not saved on SMM entry. Thus keep it simple. Change-Id: I14f0942f300085767ece44cec570fb15c761e88d Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Sat Mar 3 09:15:10 2012, giving +2 See http://review.coreboot.org/694 for details. -gerrit

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Patch merged into coreboot/master: 15e268e Fix ECC disable option for AMD Fam10 DDR2 and DDR3.
by gerrit＠coreboot.org 02 Mar '12

02 Mar '12

the following patch was just integrated into master: commit 15e268ee435d7d6f8d76997336efb38c4732042e Author: Marc Jones <marc.jones(a)se-eng.com> Date: Tue Feb 21 17:06:40 2012 -0700 Fix ECC disable option for AMD Fam10 DDR2 and DDR3. The logic was backwards on the ECC enable/disable option. Also added better debug output when the debug RAM init feature is enabled. Change-Id: I60bffb6149d96cac65011247ef51cd06ed2210c6 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Build-Tested: build bot (Jenkins) at Wed Feb 22 02:31:23 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Thu Mar 1 18:18:12 2012, giving +2 See http://review.coreboot.org/670 for details. -gerrit

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Patch set updated for coreboot: 76db020 Update xcompile to search for x86_64 toolchain.
by Marc Jones 02 Mar '12

02 Mar '12

Marc Jones (marcj303(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/673 -gerrit commit 76db020f22bbe48c3cc78fd4ec5f8b77c66ceed6 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Wed Feb 22 11:46:17 2012 -0700 Update xcompile to search for x86_64 toolchain. This adds detection of x86_64 gcc toolchain (which buildgcc can build if provided the option). Change-Id: I8b12f3e705157741279c7347f4847fb50ccc2b0e Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- util/xcompile/xcompile | 17 +++++++++++------ 1 files changed, 11 insertions(+), 6 deletions(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 4926394..3930460 100644 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -36,14 +36,19 @@ done GCCPREFIX=invalid XGCCPATH=${1:-"`pwd`/util/crossgcc/xgcc/bin/"} -echo '#XGCCPATH='${XGCCPATH} +echo '# XGCCPATH='${XGCCPATH} TMPFILE=`mktemp /tmp/temp.XXXX 2>/dev/null || echo /tmp/temp.78gOIUGz` touch $TMPFILE -# This should be a loop over all supported architectures -TARCH=i386 +# This loops over all supported architectures in TARCH +TARCH=('i386' 'x86_64') TWIDTH=32 -for gccprefixes in ${XGCCPATH}${TARCH}-elf- ${TARCH}-elf- ""; do +for search_for in "${TARCH[@]}"; do + TARCH_SEARCH=("${TARCH_SEARCH[@]}" ${XGCCPATH}${search_for}-elf- ${search_for}-elf-) +done +echo '# TARCH_SEARCH='${TARCH_SEARCH[@]} + +for gccprefixes in "${TARCH_SEARCH[@]}" ""; do if ! which ${gccprefixes}as 2>/dev/null >/dev/null; then continue fi @@ -63,8 +68,8 @@ for gccprefixes in ${XGCCPATH}${TARCH}-elf- ${TARCH}-elf- ""; do if [ ${TYPE##* } == "elf${TWIDTH}-${TARCH}" ]; then GCCPREFIX=$gccprefixes ASFLAGS=--32 - CFLAGS="-m32 " - LDFLAGS="-b elf32-i386" + CFLAGS="-m32 -Wl,-b,elf32-i386 -Wl,-melf_i386 " + LDFLAGS="-b elf32-i386 -melf_i386" break fi fi

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New patch to review for coreboot: 37a6cac Make libpaylod alloc() memory pointers volatile
by Marc Jones 02 Mar '12

02 Mar '12

Marc Jones (marcj303(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/705 -gerrit commit 37a6cacf4e04d0ee9e75f1b1c7ea307d750623c6 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Thu Mar 1 16:12:11 2012 -0700 Make libpaylod alloc() memory pointers volatile gcc4.6.2 was optimizing the libpayload alloc() function and failing to reload a pointer after the memory had been manipulated by a pointer in the inlined function setup(). I changes the pointer type to volatile and now pass it to the setup() function. I also cleaned up the declaration so that it isn't cast a bunch times in the function. Change-Id: I1637bd7bd5d9cf82ac88925cbfe76d319aa3cd82 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- payloads/libpayload/libc/malloc.c | 25 +++++++++++-------------- 1 files changed, 11 insertions(+), 14 deletions(-) diff --git a/payloads/libpayload/libc/malloc.c b/payloads/libpayload/libc/malloc.c index 6389fc9..9412cab 100644 --- a/payloads/libpayload/libc/malloc.c +++ b/payloads/libpayload/libc/malloc.c @@ -73,11 +73,9 @@ static int heap_initialized = 0; static int minimal_free = 0; #endif -static void setup(void) +static void setup(hdrtype_t volatile *start, int size) { - int size = (unsigned int)(&_eheap - &_heap) - HDRSIZE; - - *((hdrtype_t *) hstart) = FREE_BLOCK(size); + *start = FREE_BLOCK(size); #ifdef CONFIG_DEBUG_MALLOC heap_initialized = 1; @@ -88,7 +86,7 @@ static void setup(void) static void *alloc(int len) { hdrtype_t header; - void *ptr = hstart; + hdrtype_t volatile *ptr = (hdrtype_t volatile *) hstart; /* Align the size. */ len = (len + 3) & ~3; @@ -97,12 +95,12 @@ static void *alloc(int len) return (void *)NULL; /* Make sure the region is setup correctly. */ - if (!HAS_MAGIC(*((hdrtype_t *) ptr))) - setup(); + if (!HAS_MAGIC(*ptr)) + setup(ptr, len); /* Find some free space. */ do { - header = *((hdrtype_t *) ptr); + header = *ptr; int size = SIZE(header); if (!HAS_MAGIC(header) || size == 0) { @@ -114,7 +112,7 @@ static void *alloc(int len) if (header & FLAG_FREE) { if (len <= size) { - void *nptr = ptr + (HDRSIZE + len); + hdrtype_t volatile *nptr = ptr + (HDRSIZE + len); int nsize = size - (HDRSIZE + len); /* If there is still room in this block, @@ -124,14 +122,13 @@ static void *alloc(int len) if (nsize > 0) { /* Mark the block as used. */ - *((hdrtype_t *) ptr) = USED_BLOCK(len); + *ptr = USED_BLOCK(len); /* Create a new free block. */ - *((hdrtype_t *) nptr) = - FREE_BLOCK(nsize); + *nptr = FREE_BLOCK(nsize); } else { /* Mark the block as used. */ - *((hdrtype_t *) ptr) = USED_BLOCK(size); + *ptr = USED_BLOCK(size); } return (void *)(ptr + HDRSIZE); @@ -140,7 +137,7 @@ static void *alloc(int len) ptr += HDRSIZE + size; - } while (ptr < hend); + } while (ptr < (hdrtype_t *) hend); /* Nothing available. */ return (void *)NULL;

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New patch to review for coreboot: 0e9052f Increase size of the coreboot table area
by Stefan Reinauer 02 Mar '12

02 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/704 -gerrit commit 0e9052fc533f174373fb3b7ad7d2aa23f374f61b Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Sun Aug 14 13:52:03 2011 -0700 Increase size of the coreboot table area Packing a device tree into the coreboot table can easily make the table exceed the current limit of 8KB. However, right now there is no error handling in place to catch that case. Increase the maximum memory usable for all tables from 64KB to 128KB and increase the maximum coreboot table size from 8KB to 32KB. Change-Id: I2025bf070d0adb276c1cd610aa8402b50bdf2525 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/boot/tables.c | 2 +- src/include/cbmem.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index 29d2ec0..b7dc4fe 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -202,7 +202,7 @@ struct lb_memory *write_tables(void) } #endif -#define MAX_COREBOOT_TABLE_SIZE (8 * 1024) +#define MAX_COREBOOT_TABLE_SIZE (32 * 1024) post_code(0x9d); high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE, MAX_COREBOOT_TABLE_SIZE); diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 7c5ec07..9806854 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -20,8 +20,8 @@ #ifndef _CBMEM_H_ #define _CBMEM_H_ -/* Reserve 64k for ACPI and other tables */ -#define HIGH_MEMORY_DEF_SIZE ( 64 * 1024 ) +/* Reserve 128k for ACPI and other tables */ +#define HIGH_MEMORY_DEF_SIZE ( 128 * 1024 ) extern uint64_t high_tables_base, high_tables_size; #if CONFIG_HAVE_ACPI_RESUME

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New patch to review for coreboot: 75f77f5 Fix coreboot table size calculations.
by Stefan Reinauer 02 Mar '12

02 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/703 -gerrit commit 75f77f5ea36ca5f9f6ee2c3abc93eef3c8616268 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Aug 16 11:44:35 2011 -0700 Fix coreboot table size calculations. The code when reporting the coreboot table size did not account for the last added table record. This change fixes the problem. . rebuild coreboot, program it on the target, restart it . look for 'Wrote coreboot table at:' in the console log . observe the adequate table size reported $ grep 'Wrote coreboot table:' /tmp/cb.log Wrote coreboot table at: 00000500, 0x10 bytes, checksum c06f Wrote coreboot table at: 7f6fc000, 0x1a73 bytes, checksum 3e45 $ Change-Id: Ic55501a4ae06fab2bcda9aea58e362325f2edccf Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/arch/x86/boot/coreboot_table.c | 7 ++++--- 1 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c index ba1e358..b463409 100644 --- a/src/arch/x86/boot/coreboot_table.c +++ b/src/arch/x86/boot/coreboot_table.c @@ -352,9 +352,10 @@ static unsigned long lb_table_fini(struct lb_header *head, int fixup) head->table_checksum = compute_ip_checksum(first_rec, head->table_bytes); head->header_checksum = 0; head->header_checksum = compute_ip_checksum(head, sizeof(*head)); - printk(BIOS_DEBUG, "Wrote coreboot table at: %p - %p checksum %x\n", - head, rec, head->table_checksum); - return (unsigned long)rec; + printk(BIOS_DEBUG, + "Wrote coreboot table at: %p, 0x%x bytes, checksum %x\n", + head, head->table_bytes, head->table_checksum); + return (unsigned long)rec + rec->size; } static void lb_cleanup_memory_ranges(struct lb_memory *mem)

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coreboot March 2012