coreboot January 2012

coreboot@coreboot.org

40 participants
302 discussions

Patch set updated for coreboot: 2ba6d09 Add rules to pull down and uncompress gpl_vsa_lx_102.bin
by Philip Prindeville 06 Jan '12

06 Jan '12

Philip Prindeville (pprindeville(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/509 -gerrit commit 2ba6d099f1f808c4592ff273d14c0de414fe1d61 Author: Philip Prindeville <philipp(a)redfish-solutions.com> Date: Thu Dec 29 12:21:39 2011 -0700 Add rules to pull down and uncompress gpl_vsa_lx_102.bin These steps are in the Wiki, but they should be automated. Change-Id: I81528dddb47b0cfe4acd33456680f8d3211fabd7 Signed-off-by: Philip Prindeville <philipp(a)redfish-solutions.com> --- src/arch/x86/Makefile.inc | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 7bba44e..a95fd62 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -396,3 +396,8 @@ filo: CONFIG_FILO_MASTER=$(CONFIG_FILO_MASTER) \ CONFIG_FILO_STABLE=$(CONFIG_FILO_STABLE) +gpl_vsa_lx_102.bin.gz: + @wget -q http://marcjonesconsulting.com/gplvsa/gpl_vsa_lx_102.bin.gz + +gpl_vsa_lx_102.bin: gpl_vsa_lx_102.bin.gz + @gunzip $^

1 0

New patch to review for coreboot: 7f5fb24 alix2: add support for alix6
by Philip Prindeville 06 Jan '12

06 Jan '12

Philip Prindeville (pprindeville(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/521 -gerrit commit 7f5fb249802c8b4f7f26e9ef3869f14e83bba68b Author: Philip Prindeville <philipp(a)redfish-solutions.com> Date: Fri Jan 6 11:54:23 2012 -0700 alix2: add support for alix6 The Alix6 is very similar to the alix2, differing in having 1 mini-PCIe slot (USB 2.0 only), an RFKILL GPIO line going to that slot, and 1 or 2 SIM sockets. Change-Id: I19e4e756966e60bb0310c19286654d3d579b8850 Signed-off-by: Philip Prindeville <philipp(a)redfish-solutions.com> --- src/mainboard/pcengines/Kconfig | 2 ++ src/mainboard/pcengines/alix2d/Kconfig | 9 ++++++--- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/src/mainboard/pcengines/Kconfig b/src/mainboard/pcengines/Kconfig index d5d7008..d8a0201 100644 --- a/src/mainboard/pcengines/Kconfig +++ b/src/mainboard/pcengines/Kconfig @@ -7,6 +7,8 @@ config BOARD_PCENGINES_ALIX1C bool "ALIX.1C" config BOARD_PCENGINES_ALIX2D bool "ALIX.2D2 or 2D3" +config BOARD_PCENGINES_ALIX6 + bool "ALIX.6" endchoice diff --git a/src/mainboard/pcengines/alix2d/Kconfig b/src/mainboard/pcengines/alix2d/Kconfig index ea02adf..5036dcb 100644 --- a/src/mainboard/pcengines/alix2d/Kconfig +++ b/src/mainboard/pcengines/alix2d/Kconfig @@ -1,4 +1,4 @@ -if BOARD_PCENGINES_ALIX2D +if BOARD_PCENGINES_ALIX2D || BOARD_PCENGINES_ALIX6 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -12,6 +12,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_512 select POWER_BUTTON_FORCE_DISABLE select CONSOLE_SERIAL_38400 + select GEODE_VSA + select GEODE_VSA_FILE config MAINBOARD_DIR string @@ -19,10 +21,11 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER string - default "ALIX.2D" + default "ALIX.2D" if BOARD_PCENGINES_ALIX2D + default "ALIX.6" if BOARD_PCENGINES_ALIX6 config IRQ_SLOT_COUNT int default 7 -endif # BOARD_PCENGINES_ALIX2D +endif # BOARD_PCENGINES_ALIX2D || BOARD_PCENGINES_ALIX6

1 0

Patch set updated for coreboot: b731758 Set default baudrate on Alix2d to be compatible with factory default
by Philip Prindeville 06 Jan '12

06 Jan '12

Philip Prindeville (pprindeville(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/508 -gerrit commit b731758d195f1e0174afb77d6a310ebd91768fc5 Author: Philip Prindeville <philipp(a)redfish-solutions.com> Date: Wed Dec 28 16:32:44 2011 -0700 Set default baudrate on Alix2d to be compatible with factory default Boards shipping from PC Engines with the factory BIOS (tinyBios 0.99) boot up at 38400. In keeping with the principle of least astonishment, boards reflashed with SeaBIOS should probably try to keep compatible with this setting. Change-Id: Ieda47016c78e673ce2f6aec8b270c2b511ebfcf0 Signed-off-by: Philip Prindeville <philipp(a)redfish-solutions.com> --- src/mainboard/pcengines/alix2d/Kconfig | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/mainboard/pcengines/alix2d/Kconfig b/src/mainboard/pcengines/alix2d/Kconfig index 264f5d9..ea02adf 100644 --- a/src/mainboard/pcengines/alix2d/Kconfig +++ b/src/mainboard/pcengines/alix2d/Kconfig @@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select UDELAY_TSC select BOARD_ROMSIZE_KB_512 select POWER_BUTTON_FORCE_DISABLE + select CONSOLE_SERIAL_38400 config MAINBOARD_DIR string

1 0

New patch to review for coreboot: c3dc279 geos: missing Vendor information
by Philip Prindeville 06 Jan '12

06 Jan '12

Philip Prindeville (pprindeville(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/520 -gerrit commit c3dc279f497fe87af38b1efb4cc1ebf878264d9b Author: Philip Prindeville <philipp(a)redfish-solutions.com> Date: Fri Jan 6 11:52:25 2012 -0700 geos: missing Vendor information The DMI information isn't being generated correctly because of the mainboard vendor value not being set. Change-Id: I07a6620bc6938292fecd50dc3ff0cb926d9c5f97 Signed-off-by: Philip Prindeville <philipp(a)redfish-solutions.com> --- src/mainboard/traverse/geos/Kconfig | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/src/mainboard/traverse/geos/Kconfig b/src/mainboard/traverse/geos/Kconfig index b455f60..5f00230 100644 --- a/src/mainboard/traverse/geos/Kconfig +++ b/src/mainboard/traverse/geos/Kconfig @@ -17,6 +17,10 @@ config MAINBOARD_DIR string default traverse/geos +config MAINBOARD_VENDOR + string + default "PC Engines" + config MAINBOARD_PART_NUMBER string default "Geos"

1 0

Patch set updated for coreboot: dd391db Cleanup access to vendor/part # info
by Philip Prindeville 06 Jan '12

06 Jan '12

Philip Prindeville (pprindeville(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/502 -gerrit commit dd391db0f9c89c83ff8e57950765430d89cd8feb Author: Philip Prindeville <philipp(a)redfish-solutions.com> Date: Sat Dec 24 22:12:37 2011 -0700 Cleanup access to vendor/part # info Instead of macros to access MAINBOARD record, use convenience functions. Store pointers to MAINBOARD and HEADER for use outside of CB code. Change-Id: I074e3a0df7d25726cbd942538bfdc5a63dd17e12 Signed-off-by: Philip Prindeville <philipp(a)redfish-solutions.com> --- payloads/coreinfo/coreboot_module.c | 4 ++-- payloads/libpayload/arch/i386/coreboot.c | 5 +++++ payloads/libpayload/include/coreboot_tables.h | 16 ++++++++++------ payloads/libpayload/include/sysinfo.h | 3 +++ 4 files changed, 20 insertions(+), 8 deletions(-) diff --git a/payloads/coreinfo/coreboot_module.c b/payloads/coreinfo/coreboot_module.c index 7289366..d33ea9e 100644 --- a/payloads/coreinfo/coreboot_module.c +++ b/payloads/coreinfo/coreboot_module.c @@ -142,8 +142,8 @@ static void parse_mainboard(unsigned char *ptr) { struct cb_mainboard *mb = (struct cb_mainboard *)ptr; - strncpy(cb_info.vendor, (const char *)MB_VENDOR_STRING(mb), 31); - strncpy(cb_info.part, (const char *)MB_PART_STRING(mb), 31); + strncpy(cb_info.vendor, cb_mb_vendor_part(mb), 31); + strncpy(cb_info.part, cb_mb_part_string(mb), 31); } static void parse_strings(unsigned char *ptr) diff --git a/payloads/libpayload/arch/i386/coreboot.c b/payloads/libpayload/arch/i386/coreboot.c index 135c59c..7fe286e 100644 --- a/payloads/libpayload/arch/i386/coreboot.c +++ b/payloads/libpayload/arch/i386/coreboot.c @@ -137,6 +137,8 @@ static int cb_parse_header(void *addr, void *end, struct sysinfo_t *info) header->table_bytes) != header->table_checksum) return -1; + info->header = header; + /* Now, walk the tables. */ ptr += header->header_bytes; @@ -173,6 +175,9 @@ static int cb_parse_header(void *addr, void *end, struct sysinfo_t *info) cb_parse_framebuffer(ptr, info); break; #endif + case CB_TAG_MAINBOARD: + info->mainboard = (struct cb_mainboard *)ptr; + break; } ptr += rec->size; diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index e362d06..c68ccc9 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -228,6 +228,16 @@ static inline u16 cb_checksum(const void *ptr, unsigned len) return ipchksum(ptr, len); } +static inline const char *cb_mb_vendor_string(const struct cb_mainboard *cbm) +{ + return (char *)(cbm->strings + cbm->vendor_idx); +} + +static inline const char *cb_mb_part_string(const struct cb_mainboard *cbm) +{ + return (char *)(cbm->strings + cbm->part_number_idx); +} + /* Helpful macros */ #define MEM_RANGE_COUNT(_rec) \ @@ -237,10 +247,4 @@ static inline u16 cb_checksum(const void *ptr, unsigned len) (void *)(((u8 *) (_rec)) + sizeof(*(_rec)) \ + (sizeof((_rec)->map[0]) * (_idx))) -#define MB_VENDOR_STRING(_mb) \ - (((unsigned char *) ((_mb)->strings)) + (_mb)->vendor_idx) - -#define MB_PART_STRING(_mb) \ - (((unsigned char *) ((_mb)->strings)) + (_mb)->part_number_idx) - #endif diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index c1d2002..778dfe9 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -56,6 +56,9 @@ struct sysinfo_t { struct cb_framebuffer *framebuffer; unsigned long *mbtable; /** Pointer to the multiboot table */ + + struct cb_header *header; + struct cb_mainboard *mainboard; }; extern struct sysinfo_t lib_sysinfo;

1 0

Re: [coreboot] tiny bootblock problem
by Philip Prindeville 06 Jan '12

06 Jan '12

When I boot coreboot (the alix2 image) on a 6F2 I get the following spew. ========== Changing serial settings was 13/5 now 3/0 In resume (status=0) In 32bit resume Attempting a hard reboot WARNING - Timeout at i8042_wait_write:51! coreboot-4.0-1936-g33dd7a8-dirty Wed Jan 4 12:20:50 MST 2012 starting... MSR GLCP_SYS_RSTPLL (4c000014) value is 0000059c:0000182e Configuring PLL. coreboot-4.0-1936-g33dd7a8-dirty Wed Jan 4 12:20:50 MST 2012 starting... MSR GLCP_SYS_RSTPLL (4c000014) value is 0000059c:07de002e PLL configured. Castle 2.0 BTM periodic sync period. Enable Quack for fewer re-RAS on the MC GLIU port active enable Set the Delay Control in GLCP spd_read_byte dev 50 addr 0d returns 08 spd_read_byte dev 50 addr 05 returns 01 spd_read_byte dev 51 returns 0xff Enable RSDC FPU imprecise exceptions bit Enable Suspend on HLT & PAUSE instructions Enable SUSP and allow TSC to run in Suspend Setup throttling delays to proper mode Done cpuRegInit Ram1.00 Ram2.00 * sdram_set_spd_register spd_read_byte dev 50 addr 15 returns ff * Check DIMM 0 * Check DIMM 1 spd_read_byte dev 51 returns 0xff * Check DDR MAX spd_read_byte dev 50 addr 09 returns 0a spd_read_byte dev 51 returns 0xff * AUTOSIZE DIMM 0 * Check present spd_read_byte dev 50 addr 02 returns 07 * MODBANKS spd_read_byte dev 50 addr 05 returns 01 * FIELDBANKS spd_read_byte dev 50 addr 11 returns 04 * SPDNUMROWS spd_read_byte dev 50 addr 03 returns 03 spd_read_byte dev 50 addr 04 returns 0a * SPDBANKDENSITY spd_read_byte dev 50 addr 1f returns 40 * DIMMSIZE * BEFORT CTZ * TEST DIMM SIZE>8 * PAGESIZE spd_read_byte dev 50 addr 04 returns 0a * MAXCOLADDR * >12address test * RDMSR CF07 * WRMSR CF07 * ALL DONE * AUTOSIZE DIMM 1 * Check present spd_read_byte dev 51 returns 0xff * set cas latency spd_read_byte dev 50 addr 12 returns 10 spd_read_byte dev 50 addr 17 returns 3c spd_read_byte dev 50 addr 19 returns 4b spd_read_byte dev 51 returns 0xff * set all latency spd_read_byte dev 50 addr 1e returns 28 spd_read_byte dev 51 returns 0xff spd_read_byte dev 50 addr 1b returns 0f spd_read_byte dev 51 returns 0xff spd_read_byte dev 50 addr 1d returns 0f spd_read_byte dev 51 returns 0xff spd_read_byte dev 50 addr 1c returns 0a spd_read_byte dev 51 returns 0xff spd_read_byte dev 50 addr 2a returns 46 spd_read_byte dev 51 returns 0xff * set emrs spd_read_byte dev 50 addr 16 returns ff spd_read_byte dev 51 returns 0xff * set ref rate spd_read_byte dev 50 addr 0c returns 3a spd_read_byte dev 51 returns 0xff Ram3 * DRAM controller init done. RAM DLL lock Ram4 POST 02 Past wbinvd Loading image. Searching for fallback/coreboot_ram Check fallback/romstage Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x100000 (147456 bytes), entry @ 0x100000 Stage: done loading. Jumping to image. coreboot-4.0-1936-g33dd7a8-dirty Wed Jan 4 12:20:50 MST 2012 booting... clocks_per_usec: 499 Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:0f.0: enabled 1 PCI: 00:0f.1: enabled 1 PCI: 00:0f.2: enabled 1 PCI: 00:0f.4: enabled 1 PCI: 00:0f.5: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 Compare with tree... Root Device: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:0f.0: enabled 1 PCI: 00:0f.1: enabled 1 PCI: 00:0f.2: enabled 1 PCI: 00:0f.4: enabled 1 PCI: 00:0f.5: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 scan_static_bus for Root Device >> Entering northbridge.c: enable_dev with path 6 >> Entering northbridge.c: pci_domain_enable Enter northbridge_init_early writeglmsr: MSR 0x10000020, val 0x20000000:0x000fff80 writeglmsr: MSR 0x10000021, val 0x20000000:0x080fffe0 sizeram: _MSR MC_CF07_DATA: 10076013:00061a40 sizeram: sizem 0x100MB SysmemInit: enable for 256MBytes usable RAM: 268304383 bytes SysmemInit: MSR 0x10000028, val 0x2000000f:0xfdf00100 sizeram: _MSR MC_CF07_DATA: 10076013:00061a40 sizeram: sizem 0x100MB SMMGL0Init: 268304384 bytes SMMGL0Init: offset is 0x80400000 SMMGL0Init: MSR 0x10000026, val 0x28fbe080:0x400fffe0 writeglmsr: MSR 0x10000080, val 0x00000000:0x00000003 writeglmsr: MSR 0x40000020, val 0x20000000:0x000fff80 writeglmsr: MSR 0x40000021, val 0x20000000:0x080fffe0 sizeram: _MSR MC_CF07_DATA: 10076013:00061a40 sizeram: sizem 0x100MB SysmemInit: enable for 256MBytes usable RAM: 268304383 bytes SysmemInit: MSR 0x4000002a, val 0x2000000f:0xfdf00100 SMMGL1Init: SMMGL1Init: MSR 0x40000023, val 0x20000080:0x400fffe0 writeglmsr: MSR 0x40000080, val 0x00000000:0x00000001 writeglmsr: MSR 0x400000e3, val 0x60000000:0x033000f0 CPU_RCONF_DEFAULT (1808): 0x25FFFC02:0x10FFDF00 CPU_RCONF_BYPASS (180A): 0x00000000 : 0x00000000 L2 cache enabled Enabling cache GLPCI R1: system msr.lo 0x00100130 msr.hi 0x0ffdf000 GLPCI R2: system msr.lo 0x80400120 msr.hi 0x8041f000 Exit northbridge_init_early Done cpubug fixes Not Doing ChipsetFlashSetup() Preparing for VSA... VSA: Real mode stub @00000600: 862 bytes Searching for vsa Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check vsa Stage: loading vsa @ 0x60000 (57504 bytes), entry @ 0x60020 Stage: done loading. VSA: Buffer @00060000 *[0k]=ba VSA: Signature *[0x20-0x23] is b0:10:e6:80 Calling VSA module... ... VSA module returned. VSM: VSA2 VR signature verified. Graphics init... VRC_VG value: 0x2808 Finding PCI configuration type. PCI: Using configuration type 1 PCI_DOMAIN: 0000 enabled >> Entering northbridge.c: enable_dev with path 7 APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 >> Entering northbridge.c: enable_dev with path 2 PCI: 00:01.0 [1022/2080] ops PCI: 00:01.0 [1022/2080] enabled >> Entering northbridge.c: enable_dev with path 2 PCI: 00:01.1 [1022/2081] enabled PCI: 00:01.2 [1022/2082] enabled PCI: 00:09.0 [1106/3053] enabled PCI: 00:0a.0 [1106/3053] enabled PCI: 00:0c.0 [168c/0013] enabled cs5536: southbridge_enable: dev is 00112660 PCI: 00:0f.0 [1022/2090] bus ops PCI: 00:0f.0 [1022/2090] enabled cs5536: southbridge_enable: dev is 001126a8 PCI: Static device PCI: 00:0f.1 not found, disabling it. cs5536: southbridge_enable: dev is 001126f0 PCI: 00:0f.2 [1022/209a] ops PCI: 00:0f.2 [1022/209a] enabled PCI: 00:0f.3 [1022/2093] enabled cs5536: southbridge_enable: dev is 00112738 PCI: 00:0f.4 [1022/2094] enabled cs5536: southbridge_enable: dev is 00112780 PCI: 00:0f.5 [1022/2095] enabled PCI: 00:0f.6 [1022/2096] enabled PCI: 00:0f.7 [1022/2097] enabled scan_static_bus for PCI: 00:0f.0 scan_static_bus for PCI: 00:0f.0 done PCI: pci_scan_bus returning with max=000 scan_static_bus for Root Device done done Setting up VGA for PCI: 00:01.1 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 PCI_DOMAIN: 0000 read_resources bus 0 link: 0 PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done APIC_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC_CLUSTER: 0 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 PCI_DOMAIN: 0000 PCI_DOMAIN: 0000 child on link 0 PCI: 00:01.0 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:01.0 PCI: 00:01.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 10 PCI: 00:01.1 PCI: 00:01.1 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 10 PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 14 PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 18 PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 1c PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 20 PCI: 00:01.2 PCI: 00:01.2 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10 PCI: 00:09.0 PCI: 00:09.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10 PCI: 00:09.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 14 PCI: 00:0a.0 PCI: 00:0a.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10 PCI: 00:0a.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 14 PCI: 00:0c.0 PCI: 00:0c.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 200 index 10 PCI: 00:0f.0 PCI: 00:0f.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:0f.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 14 PCI: 00:0f.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 18 PCI: 00:0f.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 1c PCI: 00:0f.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 20 PCI: 00:0f.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 24 PCI: 00:0f.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 PCI: 00:0f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PCI: 00:0f.1 PCI: 00:0f.2 PCI: 00:0f.2 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:0f.3 PCI: 00:0f.3 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 10 PCI: 00:0f.4 PCI: 00:0f.4 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:0f.5 PCI: 00:0f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:0f.6 PCI: 00:0f.6 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 10 PCI: 00:0f.7 PCI: 00:0f.7 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:09.0 10 * [0x0 - 0xff] io PCI: 00:0a.0 10 * [0x400 - 0x4ff] io PCI: 00:0f.0 14 * [0x800 - 0x8ff] io PCI: 00:0f.0 20 * [0xc00 - 0xc7f] io PCI: 00:0f.3 10 * [0xc80 - 0xcff] io PCI: 00:0f.0 18 * [0x1000 - 0x103f] io PCI: 00:0f.0 24 * [0x1040 - 0x107f] io PCI: 00:0f.0 1c * [0x1080 - 0x109f] io PCI: 00:0f.2 20 * [0x10a0 - 0x10af] io PCI: 00:0f.0 10 * [0x10b0 - 0x10b7] io PCI: 00:01.0 10 * [0x10b8 - 0x10bb] io PCI_DOMAIN: 0000 compute_resources_io: base: 10bc size: 10bc align: 8 gran: 0 limit: ffff done PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:01.1 10 * [0x0 - 0xffffff] mem PCI: 00:0c.0 10 * [0x1000000 - 0x100ffff] mem PCI: 00:01.1 14 * [0x1010000 - 0x1013fff] mem PCI: 00:01.1 18 * [0x1014000 - 0x1017fff] mem PCI: 00:01.1 1c * [0x1018000 - 0x101bfff] mem PCI: 00:01.1 20 * [0x101c000 - 0x101ffff] mem PCI: 00:01.2 10 * [0x1020000 - 0x1023fff] mem PCI: 00:0f.6 10 * [0x1024000 - 0x1025fff] mem PCI: 00:0f.4 10 * [0x1026000 - 0x1026fff] mem PCI: 00:0f.5 10 * [0x1027000 - 0x1027fff] mem PCI: 00:0f.7 10 * [0x1028000 - 0x1028fff] mem PCI: 00:09.0 14 * [0x1029000 - 0x10290ff] mem PCI: 00:0a.0 14 * [0x1029100 - 0x10291ff] mem PCI_DOMAIN: 0000 compute_resources_mem: base: 1029200 size: 1029200 align: 24 gran: 0 limit: ffffffff done avoid_fixed_resources: PCI_DOMAIN: 0000 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI_DOMAIN: 0000 constrain_resources: PCI: 00:01.0 constrain_resources: PCI: 00:01.1 constrain_resources: PCI: 00:01.2 constrain_resources: PCI: 00:09.0 constrain_resources: PCI: 00:0a.0 constrain_resources: PCI: 00:0c.0 constrain_resources: PCI: 00:0f.0 constrain_resources: PCI: 00:0f.2 constrain_resources: PCI: 00:0f.3 constrain_resources: PCI: 00:0f.4 constrain_resources: PCI: 00:0f.5 constrain_resources: PCI: 00:0f.6 constrain_resources: PCI: 00:0f.7 avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff lim->base 00001000 lim->limit 0000ffff avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff lim->base 00000000 lim->limit febfffff Setting resources... PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:10bc align:8 gran:0 limit:ffff Assigned: PCI: 00:09.0 10 * [0x1000 - 0x10ff] io Assigned: PCI: 00:0a.0 10 * [0x1400 - 0x14ff] io Assigned: PCI: 00:0f.0 14 * [0x1800 - 0x18ff] io Assigned: PCI: 00:0f.0 20 * [0x1c00 - 0x1c7f] io Assigned: PCI: 00:0f.3 10 * [0x1c80 - 0x1cff] io Assigned: PCI: 00:0f.0 18 * [0x2000 - 0x203f] io Assigned: PCI: 00:0f.0 24 * [0x2040 - 0x207f] io Assigned: PCI: 00:0f.0 1c * [0x2080 - 0x209f] io Assigned: PCI: 00:0f.2 20 * [0x20a0 - 0x20af] io Assigned: PCI: 00:0f.0 10 * [0x20b0 - 0x20b7] io Assigned: PCI: 00:01.0 10 * [0x20b8 - 0x20bb] io PCI_DOMAIN: 0000 allocate_resources_io: next_base: 20bc size: 10bc align: 8 gran: 0 done PCI_DOMAIN: 0000 allocate_resources_mem: base:fd000000 size:1029200 align:24 gran:0 limit:febfffff Assigned: PCI: 00:01.1 10 * [0xfd000000 - 0xfdffffff] mem Assigned: PCI: 00:0c.0 10 * [0xfe000000 - 0xfe00ffff] mem Assigned: PCI: 00:01.1 14 * [0xfe010000 - 0xfe013fff] mem Assigned: PCI: 00:01.1 18 * [0xfe014000 - 0xfe017fff] mem Assigned: PCI: 00:01.1 1c * [0xfe018000 - 0xfe01bfff] mem Assigned: PCI: 00:01.1 20 * [0xfe01c000 - 0xfe01ffff] mem Assigned: PCI: 00:01.2 10 * [0xfe020000 - 0xfe023fff] mem Assigned: PCI: 00:0f.6 10 * [0xfe024000 - 0xfe025fff] mem Assigned: PCI: 00:0f.4 10 * [0xfe026000 - 0xfe026fff] mem Assigned: PCI: 00:0f.5 10 * [0xfe027000 - 0xfe027fff] mem Assigned: PCI: 00:0f.7 10 * [0xfe028000 - 0xfe028fff] mem Assigned: PCI: 00:09.0 14 * [0xfe029000 - 0xfe0290ff] mem Assigned: PCI: 00:0a.0 14 * [0xfe029100 - 0xfe0291ff] mem PCI_DOMAIN: 0000 allocate_resources_mem: next_base: fe029200 size: 1029200 align: 24 gran: 0 done Root Device assign_resources, bus 0 link: 0 >> Entering northbridge.c: pci_domain_set_resources PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:01.1 10 <- [0x00fd000000 - 0x00fdffffff] size 0x01000000 gran 0x18 mem PCI: 00:01.1 14 <- [0x00fe010000 - 0x00fe013fff] size 0x00004000 gran 0x0e mem PCI: 00:01.1 18 <- [0x00fe014000 - 0x00fe017fff] size 0x00004000 gran 0x0e mem PCI: 00:01.1 1c <- [0x00fe018000 - 0x00fe01bfff] size 0x00004000 gran 0x0e mem PCI: 00:01.1 20 <- [0x00fe01c000 - 0x00fe01ffff] size 0x00004000 gran 0x0e mem PCI: 00:01.2 10 <- [0x00fe020000 - 0x00fe023fff] size 0x00004000 gran 0x0e mem PCI: 00:09.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 00:09.0 14 <- [0x00fe029000 - 0x00fe0290ff] size 0x00000100 gran 0x08 mem PCI: 00:0a.0 10 <- [0x0000001400 - 0x00000014ff] size 0x00000100 gran 0x08 io PCI: 00:0a.0 14 <- [0x00fe029100 - 0x00fe0291ff] size 0x00000100 gran 0x08 mem PCI: 00:0c.0 10 <- [0x00fe000000 - 0x00fe00ffff] size 0x00010000 gran 0x10 mem PCI: 00:0f.0 10 <- [0x00000020b0 - 0x00000020b7] size 0x00000008 gran 0x03 io PCI: 00:0f.0 14 <- [0x0000001800 - 0x00000018ff] size 0x00000100 gran 0x08 io PCI: 00:0f.0 18 <- [0x0000002000 - 0x000000203f] size 0x00000040 gran 0x06 io PCI: 00:0f.0 1c <- [0x0000002080 - 0x000000209f] size 0x00000020 gran 0x05 io PCI: 00:0f.0 20 <- [0x0000001c00 - 0x0000001c7f] size 0x00000080 gran 0x07 io PCI: 00:0f.0 24 <- [0x0000002040 - 0x000000207f] size 0x00000040 gran 0x06 io PCI: 00:0f.2 20 <- [0x00000020a0 - 0x00000020af] size 0x00000010 gran 0x04 io PCI: 00:0f.3 10 <- [0x0000001c80 - 0x0000001cff] size 0x00000080 gran 0x07 io PCI: 00:0f.4 10 <- [0x00fe026000 - 0x00fe026fff] size 0x00001000 gran 0x0c mem PCI: 00:0f.5 10 <- [0x00fe027000 - 0x00fe027fff] size 0x00001000 gran 0x0c mem PCI: 00:0f.6 10 <- [0x00fe024000 - 0x00fe025fff] size 0x00002000 gran 0x0d mem PCI: 00:0f.7 10 <- [0x00fe028000 - 0x00fe028fff] size 0x00001000 gran 0x0c mem PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 PCI_DOMAIN: 0000 PCI_DOMAIN: 0000 child on link 0 PCI: 00:01.0 PCI_DOMAIN: 0000 resource base 1000 size 10bc align 8 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base fd000000 size 1029200 align 24 gran 0 limit febfffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index a PCI_DOMAIN: 0000 resource base c0000 size f720000 align 0 gran 0 limit 0 flags e0004200 index b PCI: 00:01.0 PCI: 00:01.0 resource base 20b8 size 4 align 2 gran 2 limit ffff flags 40000100 index 10 PCI: 00:01.1 PCI: 00:01.1 resource base fd000000 size 1000000 align 24 gran 24 limit febfffff flags 60000200 index 10 PCI: 00:01.1 resource base fe010000 size 4000 align 14 gran 14 limit febfffff flags 60000200 index 14 PCI: 00:01.1 resource base fe014000 size 4000 align 14 gran 14 limit febfffff flags 60000200 index 18 PCI: 00:01.1 resource base fe018000 size 4000 align 14 gran 14 limit febfffff flags 60000200 index 1c PCI: 00:01.1 resource base fe01c000 size 4000 align 14 gran 14 limit febfffff flags 60000200 index 20 PCI: 00:01.2 PCI: 00:01.2 resource base fe020000 size 4000 align 14 gran 14 limit febfffff flags 60000200 index 10 PCI: 00:09.0 PCI: 00:09.0 resource base 1000 size 100 align 8 gran 8 limit ffff flags 60000100 index 10 PCI: 00:09.0 resource base fe029000 size 100 align 8 gran 8 limit febfffff flags 60000200 index 14 PCI: 00:0a.0 PCI: 00:0a.0 resource base 1400 size 100 align 8 gran 8 limit ffff flags 60000100 index 10 PCI: 00:0a.0 resource base fe029100 size 100 align 8 gran 8 limit febfffff flags 60000200 index 14 PCI: 00:0c.0 PCI: 00:0c.0 resource base fe000000 size 10000 align 16 gran 16 limit febfffff flags 60000200 index 10 PCI: 00:0f.0 PCI: 00:0f.0 resource base 20b0 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 PCI: 00:0f.0 resource base 1800 size 100 align 8 gran 8 limit ffff flags 60000100 index 14 PCI: 00:0f.0 resource base 2000 size 40 align 6 gran 6 limit ffff flags 60000100 index 18 PCI: 00:0f.0 resource base 2080 size 20 align 5 gran 5 limit ffff flags 60000100 index 1c PCI: 00:0f.0 resource base 1c00 size 80 align 7 gran 7 limit ffff flags 60000100 index 20 PCI: 00:0f.0 resource base 2040 size 40 align 6 gran 6 limit ffff flags 60000100 index 24 PCI: 00:0f.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 PCI: 00:0f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PCI: 00:0f.1 PCI: 00:0f.2 PCI: 00:0f.2 resource base 20a0 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:0f.3 PCI: 00:0f.3 resource base 1c80 size 80 align 7 gran 7 limit ffff flags 60000100 index 10 PCI: 00:0f.4 PCI: 00:0f.4 resource base fe026000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10 PCI: 00:0f.5 PCI: 00:0f.5 resource base fe027000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10 PCI: 00:0f.6 PCI: 00:0f.6 resource base fe024000 size 2000 align 13 gran 13 limit febfffff flags 60000200 index 10 PCI: 00:0f.7 PCI: 00:0f.7 resource base fe028000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 Done allocating resources. Enabling resources... PCI: 00:01.0 cmd <- 05 PCI: 00:01.1 subsystem <- 0000/0000 PCI: 00:01.1 cmd <- 03 PCI: 00:01.2 cmd <- 02 PCI: 00:09.0 cmd <- 83 PCI: 00:0a.0 cmd <- 83 PCI: 00:0c.0 cmd <- 02 PCI: 00:0f.0 cmd <- 09 PCI: 00:0f.2 cmd <- 01 PCI: 00:0f.3 cmd <- 01 PCI: 00:0f.4 subsystem <- 0000/0000 PCI: 00:0f.4 cmd <- 02 PCI: 00:0f.5 subsystem <- 0000/0000 PCI: 00:0f.5 cmd <- 02 PCI: 00:0f.6 cmd <- 02 PCI: 00:0f.7 cmd <- 02 done. Initializing devices... Root Device init ALIX.2D ENTER init ALIX.2D EXIT init APIC_CLUSTER: 0 init >> Entering northbridge.c: cpu_bus_init Initializing CPU #0 CPU: vendor AMD device 5a2 CPU: family 05, model 0a, stepping 02 model_lx_init Enabling cache A20 (0x92): 2 A20 (0x92): 2 CPU model_lx_init DONE CPU #0 initialized PCI: 00:01.0 init >> Entering northbridge.c: northbridge_init PCI: 00:01.1 init Searching for pci1022,2081.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check vsa Check config Check ERROR: No file header found at fffffd40, attempting to recover by searching for header Could not find file 'pci1022,2081.rom'. PCI: 00:01.2 init Searching for pci1022,2082.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check vsa Check config Check ERROR: No file header found at fffffd40, attempting to recover by searching for header Could not find file 'pci1022,2082.rom'. PCI: 00:09.0 init Searching for pci1106,3053.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check vsa Check config Check ERROR: No file header found at fffffd40, attempting to recover by searching for header Could not find file 'pci1106,3053.rom'. PCI: 00:0a.0 init Searching for pci1106,3053.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check vsa Check config Check ERROR: No file header found at fffffd40, attempting to recover by searching for header Could not find file 'pci1106,3053.rom'. PCI: 00:0c.0 init Searching for pci168c,0013.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check vsa Check config Check ERROR: No file header found at fffffd40, attempting to recover by searching for header Could not find file 'pci168c,0013.rom'. PCI: 00:0f.0 init cs5536: southbridge_init RTC Init GPIO_ADDR: 00001800 uarts_init: enable COM1 uarts_init: enable COM2 uarts_init: wrote COM2 address 0x2f8 uarts_init: set COM2 irq uarts_init: set output enable uarts_init: set OUTAUX1 uarts_init: set pullup COM2 uarts_init: COM2 enabled cs5536: southbridge_init: enable_ide_nand_flash is 0 Disabling VPCI device: 0x80000900 Disabling VPCI device: 0x80007B00 PCI: 00:0f.2 init cs5536_ide: ide_init PCI: 00:0f.3 init Searching for pci1022,2093.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check vsa Check config Check ERROR: No file header found at fffffd40, attempting to recover by searching for header Could not find file 'pci1022,2093.rom'. PCI: 00:0f.4 init Searching for pci1022,2094.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check vsa Check config Check ERROR: No file header found at fffffd40, attempting to recover by searching for header Could not find file 'pci1022,2094.rom'. PCI: 00:0f.5 init Searching for pci1022,2095.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check vsa Check config Check ERROR: No file header found at fffffd40, attempting to recover by searching for header Could not find file 'pci1022,2095.rom'. PCI: 00:0f.6 init Searching for pci1022,2096.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check vsa Check config Check ERROR: No file header found at fffffd40, attempting to recover by searching for header Could not find file 'pci1022,2096.rom'. PCI: 00:0f.7 init Searching for pci1022,2097.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check vsa Check config Check ERROR: No file header found at fffffd40, attempting to recover by searching for header Could not find file 'pci1022,2097.rom'. Devices initialized Show all devs...After init. Root Device: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:0f.0: enabled 1 PCI: 00:0f.1: enabled 0 PCI: 00:0f.2: enabled 1 PCI: 00:0f.4: enabled 1 PCI: 00:0f.5: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI: 00:01.2: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:0a.0: enabled 1 PCI: 00:0c.0: enabled 1 PCI: 00:0f.3: enabled 1 PCI: 00:0f.6: enabled 1 PCI: 00:0f.7: enabled 1 CPU: 00: enabled 1 Initializing CBMEM area to 0xf7d0000 (65536 bytes) Adding CBMEM entry as no. 1 Moving GDT to 0f7d0200...ok High Tables Base is f7d0000. Copying Interrupt Routing Table to 0x000f0000... done. PIRQ Entry 0 Dev/Fn: 1 Slot: 0 INT: A link: 1 bitmap: 800 IRQ: 11 INT: B link: 0 bitmap: 0 not routed INT: C link: 0 bitmap: 0 not routed INT: D link: 0 bitmap: 0 not routed Assigning IRQ 11 to 0:1.2 i8259_configure_irq_trigger: current interrupts are 0x0 i8259_configure_irq_trigger: try to set interrupts 0x800 PIRQ Entry 1 Dev/Fn: 9 Slot: 0 INT: A link: 2 bitmap: 400 IRQ: 10 INT: B link: 0 bitmap: 0 not routed INT: C link: 0 bitmap: 0 not routed INT: D link: 0 bitmap: 0 not routed Assigning IRQ 10 to 0:9.0 i8259_configure_irq_trigger: current interrupts are 0x800 i8259_configure_irq_trigger: try to set interrupts 0xc00 PIRQ Entry 2 Dev/Fn: A Slot: 0 INT: A link: 3 bitmap: 800 IRQ: 11 INT: B link: 0 bitmap: 0 not routed INT: C link: 0 bitmap: 0 not routed INT: D link: 0 bitmap: 0 not routed Assigning IRQ 11 to 0:a.0 i8259_configure_irq_trigger: current interrupts are 0xc00 i8259_configure_irq_trigger: try to set interrupts 0xc00 PIRQ Entry 3 Dev/Fn: B Slot: 0 INT: A link: 4 bitmap: 200 IRQ: 9 INT: B link: 0 bitmap: 0 not routed INT: C link: 0 bitmap: 0 not routed INT: D link: 0 bitmap: 0 not routed PIRQ Entry 4 Dev/Fn: C Slot: 0 INT: A link: 1 bitmap: 800 IRQ: 11 INT: B link: 2 bitmap: 400 IRQ: 10 INT: C link: 0 bitmap: 0 not routed INT: D link: 0 bitmap: 0 not routed Assigning IRQ 11 to 0:c.0 i8259_configure_irq_trigger: current interrupts are 0xc00 i8259_configure_irq_trigger: try to set interrupts 0xc00 PIRQ Entry 5 Dev/Fn: E Slot: 0 INT: A link: 3 bitmap: 800 IRQ: 11 INT: B link: 4 bitmap: 200 IRQ: 9 INT: C link: 0 bitmap: 0 not routed INT: D link: 0 bitmap: 0 not routed PIRQ Entry 6 Dev/Fn: F Slot: 0 INT: A link: 1 bitmap: 800 IRQ: 11 INT: B link: 2 bitmap: 400 IRQ: 10 INT: C link: 3 bitmap: 800 IRQ: 11 INT: D link: 4 bitmap: 200 IRQ: 9 Assigning IRQ 9 to 0:f.4 i8259_configure_irq_trigger: current interrupts are 0xc00 i8259_configure_irq_trigger: try to set interrupts 0xe00 Assigning IRQ 9 to 0:f.5 i8259_configure_irq_trigger: current interrupts are 0xe00 i8259_configure_irq_trigger: try to set interrupts 0xe00 PIRQ1: 11 PIRQ2: 10 PIRQ3: 11 PIRQ4: 9 Adding CBMEM entry as no. 2 Copying Interrupt Routing Table to 0x0f7d0400... done. PIRQ Entry 0 Dev/Fn: 1 Slot: 0 INT: A link: 1 bitmap: 800 IRQ: 11 INT: B link: 0 bitmap: 0 not routed INT: C link: 0 bitmap: 0 not routed INT: D link: 0 bitmap: 0 not routed Assigning IRQ 11 to 0:1.2 i8259_configure_irq_trigger: current interrupts are 0xe00 i8259_configure_irq_trigger: try to set interrupts 0xe00 PIRQ Entry 1 Dev/Fn: 9 Slot: 0 INT: A link: 2 bitmap: 400 IRQ: 10 INT: B link: 0 bitmap: 0 not routed INT: C link: 0 bitmap: 0 not routed INT: D link: 0 bitmap: 0 not routed Assigning IRQ 10 to 0:9.0 i8259_configure_irq_trigger: current interrupts are 0xe00 i8259_configure_irq_trigger: try to set interrupts 0xe00 PIRQ Entry 2 Dev/Fn: A Slot: 0 INT: A link: 3 bitmap: 800 IRQ: 11 INT: B link: 0 bitmap: 0 not routed INT: C link: 0 bitmap: 0 not routed INT: D link: 0 bitmap: 0 not routed Assigning IRQ 11 to 0:a.0 i8259_configure_irq_trigger: current interrupts are 0xe00 i8259_configure_irq_trigger: try to set interrupts 0xe00 PIRQ Entry 3 Dev/Fn: B Slot: 0 INT: A link: 4 bitmap: 200 IRQ: 9 INT: B link: 0 bitmap: 0 not routed INT: C link: 0 bitmap: 0 not routed INT: D link: 0 bitmap: 0 not routed PIRQ Entry 4 Dev/Fn: C Slot: 0 INT: A link: 1 bitmap: 800 IRQ: 11 INT: B link: 2 bitmap: 400 IRQ: 10 INT: C link: 0 bitmap: 0 not routed INT: D link: 0 bitmap: 0 not routed Assigning IRQ 11 to 0:c.0 i8259_configure_irq_trigger: current interrupts are 0xe00 i8259_configure_irq_trigger: try to set interrupts 0xe00 PIRQ Entry 5 Dev/Fn: E Slot: 0 INT: A link: 3 bitmap: 800 IRQ: 11 INT: B link: 4 bitmap: 200 IRQ: 9 INT: C link: 0 bitmap: 0 not routed INT: D link: 0 bitmap: 0 not routed PIRQ Entry 6 Dev/Fn: F Slot: 0 INT: A link: 1 bitmap: 800 IRQ: 11 INT: B link: 2 bitmap: 400 IRQ: 10 INT: C link: 3 bitmap: 800 IRQ: 11 INT: D link: 4 bitmap: 200 IRQ: 9 Assigning IRQ 9 to 0:f.4 i8259_configure_irq_trigger: current interrupts are 0xe00 i8259_configure_irq_trigger: try to set interrupts 0xe00 Assigning IRQ 9 to 0:f.5 i8259_configure_irq_trigger: current interrupts are 0xe00 i8259_configure_irq_trigger: try to set interrupts 0xe00 PIRQ1: 11 PIRQ2: 10 PIRQ3: 11 PIRQ4: 9 PIRQ table: 144 bytes. Adding CBMEM entry as no. 3 smbios_write_tables: 0f7d1400 Root Device (PC Engines ALIX.2D Mainboard) PCI_DOMAIN: 0000 (AMD LX Northbridge) PCI: 00:01.0 (AMD LX Northbridge) PCI: 00:01.1 (AMD LX Northbridge) PCI: 00:0f.0 (AMD Geode CS5536 Southbridge) PCI: 00:0f.1 (AMD Geode CS5536 Southbridge) PCI: 00:0f.2 (AMD Geode CS5536 Southbridge) PCI: 00:0f.4 (AMD Geode CS5536 Southbridge) PCI: 00:0f.5 (AMD Geode CS5536 Southbridge) APIC_CLUSTER: 0 (AMD LX Northbridge) APIC: 00 () PCI: 00:01.2 () PCI: 00:09.0 () PCI: 00:0a.0 () PCI: 00:0c.0 () PCI: 00:0f.3 () PCI: 00:0f.6 () PCI: 00:0f.7 () CPU: 00 () SMBIOS tables: 297 bytes. Adding CBMEM entry as no. 4 Writing high table forward entry at 0x00000500 Wrote coreboot table at: 00000500 - 00000518 checksum d461 New low_table_end: 0x00000518 Now going to write high coreboot table at 0x0f7d1c00 rom_table_end = 0x0f7d1c00 Adjust low_table_end from 0x00000518 to 0x00001000 Adjust rom_table_end from 0x0f7d1c00 to 0x0f7e0000 Adding high table area coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-000000000f7cffff: RAM 3. 000000000f7d0000-000000000f7dffff: CONFIGURATION TABLES Wrote coreboot table at: 0f7d1c00 - 0f7d1dcc checksum b828 coreboot table: 460 bytes. Multiboot Information structure has been written. 0. FREE SPACE 0f7d3c00 0000c400 1. GDT 0f7d0200 00000200 2. IRQ TABLE 0f7d0400 00001000 3. SMBIOS 0f7d1400 00000800 4. COREBOOT 0f7d1c00 00002000 Searching for fallback/payload Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Got a payload Loading segment from rom address 0xfff8bcb8 data (compression=1) New segment dstaddr 0xe7e04 memsize 0x181fc srcaddr 0xfff8bcf0 filesize 0xc20b (cleaned up) New segment addr 0xe7e04 size 0x181fc offset 0xfff8bcf0 filesize 0xc20b Loading segment from rom address 0xfff8bcd4 Entry Point 0x00000000 Loading Segment: addr: 0x00000000000e7e04 memsz: 0x00000000000181fc filesz: 0x000000000000c20b lb: [0x0000000000100000, 0x0000000000124000) Post relocation: addr: 0x00000000000e7e04 memsz: 0x00000000000181fc filesz: 0x000000000000c20b using LZMA [ 0x000e7e04, 00100000, 0x00100000) <- fff8bcf0 dest 000e7e04, end 00100000, bouncebuffer f788000 Loaded segments Jumping to boot code at fc8c0 entry = 0x000fc8c0 lb_start = 0x00100000 lb_size = 0x00024000 adjust = 0x0f6ac000 buffer = 0x0f788000 elf_boot_notes = 0x001127c8 adjusted_boot_notes = 0x0f7be7c8 Start bios (version 1.6.3-20120104_122101-builder) Found mainboard PC Engines ALIX.6 Found CBFS header at 0xfffffd30 Ram Size=0x0f7d0000 (0x0000000000000000 high) Relocating init from 0x000e8450 to 0x0f7b57a0 (size 42812) CPU Mhz=498 Found 9 PCI devices (max PCI bus is 00) No apic - only the main cpu is present. Copying SMBIOS entry point from 0x0f7d1400 to 0x000fdbd0 Scan for VGA option rom EHCI init on dev 00:0f.5 (regs=0xfe027010) WARNING - Timeout at i8042_flush:69! Found 0 lpt ports Found 2 serial ports ATA controller 1 at 1f0/3f4/0 (irq 14 dev 7a) ATA controller 2 at 170/374/0 (irq 15 dev 7a) ata0-0: SanDisk SDCFH-002G ATA-4 Hard-Disk (1907 MiBytes) Searching bootorder for: /pci@i0cf8/*@f,2/drive@0/disk@0 All threads complete. Scan for option roms Press F12 for boot menu. drive 0x000fdb80: PCHS=3875/16/63 translation=large LCHS=968/64/63 s=3906560 Returned 65536 bytes of ZoneHigh e820 map has 5 items: 0: 0000000000000000 - 000000000009fc00 = 1 RAM 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED 3: 0000000000100000 - 000000000f7d0000 = 1 RAM 4: 000000000f7d0000 - 000000000f7e0000 = 2 RESERVED enter handle_19: NULL Booting from Hard Disk... Booting from 0000:7c00 Press any key to continue. Press any key to continue. ========== And then the linux early-printk logging begins. Peter suggests it's an issue with the MTRR not being set up correctly (for caching), and is the same problem. I'm seeing a 27-second pause after this line: Stage: loading fallback/coreboot_ram @ 0x100000 (147456 bytes), entry @ 0x100000 Also, the Alix 6F2 doesn't have a keyboard controller... is there a way to turn off the i8042 stuff? Thanks, -Philip

2 1

tiny bootblock problem
by Nils 05 Jan '12

05 Jan '12

Hi all, I was updating some old patches to get them ready for inclusion and tested latest coreboot trunk. (first time with tiny bootblock) My geode GX2 target does boot, but it takes 30 seconds to load fallback/coreboot_ram . Is that a caching problem introduced by tiny bootblock? What is needed to get it right? Thanks, Nils.

2 1

TOM2 and M4A785T-M
by Denis 'GNUtoo' Carikli 05 Jan '12

05 Jan '12

Hi, is it normal that TOM2 is 0 on the M4A785T-M mainboard? Here are the logs from coreboot: -------------------------------------------- Sysmem TOM = 0_80000000 Sysmem TOM2 = 0_0 [...] Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 1, base: 1792MB, range: 256MB, type UC ADDRESS_MASK_HIGH=0xffff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled And from the linux kernel: ----------------------------------- [ 0.312294] mtrr: your CPUs had inconsistent variable MTRR settings [ 0.312295] mtrr: probably your BIOS does not setup all CPUs. [ 0.312296] mtrr: corrected configuration. [...] [ 0.317404] ACPI: Executed 2 blocks of module-level executable AML code [ 0.383560] ACPI: Interpreter enabled [ 0.384025] ACPI: (supports S0 S1 S2 S3 S4 S5) [ 0.392816] ACPI: BIOS offers _BFS [ 0.396026] ACPI: If "acpi.bfs=1" improves resume, please notify linux- acpi(a)vger.kernel.org [ 0.400025] ACPI: Using IOAPIC for interrupt routing [ 0.432761] ACPI: Power Resource [PFN0] (on) [ 0.444081] ACPI: No dock devices found. [ 0.448028] HEST: Table not found. [ 0.451490] PCI: Ignoring host bridge windows from ACPI; if necessary, use "pci=use_crs" and report a bug [ 0.452071] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND (20110112/psargs-359) [ 0.460029] ACPI Error: Method parse/execution failed [\_SB_.PCI0._CRS] (Node f4426e70), AE_NOT_FOUND (20110112/psparse-536) [ 0.472033] [Firmware Bug]: ACPI: no secondary bus range in _CRS [ 0.476035] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff]) [ 0.480086] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND (20110112/psargs-359) [ 0.492031] ACPI Error: Method parse/execution failed [\_SB_.PCI0._CRS] (Node f4426e70), AE_NOT_FOUND (20110112/psparse-536) Denis.

2 1

Patch merged into coreboot/master: 4bfe8f6 rs780: use bitwise rather than boolean not
by gerrit＠coreboot.org 05 Jan '12

05 Jan '12

the following patch was just integrated into master: commit 4bfe8f667b7d237cdbed73c61fbe09442acc4d97 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Wed Jan 4 19:37:48 2012 -0600 rs780: use bitwise rather than boolean not Change-Id: Ie3872c57990f9784aafda14f8c7fc842b3a65260 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Build-Tested: build bot (Jenkins) at Thu Jan 5 17:57:08 2012, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Thu Jan 5 18:08:06 2012, giving +2 See http://review.coreboot.org/518 for details. -gerrit

1 0

Patch set updated for coreboot: 4bfe8f6 rs780: use bitwise rather than boolean not
by Jonathan A. Kollasch 05 Jan '12

05 Jan '12

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/518 -gerrit commit 4bfe8f667b7d237cdbed73c61fbe09442acc4d97 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Wed Jan 4 19:37:48 2012 -0600 rs780: use bitwise rather than boolean not Change-Id: Ie3872c57990f9784aafda14f8c7fc842b3a65260 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/southbridge/amd/rs780/pcie.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/southbridge/amd/rs780/pcie.c b/src/southbridge/amd/rs780/pcie.c index efa2e58..be80ed3 100644 --- a/src/southbridge/amd/rs780/pcie.c +++ b/src/southbridge/amd/rs780/pcie.c @@ -72,7 +72,7 @@ static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port) state = ~state; state &= (1 << 4) + (1 << 5) + (1 << 6) + (1 << 7); state_save = state << 17; - state &= !(AtiPcieCfg.PortHp); + state &= ~(AtiPcieCfg.PortHp); reg = nbmisc_read_index(nb_dev, 0x0c); reg |= state; nbmisc_write_index(nb_dev, 0x0c, reg);

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot January 2012