coreboot January 2012

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Patch set updated for coreboot: d0c03b5 geos: missing Vendor information
by Philip Prindeville 06 Jan '12

06 Jan '12

Philip Prindeville (pprindeville(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/520 -gerrit commit d0c03b53a060c24adc172d60072b0d45be530b38 Author: Philip Prindeville <philipp(a)redfish-solutions.com> Date: Fri Jan 6 11:52:25 2012 -0700 geos: missing Vendor information The DMI information isn't being generated correctly because of the mainboard vendor value not being set. Change-Id: I07a6620bc6938292fecd50dc3ff0cb926d9c5f97 Signed-off-by: Philip Prindeville <philipp(a)redfish-solutions.com> --- src/mainboard/traverse/geos/Kconfig | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/src/mainboard/traverse/geos/Kconfig b/src/mainboard/traverse/geos/Kconfig index b455f60..5f00230 100644 --- a/src/mainboard/traverse/geos/Kconfig +++ b/src/mainboard/traverse/geos/Kconfig @@ -17,6 +17,10 @@ config MAINBOARD_DIR string default traverse/geos +config MAINBOARD_VENDOR + string + default "PC Engines" + config MAINBOARD_PART_NUMBER string default "Geos"

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Patch set updated for coreboot: 54b9674 geos: Explicitly set console baud rate
by Philip Prindeville 06 Jan '12

06 Jan '12

Philip Prindeville (pprindeville(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/513 -gerrit commit 54b96744aeb672bb432ad0144e8a23b2a4afead4 Author: Philip Prindeville <philipp(a)redfish-solutions.com> Date: Sat Dec 31 19:29:21 2011 -0700 geos: Explicitly set console baud rate If the default baud rate changes, we should remain compatible with earlier published coreboot images. Change-Id: I4e6b5515395a9de237ad8f758f6f66fb825262eb Signed-off-by: Philip Prindeville <philipp(a)redfish-solutions.com> --- src/mainboard/traverse/geos/Kconfig | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/mainboard/traverse/geos/Kconfig b/src/mainboard/traverse/geos/Kconfig index dd6c8dd..b455f60 100644 --- a/src/mainboard/traverse/geos/Kconfig +++ b/src/mainboard/traverse/geos/Kconfig @@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select UDELAY_TSC select BOARD_ROMSIZE_KB_1024 select POWER_BUTTON_DEFAULT_DISABLE + select CONSOLE_SERIAL_115200 config MAINBOARD_DIR string

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Patch set updated for coreboot: 903a1d1 Add rules to pull down and uncompress gpl_vsa_lx_102.bin
by Philip Prindeville 06 Jan '12

06 Jan '12

Philip Prindeville (pprindeville(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/509 -gerrit commit 903a1d1c29527e024281d0bb3596c5e817f910b5 Author: Philip Prindeville <philipp(a)redfish-solutions.com> Date: Thu Dec 29 12:21:39 2011 -0700 Add rules to pull down and uncompress gpl_vsa_lx_102.bin These steps are in the Wiki, but they should be automated. Change-Id: I81528dddb47b0cfe4acd33456680f8d3211fabd7 Signed-off-by: Philip Prindeville <philipp(a)redfish-solutions.com> --- src/arch/x86/Makefile.inc | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 7bba44e..a95fd62 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -396,3 +396,8 @@ filo: CONFIG_FILO_MASTER=$(CONFIG_FILO_MASTER) \ CONFIG_FILO_STABLE=$(CONFIG_FILO_STABLE) +gpl_vsa_lx_102.bin.gz: + @wget -q http://marcjonesconsulting.com/gplvsa/gpl_vsa_lx_102.bin.gz + +gpl_vsa_lx_102.bin: gpl_vsa_lx_102.bin.gz + @gunzip $^

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Patch set updated for coreboot: 5616f71 Set default baudrate on Alix2d to be compatible with factory default
by Philip Prindeville 06 Jan '12

06 Jan '12

Philip Prindeville (pprindeville(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/508 -gerrit commit 5616f71e404771477770ca2ce098bbf36446ed35 Author: Philip Prindeville <philipp(a)redfish-solutions.com> Date: Wed Dec 28 16:32:44 2011 -0700 Set default baudrate on Alix2d to be compatible with factory default Boards shipping from PC Engines with the factory BIOS (tinyBios 0.99) boot up at 38400. In keeping with the principle of least astonishment, boards reflashed with SeaBIOS should probably try to keep compatible with this setting. Change-Id: Ieda47016c78e673ce2f6aec8b270c2b511ebfcf0 Signed-off-by: Philip Prindeville <philipp(a)redfish-solutions.com> --- src/mainboard/pcengines/alix2d/Kconfig | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/mainboard/pcengines/alix2d/Kconfig b/src/mainboard/pcengines/alix2d/Kconfig index 264f5d9..ea02adf 100644 --- a/src/mainboard/pcengines/alix2d/Kconfig +++ b/src/mainboard/pcengines/alix2d/Kconfig @@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select UDELAY_TSC select BOARD_ROMSIZE_KB_512 select POWER_BUTTON_FORCE_DISABLE + select CONSOLE_SERIAL_38400 config MAINBOARD_DIR string

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#185: Vtech partial success
by coreboot 06 Jan '12

06 Jan '12

#185: Vtech partial success -----------------------------------+---------------------------------- Reporter: jeroenkrabbendam@… | Owner: stepan@… Type: enhancement | Status: new Priority: trivial | Milestone: Component: coreboot | Keywords: VTech success Dependencies: | Patch Status: there is no patch -----------------------------------+---------------------------------- Picked up an oldfashioned VTech mobo (bios id: ite8671-2A69KV3IC-00), i.e. VTech, intel 440BX northbridge, intel 82371 southbridge, IT8671F superio. Gigabyte GA-6BX{CE} are close cousins, both run fine, that is, they boot from harddisk (I have no floppy anymore, why??) Soyo should be a close cousin too, but nothing happens, not even debug output on a (Atlantic) NE2K nic. However, the Gigabyte coreboot images both refuse to complete a netboot, as already noted for my Asus P2B. See next ticket. -- Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/185> coreboot <http://www.coreboot.org/>

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#184: Asus p2b with aty128 fails
by coreboot 06 Jan '12

06 Jan '12

#184: Asus p2b with aty128 fails --------------------------------+------------------------------------------ Reporter: | Owner: stepan@… jeroenkrabbendam@… | Status: new Type: defect | Milestone: Priority: minor | Keywords: Asus p2b & aty128 failure Component: coreboot | Patch Status: there is no patch Dependencies: | --------------------------------+------------------------------------------ both Asus P2B mobo's (core)boot fine with several AGP and PCI video cards. However, equipped with a ATY128, nothing happens, not even debug output by the NE2K nic. With the original BIOS, everything is OK, so I assume it's a coreboot problem. Tested with several S3 PCI cards (all ok), several AGP cards (i.e. Sis, S3, MGA), all went fine. Except for the ATY128. (Note however my next ticket, addressing netboot failure.) -- Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/184> coreboot <http://www.coreboot.org/>

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Patch set updated for coreboot: ba5be28 cb_parse_header() should not assume table in 4K of contiguous memory
by Philip Prindeville 06 Jan '12

06 Jan '12

Philip Prindeville (pprindeville(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/501 -gerrit commit ba5be2861e5adcc3cb990cc219e4207947beefde Author: Philip Prindeville <philipp(a)redfish-solutions.com> Date: Fri Dec 23 18:09:25 2011 -0700 cb_parse_header() should not assume table in 4K of contiguous memory If we have the CB table in E820 memory, we might not have an entire 4K (0x1000) bytes of memory to scan through. Instead, a better strategy is to pass in a pointer to the end of the region or the start + 4K (which ever is lower). This change prepares the cb_parse_header() calling convention for that change. Change-Id: I9257726c6a7065b5596d4c32ab451edd0a3cdc10 Signed-off-by: Philip Prindeville <philipp(a)redfish-solutions.com> --- payloads/libpayload/arch/i386/coreboot.c | 22 ++++++++++++++-------- 1 files changed, 14 insertions(+), 8 deletions(-) diff --git a/payloads/libpayload/arch/i386/coreboot.c b/payloads/libpayload/arch/i386/coreboot.c index 709f8ae..135c59c 100644 --- a/payloads/libpayload/arch/i386/coreboot.c +++ b/payloads/libpayload/arch/i386/coreboot.c @@ -109,21 +109,21 @@ static void cb_parse_framebuffer(void *ptr, struct sysinfo_t *info) } #endif -static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) +static int cb_parse_header(void *addr, void *end, struct sysinfo_t *info) { struct cb_header *header; - unsigned char *ptr = addr; + unsigned char *ptr; void *forward; int i; - for (i = 0; i < len; i += 16, ptr += 16) { + for (ptr = addr; (void *)ptr < end; ptr += 16) { header = (struct cb_header *)ptr; if (!strncmp((const char *)header->signature, "LBIO", 4)) break; } /* We walked the entire space and didn't find anything. */ - if (i >= len) + if ((void *)ptr >= end) return -1; if (!header->table_bytes) @@ -147,7 +147,7 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) switch (rec->tag) { case CB_TAG_FORWARD: forward = phys_to_virt((void *)(unsigned long)((struct cb_forward *)rec)->forward); - return cb_parse_header(forward, len, info); + return cb_parse_header(forward, forward + 0x1000, info); continue; case CB_TAG_MEMORY: cb_parse_memory(ptr, info); @@ -176,6 +176,9 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) } ptr += rec->size; + + if ((void *)ptr >= end) + return -1; } return 1; @@ -186,10 +189,13 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) int get_coreboot_info(struct sysinfo_t *info) { - int ret = cb_parse_header(phys_to_virt(0x00000000), 0x1000, info); + void *base = phys_to_virt(0x00000000); + int ret = cb_parse_header(base, base + 0x1000, info); - if (ret != 1) - ret = cb_parse_header(phys_to_virt(0x000f0000), 0x1000, info); + if (ret != 1) { + base = phys_to_virt(0x000f0000); + ret = cb_parse_header(base, base + 0x1000, info); + } return (ret == 1) ? 0 : -1; }

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Patch set updated for coreboot: c12bc24 Cleanup access to vendor/part # info
by Philip Prindeville 06 Jan '12

06 Jan '12

Philip Prindeville (pprindeville(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/502 -gerrit commit c12bc24e681e14e75699c65d3aa6575a76b89f62 Author: Philip Prindeville <philipp(a)redfish-solutions.com> Date: Sat Dec 24 22:12:37 2011 -0700 Cleanup access to vendor/part # info Instead of macros to access MAINBOARD record, use convenience functions. Store pointers to MAINBOARD and HEADER for use outside of CB code. Change-Id: I074e3a0df7d25726cbd942538bfdc5a63dd17e12 Signed-off-by: Philip Prindeville <philipp(a)redfish-solutions.com> --- payloads/coreinfo/coreboot_module.c | 4 ++-- payloads/libpayload/arch/i386/coreboot.c | 5 +++++ payloads/libpayload/include/coreboot_tables.h | 16 ++++++++++------ payloads/libpayload/include/sysinfo.h | 3 +++ 4 files changed, 20 insertions(+), 8 deletions(-) diff --git a/payloads/coreinfo/coreboot_module.c b/payloads/coreinfo/coreboot_module.c index 7289366..d33ea9e 100644 --- a/payloads/coreinfo/coreboot_module.c +++ b/payloads/coreinfo/coreboot_module.c @@ -142,8 +142,8 @@ static void parse_mainboard(unsigned char *ptr) { struct cb_mainboard *mb = (struct cb_mainboard *)ptr; - strncpy(cb_info.vendor, (const char *)MB_VENDOR_STRING(mb), 31); - strncpy(cb_info.part, (const char *)MB_PART_STRING(mb), 31); + strncpy(cb_info.vendor, cb_mb_vendor_part(mb), 31); + strncpy(cb_info.part, cb_mb_part_string(mb), 31); } static void parse_strings(unsigned char *ptr) diff --git a/payloads/libpayload/arch/i386/coreboot.c b/payloads/libpayload/arch/i386/coreboot.c index 135c59c..7fe286e 100644 --- a/payloads/libpayload/arch/i386/coreboot.c +++ b/payloads/libpayload/arch/i386/coreboot.c @@ -137,6 +137,8 @@ static int cb_parse_header(void *addr, void *end, struct sysinfo_t *info) header->table_bytes) != header->table_checksum) return -1; + info->header = header; + /* Now, walk the tables. */ ptr += header->header_bytes; @@ -173,6 +175,9 @@ static int cb_parse_header(void *addr, void *end, struct sysinfo_t *info) cb_parse_framebuffer(ptr, info); break; #endif + case CB_TAG_MAINBOARD: + info->mainboard = (struct cb_mainboard *)ptr; + break; } ptr += rec->size; diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index e362d06..c68ccc9 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -228,6 +228,16 @@ static inline u16 cb_checksum(const void *ptr, unsigned len) return ipchksum(ptr, len); } +static inline const char *cb_mb_vendor_string(const struct cb_mainboard *cbm) +{ + return (char *)(cbm->strings + cbm->vendor_idx); +} + +static inline const char *cb_mb_part_string(const struct cb_mainboard *cbm) +{ + return (char *)(cbm->strings + cbm->part_number_idx); +} + /* Helpful macros */ #define MEM_RANGE_COUNT(_rec) \ @@ -237,10 +247,4 @@ static inline u16 cb_checksum(const void *ptr, unsigned len) (void *)(((u8 *) (_rec)) + sizeof(*(_rec)) \ + (sizeof((_rec)->map[0]) * (_idx))) -#define MB_VENDOR_STRING(_mb) \ - (((unsigned char *) ((_mb)->strings)) + (_mb)->vendor_idx) - -#define MB_PART_STRING(_mb) \ - (((unsigned char *) ((_mb)->strings)) + (_mb)->part_number_idx) - #endif diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index c1d2002..778dfe9 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -56,6 +56,9 @@ struct sysinfo_t { struct cb_framebuffer *framebuffer; unsigned long *mbtable; /** Pointer to the multiboot table */ + + struct cb_header *header; + struct cb_mainboard *mainboard; }; extern struct sysinfo_t lib_sysinfo;

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Patch set updated for coreboot: c3a4a42 cb_parse_header() should not assume table in 4K of contiguous memory
by Philip Prindeville 06 Jan '12

06 Jan '12

Philip Prindeville (pprindeville(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/501 -gerrit commit c3a4a4242a4c9d428638f271e95ed6d6d8cde2d4 Author: Philip Prindeville <philipp(a)redfish-solutions.com> Date: Fri Dec 23 18:09:25 2011 -0700 cb_parse_header() should not assume table in 4K of contiguous memory If we have the CB table in E820 memory, we might not have an entire 4K (0x1000) bytes of memory to scan through. Instead, a better strategy is to pass in a pointer to the end of the region or the start + 4K (which ever is lower). This change prepares the cb_parse_header() calling convention for that change. Change-Id: I9257726c6a7065b5596d4c32ab451edd0a3cdc10 Signed-off-by: Philip Prindeville <philipp(a)redfish-solutions.com> --- payloads/libpayload/arch/i386/coreboot.c | 22 ++++++++++++++-------- 1 files changed, 14 insertions(+), 8 deletions(-) diff --git a/payloads/libpayload/arch/i386/coreboot.c b/payloads/libpayload/arch/i386/coreboot.c index 709f8ae..135c59c 100644 --- a/payloads/libpayload/arch/i386/coreboot.c +++ b/payloads/libpayload/arch/i386/coreboot.c @@ -109,21 +109,21 @@ static void cb_parse_framebuffer(void *ptr, struct sysinfo_t *info) } #endif -static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) +static int cb_parse_header(void *addr, void *end, struct sysinfo_t *info) { struct cb_header *header; - unsigned char *ptr = addr; + unsigned char *ptr; void *forward; int i; - for (i = 0; i < len; i += 16, ptr += 16) { + for (ptr = addr; (void *)ptr < end; ptr += 16) { header = (struct cb_header *)ptr; if (!strncmp((const char *)header->signature, "LBIO", 4)) break; } /* We walked the entire space and didn't find anything. */ - if (i >= len) + if ((void *)ptr >= end) return -1; if (!header->table_bytes) @@ -147,7 +147,7 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) switch (rec->tag) { case CB_TAG_FORWARD: forward = phys_to_virt((void *)(unsigned long)((struct cb_forward *)rec)->forward); - return cb_parse_header(forward, len, info); + return cb_parse_header(forward, forward + 0x1000, info); continue; case CB_TAG_MEMORY: cb_parse_memory(ptr, info); @@ -176,6 +176,9 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) } ptr += rec->size; + + if ((void *)ptr >= end) + return -1; } return 1; @@ -186,10 +189,13 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) int get_coreboot_info(struct sysinfo_t *info) { - int ret = cb_parse_header(phys_to_virt(0x00000000), 0x1000, info); + void *base = phys_to_virt(0x00000000); + int ret = cb_parse_header(base, base + 0x1000, info); - if (ret != 1) - ret = cb_parse_header(phys_to_virt(0x000f0000), 0x1000, info); + if (ret != 1) { + base = phys_to_virt(0x000f0000); + ret = cb_parse_header(base, base + 0x1000, info); + } return (ret == 1) ? 0 : -1; }

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Patch set updated for coreboot: 33dd7a8 geos: Explicitly set console baud rate
by Philip Prindeville 06 Jan '12

06 Jan '12

Philip Prindeville (pprindeville(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/513 -gerrit commit 33dd7a89e6c3214947ed8cc879819e6c89b0f6e3 Author: Philip Prindeville <philipp(a)redfish-solutions.com> Date: Sat Dec 31 19:29:21 2011 -0700 geos: Explicitly set console baud rate If the default baud rate changes, we should remain compatible with earlier published coreboot images. Change-Id: I4e6b5515395a9de237ad8f758f6f66fb825262eb Signed-off-by: Philip Prindeville <philipp(a)redfish-solutions.com> --- src/mainboard/traverse/geos/Kconfig | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/mainboard/traverse/geos/Kconfig b/src/mainboard/traverse/geos/Kconfig index dd6c8dd..b455f60 100644 --- a/src/mainboard/traverse/geos/Kconfig +++ b/src/mainboard/traverse/geos/Kconfig @@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select UDELAY_TSC select BOARD_ROMSIZE_KB_1024 select POWER_BUTTON_DEFAULT_DISABLE + select CONSOLE_SERIAL_115200 config MAINBOARD_DIR string

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coreboot January 2012