coreboot January 2012

coreboot@coreboot.org

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Patch set updated for coreboot: 8718691 geos: missing Vendor information
by Philip Prindeville 08 Jan '12

08 Jan '12

Philip Prindeville (philipp(a)redfish-solutions.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/520 -gerrit commit 87186912502c19bec6f24febed5dc64f905bb08f Author: Philip Prindeville <philipp(a)redfish-solutions.com> Date: Fri Jan 6 11:52:25 2012 -0700 geos: missing Vendor information The DMI information isn't being generated correctly because of the mainboard vendor value not being set. Change-Id: I07a6620bc6938292fecd50dc3ff0cb926d9c5f97 Signed-off-by: Philip Prindeville <philipp(a)redfish-solutions.com> --- src/mainboard/traverse/geos/Kconfig | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/src/mainboard/traverse/geos/Kconfig b/src/mainboard/traverse/geos/Kconfig index dd6c8dd..184beee 100644 --- a/src/mainboard/traverse/geos/Kconfig +++ b/src/mainboard/traverse/geos/Kconfig @@ -16,6 +16,10 @@ config MAINBOARD_DIR string default traverse/geos +config MAINBOARD_VENDOR + string + default "PC Engines" + config MAINBOARD_PART_NUMBER string default "Geos"

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Patch set updated for coreboot: cc32bd5 Set default baudrate on Alix2d to be compatible with factory default
by Philip Prindeville 08 Jan '12

08 Jan '12

Philip Prindeville (philipp(a)redfish-solutions.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/508 -gerrit commit cc32bd53cd174d32726186b107436edc699bd842 Author: Philip Prindeville <philipp(a)redfish-solutions.com> Date: Wed Dec 28 16:32:44 2011 -0700 Set default baudrate on Alix2d to be compatible with factory default Boards shipping from PC Engines with the factory BIOS (tinyBios 0.99) boot up at 38400. In keeping with the principle of least astonishment, boards reflashed with SeaBIOS should probably try to keep compatible with this setting. Change-Id: Ieda47016c78e673ce2f6aec8b270c2b511ebfcf0 Signed-off-by: Philip Prindeville <philipp(a)redfish-solutions.com> --- src/mainboard/pcengines/alix2d/Kconfig | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/mainboard/pcengines/alix2d/Kconfig b/src/mainboard/pcengines/alix2d/Kconfig index 264f5d9..ea02adf 100644 --- a/src/mainboard/pcengines/alix2d/Kconfig +++ b/src/mainboard/pcengines/alix2d/Kconfig @@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select UDELAY_TSC select BOARD_ROMSIZE_KB_512 select POWER_BUTTON_FORCE_DISABLE + select CONSOLE_SERIAL_38400 config MAINBOARD_DIR string

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Patch merged into coreboot/master: 396b232 rs780: correct comment in switching_gpp_configurations()
by gerrit＠coreboot.org 08 Jan '12

08 Jan '12

the following patch was just integrated into master: commit 396b2325b1bf5d5986a6377052f00b9cb7d2ecec Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Sat Jan 7 10:17:50 2012 -0600 rs780: correct comment in switching_gpp_configurations() Change-Id: I6417a92523eea7307d080669fbc4e16ee28c8a6c Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Build-Tested: build bot (Jenkins) at Sat Jan 7 17:28:51 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Sun Jan 8 20:42:55 2012, giving +2 See http://review.coreboot.org/524 for details. -gerrit

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Patch merged into coreboot/master: 9faab44 adm1027: add return statement
by gerrit＠coreboot.org 08 Jan '12

08 Jan '12

the following patch was just integrated into master: commit 9faab4477efb6d0102c9854dcc1ecd3f1cac6421 Author: Vikram Narayanan <vikram186(a)gmail.com> Date: Sat Jan 7 16:04:46 2012 +0530 adm1027: add return statement Adds a missing return statment which will stop misleading the users Change-Id: I53741f1136b396e9493ce959b54efc00c9b09764 Signed-off-by: Vikram Narayanan <vikram186(a)gmail.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Sat Jan 7 18:45:32 2012, giving +1 Build-Tested: build bot (Jenkins) at Sat Jan 7 12:31:23 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Sun Jan 8 20:42:07 2012, giving +2 See http://review.coreboot.org/522 for details. -gerrit

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Patch merged into coreboot/master: 2ae66cb inteltool: Add support for dumping AMB registers
by gerrit＠coreboot.org 08 Jan '12

08 Jan '12

the following patch was just integrated into master: commit 2ae66cb092deb642a0d22ed80f73d3411a51c696 Author: Sven Schnelle <svens(a)stackframe.org> Date: Sun Jan 8 15:27:18 2012 +0100 inteltool: Add support for dumping AMB registers Change-Id: I98615725afdb315caa67b2226224e3eb2a0e4393 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Build-Tested: build bot (Jenkins) at Sun Jan 8 16:08:24 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Sun Jan 8 20:41:08 2012, giving +2 See http://review.coreboot.org/525 for details. -gerrit

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New patch to review for coreboot: 2ae66cb inteltool: Add support for dumping AMB registers
by Sven Schnelle 08 Jan '12

08 Jan '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/525 -gerrit commit 2ae66cb092deb642a0d22ed80f73d3411a51c696 Author: Sven Schnelle <svens(a)stackframe.org> Date: Sun Jan 8 15:27:18 2012 +0100 inteltool: Add support for dumping AMB registers Change-Id: I98615725afdb315caa67b2226224e3eb2a0e4393 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- util/inteltool/Makefile | 2 +- util/inteltool/amb.c | 469 ++++++++++++++++++++++++++++++++++++++++++++ util/inteltool/inteltool.c | 16 ++- util/inteltool/inteltool.h | 6 + 4 files changed, 490 insertions(+), 3 deletions(-) diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile index db7fca0..6a01173 100644 --- a/util/inteltool/Makefile +++ b/util/inteltool/Makefile @@ -27,7 +27,7 @@ PREFIX = /usr/local CFLAGS = -O2 -g -Wall -W LDFLAGS = -lpci -lz -OBJS = inteltool.o cpu.o gpio.o rootcmplx.o powermgt.o memory.o pcie.o +OBJS = inteltool.o cpu.o gpio.o rootcmplx.o powermgt.o memory.o pcie.o amb.o OS_ARCH = $(shell uname) ifeq ($(OS_ARCH), Darwin) diff --git a/util/inteltool/amb.c b/util/inteltool/amb.c new file mode 100644 index 0000000..a3ee01d --- /dev/null +++ b/util/inteltool/amb.c @@ -0,0 +1,469 @@ +/* + * inteltool - dump all registers on an Intel CPU + chipset based system. + * + * Copyright (C) 2012 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + + +#include <stdio.h> +#include <stdlib.h> +#include "inteltool.h" + +#define AMB_CONFIG_SPACE_SIZE 0x20000 + +#define AMB_ADDR(base, fn, reg) (base | ((fn & 7) << 8) | ((reg & 0xff))) + +static uint32_t amb_read_config32(volatile void *base, int fn, int reg) +{ + return *(uint32_t *)(AMB_ADDR((uint64_t)base, fn, reg)); +} + +static void amb_printreg32(volatile void *base, int fn, int reg, + const char *name, int printzero) +{ + uint32_t val = amb_read_config32(base, fn, reg); + if (!val && !printzero) + return; + printf("%d:%2.2x %-16.16s: 0x%08x\n", fn, reg, name, val); +} + +static uint16_t amb_read_config16(volatile void *base, int fn, int reg) +{ + return *(uint16_t *)(AMB_ADDR((uint64_t)base, fn, reg)); +} + +static void amb_printreg16(volatile void *base, int fn, int reg, + const char *name, int printzero) +{ + uint16_t val = amb_read_config16(base, fn, reg); + if (!val && !printzero) + return; + printf("%d:%2.2x %-16.16s: 0x%04x\n", fn, reg, name, val); + +} + +static uint8_t amb_read_config8(volatile void *base, int fn, int reg) +{ + return *(uint8_t *)(AMB_ADDR((uint64_t)base, fn, reg)); +} + +static void amb_printreg8(volatile void *base, int fn, int reg, + const char *name, int printzero) +{ + uint8_t val = amb_read_config8(base, fn, reg); + if (!val && !printzero) + return; + printf("%d:%2.2x %-16.16s: 0x%02x\n", fn, reg, name, val); + +} + +static void amb_printreg24(volatile void *base, int fn, int reg, + const char *name, int printzero) +{ + uint32_t val; + + if (reg & 1) { + val = amb_read_config8(base, fn, reg) | + (amb_read_config16(base, fn, reg + 1) << 8); + } else { + val = amb_read_config16(base, fn, reg) | + (amb_read_config8(base, fn, reg + 2) << 16); + } + + if (!val && !printzero) + return; + + printf("%d:%2.2x %-16.16s: 0x%06x\n", fn, reg, name, val); +} + + +struct amb_register { + int fn; + int offset; + const char *name; + void (*printfunc)(volatile void *, int, int, const char *, int); + int width; +} amb_registers[] = { + { 0, 0x00, "VID", NULL, 2 }, + { 0, 0x02, "DID", NULL, 2 }, + { 0, 0x08, "RID", NULL, 1 }, + { 0, 0x09, "CCR", NULL, 3 }, + { 0, 0x0e, "HDR", NULL, 1 }, + { 1, 0x40, "FBDS0", NULL, 1 }, + { 1, 0x41, "FBDS1", NULL, 1 }, + { 1, 0x42, "FBDS2", NULL, 1 }, + { 1, 0x43, "FBDS3", NULL, 1 }, + { 1, 0x50, "FBDSBCFGCUR", NULL, 1 }, + { 1, 0x51, "FBDNBCFGCUR", NULL, 1 }, + { 1, 0x52, "LINKPARCUR", NULL, 2 }, + { 1, 0x54, "FBDSBCFGNXT", NULL, 1 }, + { 1, 0x55, "FBDNBCFGNXT", NULL, 1 }, + { 1, 0x56, "LINKPARNXT", NULL, 2 }, + { 1, 0x5a, "SBRXMAR", NULL, 1 }, + { 1, 0x5b, "NBRXMAR", NULL, 1 }, + { 1, 0x5c, "MODES", NULL, 1 }, + { 1, 0x60, "FEATURES", NULL, 2 }, + { 1, 0x64, "FBDLIS", NULL, 3 }, + { 1, 0x68, "FBDLOCKTO", NULL, 2 }, + { 1, 0x6c, "FBDHAC", NULL, 1 }, + { 1, 0x6e, "FBDLS", NULL, 1 }, + { 1, 0x70, "RECALDUR", NULL, 1 }, + { 1, 0x74, "LOSDUR", NULL, 1 }, + { 1, 0x78, "SYNCTRAININT", NULL, 1 }, + { 1, 0x7c, "SBCALSTATUS", NULL, 2 }, + { 1, 0x7e, "NBCALSTATUS", NULL, 2 }, + { 1, 0x88, "CBC", NULL, 1 }, + { 1, 0x8c, "EMASK", NULL, 1 }, + { 1, 0x90, "FERR", NULL, 1 }, + { 1, 0x94, "NERR", NULL, 1 }, + { 1, 0x98, "RECCFG", NULL, 2 }, + { 1, 0x9c, "RECFBD0", NULL, 2 }, + { 1, 0x9e, "RECFBD1", NULL, 2 }, + { 1, 0xa0, "RECFBD2", NULL, 2 }, + { 1, 0xa2, "RECFBD3", NULL, 2 }, + { 1, 0xa4, "RECFBD4", NULL, 2 }, + { 1, 0xa6, "RECFBD5", NULL, 2 }, + { 1, 0xa8, "RECFBD6", NULL, 2 }, + { 1, 0xaa, "RECFBD7", NULL, 2 }, + { 1, 0xac, "RECFBD8", NULL, 2 }, + { 1, 0xae, "RECFBD9", NULL, 2 }, + { 1, 0xb0, "PERSBYTE0NXT", NULL, 1 }, + { 1, 0xb1, "PERSBYTE1NXT", NULL, 1 }, + { 1, 0xb2, "PERSBYTE2NXT", NULL, 1 }, + { 1, 0xb3, "PERSBYTE3NXT", NULL, 1 }, + { 1, 0xb4, "PERSBYTE4NXT", NULL, 1 }, + { 1, 0xb5, "PERSBYTE5NXT", NULL, 1 }, + { 1, 0xb6, "PERSBYTE6NXT", NULL, 1 }, + { 1, 0xb7, "PERSBYTE7NXT", NULL, 1 }, + { 1, 0xb8, "PERSBYTE8NXT", NULL, 1 }, + { 1, 0xb9, "PERSBYTE9NXT", NULL, 1 }, + { 1, 0xba, "PERSBYTE10NXT", NULL, 1 }, + { 1, 0xbb, "PERSBYTE11NXT", NULL, 1 }, + { 1, 0xbc, "PERSBYTE12NXT", NULL, 1 }, + { 1, 0xbd, "PERSBYTE13NXT", NULL, 1 }, + { 1, 0xc0, "PERSBYTE0CUR", NULL, 1 }, + { 1, 0xc1, "PERSBYTE1CUR", NULL, 1 }, + { 1, 0xc2, "PERSBYTE2CUR", NULL, 1 }, + { 1, 0xc3, "PERSBYTE3CUR", NULL, 1 }, + { 1, 0xc4, "PERSBYTE4CUR", NULL, 1 }, + { 1, 0xc5, "PERSBYTE5CUR", NULL, 1 }, + { 1, 0xc6, "PERSBYTE6CUR", NULL, 1 }, + { 1, 0xc7, "PERSBYTE7CUR", NULL, 1 }, + { 1, 0xc8, "PERSBYTE8CUR", NULL, 1 }, + { 1, 0xc9, "PERSBYTE9CUR", NULL, 1 }, + { 1, 0xca, "PERSBYTE10CUR", NULL, 1 }, + { 1, 0xcb, "PERSBYTE11CUR", NULL, 1 }, + { 1, 0xcc, "PERSBYTE12CUR", NULL, 1 }, + { 1, 0xcd, "PERSBYTE13CUR", NULL, 1 }, + { 1, 0xe8, "CMD2DATANXT", NULL, 1 }, + { 1, 0xe9, "CMD2DATACUR", NULL, 1 }, + { 1, 0xea, "C2DINCRNXT", NULL, 1 }, + { 1, 0xeb, "C2DINCRCUR", NULL, 1 }, + { 1, 0xec, "C2DDECRNXT", NULL, 1 }, + { 1, 0xed, "C2DDECRCUR", NULL, 1 }, + { 2, 0x40, "SBDRVCFG", NULL, 1 }, + { 2, 0x41, "NBDRVCFG", NULL, 1 }, + { 2, 0x42, "FBDPDCFG", NULL, 1 }, + { 2, 0x44, "RTERMCFG", NULL, 3 }, + { 2, 0x47, "IDTCTRLCFG", NULL, 1 }, + { 2, 0x48, "FBDBUFCFG", NULL, 1 }, + { 2, 0x50, "SBRQOFFS0", NULL, 1 }, + { 2, 0x51, "SBRQOFFS1", NULL, 1 }, + { 2, 0x52, "SBRQOFFS2", NULL, 1 }, + { 2, 0x53, "SBRQOFFS3", NULL, 1 }, + { 2, 0x54, "SBRQOFFS4", NULL, 1 }, + { 2, 0x55, "SBRQOFFS5", NULL, 1 }, + { 2, 0x56, "SBRQOFFS6", NULL, 1 }, + { 2, 0x57, "SBRQOFFS7", NULL, 1 }, + { 2, 0x58, "SBRQOFFS8", NULL, 1 }, + { 2, 0x59, "SBRQOFFS9", NULL, 1 }, + + { 2, 0x60, "NBRQOFFS0", NULL, 1 }, + { 2, 0x61, "NBRQOFFS1", NULL, 1 }, + { 2, 0x62, "NBRQOFFS2", NULL, 1 }, + { 2, 0x63, "NBRQOFFS3", NULL, 1 }, + { 2, 0x64, "NBRQOFFS4", NULL, 1 }, + { 2, 0x65, "NBRQOFFS5", NULL, 1 }, + { 2, 0x66, "NBRQOFFS6", NULL, 1 }, + { 2, 0x67, "NBRQOFFS7", NULL, 1 }, + { 2, 0x68, "NBRQOFFS8", NULL, 1 }, + { 2, 0x69, "NBRQOFFS9", NULL, 1 }, + { 2, 0x6a, "NBRQOFFS10", NULL, 1 }, + { 2, 0x6b, "NBRQOFFS11", NULL, 1 }, + { 2, 0x6c, "NBRQOFFS12", NULL, 1 }, + { 2, 0x6d, "NBRQOFFS13", NULL, 1 }, + { 2, 0x90, "TESTCFG", NULL, 1 }, + { 2, 0x94, "SBTXENCFG", NULL, 2 }, + { 2, 0x96, "NBTXENCFG", NULL, 2 }, + { 2, 0x98, "IDLEDETCFG", NULL, 2 }, + { 2, 0xa4, "SBRXSTATUS", NULL, 4 }, + { 2, 0xa8, "SBRXSTATUS", NULL, 1 }, + { 3, 0x3c, "MBIDT", NULL, 1 }, + { 3, 0x40, "MBCSR", NULL, 4 }, + { 3, 0x44, "MBADDR", NULL, 4 }, + { 3, 0x40, "MBDATA0", NULL, 4 }, + { 3, 0x41, "MBDATA1", NULL, 4 }, + { 3, 0x42, "MBDATA2", NULL, 4 }, + { 3, 0x43, "MBDATA3", NULL, 4 }, + { 3, 0x44, "MBDATA4", NULL, 4 }, + { 3, 0x45, "MBDATA5", NULL, 4 }, + { 3, 0x46, "MBDATA6", NULL, 4 }, + { 3, 0x47, "MBDATA7", NULL, 4 }, + { 3, 0x48, "MBDATA8", NULL, 4 }, + { 3, 0x49, "MBDATA9", NULL, 4 }, + { 3, 0x70, "DAREFTC", NULL, 4 }, + { 3, 0x74, "DSREFTC", NULL, 3 }, + { 3, 0x77, "MTR", NULL, 1 }, + { 3, 0x78, "DRT", NULL, 4 }, + { 3, 0x7c, "DRC", NULL, 4 }, + { 3, 0x80, "TEMPLO", NULL, 1 }, + { 3, 0x81, "TEMPMID", NULL, 1 }, + { 3, 0x82, "TEMPHI", NULL, 1 }, + { 3, 0x83, "UPDATED", NULL, 1 }, + { 3, 0x84, "TEMPSTAT", NULL, 1 }, + { 3, 0x85, "TEMP", NULL, 1 }, + { 3, 0x86, "TEMPOFFSET", NULL, 1 }, + { 3, 0x9c, "MB_START_ADDR", NULL, 4 }, + { 3, 0xa0, "MB_END_ADDR", NULL, 4 }, + { 3, 0xa4, "MBLFSRSEED", NULL, 4 }, + { 3, 0xa8, "MBFADDRPTR", NULL, 4 }, + { 3, 0xb0, "MB_ERR_DATA00", NULL, 4 }, + { 3, 0xb4, "MB_ERR_DATA01", NULL, 4 }, + { 3, 0xb8, "MB_ERR_DATA02", NULL, 4 }, + { 3, 0xbc, "MB_ERR_DATA03", NULL, 4 }, + { 3, 0xc0, "MB_ERR_DATA04", NULL, 2 }, + { 3, 0xc4, "MB_ERR_DATA10", NULL, 4 }, + { 3, 0xc8, "MB_ERR_DATA11", NULL, 4 }, + { 3, 0xcc, "MB_ERR_DATA12", NULL, 4 }, + { 3, 0xd0, "MB_ERR_DATA13", NULL, 4 }, + { 3, 0xd4, "MB_ERR_DATA14", NULL, 2 }, + + { 4, 0x40, "DCALCSR", NULL, 4 }, + { 4, 0x44, "DCALADDR", NULL, 4 }, + { 4, 0x98, "DSRETC", NULL, 4 }, + { 4, 0xa4, "S3RESTORE0", NULL, 4 }, + { 4, 0xa8, "S3RESTORE1", NULL, 4 }, + { 4, 0xac, "S3RESTORE2", NULL, 4 }, + { 4, 0xb0, "S3RESTORE3", NULL, 4 }, + { 4, 0xb4, "S3RESTORE4", NULL, 4 }, + { 4, 0xb8, "S3RESTORE5", NULL, 4 }, + { 4, 0xbc, "S3RESTORE6", NULL, 4 }, + { 4, 0xc0, "S3RESTORE7", NULL, 4 }, + { 4, 0xc4, "S3RESTORE8", NULL, 4 }, + { 4, 0xc8, "S3RESTORE9", NULL, 4 }, + { 4, 0xcc, "S3RESTORE10", NULL, 4 }, + { 4, 0xe8, "FIVESREG", NULL, 4 }, + { 4, 0xea, "AAAAREG", NULL, 4 }, + + { 5, 0x3c, "TRANSCFG", NULL, 4 }, + { 5, 0x40, "TRANDERR0", NULL, 2 }, + { 5, 0x42, "TRANDERR1", NULL, 2 }, + { 5, 0x44, "TRANDERR2", NULL, 2 }, + { 5, 0x46, "TRANDERR3", NULL, 2 }, + { 5, 0x48, "TRANDERR4", NULL, 2 }, + { 5, 0x4a, "TRANDERR5", NULL, 2 }, + { 5, 0x4c, "TRANDERR6", NULL, 2 }, + { 5, 0x4e, "TRANDERR7", NULL, 2 }, + { 5, 0x50, "TRANDERR8", NULL, 2 }, + { 5, 0x80, "TRANSCTRL", NULL, 1 }, + { 5, 0xbc, "SBMATCHU", NULL, 3 }, + { 5, 0xc0, "SBMATCHL0", NULL, 4 }, + { 5, 0xcc, "SBMASKU", NULL, 3 }, + { 5, 0xd0, "SBMASKL0", NULL, 4 }, + { 5, 0xe0, "EVENTSEL0", NULL, 3 }, + { 5, 0xfc, "EICNTL", NULL, 1 }, + { 5, 0xfe, "STUCKL", NULL, 1 }, + + { 6, 0x50, "NBRXSTATUS", NULL, 4 }, + { 6, 0x7c, "SPAD0", NULL, 4 }, + { 6, 0x80, "SBFIBPORTCTL", NULL, 4 }, + { 6, 0x84, "SBFIBPGCTL", NULL, 4 }, + { 6, 0x88, "SBFIBPATTBUF1", NULL, 3 }, + { 6, 0x8c, "SBFIBTXMSK", NULL, 2 }, + { 6, 0x90, "SBFIBRXMSK", NULL, 2 }, + { 6, 0x94, "SBFIBTXSHFT", NULL, 2 }, + { 6, 0x98, "SBFIBRXSHFT", NULL, 2 }, + { 6, 0x9c, "SBFIBRXLNERR", NULL, 2 }, + { 6, 0xa0, "SBFIBPATTBUF2", NULL, 3 }, + { 6, 0xa4, "SBFIBPATT2EN", NULL, 2 }, + { 6, 0xb0, "SBFIBINIT", NULL, 4 }, + { 6, 0xb4, "SBIBISTMISC", NULL, 3 }, + { 6, 0xc0, "NBFIBPORTCTL", NULL, 4 }, + { 6, 0xc4, "NBFIBPGCTL", NULL, 4 }, + { 6, 0xc8, "NBFIBPATTBUF1", NULL, 3 }, + { 6, 0xcc, "NBFIBTXMSK", NULL, 2 }, + { 6, 0xd0, "NBFIBRXMSK", NULL, 2 }, + { 6, 0xd4, "NBFIBTXSHFT", NULL, 2 }, + { 6, 0xd8, "NBFIBRXSHFT", NULL, 2 }, + { 6, 0xdc, "NBFIBRXLNERR", NULL, 2 }, + { 6, 0xe0, "NBFIBPATTBUF2", NULL, 3 }, + { 6, 0xe4, "NBFIBPATT2EN", NULL, 2 }, + { 6, 0xf0, "NBFIBINIT", NULL, 4 }, + { 6, 0xf4, "NBIBISTMISC", NULL, 3 }, + + { 7, 0x40, "ODRV_ADJ_ADDR_A", NULL, 3 }, + { 7, 0x43, "ODRV_ADJ_CAS_A", NULL, 3 }, + { 7, 0x46, "ODRV_ADJ_CKE_A", NULL, 3 }, + { 7, 0x49, "ODRV_ADJ_ODT_A", NULL, 3 }, + { 7, 0x4c, "ODRV_ADJ_ADDR_B", NULL, 3 }, + { 7, 0x4f, "ODRV_ADJ_CAS_B", NULL, 3 }, + { 7, 0x52, "ODRV_ADJ_CKE_B", NULL, 3 }, + { 7, 0x55, "ODRV_ADJ_ODT_B", NULL, 3 }, + { 7, 0x58, "ODRV_ADJ_CLK0", NULL, 3 }, + { 7, 0x5b, "ODRV_ADJ_CLK1", NULL, 3 }, + { 7, 0x5e, "ODRV_ADJ_CLK2", NULL, 3 }, + { 7, 0x61, "ODRV_ADJ_CLK3", NULL, 3 }, + { 7, 0x64, "ODRV_ADJ_DQ_DQS", NULL, 3 }, + { 7, 0x67, "DDR_ODTCTL", NULL, 1 }, + { 7, 0x69, "DDR_ZCAL", NULL, 2 }, + { 7, 0x6c, "DDR_ZCTL", NULL, 4 }, + { 7, 0x78, "VHOSTCNTL", NULL, 1 }, + { 7, 0x79, "DQSDLY_SMBUSCTL", NULL, 1 }, + { 7, 0x7c, "SPAD1", NULL, 4 }, + { 7, 0x80, "CTL_ADDR_A", NULL, 1 }, + { 7, 0x81, "CTL_CAS_A", NULL, 1 }, + { 7, 0x82, "CTL_CKE_A", NULL, 1 }, + { 7, 0x83, "CTL_ODT_A", NULL, 1 }, + { 7, 0x84, "CTL_ADDR_B", NULL, 1 }, + { 7, 0x85, "CTL_CAS_B", NULL, 1 }, + { 7, 0x86, "CTL_CKE_B", NULL, 1 }, + { 7, 0x87, "CTL_ODT_B", NULL, 1 }, + { 7, 0x88, "CTL_CLK0", NULL, 1 }, + { 7, 0x89, "CTL_CLK1", NULL, 1 }, + { 7, 0x8a, "CTL_CLK2", NULL, 1 }, + { 7, 0x8b, "CTL_CLK3", NULL, 1 }, + { 7, 0x8c, "CTL_DQ", NULL, 1 }, + { 7, 0x8d, "CTL_DQS", NULL, 1 }, + { 0, 0x00, NULL, NULL, 0 }, +}; + +static void dump_amb(volatile void *ambconfig, int branch, int channel, int amb) +{ + struct amb_register *reg; + static int lastreg, lastfn; + int bytes; + + volatile void *base = ambconfig + \ + ((branch << 16) | (channel << 15) | (amb << 11)); + + if ((amb_read_config32(base, 0, 0) == 0xffffffff) | + (amb_read_config32(base, 0, 0) == 0x00000000)) + return; + + printf("AMB %d, branch %d, channel %d register dump:\n" + "============================================\n", + amb, branch, channel); + + for(reg = amb_registers; reg->name; reg++) { + if (reg->fn == lastfn && reg->offset > 0 && reg->offset - lastreg) { + bytes = reg->offset - lastreg; + + do { + if (!(lastreg & 3) && bytes >= 4) { + amb_printreg32(base, reg->fn, lastreg, "RESERVED", 0); + bytes -= 4; + lastreg += 4; + } else if (!(lastreg & 1) && bytes >= 2) { + amb_printreg16(base, reg->fn, lastreg, "RESERVED", 0); + bytes -= 2; + lastreg += 2; + } else { + amb_printreg8(base, reg->fn, lastreg, "RESERVED", 0); + bytes -= 1; + lastreg += 1; + } + } while(bytes > 0); + } + + switch(reg->width) { + case 1: + amb_printreg8(base, reg->fn, reg->offset, reg->name, 1); + break; + case 2: + amb_printreg16(base, reg->fn, reg->offset, reg->name, 1); + break; + + case 3: + amb_printreg24(base, reg->fn, reg->offset, reg->name, 1); + break; + + case 4: + amb_printreg32(base, reg->fn, reg->offset, reg->name, 1); + break; + + default: + break; + } + + if (reg->printfunc) + reg->printfunc(base, reg->fn, reg->offset, reg->name, 1); + lastreg = reg->offset + reg->width; + lastfn = reg->fn; + } + printf("\n\n"); +} + +int print_ambs(struct pci_dev *dev, struct pci_access *pacc) +{ + struct pci_dev *dev16; + int branch, channel, amb; + int max_branch, max_channel, max_amb; + volatile void *ambconfig; + uint64_t ambconfig_phys; + + printf("\n============= AMBs ============\n\n"); + + switch (dev->device_id) { + case PCI_DEVICE_ID_INTEL_I5000P: + case PCI_DEVICE_ID_INTEL_I5000X: + case PCI_DEVICE_ID_INTEL_I5000Z: + + max_branch = 2; + + if (!(dev16 = pci_get_dev(pacc, 0, 0, 0x10, 0))) { + perror("Error: no device 0:16.0\n"); + return 1; + } + + ambconfig_phys = ((u64)pci_read_long(dev16, 0x4c) << 32) | + pci_read_long(dev16, 0x48); + + max_channel = pci_read_byte(dev16, 0x56)/max_branch; + max_amb = pci_read_byte(dev16, 0x57); + break; + + default: + fprintf(stderr, "Error: Dumping AMBs on this MCH is not (yet) supported.\n"); + return 1; + } + + if (!(ambconfig = map_physical(ambconfig_phys, AMB_CONFIG_SPACE_SIZE))) { + fprintf(stderr, "Error mapping AMB config space\n"); + return 1; + } + + for(branch = 0; branch < max_branch; branch++) { + for(channel = 0; channel < max_channel; channel++) { + for(amb = 0; amb < max_amb; amb++) { + dump_amb(ambconfig, branch, channel, amb); + } + } + } + unmap_physical((void *)ambconfig, AMB_CONFIG_SPACE_SIZE); + return 0; +} + + diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 488d9f5..6b99605 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -83,6 +83,9 @@ static const struct { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X44, "82X38/X48" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_32X0, "3200/3210" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I63XX, "Intel 63xx I/O Controller Hub" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000P, "Intel i5000P Memory Controller Hub" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000X, "Intel i5000X Memory Controller Hub" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000Z, "Intel i5000Z Memory Controller Hub" }, }; #ifndef __DARWIN__ @@ -139,6 +142,7 @@ void print_usage(const char *name) " -d | --dmibar: dump northbridge DMIBAR registers\n" " -P | --pciexpress: dump northbridge PCIEXBAR registers\n\n" " -M | --msrs: dump CPU MSRs\n" + " -A | --ambs: dump AMB registers\n" " -a | --all: dump all known registers\n" "\n"); exit(1); @@ -155,7 +159,7 @@ int main(int argc, char *argv[]) int dump_gpios = 0, dump_mchbar = 0, dump_rcba = 0; int dump_pmbase = 0, dump_epbar = 0, dump_dmibar = 0; - int dump_pciexbar = 0, dump_coremsrs = 0; + int dump_pciexbar = 0, dump_coremsrs = 0, dump_ambs = 0; static struct option long_options[] = { {"version", 0, 0, 'v'}, @@ -168,11 +172,12 @@ int main(int argc, char *argv[]) {"dmibar", 0, 0, 'd'}, {"pciexpress", 0, 0, 'P'}, {"msrs", 0, 0, 'M'}, + {"ambs", 0, 0, 'A'}, {"all", 0, 0, 'a'}, {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "vh?grpmedPMa", + while ((opt = getopt_long(argc, argv, "vh?grpmedPMaA", long_options, &option_index)) != EOF) { switch (opt) { case 'v': @@ -212,6 +217,10 @@ int main(int argc, char *argv[]) dump_dmibar = 1; dump_pciexbar = 1; dump_coremsrs = 1; + dump_ambs = 1; + break; + case 'A': + dump_ambs = 1; break; case 'h': case '?': @@ -356,6 +365,9 @@ int main(int argc, char *argv[]) printf("\n\n"); } + if (dump_ambs) { + print_ambs(nb, pacc); + } /* Clean up */ pci_free_dev(nb); // pci_free_dev(sb); // TODO: glibc detected "double free or corruption" diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 1bfb3d1..c3fa365 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -85,6 +85,11 @@ #define PCI_DEVICE_ID_INTEL_SCH_POULSBO 0x8100 #define PCI_DEVICE_ID_INTEL_ATOM_DXXX 0xa000 #define PCI_DEVICE_ID_INTEL_I63XX 0x2670 + +#define PCI_DEVICE_ID_INTEL_I5000X 0x25d0 +#define PCI_DEVICE_ID_INTEL_I5000Z 0x25d4 +#define PCI_DEVICE_ID_INTEL_I5000P 0x25d8 + /* untested, but almost identical to D-series */ #define PCI_DEVICE_ID_INTEL_ATOM_NXXX 0xa010 @@ -125,3 +130,4 @@ int print_gpios(struct pci_dev *sb); int print_epbar(struct pci_dev *nb); int print_dmibar(struct pci_dev *nb); int print_pciexbar(struct pci_dev *nb); +int print_ambs(struct pci_dev *nb, struct pci_access *pacc);

1 0

New patch to review for coreboot: 396b232 rs780: correct comment in switching_gpp_configurations()
by Jonathan A. Kollasch 07 Jan '12

07 Jan '12

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/524 -gerrit commit 396b2325b1bf5d5986a6377052f00b9cb7d2ecec Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Sat Jan 7 10:17:50 2012 -0600 rs780: correct comment in switching_gpp_configurations() Change-Id: I6417a92523eea7307d080669fbc4e16ee28c8a6c Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/southbridge/amd/rs780/pcie.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/southbridge/amd/rs780/pcie.c b/src/southbridge/amd/rs780/pcie.c index be80ed3..527a710 100644 --- a/src/southbridge/amd/rs780/pcie.c +++ b/src/southbridge/amd/rs780/pcie.c @@ -191,7 +191,7 @@ static void switching_gpp_configurations(device_t nb_dev, device_t sb_dev) reg = nbmisc_read_index(nb_dev, 0x22); reg |= 1 << 14; nbmisc_write_index(nb_dev, 0x22, reg); - /* 5.6.2.2. sets desired GPPSB configurations, bit4-7 */ + /* 5.6.2.2. sets desired GPP configurations, bit7-10 */ reg = nbmisc_read_index(nb_dev, 0x2D); reg &= ~(0xF << 7); /* clean */ reg |= cfg->gpp_configuration << 7;

1 0

Patch merged into coreboot/master: d864203 .gitignore ectool, inteltool, msrtool, nvramtool and superiotool
by gerrit＠coreboot.org 07 Jan '12

07 Jan '12

the following patch was just integrated into master: commit d864203c152312aa8369377943312bb0fe232156 Author: Peter Stuge <peter(a)stuge.se> Date: Wed Dec 14 07:39:57 2011 +0100 .gitignore ectool, inteltool, msrtool, nvramtool and superiotool Change-Id: I06e69d97ef3646f79104ec316ce932cc53894c92 Signed-off-by: Peter Stuge <peter(a)stuge.se> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Sat Jan 7 15:19:30 2012, giving +2 See http://review.coreboot.org/485 for details. -gerrit

1 0

New patch to review for coreboot: 80f420e Add subsystem callbacks for VT8237x and VT890 family of chipsets
by Patrick Georgi 07 Jan '12

07 Jan '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/523 -gerrit commit 80f420e5d626dc84c98196c2b9dd9d58cd3ad1d5 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Fri Apr 22 20:48:21 2011 +0200 Add subsystem callbacks for VT8237x and VT890 family of chipsets Change-Id: Id34615f0c229d276d72cdf984cf82ea8cc1a85bb Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/southbridge/via/k8t890/ctrl.c | 6 +++++- src/southbridge/via/k8t890/dram.c | 8 ++++++-- src/southbridge/via/k8t890/error.c | 6 +++++- src/southbridge/via/k8t890/host.c | 8 ++++++-- src/southbridge/via/k8t890/host_ctrl.c | 8 ++++++-- src/southbridge/via/vt8237r/lpc.c | 14 ++++++++++++++ src/southbridge/via/vt8237r/sata.c | 15 +++++++++++++-- src/southbridge/via/vt8237r/usb.c | 16 ++++++++++++++-- 8 files changed, 69 insertions(+), 12 deletions(-) diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index 6e5dbf7..1ff0b74 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -181,12 +181,16 @@ static void ctrl_init(struct device *dev) } +static struct pci_operations lops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; + static const struct device_operations ctrl_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = ctrl_init, - .ops_pci = 0, + .ops_pci = &lops_pci, }; static const struct pci_driver northbridge_driver_t800 __pci_driver = { diff --git a/src/southbridge/via/k8t890/dram.c b/src/southbridge/via/k8t890/dram.c index 294e387..7e450cc 100644 --- a/src/southbridge/via/k8t890/dram.c +++ b/src/southbridge/via/k8t890/dram.c @@ -153,12 +153,16 @@ static void dram_init_fb(struct device *dev) #endif } +static struct pci_operations lops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; + static const struct device_operations dram_ops_t = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .enable = dram_enable, - .ops_pci = 0, + .ops_pci = &lops_pci, }; static const struct device_operations dram_ops_m = { @@ -167,7 +171,7 @@ static const struct device_operations dram_ops_m = { .enable_resources = pci_dev_enable_resources, .enable = dram_enable_k8m890, .init = dram_init_fb, - .ops_pci = 0, + .ops_pci = &lops_pci, }; static const struct pci_driver northbridge_driver_t800 __pci_driver = { diff --git a/src/southbridge/via/k8t890/error.c b/src/southbridge/via/k8t890/error.c index f2cab10..1f6979a 100644 --- a/src/southbridge/via/k8t890/error.c +++ b/src/southbridge/via/k8t890/error.c @@ -41,12 +41,16 @@ static void error_enable(struct device *dev) dump_south(dev); } +static struct pci_operations lops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; + static const struct device_operations error_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .enable = error_enable, - .ops_pci = 0, + .ops_pci = &lops_pci, }; static const struct pci_driver northbridge_driver_t800 __pci_driver = { diff --git a/src/southbridge/via/k8t890/host.c b/src/southbridge/via/k8t890/host.c index 700a637..54d79b4 100644 --- a/src/southbridge/via/k8t890/host.c +++ b/src/southbridge/via/k8t890/host.c @@ -95,12 +95,16 @@ static const struct device_operations host_ops_old = { .ops_pci = 0, }; +static struct pci_operations lops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; + static const struct device_operations host_ops_t = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .enable = host_enable, - .ops_pci = 0, + .ops_pci = &lops_pci, }; static const struct device_operations host_ops_m = { @@ -109,7 +113,7 @@ static const struct device_operations host_ops_m = { .enable_resources = pci_dev_enable_resources, .enable = host_enable, .init = host_init, - .ops_pci = 0, + .ops_pci = &lops_pci, }; static const struct pci_driver northbridge_driver_t800_old __pci_driver = { diff --git a/src/southbridge/via/k8t890/host_ctrl.c b/src/southbridge/via/k8t890/host_ctrl.c index 5d46a00..c5d751e 100644 --- a/src/southbridge/via/k8t890/host_ctrl.c +++ b/src/southbridge/via/k8t890/host_ctrl.c @@ -122,12 +122,16 @@ void set_cbmem_toc(struct cbmem_entry *toc) { outl((u32) toc, K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC); } +static struct pci_operations lops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; + static const struct device_operations host_ctrl_ops_t = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .enable = host_ctrl_enable_k8t8xx, - .ops_pci = 0, + .ops_pci = &lops_pci, }; static const struct device_operations host_ctrl_ops_m = { @@ -135,7 +139,7 @@ static const struct device_operations host_ctrl_ops_m = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .enable = host_ctrl_enable_k8m8xx, - .ops_pci = 0, + .ops_pci = &lops_pci, }; static const struct pci_driver northbridge_driver_t800 __pci_driver = { diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index cd1064f..d57d471 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -639,12 +639,24 @@ static void southbridge_init_common(struct device *dev) init_keyboard(dev); } + +static void vt8237_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + pci_write_config16(dev, 0x70, vendor); + pci_write_config16(dev, 0x72, device); +} + +static struct pci_operations lops_pci = { + .set_subsystem = vt8237_set_subsystem, +}; + static const struct device_operations vt8237r_lpc_ops_s = { .read_resources = vt8237r_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = vt8237s_init, .scan_bus = scan_static_bus, + .ops_pci = &lops_pci, }; static const struct device_operations vt8237r_lpc_ops_r = { @@ -653,6 +665,7 @@ static const struct device_operations vt8237r_lpc_ops_r = { .enable_resources = pci_dev_enable_resources, .init = vt8237r_init, .scan_bus = scan_static_bus, + .ops_pci = &lops_pci, }; static const struct device_operations vt8237r_lpc_ops_a = { @@ -661,6 +674,7 @@ static const struct device_operations vt8237r_lpc_ops_a = { .enable_resources = pci_dev_enable_resources, .init = vt8237a_init, .scan_bus = scan_static_bus, + .ops_pci = &lops_pci, }; static const struct pci_driver lpc_driver_r __pci_driver = { diff --git a/src/southbridge/via/vt8237r/sata.c b/src/southbridge/via/vt8237r/sata.c index 777d605..2f07e69 100644 --- a/src/southbridge/via/vt8237r/sata.c +++ b/src/southbridge/via/vt8237r/sata.c @@ -95,13 +95,24 @@ static void sata_ii_init(struct device *dev) } } + +static void vt8237_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + pci_write_config16(dev, 0xd4, vendor); + pci_write_config16(dev, 0xd6, device); +} + +static struct pci_operations lops_pci = { + .set_subsystem = vt8237_set_subsystem, +}; + static const struct device_operations sata_i_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = sata_i_init, .enable = 0, - .ops_pci = 0, + .ops_pci = &lops_pci, }; static const struct device_operations sata_ii_ops = { @@ -110,7 +121,7 @@ static const struct device_operations sata_ii_ops = { .enable_resources = pci_dev_enable_resources, .init = sata_ii_init, .enable = 0, - .ops_pci = 0, + .ops_pci = &lops_pci, }; static const struct pci_driver northbridge_driver_ii __pci_driver = { diff --git a/src/southbridge/via/vt8237r/usb.c b/src/southbridge/via/vt8237r/usb.c index 2bdcf9d..ac27f43 100644 --- a/src/southbridge/via/vt8237r/usb.c +++ b/src/southbridge/via/vt8237r/usb.c @@ -158,13 +158,25 @@ static void vt8237_usb_ii_read_resources(struct device *dev) return; } +static void vt8237_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + pci_write_config32(dev, 0x42, pci_read_config32(dev, 0x42) | 0x10); + pci_write_config16(dev, 0x2c, vendor); + pci_write_config16(dev, 0x2e, device); + pci_write_config32(dev, 0x42, pci_read_config32(dev, 0x42) & ~0x10); +} + +static struct pci_operations lops_pci = { + .set_subsystem = vt8237_set_subsystem, +}; + static const struct device_operations usb_i_ops = { .read_resources = vt8237_usb_i_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb_i_init, .enable = 0, - .ops_pci = 0, + .ops_pci = &lops_pci, }; static const struct device_operations usb_ii_ops = { @@ -173,7 +185,7 @@ static const struct device_operations usb_ii_ops = { .enable_resources = pci_dev_enable_resources, .init = usb_ii_init, .enable = 0, - .ops_pci = 0, + .ops_pci = &lops_pci, }; static const struct pci_driver vt8237r_driver_usbii __pci_driver = {

1 0

Patch set updated for coreboot: d864203 .gitignore ectool, inteltool, msrtool, nvramtool and superiotool
by Patrick Georgi 07 Jan '12

07 Jan '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/485 -gerrit commit d864203c152312aa8369377943312bb0fe232156 Author: Peter Stuge <peter(a)stuge.se> Date: Wed Dec 14 07:39:57 2011 +0100 .gitignore ectool, inteltool, msrtool, nvramtool and superiotool Change-Id: I06e69d97ef3646f79104ec316ce932cc53894c92 Signed-off-by: Peter Stuge <peter(a)stuge.se> --- .gitignore | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/.gitignore b/.gitignore index a4bbacd..a08cb12 100644 --- a/.gitignore +++ b/.gitignore @@ -35,3 +35,12 @@ util/crossgcc/w32api-*/ *.\# *.swp *.bin +util/ectool/ectool +util/inteltool/.dependencies +util/inteltool/inteltool +util/msrtool/Makefile +util/msrtool/Makefile.deps +util/msrtool/msrtool +util/nvramtool/.dependencies +util/nvramtool/nvramtool +util/superiotool/superiotool

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coreboot January 2012