coreboot January 2012

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New patch to review for coreboot: 898b606 Fix Fam14 AGESA ACPI table generation
by Marc Jones 04 Jan '12

04 Jan '12

Marc Jones (marcj303(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/517 -gerrit commit 898b6065fdc2b26bf8cd4a8f0bf48ff8647e086b Author: Marc Jones <marcj303(a)gmail.com> Date: Mon Dec 12 22:04:25 2011 -0700 Fix Fam14 AGESA ACPI table generation The AGESA wrapper init late call generates the SSDT and other ACPI tables. The call was failing without heap space allocated causing the ASSERT messages in the output. I think are there may still be other issues in integrating the SSDT table with the DSDT, but now it is there to debug. The changes were made in Persimmon and copied to the other Fam14 mainboards. Change-Id: I2cfd14e07cb46d2f46f5a8cd21c4c9aab44e4ffd Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/mainboard/amd/inagua/acpi_tables.c | 16 ++ src/mainboard/amd/inagua/agesawrapper.c | 175 +++++++++++++----------- src/mainboard/amd/persimmon/acpi_tables.c | 23 +++- src/mainboard/amd/persimmon/agesawrapper.c | 56 +++++--- src/mainboard/amd/persimmon/buildOpts.c | 6 +- src/mainboard/amd/south_station/acpi_tables.c | 16 ++ src/mainboard/amd/south_station/agesawrapper.c | 51 ++++--- src/mainboard/amd/union_station/acpi_tables.c | 16 ++ src/mainboard/amd/union_station/agesawrapper.c | 51 ++++--- src/mainboard/asrock/e350m1/acpi_tables.c | 16 ++ src/mainboard/asrock/e350m1/agesawrapper.c | 97 ++++++++----- 11 files changed, 344 insertions(+), 179 deletions(-) diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c index 74df922..2e6e50f 100644 --- a/src/mainboard/amd/inagua/acpi_tables.c +++ b/src/mainboard/amd/inagua/acpi_tables.c @@ -130,6 +130,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *dsdt; acpi_header_t *ssdt; acpi_header_t *ssdt2; + acpi_header_t *alib; get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ @@ -224,6 +225,20 @@ unsigned long write_acpi_tables(unsigned long start) /* SSDT */ current = ( current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); + alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); + if (alib != NULL) { + memcpy((void *)current, alib, alib->length); + ssdt = (acpi_header_t *) current; + current += alib->length; + acpi_add_table(rsdp,alib); + } + else { + printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); + } + +#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); if (ssdt != NULL) { @@ -235,6 +250,7 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); } acpi_add_table(rsdp,ssdt); +#endif current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/amd/inagua/agesawrapper.c b/src/mainboard/amd/inagua/agesawrapper.c index 727436c..c33d20f 100644 --- a/src/mainboard/amd/inagua/agesawrapper.c +++ b/src/mainboard/amd/inagua/agesawrapper.c @@ -36,6 +36,7 @@ #include "amdlib.h" #include "PlatformGnbPcieComplex.h" #include "Filecode.h" +#include <arch/io.h> #define FILECODE UNASSIGNED_FILE_FILECODE @@ -44,6 +45,8 @@ *------------------------------------------------------------------------------ */ +#define MMCONF_ENABLE 1 + /* ACPI table pointers returned by AmdInitLate */ VOID *DmiTable = NULL; VOID *AcpiPstate = NULL; @@ -79,44 +82,45 @@ agesawrapper_amdinitcpuio ( VOID ) { - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; - - /* Enable MMIO on AMD CPU Address Map Controller */ + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* Enable legacy video routing: D18F1xF4 VGA Enable */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); + PciData = 1; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Start to set MMIO 0000A0000-0000BFFFF to Node0 Link0 */ + /* The platform BIOS needs to ensure the memory ranges of SB800 legacy + * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are + * set to non-posted regions. + */ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); - PciData = 0x00000B00; + PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000 + PciData |= 1 << 7; // set NP (non-posted) bit LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); - PciData = 0x00000A03; + PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set TOM-DFFFFFFF to Node0 Link0. */ + /* Map the remaining PCI hole as posted MMIO */ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); - PciData = 0x00DFFF00; + PciData = 0x00FECF00; // last address before non-posted range LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); MsrReg = (MsrReg >> 8) | 3; PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); PciData = (UINT32)MsrReg; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set E0000000-FFFFFFFF to Node0 Link0 with NP set. */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xBC); - PciData = 0x00FFFF00 | 0x80; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xB8); - PciData = (PCIE_BASE_ADDRESS >> 8) | 03; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Start to set PCIIO 0000-FFFF to Node0 Link0 with ISA&VGA set. */ + + /* Send all IO (0000-FFFF) to southbridge. */ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); PciData = 0x0000F000; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); - PciData = 0x00000013; + PciData = 0x00000003; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); Status = AGESA_SUCCESS; return (UINT32)Status; @@ -127,24 +131,37 @@ agesawrapper_amdinitmmio ( VOID ) { - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + UINT8 BusRangeVal = 0; + UINT8 BusNum; + UINT8 Index; /* Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base Address MSR register. */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (8 << 2) | 1; + + for (Index = 0; Index < 8; Index++) { + BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index; + if (BusNum == 1) { + BusRangeVal = Index; + break; + } + } + + MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (UINT64)(BusRangeVal << 2) | MMCONF_ENABLE); LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); /* Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. */ LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); - MsrReg = MsrReg | 0x0000400000000000; + MsrReg = MsrReg | 0x0000400000000000ull; LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); /* Set Ontario Link Data */ @@ -155,13 +172,6 @@ agesawrapper_amdinitmmio ( PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5; - LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800; - LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); - Status = AGESA_SUCCESS; return (UINT32)Status; } @@ -262,12 +272,12 @@ agesawrapper_amdinitpost ( status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); AmdReleaseStruct (&AmdParamStruct); + /* Initialize heap space */ BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS; HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); - for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) - { + for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) { *HeadPtr = 0x00000000; HeadPtr++; } @@ -354,7 +364,6 @@ agesawrapper_amdinitenv ( PciValue |= 0x80000000; LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - /* Initialize MMIO Base and Limit Address * Modify B0D1F0x20 */ @@ -442,68 +451,76 @@ agesawrapper_amdinitlate ( ) { AGESA_STATUS Status; - AMD_LATE_PARAMS AmdLateParams; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_LATE_PARAMS * AmdLateParamsPtr; - LibAmdMemFill (&AmdLateParams, - 0, - sizeof (AMD_LATE_PARAMS), - &(AmdLateParams.StdHeader)); + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); - AmdLateParams.StdHeader.AltImageBasePtr = 0; - AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdLateParams.StdHeader.Func = 0; - AmdLateParams.StdHeader.ImageBasePtr = 0; + AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct (&AmdParamStruct); + AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; - Status = AmdInitLate (&AmdLateParams); + printk (BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr); + + Status = AmdInitLate (AmdLateParamsPtr); if (Status != AGESA_SUCCESS) { agesawrapper_amdreadeventlog(); ASSERT(Status == AGESA_SUCCESS); } - DmiTable = AmdLateParams.DmiTable; - AcpiPstate = AmdLateParams.AcpiPState; - AcpiSrat = AmdLateParams.AcpiSrat; - AcpiSlit = AmdLateParams.AcpiSlit; - AcpiWheaMce = AmdLateParams.AcpiWheaMce; - AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; - AcpiAlib = AmdLateParams.AcpiAlib; + DmiTable = AmdLateParamsPtr->DmiTable; + AcpiPstate = AmdLateParamsPtr->AcpiPState; + AcpiSrat = AmdLateParamsPtr->AcpiSrat; + AcpiSlit = AmdLateParamsPtr->AcpiSlit; + AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce; + AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc; + AcpiAlib = AmdLateParamsPtr->AcpiAlib; + + /* Don't release the structure until coreboot has copied the ACPI tables. + * AmdReleaseStruct (&AmdLateParams); + */ return (UINT32)Status; } UINT32 agesawrapper_amdlaterunaptask ( + UINT32 Func, UINT32 Data, VOID *ConfigPtr ) { AGESA_STATUS Status; - AMD_LATE_PARAMS AmdLateParams; - - LibAmdMemFill (&AmdLateParams, - 0, - sizeof (AMD_LATE_PARAMS), - &(AmdLateParams.StdHeader)); - - AmdLateParams.StdHeader.AltImageBasePtr = 0; - AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdLateParams.StdHeader.Func = 0; - AmdLateParams.StdHeader.ImageBasePtr = 0; - - Status = AmdLateRunApTask (&AmdLateParams); + AP_EXE_PARAMS ApExeParams; + + LibAmdMemFill (&ApExeParams, + 0, + sizeof (AP_EXE_PARAMS), + &(ApExeParams.StdHeader)); + + ApExeParams.StdHeader.AltImageBasePtr = 0; + ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + ApExeParams.StdHeader.Func = 0; + ApExeParams.StdHeader.ImageBasePtr = 0; + ApExeParams.StdHeader.ImageBasePtr = 0; + ApExeParams.FunctionNumber = Func; + ApExeParams.RelatedDataBlock = ConfigPtr; + + Status = AmdLateRunApTask (&ApExeParams); if (Status != AGESA_SUCCESS) { agesawrapper_amdreadeventlog(); ASSERT(Status == AGESA_SUCCESS); } - DmiTable = AmdLateParams.DmiTable; - AcpiPstate = AmdLateParams.AcpiPState; - AcpiSrat = AmdLateParams.AcpiSrat; - AcpiSlit = AmdLateParams.AcpiSlit; - AcpiWheaMce = AmdLateParams.AcpiWheaMce; - AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; - AcpiAlib = AmdLateParams.AcpiAlib; - return (UINT32)Status; } @@ -526,9 +543,9 @@ agesawrapper_amdreadeventlog ( AmdEventParams.StdHeader.ImageBasePtr = 0; Status = AmdReadEventLog (&AmdEventParams); while (AmdEventParams.EventClass != 0) { - printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo); - printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2); - printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4); + printk(BIOS_DEBUG,"\nEventLog: EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo); + printk(BIOS_DEBUG," Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2); + printk(BIOS_DEBUG," Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4); Status = AmdReadEventLog (&AmdEventParams); } diff --git a/src/mainboard/amd/persimmon/acpi_tables.c b/src/mainboard/amd/persimmon/acpi_tables.c index 47e35af..9526fea 100644 --- a/src/mainboard/amd/persimmon/acpi_tables.c +++ b/src/mainboard/amd/persimmon/acpi_tables.c @@ -20,6 +20,7 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/acpigen.h> #include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -130,6 +131,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *dsdt; acpi_header_t *ssdt; acpi_header_t *ssdt2; + acpi_header_t *alib; get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ @@ -224,17 +226,33 @@ unsigned long write_acpi_tables(unsigned long start) /* SSDT */ current = ( current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); + alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); + if (alib != NULL) { + memcpy((void *)current, alib, alib->length); + ssdt = (acpi_header_t *) current; + current += alib->length; + acpi_add_table(rsdp,alib); + } + else { + printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); + } + +#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); if (ssdt != NULL) { memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; current += ssdt->length; + acpi_add_table(rsdp,ssdt); } else { - printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); + printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } acpi_add_table(rsdp,ssdt); +#endif current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); @@ -259,6 +277,9 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "slit\n"); dump_mem(slit, ((void *)slit) + slit->header.length); + printk(BIOS_DEBUG, "alib\n"); + dump_mem(ssdt, ((void *)alib) + alib->length); + printk(BIOS_DEBUG, "ssdt\n"); dump_mem(ssdt, ((void *)ssdt) + ssdt->length); diff --git a/src/mainboard/amd/persimmon/agesawrapper.c b/src/mainboard/amd/persimmon/agesawrapper.c index 55e8488..f9847c2 100644 --- a/src/mainboard/amd/persimmon/agesawrapper.c +++ b/src/mainboard/amd/persimmon/agesawrapper.c @@ -275,8 +275,7 @@ agesawrapper_amdinitpost ( BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS; HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); - for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) - { + for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) { *HeadPtr = 0x00000000; HeadPtr++; } @@ -450,32 +449,49 @@ agesawrapper_amdinitlate ( ) { AGESA_STATUS Status; - AMD_LATE_PARAMS AmdLateParams; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_LATE_PARAMS * AmdLateParamsPtr; - LibAmdMemFill (&AmdLateParams, - 0, - sizeof (AMD_LATE_PARAMS), - &(AmdLateParams.StdHeader)); + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); - AmdLateParams.StdHeader.AltImageBasePtr = 0; - AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdLateParams.StdHeader.Func = 0; - AmdLateParams.StdHeader.ImageBasePtr = 0; + AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct (&AmdParamStruct); + AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; - Status = AmdInitLate (&AmdLateParams); + printk (BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr); + + Status = AmdInitLate (AmdLateParamsPtr); if (Status != AGESA_SUCCESS) { agesawrapper_amdreadeventlog(); ASSERT(Status == AGESA_SUCCESS); } - DmiTable = AmdLateParams.DmiTable; - AcpiPstate = AmdLateParams.AcpiPState; - AcpiSrat = AmdLateParams.AcpiSrat; - AcpiSlit = AmdLateParams.AcpiSlit; - - AcpiWheaMce = AmdLateParams.AcpiWheaMce; - AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; - AcpiAlib = AmdLateParams.AcpiAlib; + DmiTable = AmdLateParamsPtr->DmiTable; + AcpiPstate = AmdLateParamsPtr->AcpiPState; + AcpiSrat = AmdLateParamsPtr->AcpiSrat; + AcpiSlit = AmdLateParamsPtr->AcpiSlit; + AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce; + AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc; + AcpiAlib = AmdLateParamsPtr->AcpiAlib; + + printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n" + " DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n" + " Mce:%p\n Cmc:%p\n Alib:%p\n", + __func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit, + AcpiWheaMce, AcpiWheaCmc, AcpiAlib); + + /* Don't release the structure until coreboot has copied the ACPI tables. + * AmdReleaseStruct (&AmdLateParams); + */ return (UINT32)Status; } diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c index 368eed2..3e5b14e 100644 --- a/src/mainboard/amd/persimmon/buildOpts.c +++ b/src/mainboard/amd/persimmon/buildOpts.c @@ -95,9 +95,9 @@ #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE -#define BLDOPT_REMOVE_SRAT TRUE -#define BLDOPT_REMOVE_SLIT TRUE -#define BLDOPT_REMOVE_WHEA TRUE +#define BLDOPT_REMOVE_SRAT FALSE +#define BLDOPT_REMOVE_SLIT FALSE +#define BLDOPT_REMOVE_WHEA FALSE #define BLDOPT_REMOVE_DMI TRUE #define BLDOPT_REMOVE_HT_ASSIST TRUE #define BLDOPT_REMOVE_ATM_MODE TRUE diff --git a/src/mainboard/amd/south_station/acpi_tables.c b/src/mainboard/amd/south_station/acpi_tables.c index 74df922..2e6e50f 100644 --- a/src/mainboard/amd/south_station/acpi_tables.c +++ b/src/mainboard/amd/south_station/acpi_tables.c @@ -130,6 +130,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *dsdt; acpi_header_t *ssdt; acpi_header_t *ssdt2; + acpi_header_t *alib; get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ @@ -224,6 +225,20 @@ unsigned long write_acpi_tables(unsigned long start) /* SSDT */ current = ( current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); + alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); + if (alib != NULL) { + memcpy((void *)current, alib, alib->length); + ssdt = (acpi_header_t *) current; + current += alib->length; + acpi_add_table(rsdp,alib); + } + else { + printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); + } + +#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); if (ssdt != NULL) { @@ -235,6 +250,7 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); } acpi_add_table(rsdp,ssdt); +#endif current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/amd/south_station/agesawrapper.c b/src/mainboard/amd/south_station/agesawrapper.c index 55e8488..0fbb3e4 100644 --- a/src/mainboard/amd/south_station/agesawrapper.c +++ b/src/mainboard/amd/south_station/agesawrapper.c @@ -98,7 +98,7 @@ agesawrapper_amdinitcpuio ( */ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000 - PciData |= 1 << 7; // set NP (non-posted) bit + PciData |= 1 << 7; // set NP (non-posted) bit LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000 @@ -275,8 +275,7 @@ agesawrapper_amdinitpost ( BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS; HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); - for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) - { + for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) { *HeadPtr = 0x00000000; HeadPtr++; } @@ -450,32 +449,44 @@ agesawrapper_amdinitlate ( ) { AGESA_STATUS Status; - AMD_LATE_PARAMS AmdLateParams; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_LATE_PARAMS * AmdLateParamsPtr; - LibAmdMemFill (&AmdLateParams, - 0, - sizeof (AMD_LATE_PARAMS), - &(AmdLateParams.StdHeader)); + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); - AmdLateParams.StdHeader.AltImageBasePtr = 0; - AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdLateParams.StdHeader.Func = 0; - AmdLateParams.StdHeader.ImageBasePtr = 0; + AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct (&AmdParamStruct); + AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; - Status = AmdInitLate (&AmdLateParams); + printk (BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr); + + Status = AmdInitLate (AmdLateParamsPtr); if (Status != AGESA_SUCCESS) { agesawrapper_amdreadeventlog(); ASSERT(Status == AGESA_SUCCESS); } - DmiTable = AmdLateParams.DmiTable; - AcpiPstate = AmdLateParams.AcpiPState; - AcpiSrat = AmdLateParams.AcpiSrat; - AcpiSlit = AmdLateParams.AcpiSlit; + DmiTable = AmdLateParamsPtr->DmiTable; + AcpiPstate = AmdLateParamsPtr->AcpiPState; + AcpiSrat = AmdLateParamsPtr->AcpiSrat; + AcpiSlit = AmdLateParamsPtr->AcpiSlit; + + AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce; + AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc; + AcpiAlib = AmdLateParamsPtr->AcpiAlib; - AcpiWheaMce = AmdLateParams.AcpiWheaMce; - AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; - AcpiAlib = AmdLateParams.AcpiAlib; + /* Don't release the structure until coreboot has copied the ACPI tables. + * AmdReleaseStruct (&AmdLateParams); + */ return (UINT32)Status; } diff --git a/src/mainboard/amd/union_station/acpi_tables.c b/src/mainboard/amd/union_station/acpi_tables.c index 74df922..2e6e50f 100644 --- a/src/mainboard/amd/union_station/acpi_tables.c +++ b/src/mainboard/amd/union_station/acpi_tables.c @@ -130,6 +130,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *dsdt; acpi_header_t *ssdt; acpi_header_t *ssdt2; + acpi_header_t *alib; get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ @@ -224,6 +225,20 @@ unsigned long write_acpi_tables(unsigned long start) /* SSDT */ current = ( current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); + alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); + if (alib != NULL) { + memcpy((void *)current, alib, alib->length); + ssdt = (acpi_header_t *) current; + current += alib->length; + acpi_add_table(rsdp,alib); + } + else { + printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); + } + +#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); if (ssdt != NULL) { @@ -235,6 +250,7 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); } acpi_add_table(rsdp,ssdt); +#endif current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/amd/union_station/agesawrapper.c b/src/mainboard/amd/union_station/agesawrapper.c index 55e8488..0fbb3e4 100644 --- a/src/mainboard/amd/union_station/agesawrapper.c +++ b/src/mainboard/amd/union_station/agesawrapper.c @@ -98,7 +98,7 @@ agesawrapper_amdinitcpuio ( */ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000 - PciData |= 1 << 7; // set NP (non-posted) bit + PciData |= 1 << 7; // set NP (non-posted) bit LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000 @@ -275,8 +275,7 @@ agesawrapper_amdinitpost ( BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS; HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); - for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) - { + for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) { *HeadPtr = 0x00000000; HeadPtr++; } @@ -450,32 +449,44 @@ agesawrapper_amdinitlate ( ) { AGESA_STATUS Status; - AMD_LATE_PARAMS AmdLateParams; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_LATE_PARAMS * AmdLateParamsPtr; - LibAmdMemFill (&AmdLateParams, - 0, - sizeof (AMD_LATE_PARAMS), - &(AmdLateParams.StdHeader)); + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); - AmdLateParams.StdHeader.AltImageBasePtr = 0; - AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdLateParams.StdHeader.Func = 0; - AmdLateParams.StdHeader.ImageBasePtr = 0; + AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct (&AmdParamStruct); + AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; - Status = AmdInitLate (&AmdLateParams); + printk (BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr); + + Status = AmdInitLate (AmdLateParamsPtr); if (Status != AGESA_SUCCESS) { agesawrapper_amdreadeventlog(); ASSERT(Status == AGESA_SUCCESS); } - DmiTable = AmdLateParams.DmiTable; - AcpiPstate = AmdLateParams.AcpiPState; - AcpiSrat = AmdLateParams.AcpiSrat; - AcpiSlit = AmdLateParams.AcpiSlit; + DmiTable = AmdLateParamsPtr->DmiTable; + AcpiPstate = AmdLateParamsPtr->AcpiPState; + AcpiSrat = AmdLateParamsPtr->AcpiSrat; + AcpiSlit = AmdLateParamsPtr->AcpiSlit; + + AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce; + AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc; + AcpiAlib = AmdLateParamsPtr->AcpiAlib; - AcpiWheaMce = AmdLateParams.AcpiWheaMce; - AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; - AcpiAlib = AmdLateParams.AcpiAlib; + /* Don't release the structure until coreboot has copied the ACPI tables. + * AmdReleaseStruct (&AmdLateParams); + */ return (UINT32)Status; } diff --git a/src/mainboard/asrock/e350m1/acpi_tables.c b/src/mainboard/asrock/e350m1/acpi_tables.c index 74df922..2e6e50f 100644 --- a/src/mainboard/asrock/e350m1/acpi_tables.c +++ b/src/mainboard/asrock/e350m1/acpi_tables.c @@ -130,6 +130,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *dsdt; acpi_header_t *ssdt; acpi_header_t *ssdt2; + acpi_header_t *alib; get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ @@ -224,6 +225,20 @@ unsigned long write_acpi_tables(unsigned long start) /* SSDT */ current = ( current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); + alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); + if (alib != NULL) { + memcpy((void *)current, alib, alib->length); + ssdt = (acpi_header_t *) current; + current += alib->length; + acpi_add_table(rsdp,alib); + } + else { + printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); + } + +#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); if (ssdt != NULL) { @@ -235,6 +250,7 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); } acpi_add_table(rsdp,ssdt); +#endif current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/asrock/e350m1/agesawrapper.c b/src/mainboard/asrock/e350m1/agesawrapper.c index 8ecc885..fc87029 100644 --- a/src/mainboard/asrock/e350m1/agesawrapper.c +++ b/src/mainboard/asrock/e350m1/agesawrapper.c @@ -36,6 +36,7 @@ #include "amdlib.h" #include "PlatformGnbPcieComplex.h" #include "Filecode.h" +#include <arch/io.h> #define FILECODE UNASSIGNED_FILE_FILECODE @@ -44,6 +45,7 @@ *------------------------------------------------------------------------------ */ +#define MMCONF_ENABLE 1 /* ACPI table pointers returned by AmdInitLate */ VOID *DmiTable = NULL; @@ -96,7 +98,7 @@ agesawrapper_amdinitcpuio ( */ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000 - PciData |= 1 << 7; // set NP (non-posted) bit + PciData |= 1 << 7; // set NP (non-posted) bit LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000 @@ -128,25 +130,37 @@ agesawrapper_amdinitmmio ( VOID ) { - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + UINT8 BusRangeVal = 0; + UINT8 BusNum; + UINT8 Index; /* - Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base - Address MSR register. + Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base + Address MSR register. */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; + for (Index = 0; Index < 8; Index++) { + BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index; + if (BusNum == 1) { + BusRangeVal = Index; + break; + } + } + + MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (UINT64)(BusRangeVal << 2) | MMCONF_ENABLE); LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); /* - Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. + Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. */ LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); - MsrReg = MsrReg | 0x0000400000000000; + MsrReg = MsrReg | 0x0000400000000000ull; LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); /* Set Ontario Link Data */ @@ -261,10 +275,9 @@ agesawrapper_amdinitpost ( BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS; HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); - for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) - { - *HeadPtr = 0x00000000; - HeadPtr++; + for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) { + *HeadPtr = 0x00000000; + HeadPtr++; } BiosManagerPtr->StartOfAllocatedNodes = 0; BiosManagerPtr->StartOfFreedNodes = 0; @@ -436,32 +449,44 @@ agesawrapper_amdinitlate ( ) { AGESA_STATUS Status; - AMD_LATE_PARAMS AmdLateParams; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_LATE_PARAMS * AmdLateParamsPtr; - LibAmdMemFill (&AmdLateParams, - 0, - sizeof (AMD_LATE_PARAMS), - &(AmdLateParams.StdHeader)); + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); - AmdLateParams.StdHeader.AltImageBasePtr = 0; - AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdLateParams.StdHeader.Func = 0; - AmdLateParams.StdHeader.ImageBasePtr = 0; + AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; - Status = AmdInitLate (&AmdLateParams); + AmdCreateStruct (&AmdParamStruct); + AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; + + printk (BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr); + + Status = AmdInitLate (AmdLateParamsPtr); if (Status != AGESA_SUCCESS) { agesawrapper_amdreadeventlog(); ASSERT(Status == AGESA_SUCCESS); } - DmiTable = AmdLateParams.DmiTable; - AcpiPstate = AmdLateParams.AcpiPState; - AcpiSrat = AmdLateParams.AcpiSrat; - AcpiSlit = AmdLateParams.AcpiSlit; + DmiTable = AmdLateParamsPtr->DmiTable; + AcpiPstate = AmdLateParamsPtr->AcpiPState; + AcpiSrat = AmdLateParamsPtr->AcpiSrat; + AcpiSlit = AmdLateParamsPtr->AcpiSlit; - AcpiWheaMce = AmdLateParams.AcpiWheaMce; - AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; - AcpiAlib = AmdLateParams.AcpiAlib; + AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce; + AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc; + AcpiAlib = AmdLateParamsPtr->AcpiAlib; + + /* Don't release the structure until coreboot has copied the ACPI tables. + * AmdReleaseStruct (&AmdLateParams); + */ return (UINT32)Status; } @@ -517,10 +542,10 @@ agesawrapper_amdreadeventlog ( AmdEventParams.StdHeader.ImageBasePtr = 0; Status = AmdReadEventLog (&AmdEventParams); while (AmdEventParams.EventClass != 0) { - printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo); - printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2); - printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4); - Status = AmdReadEventLog (&AmdEventParams); + printk(BIOS_DEBUG,"\nEventLog: EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo); + printk(BIOS_DEBUG," Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2); + printk(BIOS_DEBUG," Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4); + Status = AmdReadEventLog (&AmdEventParams); } return (UINT32)Status;

1 0

New patch to review for coreboot: a2f4c41 Fix Fam14 mainboard whitespace
by Marc Jones 04 Jan '12

04 Jan '12

Marc Jones (marcj303(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/515 -gerrit commit a2f4c419f0526c66cfc51217baf64729f60affca Author: Marc Jones <marcj303(a)gmail.com> Date: Tue Jan 3 16:02:07 2012 -0700 Fix Fam14 mainboard whitespace Fix whitespace and tab issues on fam14 mainbords in preperations for upcoming changes Change-Id: I6d63d428dde0a5d9748027e603b03de25d3be472 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/mainboard/amd/inagua/acpi_tables.c | 334 +++++----- src/mainboard/amd/inagua/agesawrapper.c | 855 ++++++++++++------------ src/mainboard/amd/persimmon/acpi_tables.c | 44 +- src/mainboard/amd/persimmon/agesawrapper.c | 159 +++--- src/mainboard/amd/south_station/acpi_tables.c | 352 +++++----- src/mainboard/amd/south_station/agesawrapper.c | 862 ++++++++++++------------ src/mainboard/amd/union_station/acpi_tables.c | 352 +++++----- src/mainboard/amd/union_station/agesawrapper.c | 862 ++++++++++++------------ src/mainboard/asrock/e350m1/acpi_tables.c | 355 +++++----- src/mainboard/asrock/e350m1/agesawrapper.c | 839 ++++++++++++------------ 10 files changed, 2505 insertions(+), 2509 deletions(-) diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c index cc37ed2..6450f35 100644 --- a/src/mainboard/amd/inagua/acpi_tables.c +++ b/src/mainboard/amd/inagua/acpi_tables.c @@ -38,15 +38,15 @@ extern u32 apicid_sb800; static void dump_mem(u32 start, u32 end) { - u32 i; - print_debug("dump_mem:"); - for (i = start; i < end; i++) { - if ((i & 0xf) == 0) { - printk(BIOS_DEBUG, "\n%08x:", i); - } - printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i)); - } - print_debug("\n"); + u32 i; + print_debug("dump_mem:"); + for (i = start; i < end; i++) { + if ((i & 0xf) == 0) { + printk(BIOS_DEBUG, "\n%08x:", i); + } + printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i)); + } + print_debug("\n"); } #endif @@ -56,197 +56,197 @@ extern const unsigned char AmlCode_ssdt[]; unsigned long acpi_fill_mcfg(unsigned long current) { - /* Just a dummy */ - return current; + /* Just a dummy */ + return current; } unsigned long acpi_fill_madt(unsigned long current) { - /* create all subtables for processors */ - current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0); - current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 1); + /* create all subtables for processors */ + current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0); + current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 1); - /* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sb800, - IO_APIC_ADDR, 0); + /* Write SB800 IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sb800, + IO_APIC_ADDR, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edige-triggered, Active high */ + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edige-triggered, Active high */ - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0, 5, 1); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 1, 5, 1); - /* 1: LINT1 connect to NMI */ + /* create all subtables for processors */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0, 5, 1); + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 1, 5, 1); + /* 1: LINT1 connect to NMI */ - return current; + return current; } unsigned long acpi_fill_slit(unsigned long current) { - // Not implemented - return current; + // Not implemented + return current; } unsigned long acpi_fill_srat(unsigned long current) { - /* No NUMA, no SRAT */ - return current; + /* No NUMA, no SRAT */ + return current; } unsigned long write_acpi_tables(unsigned long start) { - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_srat_t *srat; - acpi_slit_t *slit; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; - - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - - /* Align ACPI tables to 16 bytes */ - start = (start + 0x0f) & -0x10; - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* DSDT */ - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); - dsdt = (acpi_header_t *)current; // it will used by fadt - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); - - /* FACS */ // it needs 64 bit alignment - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); - facs = (acpi_facs_t *) current; // it will be used by fadt - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* FADT */ - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - /* - * We explicitly add these tables later on: - */ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_srat_t *srat; + acpi_slit_t *slit; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *dsdt; + acpi_header_t *ssdt; + + get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ + + /* Align ACPI tables to 16 bytes */ + start = (start + 0x0f) & -0x10; + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* clear all table memory */ + memset((void *)start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* DSDT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); + dsdt = (acpi_header_t *)current; // it will used by fadt + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); + + /* FACS */ // it needs 64 bit alignment + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); + facs = (acpi_facs_t *) current; // it will be used by fadt + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + /* FADT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* + * We explicitly add these tables later on: + */ #if 0 // Don't need HPET table. - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + acpi_create_hpet(hpet); + acpi_add_table(rsdp, hpet); #endif - /* If we want to use HPET Timers Linux wants an MADT */ - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - /* SRAT */ - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); - srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); - if (srat != NULL) { - memcpy(current, srat, srat->header.length); - srat = (acpi_srat_t *) current; - //acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - } - - /* SLIT */ - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); - slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); - if (slit != NULL) { - memcpy(current, slit, slit->header.length); - slit = (acpi_slit_t *) current; - //acpi_create_slit(slit); - current += slit->header.length; - acpi_add_table(rsdp, slit); - } - - /* SSDT */ - current = ( current + 0x0f) & -0x10; - printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); - ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); - if (ssdt != NULL) { - memcpy(current, ssdt, ssdt->length); - ssdt = (acpi_header_t *) current; - current += ssdt->length; - } - else { - ssdt = (acpi_header_t *) current; - memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); - current += ssdt->length; - memcpy(ssdt, &AmlCode_ssdt, ssdt->length); - /* recalculate checksum */ - ssdt->checksum = 0; - ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); - } - acpi_add_table(rsdp,ssdt); - - printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); + /* If we want to use HPET Timers Linux wants an MADT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdp, madt); + + /* SRAT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); + srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); + if (srat != NULL) { + memcpy(current, srat, srat->header.length); + srat = (acpi_srat_t *) current; + //acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + } + + /* SLIT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); + slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); + if (slit != NULL) { + memcpy(current, slit, slit->header.length); + slit = (acpi_slit_t *) current; + //acpi_create_slit(slit); + current += slit->header.length; + acpi_add_table(rsdp, slit); + } + + /* SSDT */ + current = ( current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); + ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); + if (ssdt != NULL) { + memcpy(current, ssdt, ssdt->length); + ssdt = (acpi_header_t *) current; + current += ssdt->length; + } + else { + ssdt = (acpi_header_t *) current; + memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); + current += ssdt->length; + memcpy(ssdt, &AmlCode_ssdt, ssdt->length); + /* recalculate checksum */ + ssdt->checksum = 0; + ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); + } + acpi_add_table(rsdp,ssdt); + + printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); #if DUMP_ACPI_TABLES == 1 - printk(BIOS_DEBUG, "rsdp\n"); - dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t)); + printk(BIOS_DEBUG, "rsdp\n"); + dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t)); - printk(BIOS_DEBUG, "rsdt\n"); - dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t)); + printk(BIOS_DEBUG, "rsdt\n"); + dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t)); - printk(BIOS_DEBUG, "madt\n"); - dump_mem(madt, ((void *)madt) + madt->header.length); + printk(BIOS_DEBUG, "madt\n"); + dump_mem(madt, ((void *)madt) + madt->header.length); - printk(BIOS_DEBUG, "srat\n"); - dump_mem(srat, ((void *)srat) + srat->header.length); + printk(BIOS_DEBUG, "srat\n"); + dump_mem(srat, ((void *)srat) + srat->header.length); - printk(BIOS_DEBUG, "slit\n"); - dump_mem(slit, ((void *)slit) + slit->header.length); + printk(BIOS_DEBUG, "slit\n"); + dump_mem(slit, ((void *)slit) + slit->header.length); - printk(BIOS_DEBUG, "ssdt\n"); - dump_mem(ssdt, ((void *)ssdt) + ssdt->length); + printk(BIOS_DEBUG, "ssdt\n"); + dump_mem(ssdt, ((void *)ssdt) + ssdt->length); - printk(BIOS_DEBUG, "fadt\n"); - dump_mem(fadt, ((void *)fadt) + fadt->header.length); + printk(BIOS_DEBUG, "fadt\n"); + dump_mem(fadt, ((void *)fadt) + fadt->header.length); #endif - printk(BIOS_INFO, "ACPI: done.\n"); - return current; + printk(BIOS_INFO, "ACPI: done.\n"); + return current; } diff --git a/src/mainboard/amd/inagua/agesawrapper.c b/src/mainboard/amd/inagua/agesawrapper.c index df5cd1e..727436c 100644 --- a/src/mainboard/amd/inagua/agesawrapper.c +++ b/src/mainboard/amd/inagua/agesawrapper.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- +/*----------------------------------------------------------------------------- + * M O D U L E S U S E D + *----------------------------------------------------------------------------- */ #include <stdint.h> @@ -39,503 +39,498 @@ #define FILECODE UNASSIGNED_FILE_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- +/*------------------------------------------------------------------------------ + * D E F I N I T I O N S A N D M A C R O S + *------------------------------------------------------------------------------ */ /* ACPI table pointers returned by AmdInitLate */ -VOID *DmiTable = NULL; -VOID *AcpiPstate = NULL; -VOID *AcpiSrat = NULL; -VOID *AcpiSlit = NULL; +VOID *DmiTable = NULL; +VOID *AcpiPstate = NULL; +VOID *AcpiSrat = NULL; +VOID *AcpiSlit = NULL; -VOID *AcpiWheaMce = NULL; -VOID *AcpiWheaCmc = NULL; -VOID *AcpiAlib = NULL; +VOID *AcpiWheaMce = NULL; +VOID *AcpiWheaCmc = NULL; +VOID *AcpiAlib = NULL; -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- +/*------------------------------------------------------------------------------ + * T Y P E D E F S A N D S T R U C T U R E S + *------------------------------------------------------------------------------ */ -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- +/*------------------------------------------------------------------------------ + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *------------------------------------------------------------------------------ */ -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- +/*------------------------------------------------------------------------------ + * E X P O R T E D F U N C T I O N S + *------------------------------------------------------------------------------ */ -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- +/*------------------------------------------------------------------------------ + * L O C A L F U N C T I O N S + *------------------------------------------------------------------------------ */ UINT32 agesawrapper_amdinitcpuio ( - VOID - ) + VOID + ) { - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; - - /* Enable MMIO on AMD CPU Address Map Controller */ - - /* Start to set MMIO 0000A0000-0000BFFFF to Node0 Link0 */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); - PciData = 0x00000B00; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); - PciData = 0x00000A03; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Set TOM-DFFFFFFF to Node0 Link0. */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); - PciData = 0x00DFFF00; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); - MsrReg = (MsrReg >> 8) | 3; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); - PciData = (UINT32)MsrReg; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set E0000000-FFFFFFFF to Node0 Link0 with NP set. */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xBC); - PciData = 0x00FFFF00 | 0x80; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xB8); - PciData = (PCIE_BASE_ADDRESS >> 8) | 03; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Start to set PCIIO 0000-FFFF to Node0 Link0 with ISA&VGA set. */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); - PciData = 0x0000F000; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); - PciData = 0x00000013; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - Status = AGESA_SUCCESS; - return (UINT32)Status; + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* Enable MMIO on AMD CPU Address Map Controller */ + + /* Start to set MMIO 0000A0000-0000BFFFF to Node0 Link0 */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); + PciData = 0x00000B00; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); + PciData = 0x00000A03; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Set TOM-DFFFFFFF to Node0 Link0. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); + PciData = 0x00DFFF00; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); + MsrReg = (MsrReg >> 8) | 3; + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); + PciData = (UINT32)MsrReg; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + /* Set E0000000-FFFFFFFF to Node0 Link0 with NP set. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xBC); + PciData = 0x00FFFF00 | 0x80; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xB8); + PciData = (PCIE_BASE_ADDRESS >> 8) | 03; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + /* Start to set PCIIO 0000-FFFF to Node0 Link0 with ISA&VGA set. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); + PciData = 0x0000F000; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); + PciData = 0x00000013; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + Status = AGESA_SUCCESS; + return (UINT32)Status; } UINT32 agesawrapper_amdinitmmio ( - VOID - ) + VOID + ) { - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; - - /* - Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base - Address MSR register. - */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (8 << 2) | 1; - LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); - - /* - Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. - */ - LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); - MsrReg = MsrReg | 0x0000400000000000; - LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - - /* Set Ontario Link Data */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0); - PciData = 0x01308002; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4); - PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - - /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5; - LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800; - LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); - - Status = AGESA_SUCCESS; - return (UINT32)Status; + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* + Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base + Address MSR register. + */ + MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (8 << 2) | 1; + LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); + + /* + Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. + */ + LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); + MsrReg = MsrReg | 0x0000400000000000; + LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); + + /* Set Ontario Link Data */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0); + PciData = 0x01308002; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4); + PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + + /* Set ROM cache onto WP to decrease post time */ + MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5; + LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); + MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800; + LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); + + Status = AGESA_SUCCESS; + return (UINT32)Status; } UINT32 agesawrapper_amdinitreset ( - VOID - ) + VOID + ) { - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESET_PARAMS AmdResetParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - - LibAmdMemFill (&AmdResetParams, - 0, - sizeof (AMD_RESET_PARAMS), - &(AmdResetParams.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; - AmdParamStruct.AllocationMethod = ByHost; - AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); - AmdParamStruct.NewStructPtr = &AmdResetParams; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = NULL; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - AmdResetParams.HtConfig.Depth = 0; - - status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); - AmdReleaseStruct (&AmdParamStruct); - return (UINT32)status; + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESET_PARAMS AmdResetParams; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + + LibAmdMemFill (&AmdResetParams, + 0, + sizeof (AMD_RESET_PARAMS), + &(AmdResetParams.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; + AmdParamStruct.AllocationMethod = ByHost; + AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); + AmdParamStruct.NewStructPtr = &AmdResetParams; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = NULL; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + AmdResetParams.HtConfig.Depth = 0; + + status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + return (UINT32)status; } UINT32 agesawrapper_amdinitearly ( - VOID - ) + VOID + ) { - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_EARLY_PARAMS *AmdEarlyParamsPtr; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - - AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; - OemCustomizeInitEarly (AmdEarlyParamsPtr); - - status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); - AmdReleaseStruct (&AmdParamStruct); - - return (UINT32)status; + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_EARLY_PARAMS *AmdEarlyParamsPtr; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + + AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; + OemCustomizeInitEarly (AmdEarlyParamsPtr); + + status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; } UINT32 agesawrapper_amdinitpost ( - VOID - ) + VOID + ) { - AGESA_STATUS status; - UINT16 i; - UINT32 *HeadPtr; - AMD_INTERFACE_PARAMS AmdParamStruct; - BIOS_HEAP_MANAGER *BiosManagerPtr; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct (&AmdParamStruct); - status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); - AmdReleaseStruct (&AmdParamStruct); - /* Initialize heap space */ - BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS; - - HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); - for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) - { - *HeadPtr = 0x00000000; - HeadPtr++; - } - BiosManagerPtr->StartOfAllocatedNodes = 0; - BiosManagerPtr->StartOfFreedNodes = 0; - - return (UINT32)status; + AGESA_STATUS status; + UINT16 i; + UINT32 *HeadPtr; + AMD_INTERFACE_PARAMS AmdParamStruct; + BIOS_HEAP_MANAGER *BiosManagerPtr; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct (&AmdParamStruct); + status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + /* Initialize heap space */ + BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS; + + HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); + for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) + { + *HeadPtr = 0x00000000; + HeadPtr++; + } + BiosManagerPtr->StartOfAllocatedNodes = 0; + BiosManagerPtr->StartOfFreedNodes = 0; + + return (UINT32)status; } UINT32 agesawrapper_amdinitenv ( - VOID - ) + VOID + ) { - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - PCI_ADDR PciAddress; - UINT32 PciValue; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); - /* Initialize Subordinate Bus Number and Secondary Bus Number - * In platform BIOS this address is allocated by PCI enumeration code - Modify D1F0x18 - */ - PciAddress.Address.Bus = 0; - PciAddress.Address.Device = 1; - PciAddress.Address.Function = 0; - PciAddress.Address.Register = 0x18; - /* Write to D1F0x18 */ - LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - PciValue |= 0x00010100; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - - /* Initialize GMM Base Address for Legacy Bridge Mode - * Modify B1D5F0x18 - */ - PciAddress.Address.Bus = 1; - PciAddress.Address.Device = 5; - PciAddress.Address.Function = 0; - PciAddress.Address.Register = 0x18; - - LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - PciValue |= 0x96000000; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - - /* Initialize FB Base Address for Legacy Bridge Mode - * Modify B1D5F0x10 - */ - PciAddress.Address.Register = 0x10; - LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - PciValue |= 0x80000000; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - - /* Initialize GMM Base Address for Pcie Mode - * Modify B0D1F0x18 - */ - PciAddress.Address.Bus = 0; - PciAddress.Address.Device = 1; - PciAddress.Address.Function = 0; - PciAddress.Address.Register = 0x18; - - LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - PciValue |= 0x96000000; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - - /* Initialize FB Base Address for Pcie Mode - * Modify B0D1F0x10 - */ - PciAddress.Address.Register = 0x10; - LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - PciValue |= 0x80000000; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - - - /* Initialize MMIO Base and Limit Address - * Modify B0D1F0x20 - */ - PciAddress.Address.Bus = 0; - PciAddress.Address.Device = 1; - PciAddress.Address.Function = 0; - PciAddress.Address.Register = 0x20; - - LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - PciValue |= 0x96009600; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - - /* Initialize MMIO Prefetchable Memory Limit and Base - * Modify B0D1F0x24 - */ - PciAddress.Address.Register = 0x24; - LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - PciValue |= 0x8FF18001; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - AmdReleaseStruct (&AmdParamStruct); - - return (UINT32)status; + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + PCI_ADDR PciAddress; + UINT32 PciValue; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + /* Initialize Subordinate Bus Number and Secondary Bus Number + * In platform BIOS this address is allocated by PCI enumeration code + Modify D1F0x18 + */ + PciAddress.Address.Bus = 0; + PciAddress.Address.Device = 1; + PciAddress.Address.Function = 0; + PciAddress.Address.Register = 0x18; + /* Write to D1F0x18 */ + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x00010100; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize GMM Base Address for Legacy Bridge Mode + * Modify B1D5F0x18 + */ + PciAddress.Address.Bus = 1; + PciAddress.Address.Device = 5; + PciAddress.Address.Function = 0; + PciAddress.Address.Register = 0x18; + + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x96000000; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize FB Base Address for Legacy Bridge Mode + * Modify B1D5F0x10 + */ + PciAddress.Address.Register = 0x10; + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x80000000; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize GMM Base Address for Pcie Mode + * Modify B0D1F0x18 + */ + PciAddress.Address.Bus = 0; + PciAddress.Address.Device = 1; + PciAddress.Address.Function = 0; + PciAddress.Address.Register = 0x18; + + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x96000000; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize FB Base Address for Pcie Mode + * Modify B0D1F0x10 + */ + PciAddress.Address.Register = 0x10; + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x80000000; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + + /* Initialize MMIO Base and Limit Address + * Modify B0D1F0x20 + */ + PciAddress.Address.Bus = 0; + PciAddress.Address.Device = 1; + PciAddress.Address.Function = 0; + PciAddress.Address.Register = 0x20; + + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x96009600; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize MMIO Prefetchable Memory Limit and Base + * Modify B0D1F0x24 + */ + PciAddress.Address.Register = 0x24; + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x8FF18001; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; } VOID * agesawrapper_getlateinitptr ( - int pick - ) + int pick + ) { - switch (pick) { - case PICK_DMI: - return DmiTable; - - case PICK_PSTATE: - return AcpiPstate; - - case PICK_SRAT: - return AcpiSrat; - - case PICK_SLIT: - return AcpiSlit; - case PICK_WHEA_MCE: - return AcpiWheaMce; - case PICK_WHEA_CMC: - return AcpiWheaCmc; - case PICK_ALIB: - return AcpiAlib; - default: - return NULL; - } + switch (pick) { + case PICK_DMI: + return DmiTable; + case PICK_PSTATE: + return AcpiPstate; + case PICK_SRAT: + return AcpiSrat; + case PICK_SLIT: + return AcpiSlit; + case PICK_WHEA_MCE: + return AcpiWheaMce; + case PICK_WHEA_CMC: + return AcpiWheaCmc; + case PICK_ALIB: + return AcpiAlib; + default: + return NULL; + } } UINT32 agesawrapper_amdinitmid ( - VOID - ) + VOID + ) { - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; - /* Enable MMIO on AMD CPU Address Map Controller */ - agesawrapper_amdinitcpuio (); + /* Enable MMIO on AMD CPU Address Map Controller */ + agesawrapper_amdinitcpuio (); - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); - AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); + AmdCreateStruct (&AmdParamStruct); - status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); - AmdReleaseStruct (&AmdParamStruct); + status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); - return (UINT32)status; + return (UINT32)status; } UINT32 agesawrapper_amdinitlate ( - VOID - ) + VOID + ) { - AGESA_STATUS Status; - AMD_LATE_PARAMS AmdLateParams; - - LibAmdMemFill (&AmdLateParams, - 0, - sizeof (AMD_LATE_PARAMS), - &(AmdLateParams.StdHeader)); - - AmdLateParams.StdHeader.AltImageBasePtr = 0; - AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdLateParams.StdHeader.Func = 0; - AmdLateParams.StdHeader.ImageBasePtr = 0; - - Status = AmdInitLate (&AmdLateParams); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); - } - - DmiTable = AmdLateParams.DmiTable; - AcpiPstate = AmdLateParams.AcpiPState; - AcpiSrat = AmdLateParams.AcpiSrat; - AcpiSlit = AmdLateParams.AcpiSlit; - - AcpiWheaMce = AmdLateParams.AcpiWheaMce; - AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; - AcpiAlib = AmdLateParams.AcpiAlib; - - return (UINT32)Status; + AGESA_STATUS Status; + AMD_LATE_PARAMS AmdLateParams; + + LibAmdMemFill (&AmdLateParams, + 0, + sizeof (AMD_LATE_PARAMS), + &(AmdLateParams.StdHeader)); + + AmdLateParams.StdHeader.AltImageBasePtr = 0; + AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdLateParams.StdHeader.Func = 0; + AmdLateParams.StdHeader.ImageBasePtr = 0; + + Status = AmdInitLate (&AmdLateParams); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(); + ASSERT(Status == AGESA_SUCCESS); + } + + DmiTable = AmdLateParams.DmiTable; + AcpiPstate = AmdLateParams.AcpiPState; + AcpiSrat = AmdLateParams.AcpiSrat; + AcpiSlit = AmdLateParams.AcpiSlit; + AcpiWheaMce = AmdLateParams.AcpiWheaMce; + AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; + AcpiAlib = AmdLateParams.AcpiAlib; + + return (UINT32)Status; } UINT32 agesawrapper_amdlaterunaptask ( - UINT32 Data, - VOID *ConfigPtr - ) + UINT32 Data, + VOID *ConfigPtr + ) { - AGESA_STATUS Status; - AMD_LATE_PARAMS AmdLateParams; - - LibAmdMemFill (&AmdLateParams, - 0, - sizeof (AMD_LATE_PARAMS), - &(AmdLateParams.StdHeader)); - - AmdLateParams.StdHeader.AltImageBasePtr = 0; - AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdLateParams.StdHeader.Func = 0; - AmdLateParams.StdHeader.ImageBasePtr = 0; - - Status = AmdLateRunApTask (&AmdLateParams); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); - } - - DmiTable = AmdLateParams.DmiTable; - AcpiPstate = AmdLateParams.AcpiPState; - AcpiSrat = AmdLateParams.AcpiSrat; - AcpiSlit = AmdLateParams.AcpiSlit; - - AcpiWheaMce = AmdLateParams.AcpiWheaMce; - AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; - AcpiAlib = AmdLateParams.AcpiAlib; - - return (UINT32)Status; + AGESA_STATUS Status; + AMD_LATE_PARAMS AmdLateParams; + + LibAmdMemFill (&AmdLateParams, + 0, + sizeof (AMD_LATE_PARAMS), + &(AmdLateParams.StdHeader)); + + AmdLateParams.StdHeader.AltImageBasePtr = 0; + AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdLateParams.StdHeader.Func = 0; + AmdLateParams.StdHeader.ImageBasePtr = 0; + + Status = AmdLateRunApTask (&AmdLateParams); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(); + ASSERT(Status == AGESA_SUCCESS); + } + + DmiTable = AmdLateParams.DmiTable; + AcpiPstate = AmdLateParams.AcpiPState; + AcpiSrat = AmdLateParams.AcpiSrat; + AcpiSlit = AmdLateParams.AcpiSlit; + AcpiWheaMce = AmdLateParams.AcpiWheaMce; + AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; + AcpiAlib = AmdLateParams.AcpiAlib; + + return (UINT32)Status; } UINT32 agesawrapper_amdreadeventlog ( - VOID - ) + VOID + ) { - AGESA_STATUS Status; - EVENT_PARAMS AmdEventParams; - - LibAmdMemFill (&AmdEventParams, - 0, - sizeof (EVENT_PARAMS), - &(AmdEventParams.StdHeader)); - - AmdEventParams.StdHeader.AltImageBasePtr = 0; - AmdEventParams.StdHeader.CalloutPtr = NULL; - AmdEventParams.StdHeader.Func = 0; - AmdEventParams.StdHeader.ImageBasePtr = 0; - Status = AmdReadEventLog (&AmdEventParams); - while (AmdEventParams.EventClass != 0) { - printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo); - printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2); - printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4); - Status = AmdReadEventLog (&AmdEventParams); - } - - return (UINT32)Status; + AGESA_STATUS Status; + EVENT_PARAMS AmdEventParams; + + LibAmdMemFill (&AmdEventParams, + 0, + sizeof (EVENT_PARAMS), + &(AmdEventParams.StdHeader)); + + AmdEventParams.StdHeader.AltImageBasePtr = 0; + AmdEventParams.StdHeader.CalloutPtr = NULL; + AmdEventParams.StdHeader.Func = 0; + AmdEventParams.StdHeader.ImageBasePtr = 0; + Status = AmdReadEventLog (&AmdEventParams); + while (AmdEventParams.EventClass != 0) { + printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo); + printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2); + printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4); + Status = AmdReadEventLog (&AmdEventParams); + } + + return (UINT32)Status; } diff --git a/src/mainboard/amd/persimmon/acpi_tables.c b/src/mainboard/amd/persimmon/acpi_tables.c index 637a304..99a6e88 100644 --- a/src/mainboard/amd/persimmon/acpi_tables.c +++ b/src/mainboard/amd/persimmon/acpi_tables.c @@ -9,12 +9,12 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <console/console.h> @@ -130,23 +130,23 @@ unsigned long write_acpi_tables(unsigned long start) /* DSDT */ current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); + printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); dsdt = (acpi_header_t *)current; // it will used by fadt memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); current += dsdt->length; memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); /* FACS */ // it needs 64 bit alignment current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); + printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); facs = (acpi_facs_t *) current; // it will be used by fadt current += sizeof(acpi_facs_t); acpi_create_facs(facs); /* FDAT */ current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); + printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); fadt = (acpi_fadt_t *) current; current += sizeof(acpi_fadt_t); @@ -157,7 +157,7 @@ unsigned long write_acpi_tables(unsigned long start) * We explicitly add these tables later on: */ current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); + printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); hpet = (acpi_hpet_t *) current; current += sizeof(acpi_hpet_t); acpi_create_hpet(hpet); @@ -165,7 +165,7 @@ unsigned long write_acpi_tables(unsigned long start) /* If we want to use HPET Timers Linux wants an MADT */ current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); + printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); madt = (acpi_madt_t *) current; acpi_create_madt(madt); current += madt->header.length; @@ -173,31 +173,31 @@ unsigned long write_acpi_tables(unsigned long start) /* SRAT */ current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); + printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); if (srat != NULL) { - memcpy((void *)current, srat, srat->header.length); - srat = (acpi_srat_t *) current; - //acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); + memcpy((void *)current, srat, srat->header.length); + srat = (acpi_srat_t *) current; + //acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); } /* SLIT */ current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); + printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); if (slit != NULL) { - memcpy((void *)current, slit, slit->header.length); - slit = (acpi_slit_t *) current; - //acpi_create_slit(slit); - current += slit->header.length; - acpi_add_table(rsdp, slit); + memcpy((void *)current, slit, slit->header.length); + slit = (acpi_slit_t *) current; + //acpi_create_slit(slit); + current += slit->header.length; + acpi_add_table(rsdp, slit); } /* SSDT */ current = ( current + 0x0f) & -0x10; - printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); + printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); if (ssdt != NULL) { memcpy((void *)current, ssdt, ssdt->length); @@ -215,7 +215,7 @@ unsigned long write_acpi_tables(unsigned long start) } acpi_add_table(rsdp,ssdt); - printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); + printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); #if DUMP_ACPI_TABLES == 1 printk(BIOS_DEBUG, "rsdp\n"); diff --git a/src/mainboard/amd/persimmon/agesawrapper.c b/src/mainboard/amd/persimmon/agesawrapper.c index 89f171b..55e8488 100644 --- a/src/mainboard/amd/persimmon/agesawrapper.c +++ b/src/mainboard/amd/persimmon/agesawrapper.c @@ -9,17 +9,17 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- +/*----------------------------------------------------------------------------- + * M O D U L E S U S E D + *----------------------------------------------------------------------------- */ #include <stdint.h> @@ -40,52 +40,52 @@ #define FILECODE UNASSIGNED_FILE_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- +/*------------------------------------------------------------------------------ + * D E F I N I T I O N S A N D M A C R O S + *------------------------------------------------------------------------------ */ #define MMCONF_ENABLE 1 /* ACPI table pointers returned by AmdInitLate */ -VOID *DmiTable = NULL; +VOID *DmiTable = NULL; VOID *AcpiPstate = NULL; -VOID *AcpiSrat = NULL; -VOID *AcpiSlit = NULL; +VOID *AcpiSrat = NULL; +VOID *AcpiSlit = NULL; -VOID *AcpiWheaMce = NULL; -VOID *AcpiWheaCmc = NULL; -VOID *AcpiAlib = NULL; +VOID *AcpiWheaMce = NULL; +VOID *AcpiWheaCmc = NULL; +VOID *AcpiAlib = NULL; -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- +/*------------------------------------------------------------------------------ + * T Y P E D E F S A N D S T R U C T U R E S + *------------------------------------------------------------------------------ */ -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- +/*------------------------------------------------------------------------------ + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *------------------------------------------------------------------------------ */ -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- +/*------------------------------------------------------------------------------ + * E X P O R T E D F U N C T I O N S + *------------------------------------------------------------------------------ */ -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- +/*------------------------------------------------------------------------------ + * L O C A L F U N C T I O N S + *------------------------------------------------------------------------------ */ UINT32 agesawrapper_amdinitcpuio ( VOID ) { - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; /* Enable legacy video routing: D18F1xF4 VGA Enable */ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); @@ -98,7 +98,7 @@ agesawrapper_amdinitcpuio ( */ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000 - PciData |= 1 << 7; // set NP (non-posted) bit + PciData |= 1 << 7; // set NP (non-posted) bit LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000 @@ -130,15 +130,15 @@ agesawrapper_amdinitmmio ( VOID ) { - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; - UINT8 BusRangeVal = 0; - UINT8 BusNum; - UINT8 Index; + UINT8 BusRangeVal = 0; + UINT8 BusNum; + UINT8 Index; /* Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base @@ -185,14 +185,14 @@ agesawrapper_amdinitreset ( AMD_RESET_PARAMS AmdResetParams; LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); LibAmdMemFill (&AmdResetParams, - 0, - sizeof (AMD_RESET_PARAMS), - &(AmdResetParams.StdHeader)); + 0, + sizeof (AMD_RESET_PARAMS), + &(AmdResetParams.StdHeader)); AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; AmdParamStruct.AllocationMethod = ByHost; @@ -218,12 +218,12 @@ agesawrapper_amdinitearly ( { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_EARLY_PARAMS *AmdEarlyParamsPtr; + AMD_EARLY_PARAMS *AmdEarlyParamsPtr; LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -250,14 +250,14 @@ agesawrapper_amdinitpost ( { AGESA_STATUS status; UINT16 i; - UINT32 *HeadPtr; + UINT32 *HeadPtr; AMD_INTERFACE_PARAMS AmdParamStruct; - BIOS_HEAP_MANAGER *BiosManagerPtr; + BIOS_HEAP_MANAGER *BiosManagerPtr; LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -275,7 +275,8 @@ agesawrapper_amdinitpost ( BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS; HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); - for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) { + for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) + { *HeadPtr = 0x00000000; HeadPtr++; } @@ -296,9 +297,9 @@ agesawrapper_amdinitenv ( UINT32 PciValue; LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; AmdParamStruct.AllocationMethod = PostMemDram; @@ -311,7 +312,7 @@ agesawrapper_amdinitenv ( if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); /* Initialize Subordinate Bus Number and Secondary Bus Number * In platform BIOS this address is allocated by PCI enumeration code - Modify D1F0x18 + Modify D1F0x18 */ PciAddress.Address.Bus = 0; PciAddress.Address.Device = 1; @@ -423,9 +424,9 @@ agesawrapper_amdinitmid ( agesawrapper_amdinitcpuio (); LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; AmdParamStruct.AllocationMethod = PostMemDram; @@ -452,9 +453,9 @@ agesawrapper_amdinitlate ( AMD_LATE_PARAMS AmdLateParams; LibAmdMemFill (&AmdLateParams, - 0, - sizeof (AMD_LATE_PARAMS), - &(AmdLateParams.StdHeader)); + 0, + sizeof (AMD_LATE_PARAMS), + &(AmdLateParams.StdHeader)); AmdLateParams.StdHeader.AltImageBasePtr = 0; AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; @@ -467,14 +468,14 @@ agesawrapper_amdinitlate ( ASSERT(Status == AGESA_SUCCESS); } - DmiTable = AmdLateParams.DmiTable; - AcpiPstate = AmdLateParams.AcpiPState; - AcpiSrat = AmdLateParams.AcpiSrat; - AcpiSlit = AmdLateParams.AcpiSlit; + DmiTable = AmdLateParams.DmiTable; + AcpiPstate = AmdLateParams.AcpiPState; + AcpiSrat = AmdLateParams.AcpiSrat; + AcpiSlit = AmdLateParams.AcpiSlit; - AcpiWheaMce = AmdLateParams.AcpiWheaMce; - AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; - AcpiAlib = AmdLateParams.AcpiAlib; + AcpiWheaMce = AmdLateParams.AcpiWheaMce; + AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; + AcpiAlib = AmdLateParams.AcpiAlib; return (UINT32)Status; } @@ -490,9 +491,9 @@ agesawrapper_amdlaterunaptask ( AP_EXE_PARAMS ApExeParams; LibAmdMemFill (&ApExeParams, - 0, - sizeof (AP_EXE_PARAMS), - &(ApExeParams.StdHeader)); + 0, + sizeof (AP_EXE_PARAMS), + &(ApExeParams.StdHeader)); ApExeParams.StdHeader.AltImageBasePtr = 0; ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; @@ -520,9 +521,9 @@ agesawrapper_amdreadeventlog ( EVENT_PARAMS AmdEventParams; LibAmdMemFill (&AmdEventParams, - 0, - sizeof (EVENT_PARAMS), - &(AmdEventParams.StdHeader)); + 0, + sizeof (EVENT_PARAMS), + &(AmdEventParams.StdHeader)); AmdEventParams.StdHeader.AltImageBasePtr = 0; AmdEventParams.StdHeader.CalloutPtr = NULL; diff --git a/src/mainboard/amd/south_station/acpi_tables.c b/src/mainboard/amd/south_station/acpi_tables.c index 2a299d8..ae058d6 100644 --- a/src/mainboard/amd/south_station/acpi_tables.c +++ b/src/mainboard/amd/south_station/acpi_tables.c @@ -35,15 +35,15 @@ static void dump_mem(u32 start, u32 end) { - u32 i; - print_debug("dump_mem:"); - for (i = start; i < end; i++) { - if ((i & 0xf) == 0) { - printk(BIOS_DEBUG, "\n%08x:", i); - } - printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i)); - } - print_debug("\n"); + u32 i; + print_debug("dump_mem:"); + for (i = start; i < end; i++) { + if ((i & 0xf) == 0) { + printk(BIOS_DEBUG, "\n%08x:", i); + } + printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i)); + } + print_debug("\n"); } #endif @@ -52,197 +52,197 @@ extern const unsigned char AmlCode_ssdt[]; unsigned long acpi_fill_mcfg(unsigned long current) { - /* Just a dummy */ - return current; + /* Just a dummy */ + return current; } unsigned long acpi_fill_madt(unsigned long current) { - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, - IO_APIC_ADDR, 0); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edige-triggered, Active high */ - - /* create all subtables for processors */ - /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ - /* 1: LINT1 connect to NMI */ - - return current; + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write SB800 IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, + IO_APIC_ADDR, 0); + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, 0xF); + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edige-triggered, Active high */ + + /* create all subtables for processors */ + /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ + /* 1: LINT1 connect to NMI */ + + return current; } unsigned long acpi_fill_slit(unsigned long current) { - // Not implemented - return current; + // Not implemented + return current; } unsigned long acpi_fill_srat(unsigned long current) { - /* No NUMA, no SRAT */ - return current; + /* No NUMA, no SRAT */ + return current; } unsigned long write_acpi_tables(unsigned long start) { - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_srat_t *srat; - acpi_slit_t *slit; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; - - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - - /* Align ACPI tables to 16 bytes */ - start = (start + 0x0f) & -0x10; - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* DSDT */ - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); - dsdt = (acpi_header_t *)current; // it will used by fadt - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); - - /* FACS */ // it needs 64 bit alignment - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); - facs = (acpi_facs_t *) current; // it will be used by fadt - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* FDAT */ - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - /* - * We explicitly add these tables later on: - */ - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - /* If we want to use HPET Timers Linux wants an MADT */ - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - /* SRAT */ - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); - srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); - if (srat != NULL) { - memcpy((void *)current, srat, srat->header.length); - srat = (acpi_srat_t *) current; - //acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - } - - /* SLIT */ - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); - slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); - if (slit != NULL) { - memcpy((void *)current, slit, slit->header.length); - slit = (acpi_slit_t *) current; - //acpi_create_slit(slit); - current += slit->header.length; - acpi_add_table(rsdp, slit); - } - - /* SSDT */ - current = ( current + 0x0f) & -0x10; - printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); - ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); - if (ssdt != NULL) { - memcpy((void *)current, ssdt, ssdt->length); - ssdt = (acpi_header_t *) current; - current += ssdt->length; - } - else { - ssdt = (acpi_header_t *) current; - memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); - current += ssdt->length; - memcpy(ssdt, &AmlCode_ssdt, ssdt->length); - char *position = ssdt; - if (memcmp(position + 50, "TOM1", 4) == 0) - *(u32 *)(position + 55) = __readmsr(0xc001001a); - - /* recalculate checksum */ - ssdt->checksum = 0; - ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); - } - acpi_add_table(rsdp,ssdt); - - printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_srat_t *srat; + acpi_slit_t *slit; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *dsdt; + acpi_header_t *ssdt; + + get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ + + /* Align ACPI tables to 16 bytes */ + start = (start + 0x0f) & -0x10; + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* clear all table memory */ + memset((void *)start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* DSDT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); + dsdt = (acpi_header_t *)current; // it will used by fadt + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); + + /* FACS */ // it needs 64 bit alignment + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); + facs = (acpi_facs_t *) current; // it will be used by fadt + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + /* FDAT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* + * We explicitly add these tables later on: + */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + acpi_create_hpet(hpet); + acpi_add_table(rsdp, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdp, madt); + + /* SRAT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); + srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); + if (srat != NULL) { + memcpy((void *)current, srat, srat->header.length); + srat = (acpi_srat_t *) current; + //acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + } + + /* SLIT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); + slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); + if (slit != NULL) { + memcpy((void *)current, slit, slit->header.length); + slit = (acpi_slit_t *) current; + //acpi_create_slit(slit); + current += slit->header.length; + acpi_add_table(rsdp, slit); + } + + /* SSDT */ + current = ( current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); + ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); + if (ssdt != NULL) { + memcpy((void *)current, ssdt, ssdt->length); + ssdt = (acpi_header_t *) current; + current += ssdt->length; + } + else { + ssdt = (acpi_header_t *) current; + memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); + current += ssdt->length; + memcpy(ssdt, &AmlCode_ssdt, ssdt->length); + char *position = ssdt; + if (memcmp(position + 50, "TOM1", 4) == 0) + *(u32 *)(position + 55) = __readmsr(0xc001001a); + + /* recalculate checksum */ + ssdt->checksum = 0; + ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); + } + acpi_add_table(rsdp,ssdt); + + printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); #if DUMP_ACPI_TABLES == 1 - printk(BIOS_DEBUG, "rsdp\n"); - dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t)); + printk(BIOS_DEBUG, "rsdp\n"); + dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t)); - printk(BIOS_DEBUG, "rsdt\n"); - dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t)); + printk(BIOS_DEBUG, "rsdt\n"); + dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t)); - printk(BIOS_DEBUG, "madt\n"); - dump_mem(madt, ((void *)madt) + madt->header.length); + printk(BIOS_DEBUG, "madt\n"); + dump_mem(madt, ((void *)madt) + madt->header.length); - printk(BIOS_DEBUG, "srat\n"); - dump_mem(srat, ((void *)srat) + srat->header.length); + printk(BIOS_DEBUG, "srat\n"); + dump_mem(srat, ((void *)srat) + srat->header.length); - printk(BIOS_DEBUG, "slit\n"); - dump_mem(slit, ((void *)slit) + slit->header.length); + printk(BIOS_DEBUG, "slit\n"); + dump_mem(slit, ((void *)slit) + slit->header.length); - printk(BIOS_DEBUG, "ssdt\n"); - dump_mem(ssdt, ((void *)ssdt) + ssdt->length); + printk(BIOS_DEBUG, "ssdt\n"); + dump_mem(ssdt, ((void *)ssdt) + ssdt->length); - printk(BIOS_DEBUG, "fadt\n"); - dump_mem(fadt, ((void *)fadt) + fadt->header.length); + printk(BIOS_DEBUG, "fadt\n"); + dump_mem(fadt, ((void *)fadt) + fadt->header.length); #endif - printk(BIOS_INFO, "ACPI: done.\n"); - return current; + printk(BIOS_INFO, "ACPI: done.\n"); + return current; } diff --git a/src/mainboard/amd/south_station/agesawrapper.c b/src/mainboard/amd/south_station/agesawrapper.c index 74aa73d..55e8488 100644 --- a/src/mainboard/amd/south_station/agesawrapper.c +++ b/src/mainboard/amd/south_station/agesawrapper.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- +/*----------------------------------------------------------------------------- + * M O D U L E S U S E D + *----------------------------------------------------------------------------- */ #include <stdint.h> @@ -40,502 +40,502 @@ #define FILECODE UNASSIGNED_FILE_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- +/*------------------------------------------------------------------------------ + * D E F I N I T I O N S A N D M A C R O S + *------------------------------------------------------------------------------ */ #define MMCONF_ENABLE 1 /* ACPI table pointers returned by AmdInitLate */ -VOID *DmiTable = NULL; -VOID *AcpiPstate = NULL; -VOID *AcpiSrat = NULL; -VOID *AcpiSlit = NULL; - -VOID *AcpiWheaMce = NULL; -VOID *AcpiWheaCmc = NULL; -VOID *AcpiAlib = NULL; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- +VOID *DmiTable = NULL; +VOID *AcpiPstate = NULL; +VOID *AcpiSrat = NULL; +VOID *AcpiSlit = NULL; + +VOID *AcpiWheaMce = NULL; +VOID *AcpiWheaCmc = NULL; +VOID *AcpiAlib = NULL; + +/*------------------------------------------------------------------------------ + * T Y P E D E F S A N D S T R U C T U R E S + *------------------------------------------------------------------------------ */ -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- +/*------------------------------------------------------------------------------ + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *------------------------------------------------------------------------------ */ -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- +/*------------------------------------------------------------------------------ + * E X P O R T E D F U N C T I O N S + *------------------------------------------------------------------------------ */ -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- +/*------------------------------------------------------------------------------ + * L O C A L F U N C T I O N S + *------------------------------------------------------------------------------ */ UINT32 agesawrapper_amdinitcpuio ( - VOID - ) + VOID + ) { - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; - - /* Enable legacy video routing: D18F1xF4 VGA Enable */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); - PciData = 1; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* The platform BIOS needs to ensure the memory ranges of SB800 legacy - * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are - * set to non-posted regions. - */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); - PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000 - PciData |= 1 << 7; // set NP (non-posted) bit - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); - PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000 - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Map the remaining PCI hole as posted MMIO */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); - PciData = 0x00FECF00; // last address before non-posted range - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); - MsrReg = (MsrReg >> 8) | 3; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); - PciData = (UINT32)MsrReg; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Send all IO (0000-FFFF) to southbridge. */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); - PciData = 0x0000F000; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); - PciData = 0x00000003; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - Status = AGESA_SUCCESS; - return (UINT32)Status; + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* Enable legacy video routing: D18F1xF4 VGA Enable */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); + PciData = 1; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* The platform BIOS needs to ensure the memory ranges of SB800 legacy + * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are + * set to non-posted regions. + */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); + PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000 + PciData |= 1 << 7; // set NP (non-posted) bit + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); + PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000 + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Map the remaining PCI hole as posted MMIO */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); + PciData = 0x00FECF00; // last address before non-posted range + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); + MsrReg = (MsrReg >> 8) | 3; + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); + PciData = (UINT32)MsrReg; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Send all IO (0000-FFFF) to southbridge. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); + PciData = 0x0000F000; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); + PciData = 0x00000003; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + Status = AGESA_SUCCESS; + return (UINT32)Status; } UINT32 agesawrapper_amdinitmmio ( - VOID - ) + VOID + ) { - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; - - UINT8 BusRangeVal = 0; - UINT8 BusNum; - UINT8 Index; - - /* - Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base - Address MSR register. - */ - - for (Index = 0; Index < 8; Index++) { - BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index; - if (BusNum == 1) { - BusRangeVal = Index; - break; - } - } - - MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (UINT64)(BusRangeVal << 2) | MMCONF_ENABLE); - LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); - - /* - Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. - */ - LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); - MsrReg = MsrReg | 0x0000400000000000ull; - LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - - /* Set Ontario Link Data */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0); - PciData = 0x01308002; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4); - PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - Status = AGESA_SUCCESS; - return (UINT32)Status; + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + UINT8 BusRangeVal = 0; + UINT8 BusNum; + UINT8 Index; + + /* + Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base + Address MSR register. + */ + + for (Index = 0; Index < 8; Index++) { + BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index; + if (BusNum == 1) { + BusRangeVal = Index; + break; + } + } + + MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (UINT64)(BusRangeVal << 2) | MMCONF_ENABLE); + LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); + + /* + Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. + */ + LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); + MsrReg = MsrReg | 0x0000400000000000ull; + LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); + + /* Set Ontario Link Data */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0); + PciData = 0x01308002; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4); + PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + Status = AGESA_SUCCESS; + return (UINT32)Status; } UINT32 agesawrapper_amdinitreset ( - VOID - ) + VOID + ) { - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESET_PARAMS AmdResetParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - LibAmdMemFill (&AmdResetParams, - 0, - sizeof (AMD_RESET_PARAMS), - &(AmdResetParams.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; - AmdParamStruct.AllocationMethod = ByHost; - AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); - AmdParamStruct.NewStructPtr = &AmdResetParams; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = NULL; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - AmdResetParams.HtConfig.Depth = 0; - - status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); - AmdReleaseStruct (&AmdParamStruct); - return (UINT32)status; + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESET_PARAMS AmdResetParams; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + LibAmdMemFill (&AmdResetParams, + 0, + sizeof (AMD_RESET_PARAMS), + &(AmdResetParams.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; + AmdParamStruct.AllocationMethod = ByHost; + AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); + AmdParamStruct.NewStructPtr = &AmdResetParams; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = NULL; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + AmdResetParams.HtConfig.Depth = 0; + + status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + return (UINT32)status; } UINT32 agesawrapper_amdinitearly ( - VOID - ) + VOID + ) { - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_EARLY_PARAMS *AmdEarlyParamsPtr; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - - AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; - OemCustomizeInitEarly (AmdEarlyParamsPtr); - - status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); - AmdReleaseStruct (&AmdParamStruct); - - return (UINT32)status; + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_EARLY_PARAMS *AmdEarlyParamsPtr; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + + AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; + OemCustomizeInitEarly (AmdEarlyParamsPtr); + + status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; } UINT32 agesawrapper_amdinitpost ( - VOID - ) + VOID + ) { - AGESA_STATUS status; - UINT16 i; - UINT32 *HeadPtr; - AMD_INTERFACE_PARAMS AmdParamStruct; - BIOS_HEAP_MANAGER *BiosManagerPtr; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct (&AmdParamStruct); - status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); - AmdReleaseStruct (&AmdParamStruct); - - /* Initialize heap space */ - BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS; - - HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); - for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) - { - *HeadPtr = 0x00000000; - HeadPtr++; - } - BiosManagerPtr->StartOfAllocatedNodes = 0; - BiosManagerPtr->StartOfFreedNodes = 0; - - return (UINT32)status; + AGESA_STATUS status; + UINT16 i; + UINT32 *HeadPtr; + AMD_INTERFACE_PARAMS AmdParamStruct; + BIOS_HEAP_MANAGER *BiosManagerPtr; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct (&AmdParamStruct); + status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + /* Initialize heap space */ + BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS; + + HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); + for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) + { + *HeadPtr = 0x00000000; + HeadPtr++; + } + BiosManagerPtr->StartOfAllocatedNodes = 0; + BiosManagerPtr->StartOfFreedNodes = 0; + + return (UINT32)status; } UINT32 agesawrapper_amdinitenv ( - VOID - ) + VOID + ) { - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - PCI_ADDR PciAddress; - UINT32 PciValue; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); - /* Initialize Subordinate Bus Number and Secondary Bus Number - * In platform BIOS this address is allocated by PCI enumeration code - Modify D1F0x18 - */ - PciAddress.Address.Bus = 0; - PciAddress.Address.Device = 1; - PciAddress.Address.Function = 0; - PciAddress.Address.Register = 0x18; - /* Write to D1F0x18 */ - LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - PciValue |= 0x00010100; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - - /* Initialize GMM Base Address for Legacy Bridge Mode - * Modify B1D5F0x18 - */ - PciAddress.Address.Bus = 1; - PciAddress.Address.Device = 5; - PciAddress.Address.Function = 0; - PciAddress.Address.Register = 0x18; - - LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - PciValue |= 0x96000000; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - - /* Initialize FB Base Address for Legacy Bridge Mode - * Modify B1D5F0x10 - */ - PciAddress.Address.Register = 0x10; - LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - PciValue |= 0x80000000; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - - /* Initialize GMM Base Address for Pcie Mode - * Modify B0D1F0x18 - */ - PciAddress.Address.Bus = 0; - PciAddress.Address.Device = 1; - PciAddress.Address.Function = 0; - PciAddress.Address.Register = 0x18; - - LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - PciValue |= 0x96000000; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - - /* Initialize FB Base Address for Pcie Mode - * Modify B0D1F0x10 - */ - PciAddress.Address.Register = 0x10; - LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - PciValue |= 0x80000000; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - - /* Initialize MMIO Base and Limit Address - * Modify B0D1F0x20 - */ - PciAddress.Address.Bus = 0; - PciAddress.Address.Device = 1; - PciAddress.Address.Function = 0; - PciAddress.Address.Register = 0x20; - - LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - PciValue |= 0x96009600; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - - /* Initialize MMIO Prefetchable Memory Limit and Base - * Modify B0D1F0x24 - */ - PciAddress.Address.Register = 0x24; - LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - PciValue |= 0x8FF18001; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - AmdReleaseStruct (&AmdParamStruct); - - return (UINT32)status; + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + PCI_ADDR PciAddress; + UINT32 PciValue; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + /* Initialize Subordinate Bus Number and Secondary Bus Number + * In platform BIOS this address is allocated by PCI enumeration code + Modify D1F0x18 + */ + PciAddress.Address.Bus = 0; + PciAddress.Address.Device = 1; + PciAddress.Address.Function = 0; + PciAddress.Address.Register = 0x18; + /* Write to D1F0x18 */ + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x00010100; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize GMM Base Address for Legacy Bridge Mode + * Modify B1D5F0x18 + */ + PciAddress.Address.Bus = 1; + PciAddress.Address.Device = 5; + PciAddress.Address.Function = 0; + PciAddress.Address.Register = 0x18; + + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x96000000; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize FB Base Address for Legacy Bridge Mode + * Modify B1D5F0x10 + */ + PciAddress.Address.Register = 0x10; + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x80000000; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize GMM Base Address for Pcie Mode + * Modify B0D1F0x18 + */ + PciAddress.Address.Bus = 0; + PciAddress.Address.Device = 1; + PciAddress.Address.Function = 0; + PciAddress.Address.Register = 0x18; + + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x96000000; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize FB Base Address for Pcie Mode + * Modify B0D1F0x10 + */ + PciAddress.Address.Register = 0x10; + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x80000000; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize MMIO Base and Limit Address + * Modify B0D1F0x20 + */ + PciAddress.Address.Bus = 0; + PciAddress.Address.Device = 1; + PciAddress.Address.Function = 0; + PciAddress.Address.Register = 0x20; + + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x96009600; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize MMIO Prefetchable Memory Limit and Base + * Modify B0D1F0x24 + */ + PciAddress.Address.Register = 0x24; + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x8FF18001; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; } VOID * agesawrapper_getlateinitptr ( - int pick - ) + int pick + ) { - switch (pick) { - case PICK_DMI: - return DmiTable; - case PICK_PSTATE: - return AcpiPstate; - case PICK_SRAT: - return AcpiSrat; - case PICK_SLIT: - return AcpiSlit; - case PICK_WHEA_MCE: - return AcpiWheaMce; - case PICK_WHEA_CMC: - return AcpiWheaCmc; - case PICK_ALIB: - return AcpiAlib; - default: - return NULL; - } + switch (pick) { + case PICK_DMI: + return DmiTable; + case PICK_PSTATE: + return AcpiPstate; + case PICK_SRAT: + return AcpiSrat; + case PICK_SLIT: + return AcpiSlit; + case PICK_WHEA_MCE: + return AcpiWheaMce; + case PICK_WHEA_CMC: + return AcpiWheaCmc; + case PICK_ALIB: + return AcpiAlib; + default: + return NULL; + } } UINT32 agesawrapper_amdinitmid ( - VOID - ) + VOID + ) { - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; - /* Enable MMIO on AMD CPU Address Map Controller */ - agesawrapper_amdinitcpuio (); + /* Enable MMIO on AMD CPU Address Map Controller */ + agesawrapper_amdinitcpuio (); - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); - AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); + AmdCreateStruct (&AmdParamStruct); - status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); - AmdReleaseStruct (&AmdParamStruct); + status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); - return (UINT32)status; + return (UINT32)status; } UINT32 agesawrapper_amdinitlate ( - VOID - ) + VOID + ) { - AGESA_STATUS Status; - AMD_LATE_PARAMS AmdLateParams; - - LibAmdMemFill (&AmdLateParams, - 0, - sizeof (AMD_LATE_PARAMS), - &(AmdLateParams.StdHeader)); - - AmdLateParams.StdHeader.AltImageBasePtr = 0; - AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdLateParams.StdHeader.Func = 0; - AmdLateParams.StdHeader.ImageBasePtr = 0; - - Status = AmdInitLate (&AmdLateParams); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); - } - - DmiTable = AmdLateParams.DmiTable; - AcpiPstate = AmdLateParams.AcpiPState; - AcpiSrat = AmdLateParams.AcpiSrat; - AcpiSlit = AmdLateParams.AcpiSlit; - - AcpiWheaMce = AmdLateParams.AcpiWheaMce; - AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; - AcpiAlib = AmdLateParams.AcpiAlib; - - return (UINT32)Status; + AGESA_STATUS Status; + AMD_LATE_PARAMS AmdLateParams; + + LibAmdMemFill (&AmdLateParams, + 0, + sizeof (AMD_LATE_PARAMS), + &(AmdLateParams.StdHeader)); + + AmdLateParams.StdHeader.AltImageBasePtr = 0; + AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdLateParams.StdHeader.Func = 0; + AmdLateParams.StdHeader.ImageBasePtr = 0; + + Status = AmdInitLate (&AmdLateParams); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(); + ASSERT(Status == AGESA_SUCCESS); + } + + DmiTable = AmdLateParams.DmiTable; + AcpiPstate = AmdLateParams.AcpiPState; + AcpiSrat = AmdLateParams.AcpiSrat; + AcpiSlit = AmdLateParams.AcpiSlit; + + AcpiWheaMce = AmdLateParams.AcpiWheaMce; + AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; + AcpiAlib = AmdLateParams.AcpiAlib; + + return (UINT32)Status; } -UINT32 +UINT32 agesawrapper_amdlaterunaptask ( - UINT32 Func, - UINT32 Data, - VOID *ConfigPtr - ) + UINT32 Func, + UINT32 Data, + VOID *ConfigPtr + ) { - AGESA_STATUS Status; - AP_EXE_PARAMS ApExeParams; - - LibAmdMemFill (&ApExeParams, - 0, - sizeof (AP_EXE_PARAMS), - &(ApExeParams.StdHeader)); - - ApExeParams.StdHeader.AltImageBasePtr = 0; - ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - ApExeParams.StdHeader.Func = 0; - ApExeParams.StdHeader.ImageBasePtr = 0; - ApExeParams.StdHeader.ImageBasePtr = 0; - ApExeParams.FunctionNumber = Func; - ApExeParams.RelatedDataBlock = ConfigPtr; - - Status = AmdLateRunApTask (&ApExeParams); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); - } - - return (UINT32)Status; + AGESA_STATUS Status; + AP_EXE_PARAMS ApExeParams; + + LibAmdMemFill (&ApExeParams, + 0, + sizeof (AP_EXE_PARAMS), + &(ApExeParams.StdHeader)); + + ApExeParams.StdHeader.AltImageBasePtr = 0; + ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + ApExeParams.StdHeader.Func = 0; + ApExeParams.StdHeader.ImageBasePtr = 0; + ApExeParams.StdHeader.ImageBasePtr = 0; + ApExeParams.FunctionNumber = Func; + ApExeParams.RelatedDataBlock = ConfigPtr; + + Status = AmdLateRunApTask (&ApExeParams); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(); + ASSERT(Status == AGESA_SUCCESS); + } + + return (UINT32)Status; } UINT32 agesawrapper_amdreadeventlog ( - VOID - ) + VOID + ) { - AGESA_STATUS Status; - EVENT_PARAMS AmdEventParams; - - LibAmdMemFill (&AmdEventParams, - 0, - sizeof (EVENT_PARAMS), - &(AmdEventParams.StdHeader)); - - AmdEventParams.StdHeader.AltImageBasePtr = 0; - AmdEventParams.StdHeader.CalloutPtr = NULL; - AmdEventParams.StdHeader.Func = 0; - AmdEventParams.StdHeader.ImageBasePtr = 0; - Status = AmdReadEventLog (&AmdEventParams); - while (AmdEventParams.EventClass != 0) { - printk(BIOS_DEBUG,"\nEventLog: EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo); - printk(BIOS_DEBUG," Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2); - printk(BIOS_DEBUG," Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4); - Status = AmdReadEventLog (&AmdEventParams); - } - - return (UINT32)Status; + AGESA_STATUS Status; + EVENT_PARAMS AmdEventParams; + + LibAmdMemFill (&AmdEventParams, + 0, + sizeof (EVENT_PARAMS), + &(AmdEventParams.StdHeader)); + + AmdEventParams.StdHeader.AltImageBasePtr = 0; + AmdEventParams.StdHeader.CalloutPtr = NULL; + AmdEventParams.StdHeader.Func = 0; + AmdEventParams.StdHeader.ImageBasePtr = 0; + Status = AmdReadEventLog (&AmdEventParams); + while (AmdEventParams.EventClass != 0) { + printk(BIOS_DEBUG,"\nEventLog: EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo); + printk(BIOS_DEBUG," Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2); + printk(BIOS_DEBUG," Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4); + Status = AmdReadEventLog (&AmdEventParams); + } + + return (UINT32)Status; } diff --git a/src/mainboard/amd/union_station/acpi_tables.c b/src/mainboard/amd/union_station/acpi_tables.c index 2a299d8..ae058d6 100644 --- a/src/mainboard/amd/union_station/acpi_tables.c +++ b/src/mainboard/amd/union_station/acpi_tables.c @@ -35,15 +35,15 @@ static void dump_mem(u32 start, u32 end) { - u32 i; - print_debug("dump_mem:"); - for (i = start; i < end; i++) { - if ((i & 0xf) == 0) { - printk(BIOS_DEBUG, "\n%08x:", i); - } - printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i)); - } - print_debug("\n"); + u32 i; + print_debug("dump_mem:"); + for (i = start; i < end; i++) { + if ((i & 0xf) == 0) { + printk(BIOS_DEBUG, "\n%08x:", i); + } + printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i)); + } + print_debug("\n"); } #endif @@ -52,197 +52,197 @@ extern const unsigned char AmlCode_ssdt[]; unsigned long acpi_fill_mcfg(unsigned long current) { - /* Just a dummy */ - return current; + /* Just a dummy */ + return current; } unsigned long acpi_fill_madt(unsigned long current) { - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, - IO_APIC_ADDR, 0); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edige-triggered, Active high */ - - /* create all subtables for processors */ - /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ - /* 1: LINT1 connect to NMI */ - - return current; + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write SB800 IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, + IO_APIC_ADDR, 0); + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, 0xF); + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edige-triggered, Active high */ + + /* create all subtables for processors */ + /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ + /* 1: LINT1 connect to NMI */ + + return current; } unsigned long acpi_fill_slit(unsigned long current) { - // Not implemented - return current; + // Not implemented + return current; } unsigned long acpi_fill_srat(unsigned long current) { - /* No NUMA, no SRAT */ - return current; + /* No NUMA, no SRAT */ + return current; } unsigned long write_acpi_tables(unsigned long start) { - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_srat_t *srat; - acpi_slit_t *slit; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; - - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - - /* Align ACPI tables to 16 bytes */ - start = (start + 0x0f) & -0x10; - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* DSDT */ - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); - dsdt = (acpi_header_t *)current; // it will used by fadt - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); - - /* FACS */ // it needs 64 bit alignment - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); - facs = (acpi_facs_t *) current; // it will be used by fadt - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* FDAT */ - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - /* - * We explicitly add these tables later on: - */ - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - /* If we want to use HPET Timers Linux wants an MADT */ - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - /* SRAT */ - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); - srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); - if (srat != NULL) { - memcpy((void *)current, srat, srat->header.length); - srat = (acpi_srat_t *) current; - //acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - } - - /* SLIT */ - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); - slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); - if (slit != NULL) { - memcpy((void *)current, slit, slit->header.length); - slit = (acpi_slit_t *) current; - //acpi_create_slit(slit); - current += slit->header.length; - acpi_add_table(rsdp, slit); - } - - /* SSDT */ - current = ( current + 0x0f) & -0x10; - printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); - ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); - if (ssdt != NULL) { - memcpy((void *)current, ssdt, ssdt->length); - ssdt = (acpi_header_t *) current; - current += ssdt->length; - } - else { - ssdt = (acpi_header_t *) current; - memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); - current += ssdt->length; - memcpy(ssdt, &AmlCode_ssdt, ssdt->length); - char *position = ssdt; - if (memcmp(position + 50, "TOM1", 4) == 0) - *(u32 *)(position + 55) = __readmsr(0xc001001a); - - /* recalculate checksum */ - ssdt->checksum = 0; - ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); - } - acpi_add_table(rsdp,ssdt); - - printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_srat_t *srat; + acpi_slit_t *slit; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *dsdt; + acpi_header_t *ssdt; + + get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ + + /* Align ACPI tables to 16 bytes */ + start = (start + 0x0f) & -0x10; + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* clear all table memory */ + memset((void *)start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* DSDT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); + dsdt = (acpi_header_t *)current; // it will used by fadt + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); + + /* FACS */ // it needs 64 bit alignment + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); + facs = (acpi_facs_t *) current; // it will be used by fadt + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + /* FDAT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* + * We explicitly add these tables later on: + */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + acpi_create_hpet(hpet); + acpi_add_table(rsdp, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdp, madt); + + /* SRAT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); + srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); + if (srat != NULL) { + memcpy((void *)current, srat, srat->header.length); + srat = (acpi_srat_t *) current; + //acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + } + + /* SLIT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); + slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); + if (slit != NULL) { + memcpy((void *)current, slit, slit->header.length); + slit = (acpi_slit_t *) current; + //acpi_create_slit(slit); + current += slit->header.length; + acpi_add_table(rsdp, slit); + } + + /* SSDT */ + current = ( current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); + ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); + if (ssdt != NULL) { + memcpy((void *)current, ssdt, ssdt->length); + ssdt = (acpi_header_t *) current; + current += ssdt->length; + } + else { + ssdt = (acpi_header_t *) current; + memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); + current += ssdt->length; + memcpy(ssdt, &AmlCode_ssdt, ssdt->length); + char *position = ssdt; + if (memcmp(position + 50, "TOM1", 4) == 0) + *(u32 *)(position + 55) = __readmsr(0xc001001a); + + /* recalculate checksum */ + ssdt->checksum = 0; + ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); + } + acpi_add_table(rsdp,ssdt); + + printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); #if DUMP_ACPI_TABLES == 1 - printk(BIOS_DEBUG, "rsdp\n"); - dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t)); + printk(BIOS_DEBUG, "rsdp\n"); + dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t)); - printk(BIOS_DEBUG, "rsdt\n"); - dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t)); + printk(BIOS_DEBUG, "rsdt\n"); + dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t)); - printk(BIOS_DEBUG, "madt\n"); - dump_mem(madt, ((void *)madt) + madt->header.length); + printk(BIOS_DEBUG, "madt\n"); + dump_mem(madt, ((void *)madt) + madt->header.length); - printk(BIOS_DEBUG, "srat\n"); - dump_mem(srat, ((void *)srat) + srat->header.length); + printk(BIOS_DEBUG, "srat\n"); + dump_mem(srat, ((void *)srat) + srat->header.length); - printk(BIOS_DEBUG, "slit\n"); - dump_mem(slit, ((void *)slit) + slit->header.length); + printk(BIOS_DEBUG, "slit\n"); + dump_mem(slit, ((void *)slit) + slit->header.length); - printk(BIOS_DEBUG, "ssdt\n"); - dump_mem(ssdt, ((void *)ssdt) + ssdt->length); + printk(BIOS_DEBUG, "ssdt\n"); + dump_mem(ssdt, ((void *)ssdt) + ssdt->length); - printk(BIOS_DEBUG, "fadt\n"); - dump_mem(fadt, ((void *)fadt) + fadt->header.length); + printk(BIOS_DEBUG, "fadt\n"); + dump_mem(fadt, ((void *)fadt) + fadt->header.length); #endif - printk(BIOS_INFO, "ACPI: done.\n"); - return current; + printk(BIOS_INFO, "ACPI: done.\n"); + return current; } diff --git a/src/mainboard/amd/union_station/agesawrapper.c b/src/mainboard/amd/union_station/agesawrapper.c index 74aa73d..55e8488 100644 --- a/src/mainboard/amd/union_station/agesawrapper.c +++ b/src/mainboard/amd/union_station/agesawrapper.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- +/*----------------------------------------------------------------------------- + * M O D U L E S U S E D + *----------------------------------------------------------------------------- */ #include <stdint.h> @@ -40,502 +40,502 @@ #define FILECODE UNASSIGNED_FILE_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- +/*------------------------------------------------------------------------------ + * D E F I N I T I O N S A N D M A C R O S + *------------------------------------------------------------------------------ */ #define MMCONF_ENABLE 1 /* ACPI table pointers returned by AmdInitLate */ -VOID *DmiTable = NULL; -VOID *AcpiPstate = NULL; -VOID *AcpiSrat = NULL; -VOID *AcpiSlit = NULL; - -VOID *AcpiWheaMce = NULL; -VOID *AcpiWheaCmc = NULL; -VOID *AcpiAlib = NULL; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- +VOID *DmiTable = NULL; +VOID *AcpiPstate = NULL; +VOID *AcpiSrat = NULL; +VOID *AcpiSlit = NULL; + +VOID *AcpiWheaMce = NULL; +VOID *AcpiWheaCmc = NULL; +VOID *AcpiAlib = NULL; + +/*------------------------------------------------------------------------------ + * T Y P E D E F S A N D S T R U C T U R E S + *------------------------------------------------------------------------------ */ -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- +/*------------------------------------------------------------------------------ + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *------------------------------------------------------------------------------ */ -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- +/*------------------------------------------------------------------------------ + * E X P O R T E D F U N C T I O N S + *------------------------------------------------------------------------------ */ -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- +/*------------------------------------------------------------------------------ + * L O C A L F U N C T I O N S + *------------------------------------------------------------------------------ */ UINT32 agesawrapper_amdinitcpuio ( - VOID - ) + VOID + ) { - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; - - /* Enable legacy video routing: D18F1xF4 VGA Enable */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); - PciData = 1; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* The platform BIOS needs to ensure the memory ranges of SB800 legacy - * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are - * set to non-posted regions. - */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); - PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000 - PciData |= 1 << 7; // set NP (non-posted) bit - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); - PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000 - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Map the remaining PCI hole as posted MMIO */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); - PciData = 0x00FECF00; // last address before non-posted range - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); - MsrReg = (MsrReg >> 8) | 3; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); - PciData = (UINT32)MsrReg; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Send all IO (0000-FFFF) to southbridge. */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); - PciData = 0x0000F000; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); - PciData = 0x00000003; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - Status = AGESA_SUCCESS; - return (UINT32)Status; + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* Enable legacy video routing: D18F1xF4 VGA Enable */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); + PciData = 1; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* The platform BIOS needs to ensure the memory ranges of SB800 legacy + * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are + * set to non-posted regions. + */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); + PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000 + PciData |= 1 << 7; // set NP (non-posted) bit + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); + PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000 + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Map the remaining PCI hole as posted MMIO */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); + PciData = 0x00FECF00; // last address before non-posted range + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); + MsrReg = (MsrReg >> 8) | 3; + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); + PciData = (UINT32)MsrReg; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Send all IO (0000-FFFF) to southbridge. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); + PciData = 0x0000F000; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); + PciData = 0x00000003; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + Status = AGESA_SUCCESS; + return (UINT32)Status; } UINT32 agesawrapper_amdinitmmio ( - VOID - ) + VOID + ) { - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; - - UINT8 BusRangeVal = 0; - UINT8 BusNum; - UINT8 Index; - - /* - Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base - Address MSR register. - */ - - for (Index = 0; Index < 8; Index++) { - BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index; - if (BusNum == 1) { - BusRangeVal = Index; - break; - } - } - - MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (UINT64)(BusRangeVal << 2) | MMCONF_ENABLE); - LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); - - /* - Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. - */ - LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); - MsrReg = MsrReg | 0x0000400000000000ull; - LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - - /* Set Ontario Link Data */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0); - PciData = 0x01308002; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4); - PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - Status = AGESA_SUCCESS; - return (UINT32)Status; + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + UINT8 BusRangeVal = 0; + UINT8 BusNum; + UINT8 Index; + + /* + Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base + Address MSR register. + */ + + for (Index = 0; Index < 8; Index++) { + BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index; + if (BusNum == 1) { + BusRangeVal = Index; + break; + } + } + + MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (UINT64)(BusRangeVal << 2) | MMCONF_ENABLE); + LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); + + /* + Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. + */ + LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); + MsrReg = MsrReg | 0x0000400000000000ull; + LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); + + /* Set Ontario Link Data */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0); + PciData = 0x01308002; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4); + PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + Status = AGESA_SUCCESS; + return (UINT32)Status; } UINT32 agesawrapper_amdinitreset ( - VOID - ) + VOID + ) { - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESET_PARAMS AmdResetParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - LibAmdMemFill (&AmdResetParams, - 0, - sizeof (AMD_RESET_PARAMS), - &(AmdResetParams.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; - AmdParamStruct.AllocationMethod = ByHost; - AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); - AmdParamStruct.NewStructPtr = &AmdResetParams; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = NULL; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - AmdResetParams.HtConfig.Depth = 0; - - status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); - AmdReleaseStruct (&AmdParamStruct); - return (UINT32)status; + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESET_PARAMS AmdResetParams; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + LibAmdMemFill (&AmdResetParams, + 0, + sizeof (AMD_RESET_PARAMS), + &(AmdResetParams.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; + AmdParamStruct.AllocationMethod = ByHost; + AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); + AmdParamStruct.NewStructPtr = &AmdResetParams; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = NULL; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + AmdResetParams.HtConfig.Depth = 0; + + status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + return (UINT32)status; } UINT32 agesawrapper_amdinitearly ( - VOID - ) + VOID + ) { - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_EARLY_PARAMS *AmdEarlyParamsPtr; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - - AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; - OemCustomizeInitEarly (AmdEarlyParamsPtr); - - status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); - AmdReleaseStruct (&AmdParamStruct); - - return (UINT32)status; + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_EARLY_PARAMS *AmdEarlyParamsPtr; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + + AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; + OemCustomizeInitEarly (AmdEarlyParamsPtr); + + status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; } UINT32 agesawrapper_amdinitpost ( - VOID - ) + VOID + ) { - AGESA_STATUS status; - UINT16 i; - UINT32 *HeadPtr; - AMD_INTERFACE_PARAMS AmdParamStruct; - BIOS_HEAP_MANAGER *BiosManagerPtr; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct (&AmdParamStruct); - status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); - AmdReleaseStruct (&AmdParamStruct); - - /* Initialize heap space */ - BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS; - - HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); - for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) - { - *HeadPtr = 0x00000000; - HeadPtr++; - } - BiosManagerPtr->StartOfAllocatedNodes = 0; - BiosManagerPtr->StartOfFreedNodes = 0; - - return (UINT32)status; + AGESA_STATUS status; + UINT16 i; + UINT32 *HeadPtr; + AMD_INTERFACE_PARAMS AmdParamStruct; + BIOS_HEAP_MANAGER *BiosManagerPtr; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct (&AmdParamStruct); + status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + /* Initialize heap space */ + BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS; + + HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); + for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) + { + *HeadPtr = 0x00000000; + HeadPtr++; + } + BiosManagerPtr->StartOfAllocatedNodes = 0; + BiosManagerPtr->StartOfFreedNodes = 0; + + return (UINT32)status; } UINT32 agesawrapper_amdinitenv ( - VOID - ) + VOID + ) { - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - PCI_ADDR PciAddress; - UINT32 PciValue; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); - /* Initialize Subordinate Bus Number and Secondary Bus Number - * In platform BIOS this address is allocated by PCI enumeration code - Modify D1F0x18 - */ - PciAddress.Address.Bus = 0; - PciAddress.Address.Device = 1; - PciAddress.Address.Function = 0; - PciAddress.Address.Register = 0x18; - /* Write to D1F0x18 */ - LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - PciValue |= 0x00010100; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - - /* Initialize GMM Base Address for Legacy Bridge Mode - * Modify B1D5F0x18 - */ - PciAddress.Address.Bus = 1; - PciAddress.Address.Device = 5; - PciAddress.Address.Function = 0; - PciAddress.Address.Register = 0x18; - - LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - PciValue |= 0x96000000; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - - /* Initialize FB Base Address for Legacy Bridge Mode - * Modify B1D5F0x10 - */ - PciAddress.Address.Register = 0x10; - LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - PciValue |= 0x80000000; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - - /* Initialize GMM Base Address for Pcie Mode - * Modify B0D1F0x18 - */ - PciAddress.Address.Bus = 0; - PciAddress.Address.Device = 1; - PciAddress.Address.Function = 0; - PciAddress.Address.Register = 0x18; - - LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - PciValue |= 0x96000000; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - - /* Initialize FB Base Address for Pcie Mode - * Modify B0D1F0x10 - */ - PciAddress.Address.Register = 0x10; - LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - PciValue |= 0x80000000; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - - /* Initialize MMIO Base and Limit Address - * Modify B0D1F0x20 - */ - PciAddress.Address.Bus = 0; - PciAddress.Address.Device = 1; - PciAddress.Address.Function = 0; - PciAddress.Address.Register = 0x20; - - LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - PciValue |= 0x96009600; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - - /* Initialize MMIO Prefetchable Memory Limit and Base - * Modify B0D1F0x24 - */ - PciAddress.Address.Register = 0x24; - LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - PciValue |= 0x8FF18001; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - AmdReleaseStruct (&AmdParamStruct); - - return (UINT32)status; + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + PCI_ADDR PciAddress; + UINT32 PciValue; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + /* Initialize Subordinate Bus Number and Secondary Bus Number + * In platform BIOS this address is allocated by PCI enumeration code + Modify D1F0x18 + */ + PciAddress.Address.Bus = 0; + PciAddress.Address.Device = 1; + PciAddress.Address.Function = 0; + PciAddress.Address.Register = 0x18; + /* Write to D1F0x18 */ + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x00010100; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize GMM Base Address for Legacy Bridge Mode + * Modify B1D5F0x18 + */ + PciAddress.Address.Bus = 1; + PciAddress.Address.Device = 5; + PciAddress.Address.Function = 0; + PciAddress.Address.Register = 0x18; + + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x96000000; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize FB Base Address for Legacy Bridge Mode + * Modify B1D5F0x10 + */ + PciAddress.Address.Register = 0x10; + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x80000000; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize GMM Base Address for Pcie Mode + * Modify B0D1F0x18 + */ + PciAddress.Address.Bus = 0; + PciAddress.Address.Device = 1; + PciAddress.Address.Function = 0; + PciAddress.Address.Register = 0x18; + + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x96000000; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize FB Base Address for Pcie Mode + * Modify B0D1F0x10 + */ + PciAddress.Address.Register = 0x10; + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x80000000; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize MMIO Base and Limit Address + * Modify B0D1F0x20 + */ + PciAddress.Address.Bus = 0; + PciAddress.Address.Device = 1; + PciAddress.Address.Function = 0; + PciAddress.Address.Register = 0x20; + + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x96009600; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize MMIO Prefetchable Memory Limit and Base + * Modify B0D1F0x24 + */ + PciAddress.Address.Register = 0x24; + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x8FF18001; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; } VOID * agesawrapper_getlateinitptr ( - int pick - ) + int pick + ) { - switch (pick) { - case PICK_DMI: - return DmiTable; - case PICK_PSTATE: - return AcpiPstate; - case PICK_SRAT: - return AcpiSrat; - case PICK_SLIT: - return AcpiSlit; - case PICK_WHEA_MCE: - return AcpiWheaMce; - case PICK_WHEA_CMC: - return AcpiWheaCmc; - case PICK_ALIB: - return AcpiAlib; - default: - return NULL; - } + switch (pick) { + case PICK_DMI: + return DmiTable; + case PICK_PSTATE: + return AcpiPstate; + case PICK_SRAT: + return AcpiSrat; + case PICK_SLIT: + return AcpiSlit; + case PICK_WHEA_MCE: + return AcpiWheaMce; + case PICK_WHEA_CMC: + return AcpiWheaCmc; + case PICK_ALIB: + return AcpiAlib; + default: + return NULL; + } } UINT32 agesawrapper_amdinitmid ( - VOID - ) + VOID + ) { - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; - /* Enable MMIO on AMD CPU Address Map Controller */ - agesawrapper_amdinitcpuio (); + /* Enable MMIO on AMD CPU Address Map Controller */ + agesawrapper_amdinitcpuio (); - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); - AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); + AmdCreateStruct (&AmdParamStruct); - status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); - AmdReleaseStruct (&AmdParamStruct); + status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); - return (UINT32)status; + return (UINT32)status; } UINT32 agesawrapper_amdinitlate ( - VOID - ) + VOID + ) { - AGESA_STATUS Status; - AMD_LATE_PARAMS AmdLateParams; - - LibAmdMemFill (&AmdLateParams, - 0, - sizeof (AMD_LATE_PARAMS), - &(AmdLateParams.StdHeader)); - - AmdLateParams.StdHeader.AltImageBasePtr = 0; - AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdLateParams.StdHeader.Func = 0; - AmdLateParams.StdHeader.ImageBasePtr = 0; - - Status = AmdInitLate (&AmdLateParams); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); - } - - DmiTable = AmdLateParams.DmiTable; - AcpiPstate = AmdLateParams.AcpiPState; - AcpiSrat = AmdLateParams.AcpiSrat; - AcpiSlit = AmdLateParams.AcpiSlit; - - AcpiWheaMce = AmdLateParams.AcpiWheaMce; - AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; - AcpiAlib = AmdLateParams.AcpiAlib; - - return (UINT32)Status; + AGESA_STATUS Status; + AMD_LATE_PARAMS AmdLateParams; + + LibAmdMemFill (&AmdLateParams, + 0, + sizeof (AMD_LATE_PARAMS), + &(AmdLateParams.StdHeader)); + + AmdLateParams.StdHeader.AltImageBasePtr = 0; + AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdLateParams.StdHeader.Func = 0; + AmdLateParams.StdHeader.ImageBasePtr = 0; + + Status = AmdInitLate (&AmdLateParams); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(); + ASSERT(Status == AGESA_SUCCESS); + } + + DmiTable = AmdLateParams.DmiTable; + AcpiPstate = AmdLateParams.AcpiPState; + AcpiSrat = AmdLateParams.AcpiSrat; + AcpiSlit = AmdLateParams.AcpiSlit; + + AcpiWheaMce = AmdLateParams.AcpiWheaMce; + AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; + AcpiAlib = AmdLateParams.AcpiAlib; + + return (UINT32)Status; } -UINT32 +UINT32 agesawrapper_amdlaterunaptask ( - UINT32 Func, - UINT32 Data, - VOID *ConfigPtr - ) + UINT32 Func, + UINT32 Data, + VOID *ConfigPtr + ) { - AGESA_STATUS Status; - AP_EXE_PARAMS ApExeParams; - - LibAmdMemFill (&ApExeParams, - 0, - sizeof (AP_EXE_PARAMS), - &(ApExeParams.StdHeader)); - - ApExeParams.StdHeader.AltImageBasePtr = 0; - ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - ApExeParams.StdHeader.Func = 0; - ApExeParams.StdHeader.ImageBasePtr = 0; - ApExeParams.StdHeader.ImageBasePtr = 0; - ApExeParams.FunctionNumber = Func; - ApExeParams.RelatedDataBlock = ConfigPtr; - - Status = AmdLateRunApTask (&ApExeParams); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); - } - - return (UINT32)Status; + AGESA_STATUS Status; + AP_EXE_PARAMS ApExeParams; + + LibAmdMemFill (&ApExeParams, + 0, + sizeof (AP_EXE_PARAMS), + &(ApExeParams.StdHeader)); + + ApExeParams.StdHeader.AltImageBasePtr = 0; + ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + ApExeParams.StdHeader.Func = 0; + ApExeParams.StdHeader.ImageBasePtr = 0; + ApExeParams.StdHeader.ImageBasePtr = 0; + ApExeParams.FunctionNumber = Func; + ApExeParams.RelatedDataBlock = ConfigPtr; + + Status = AmdLateRunApTask (&ApExeParams); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(); + ASSERT(Status == AGESA_SUCCESS); + } + + return (UINT32)Status; } UINT32 agesawrapper_amdreadeventlog ( - VOID - ) + VOID + ) { - AGESA_STATUS Status; - EVENT_PARAMS AmdEventParams; - - LibAmdMemFill (&AmdEventParams, - 0, - sizeof (EVENT_PARAMS), - &(AmdEventParams.StdHeader)); - - AmdEventParams.StdHeader.AltImageBasePtr = 0; - AmdEventParams.StdHeader.CalloutPtr = NULL; - AmdEventParams.StdHeader.Func = 0; - AmdEventParams.StdHeader.ImageBasePtr = 0; - Status = AmdReadEventLog (&AmdEventParams); - while (AmdEventParams.EventClass != 0) { - printk(BIOS_DEBUG,"\nEventLog: EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo); - printk(BIOS_DEBUG," Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2); - printk(BIOS_DEBUG," Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4); - Status = AmdReadEventLog (&AmdEventParams); - } - - return (UINT32)Status; + AGESA_STATUS Status; + EVENT_PARAMS AmdEventParams; + + LibAmdMemFill (&AmdEventParams, + 0, + sizeof (EVENT_PARAMS), + &(AmdEventParams.StdHeader)); + + AmdEventParams.StdHeader.AltImageBasePtr = 0; + AmdEventParams.StdHeader.CalloutPtr = NULL; + AmdEventParams.StdHeader.Func = 0; + AmdEventParams.StdHeader.ImageBasePtr = 0; + Status = AmdReadEventLog (&AmdEventParams); + while (AmdEventParams.EventClass != 0) { + printk(BIOS_DEBUG,"\nEventLog: EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo); + printk(BIOS_DEBUG," Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2); + printk(BIOS_DEBUG," Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4); + Status = AmdReadEventLog (&AmdEventParams); + } + + return (UINT32)Status; } diff --git a/src/mainboard/asrock/e350m1/acpi_tables.c b/src/mainboard/asrock/e350m1/acpi_tables.c index cd0a996..593ec46 100644 --- a/src/mainboard/asrock/e350m1/acpi_tables.c +++ b/src/mainboard/asrock/e350m1/acpi_tables.c @@ -37,15 +37,15 @@ static void dump_mem(u32 start, u32 end) { - u32 i; - print_debug("dump_mem:"); - for (i = start; i < end; i++) { - if ((i & 0xf) == 0) { - printk(BIOS_DEBUG, "\n%08x:", i); - } - printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i)); - } - print_debug("\n"); + u32 i; + print_debug("dump_mem:"); + for (i = start; i < end; i++) { + if ((i & 0xf) == 0) { + printk(BIOS_DEBUG, "\n%08x:", i); + } + printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i)); + } + print_debug("\n"); } #endif @@ -54,198 +54,199 @@ extern const unsigned char AmlCode_ssdt[]; unsigned long acpi_fill_mcfg(unsigned long current) { - /* Just a dummy */ - return current; + /* Just a dummy */ + return current; } unsigned long acpi_fill_madt(unsigned long current) { - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, - IO_APIC_ADDR, 0); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edige-triggered, Active high */ - - /* create all subtables for processors */ - /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ - /* 1: LINT1 connect to NMI */ - - return current; + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write SB800 IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, 0xF); + + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edige-triggered, Active high */ + + /* create all subtables for processors */ + /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ + /* 1: LINT1 connect to NMI */ + + return current; } unsigned long acpi_fill_slit(unsigned long current) { - // Not implemented - return current; + // Not implemented + return current; } unsigned long acpi_fill_srat(unsigned long current) { - /* No NUMA, no SRAT */ - return current; + /* No NUMA, no SRAT */ + return current; } unsigned long write_acpi_tables(unsigned long start) { - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_srat_t *srat; - acpi_slit_t *slit; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - acpi_header_t *ssdt; - - get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ - - /* Align ACPI tables to 16 bytes */ - start = (start + 0x0f) & -0x10; - current = start; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, NULL); - acpi_write_rsdt(rsdt); - - /* - * We explicitly add these tables later on: - */ - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - /* If we want to use HPET Timers Linux wants an MADT */ - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - - /* SRAT */ - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); - srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); - if (srat != NULL) { - memcpy(current, srat, srat->header.length); - srat = (acpi_srat_t *) current; - //acpi_create_srat(srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); - } - - /* SLIT */ - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); - slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); - if (slit != NULL) { - memcpy(current, slit, slit->header.length); - slit = (acpi_slit_t *) current; - //acpi_create_slit(slit); - current += slit->header.length; - acpi_add_table(rsdp, slit); - } - - /* SSDT */ - current = ( current + 0x0f) & -0x10; - printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); - ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); - if (ssdt != NULL) { - memcpy(current, ssdt, ssdt->length); - ssdt = (acpi_header_t *) current; - current += ssdt->length; - } - else { - ssdt = (acpi_header_t *) current; - memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); - current += ssdt->length; - memcpy(ssdt, &AmlCode_ssdt, ssdt->length); - - char *position = ssdt; - if (memcmp (position + 50, "TOM1", 4) == 0) - *(u32 *) (position + 55) = __readmsr (0xc001001a); - - /* recalculate checksum */ - ssdt->checksum = 0; - ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); - } - acpi_add_table(rsdp,ssdt); - - printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); - - /* DSDT */ - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); - dsdt = (acpi_header_t *)current; // it will used by fadt - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); - - /* FACS */ // it needs 64 bit alignment - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); - facs = (acpi_facs_t *) current; // it will be used by fadt - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* FDAT */ - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_srat_t *srat; + acpi_slit_t *slit; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *dsdt; + acpi_header_t *ssdt; + + get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ + + /* Align ACPI tables to 16 bytes */ + start = (start + 0x0f) & -0x10; + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* clear all table memory */ + memset((void *)start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* + * We explicitly add these tables later on: + */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + acpi_create_hpet(hpet); + acpi_add_table(rsdp, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdp, madt); + + /* SRAT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); + srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); + if (srat != NULL) { + memcpy(current, srat, srat->header.length); + srat = (acpi_srat_t *) current; + //acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + } + + /* SLIT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); + slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); + if (slit != NULL) { + memcpy(current, slit, slit->header.length); + slit = (acpi_slit_t *) current; + //acpi_create_slit(slit); + current += slit->header.length; + acpi_add_table(rsdp, slit); + } + + /* SSDT */ + current = ( current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); + ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); + if (ssdt != NULL) { + memcpy(current, ssdt, ssdt->length); + ssdt = (acpi_header_t *) current; + current += ssdt->length; + } + else { + ssdt = (acpi_header_t *) current; + memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); + current += ssdt->length; + memcpy(ssdt, &AmlCode_ssdt, ssdt->length); + + char *position = ssdt; + if (memcmp (position + 50, "TOM1", 4) == 0) + *(u32 *) (position + 55) = __readmsr (0xc001001a); + + /* recalculate checksum */ + ssdt->checksum = 0; + ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); + } + acpi_add_table(rsdp,ssdt); + + printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); + + /* DSDT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); + dsdt = (acpi_header_t *)current; // it will used by fadt + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); + + /* FACS */ // it needs 64 bit alignment + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); + facs = (acpi_facs_t *) current; // it will be used by fadt + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + /* FDAT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); #if DUMP_ACPI_TABLES == 1 - printk(BIOS_DEBUG, "rsdp\n"); - dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t)); + printk(BIOS_DEBUG, "rsdp\n"); + dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t)); - printk(BIOS_DEBUG, "rsdt\n"); - dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t)); + printk(BIOS_DEBUG, "rsdt\n"); + dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t)); - printk(BIOS_DEBUG, "madt\n"); - dump_mem(madt, ((void *)madt) + madt->header.length); + printk(BIOS_DEBUG, "madt\n"); + dump_mem(madt, ((void *)madt) + madt->header.length); - printk(BIOS_DEBUG, "srat\n"); - dump_mem(srat, ((void *)srat) + srat->header.length); + printk(BIOS_DEBUG, "srat\n"); + dump_mem(srat, ((void *)srat) + srat->header.length); - printk(BIOS_DEBUG, "slit\n"); - dump_mem(slit, ((void *)slit) + slit->header.length); + printk(BIOS_DEBUG, "slit\n"); + dump_mem(slit, ((void *)slit) + slit->header.length); - printk(BIOS_DEBUG, "ssdt\n"); - dump_mem(ssdt, ((void *)ssdt) + ssdt->length); + printk(BIOS_DEBUG, "ssdt\n"); + dump_mem(ssdt, ((void *)ssdt) + ssdt->length); - printk(BIOS_DEBUG, "fadt\n"); - dump_mem(fadt, ((void *)fadt) + fadt->header.length); + printk(BIOS_DEBUG, "fadt\n"); + dump_mem(fadt, ((void *)fadt) + fadt->header.length); #endif - printk(BIOS_INFO, "ACPI: done.\n"); - return current; + printk(BIOS_INFO, "ACPI: done.\n"); + return current; } diff --git a/src/mainboard/asrock/e350m1/agesawrapper.c b/src/mainboard/asrock/e350m1/agesawrapper.c index 7fc2fd6..8ecc885 100644 --- a/src/mainboard/asrock/e350m1/agesawrapper.c +++ b/src/mainboard/asrock/e350m1/agesawrapper.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- +/*----------------------------------------------------------------------------- + * M O D U L E S U S E D + *----------------------------------------------------------------------------- */ #include <stdint.h> @@ -39,490 +39,489 @@ #define FILECODE UNASSIGNED_FILE_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- +/*------------------------------------------------------------------------------ + * D E F I N I T I O N S A N D M A C R O S + *------------------------------------------------------------------------------ */ -/* ACPI table pointers returned by AmdInitLate */ -VOID *DmiTable = NULL; -VOID *AcpiPstate = NULL; -VOID *AcpiSrat = NULL; -VOID *AcpiSlit = NULL; - -VOID *AcpiWheaMce = NULL; -VOID *AcpiWheaCmc = NULL; -VOID *AcpiAlib = NULL; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- +/* ACPI table pointers returned by AmdInitLate */ +VOID *DmiTable = NULL; +VOID *AcpiPstate = NULL; +VOID *AcpiSrat = NULL; +VOID *AcpiSlit = NULL; + +VOID *AcpiWheaMce = NULL; +VOID *AcpiWheaCmc = NULL; +VOID *AcpiAlib = NULL; + +/*------------------------------------------------------------------------------ + * T Y P E D E F S A N D S T R U C T U R E S + *------------------------------------------------------------------------------ */ -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- +/*------------------------------------------------------------------------------ + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *------------------------------------------------------------------------------ */ -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- +/*------------------------------------------------------------------------------ + * E X P O R T E D F U N C T I O N S + *------------------------------------------------------------------------------ */ -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- +/*------------------------------------------------------------------------------ + * L O C A L F U N C T I O N S + *------------------------------------------------------------------------------ */ UINT32 agesawrapper_amdinitcpuio ( - VOID - ) + VOID + ) { - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; - - /* Enable legacy video routing: D18F1xF4 VGA Enable */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); - PciData = 1; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* The platform BIOS needs to ensure the memory ranges of SB800 legacy - * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are - * set to non-posted regions. - */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); - PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000 - PciData |= 1 << 7; // set NP (non-posted) bit - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); - PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000 - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Map the remaining PCI hole as posted MMIO */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); - PciData = 0x00FECF00; // last address before non-posted range - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); - MsrReg = (MsrReg >> 8) | 3; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); - PciData = (UINT32)MsrReg; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Send all IO (0000-FFFF) to southbridge. */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); - PciData = 0x0000F000; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); - PciData = 0x00000003; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - Status = AGESA_SUCCESS; - return (UINT32)Status; + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* Enable legacy video routing: D18F1xF4 VGA Enable */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); + PciData = 1; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* The platform BIOS needs to ensure the memory ranges of SB800 legacy + * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are + * set to non-posted regions. + */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); + PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000 + PciData |= 1 << 7; // set NP (non-posted) bit + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); + PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000 + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Map the remaining PCI hole as posted MMIO */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); + PciData = 0x00FECF00; // last address before non-posted range + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); + MsrReg = (MsrReg >> 8) | 3; + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); + PciData = (UINT32)MsrReg; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Send all IO (0000-FFFF) to southbridge. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); + PciData = 0x0000F000; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); + PciData = 0x00000003; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + Status = AGESA_SUCCESS; + return (UINT32)Status; } UINT32 agesawrapper_amdinitmmio ( - VOID - ) + VOID + ) { - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; - - /* - Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base - Address MSR register. - */ - - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); - - /* - Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. - */ - LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); - MsrReg = MsrReg | 0x0000400000000000; - LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - - /* Set Ontario Link Data */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0); - PciData = 0x01308002; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4); - PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - Status = AGESA_SUCCESS; - return (UINT32)Status; + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* + Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base + Address MSR register. + */ + + MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; + LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); + + /* + Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. + */ + LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); + MsrReg = MsrReg | 0x0000400000000000; + LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); + + /* Set Ontario Link Data */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0); + PciData = 0x01308002; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4); + PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + Status = AGESA_SUCCESS; + return (UINT32)Status; } UINT32 agesawrapper_amdinitreset ( - VOID - ) + VOID + ) { - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESET_PARAMS AmdResetParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - - LibAmdMemFill (&AmdResetParams, - 0, - sizeof (AMD_RESET_PARAMS), - &(AmdResetParams.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; - AmdParamStruct.AllocationMethod = ByHost; - AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); - AmdParamStruct.NewStructPtr = &AmdResetParams; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = NULL; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - AmdResetParams.HtConfig.Depth = 0; - - status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); - AmdReleaseStruct (&AmdParamStruct); - return (UINT32)status; + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESET_PARAMS AmdResetParams; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + LibAmdMemFill (&AmdResetParams, + 0, + sizeof (AMD_RESET_PARAMS), + &(AmdResetParams.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; + AmdParamStruct.AllocationMethod = ByHost; + AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); + AmdParamStruct.NewStructPtr = &AmdResetParams; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = NULL; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + AmdResetParams.HtConfig.Depth = 0; + + status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + return (UINT32)status; } UINT32 agesawrapper_amdinitearly ( - VOID - ) + VOID + ) { - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_EARLY_PARAMS *AmdEarlyParamsPtr; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - - AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; - OemCustomizeInitEarly (AmdEarlyParamsPtr); - - status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); - AmdReleaseStruct (&AmdParamStruct); - - return (UINT32)status; + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_EARLY_PARAMS *AmdEarlyParamsPtr; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + + AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; + OemCustomizeInitEarly (AmdEarlyParamsPtr); + + status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; } UINT32 agesawrapper_amdinitpost ( - VOID - ) + VOID + ) { - AGESA_STATUS status; - UINT16 i; - UINT32 *HeadPtr; - AMD_INTERFACE_PARAMS AmdParamStruct; - BIOS_HEAP_MANAGER *BiosManagerPtr; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct (&AmdParamStruct); - status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); - AmdReleaseStruct (&AmdParamStruct); - /* Initialize heap space */ - BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS; - - HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); - for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) - { - *HeadPtr = 0x00000000; - HeadPtr++; - } - BiosManagerPtr->StartOfAllocatedNodes = 0; - BiosManagerPtr->StartOfFreedNodes = 0; - - return (UINT32)status; + AGESA_STATUS status; + UINT16 i; + UINT32 *HeadPtr; + AMD_INTERFACE_PARAMS AmdParamStruct; + BIOS_HEAP_MANAGER *BiosManagerPtr; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct (&AmdParamStruct); + status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + /* Initialize heap space */ + BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS; + + HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); + for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) + { + *HeadPtr = 0x00000000; + HeadPtr++; + } + BiosManagerPtr->StartOfAllocatedNodes = 0; + BiosManagerPtr->StartOfFreedNodes = 0; + + return (UINT32)status; } UINT32 agesawrapper_amdinitenv ( - VOID - ) + VOID + ) { - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - PCI_ADDR PciAddress; - UINT32 PciValue; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); - /* Initialize Subordinate Bus Number and Secondary Bus Number - * In platform BIOS this address is allocated by PCI enumeration code - Modify D1F0x18 - */ - PciAddress.Address.Bus = 0; - PciAddress.Address.Device = 1; - PciAddress.Address.Function = 0; - PciAddress.Address.Register = 0x18; - /* Write to D1F0x18 */ - LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - PciValue |= 0x00010100; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - - /* Initialize GMM Base Address for Legacy Bridge Mode - * Modify B1D5F0x18 - */ - PciAddress.Address.Bus = 1; - PciAddress.Address.Device = 5; - PciAddress.Address.Function = 0; - PciAddress.Address.Register = 0x18; - - LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - PciValue |= 0x96000000; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - - /* Initialize FB Base Address for Legacy Bridge Mode - * Modify B1D5F0x10 - */ - PciAddress.Address.Register = 0x10; - LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - PciValue |= 0x80000000; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - - /* Initialize GMM Base Address for Pcie Mode - * Modify B0D1F0x18 - */ - PciAddress.Address.Bus = 0; - PciAddress.Address.Device = 1; - PciAddress.Address.Function = 0; - PciAddress.Address.Register = 0x18; - - LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - PciValue |= 0x96000000; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - - /* Initialize FB Base Address for Pcie Mode - * Modify B0D1F0x10 - */ - PciAddress.Address.Register = 0x10; - LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - PciValue |= 0x80000000; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - - - /* Initialize MMIO Base and Limit Address - * Modify B0D1F0x20 - */ - PciAddress.Address.Bus = 0; - PciAddress.Address.Device = 1; - PciAddress.Address.Function = 0; - PciAddress.Address.Register = 0x20; - - LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - PciValue |= 0x96009600; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - - /* Initialize MMIO Prefetchable Memory Limit and Base - * Modify B0D1F0x24 - */ - PciAddress.Address.Register = 0x24; - LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - PciValue |= 0x8FF18001; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - AmdReleaseStruct (&AmdParamStruct); - - return (UINT32)status; + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + PCI_ADDR PciAddress; + UINT32 PciValue; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + /* Initialize Subordinate Bus Number and Secondary Bus Number + * In platform BIOS this address is allocated by PCI enumeration code + Modify D1F0x18 + */ + PciAddress.Address.Bus = 0; + PciAddress.Address.Device = 1; + PciAddress.Address.Function = 0; + PciAddress.Address.Register = 0x18; + /* Write to D1F0x18 */ + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x00010100; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize GMM Base Address for Legacy Bridge Mode + * Modify B1D5F0x18 + */ + PciAddress.Address.Bus = 1; + PciAddress.Address.Device = 5; + PciAddress.Address.Function = 0; + PciAddress.Address.Register = 0x18; + + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x96000000; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize FB Base Address for Legacy Bridge Mode + * Modify B1D5F0x10 + */ + PciAddress.Address.Register = 0x10; + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x80000000; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize GMM Base Address for Pcie Mode + * Modify B0D1F0x18 + */ + PciAddress.Address.Bus = 0; + PciAddress.Address.Device = 1; + PciAddress.Address.Function = 0; + PciAddress.Address.Register = 0x18; + + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x96000000; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize FB Base Address for Pcie Mode + * Modify B0D1F0x10 + */ + PciAddress.Address.Register = 0x10; + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x80000000; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize MMIO Base and Limit Address + * Modify B0D1F0x20 + */ + PciAddress.Address.Bus = 0; + PciAddress.Address.Device = 1; + PciAddress.Address.Function = 0; + PciAddress.Address.Register = 0x20; + + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x96009600; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + + /* Initialize MMIO Prefetchable Memory Limit and Base + * Modify B0D1F0x24 + */ + PciAddress.Address.Register = 0x24; + LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + PciValue |= 0x8FF18001; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; } VOID * agesawrapper_getlateinitptr ( - int pick - ) + int pick + ) { - switch (pick) { - case PICK_DMI: - return DmiTable; - case PICK_PSTATE: - return AcpiPstate; - case PICK_SRAT: - return AcpiSrat; - case PICK_SLIT: - return AcpiSlit; - case PICK_WHEA_MCE: - return AcpiWheaMce; - case PICK_WHEA_CMC: - return AcpiWheaCmc; - case PICK_ALIB: - return AcpiAlib; - default: - return NULL; - } + switch (pick) { + case PICK_DMI: + return DmiTable; + case PICK_PSTATE: + return AcpiPstate; + case PICK_SRAT: + return AcpiSrat; + case PICK_SLIT: + return AcpiSlit; + case PICK_WHEA_MCE: + return AcpiWheaMce; + case PICK_WHEA_CMC: + return AcpiWheaCmc; + case PICK_ALIB: + return AcpiAlib; + default: + return NULL; + } } UINT32 agesawrapper_amdinitmid ( - VOID - ) + VOID + ) { - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; - /* Enable MMIO on AMD CPU Address Map Controller */ - agesawrapper_amdinitcpuio (); + /* Enable MMIO on AMD CPU Address Map Controller */ + agesawrapper_amdinitcpuio (); - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); - AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); + AmdCreateStruct (&AmdParamStruct); - status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); - AmdReleaseStruct (&AmdParamStruct); + status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); - return (UINT32)status; + return (UINT32)status; } UINT32 agesawrapper_amdinitlate ( - VOID - ) + VOID + ) { - AGESA_STATUS Status; - AMD_LATE_PARAMS AmdLateParams; - - LibAmdMemFill (&AmdLateParams, - 0, - sizeof (AMD_LATE_PARAMS), - &(AmdLateParams.StdHeader)); - - AmdLateParams.StdHeader.AltImageBasePtr = 0; - AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdLateParams.StdHeader.Func = 0; - AmdLateParams.StdHeader.ImageBasePtr = 0; - - Status = AmdInitLate (&AmdLateParams); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); - } - - DmiTable = AmdLateParams.DmiTable; - AcpiPstate = AmdLateParams.AcpiPState; - AcpiSrat = AmdLateParams.AcpiSrat; - AcpiSlit = AmdLateParams.AcpiSlit; - - AcpiWheaMce = AmdLateParams.AcpiWheaMce; - AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; - AcpiAlib = AmdLateParams.AcpiAlib; - - return (UINT32)Status; + AGESA_STATUS Status; + AMD_LATE_PARAMS AmdLateParams; + + LibAmdMemFill (&AmdLateParams, + 0, + sizeof (AMD_LATE_PARAMS), + &(AmdLateParams.StdHeader)); + + AmdLateParams.StdHeader.AltImageBasePtr = 0; + AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdLateParams.StdHeader.Func = 0; + AmdLateParams.StdHeader.ImageBasePtr = 0; + + Status = AmdInitLate (&AmdLateParams); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(); + ASSERT(Status == AGESA_SUCCESS); + } + + DmiTable = AmdLateParams.DmiTable; + AcpiPstate = AmdLateParams.AcpiPState; + AcpiSrat = AmdLateParams.AcpiSrat; + AcpiSlit = AmdLateParams.AcpiSlit; + + AcpiWheaMce = AmdLateParams.AcpiWheaMce; + AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; + AcpiAlib = AmdLateParams.AcpiAlib; + + return (UINT32)Status; } UINT32 agesawrapper_amdlaterunaptask ( - UINT32 Func, - UINT32 Data, - VOID *ConfigPtr - ) + UINT32 Func, + UINT32 Data, + VOID *ConfigPtr + ) { - AGESA_STATUS Status; - AP_EXE_PARAMS ApExeParams; - - LibAmdMemFill (&ApExeParams, - 0, - sizeof (AP_EXE_PARAMS), - &(ApExeParams.StdHeader)); - - ApExeParams.StdHeader.AltImageBasePtr = 0; - ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - ApExeParams.StdHeader.Func = 0; - ApExeParams.StdHeader.ImageBasePtr = 0; - ApExeParams.StdHeader.ImageBasePtr = 0; - ApExeParams.FunctionNumber = Func; - ApExeParams.RelatedDataBlock = ConfigPtr; - - Status = AmdLateRunApTask (&ApExeParams); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); - } - - return (UINT32)Status; + AGESA_STATUS Status; + AP_EXE_PARAMS ApExeParams; + + LibAmdMemFill (&ApExeParams, + 0, + sizeof (AP_EXE_PARAMS), + &(ApExeParams.StdHeader)); + + ApExeParams.StdHeader.AltImageBasePtr = 0; + ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + ApExeParams.StdHeader.Func = 0; + ApExeParams.StdHeader.ImageBasePtr = 0; + ApExeParams.StdHeader.ImageBasePtr = 0; + ApExeParams.FunctionNumber = Func; + ApExeParams.RelatedDataBlock = ConfigPtr; + + Status = AmdLateRunApTask (&ApExeParams); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(); + ASSERT(Status == AGESA_SUCCESS); + } + + return (UINT32)Status; } UINT32 agesawrapper_amdreadeventlog ( - VOID - ) + VOID + ) { - AGESA_STATUS Status; - EVENT_PARAMS AmdEventParams; - - LibAmdMemFill (&AmdEventParams, - 0, - sizeof (EVENT_PARAMS), - &(AmdEventParams.StdHeader)); - - AmdEventParams.StdHeader.AltImageBasePtr = 0; - AmdEventParams.StdHeader.CalloutPtr = NULL; - AmdEventParams.StdHeader.Func = 0; - AmdEventParams.StdHeader.ImageBasePtr = 0; - Status = AmdReadEventLog (&AmdEventParams); - while (AmdEventParams.EventClass != 0) { - printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo); - printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2); - printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4); - Status = AmdReadEventLog (&AmdEventParams); - } - - return (UINT32)Status; + AGESA_STATUS Status; + EVENT_PARAMS AmdEventParams; + + LibAmdMemFill (&AmdEventParams, + 0, + sizeof (EVENT_PARAMS), + &(AmdEventParams.StdHeader)); + + AmdEventParams.StdHeader.AltImageBasePtr = 0; + AmdEventParams.StdHeader.CalloutPtr = NULL; + AmdEventParams.StdHeader.Func = 0; + AmdEventParams.StdHeader.ImageBasePtr = 0; + Status = AmdReadEventLog (&AmdEventParams); + while (AmdEventParams.EventClass != 0) { + printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo); + printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2); + printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4); + Status = AmdReadEventLog (&AmdEventParams); + } + + return (UINT32)Status; }

1 0

I/O ports don't work
by Abhinav Hardikar 03 Jan '12

03 Jan '12

Hi there. I finally got coreboot working with my mobo in September and now I am back to resolve more issues. None of my I/O ports, PCI/ISA slots work. I some how got output from the serial ports. To get the output, I flashed my mobo with coreboot and restarted the PC without losing power. I think because of this the serial ports remained initialized and I got output on minicom on another computer. But when I powered down my PC and started it up again I had no response on minicom. Is there a solution to this: http://pastebin.com/r5E2Qnuq is the output on minicom. Abhinav

1 1

Patch merged into coreboot/master: 098c3a7 Add missing EOT marker.
by gerrit＠coreboot.org 03 Jan '12

03 Jan '12

the following patch was just integrated into master: commit 098c3a7c8881934249624d28a6e1889c061d9c35 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Mon Jan 2 19:11:49 2012 -0600 Add missing EOT marker. Omitted from commit 3d1d6bb4ecb15a12f48f871c623882bee9c0c576 Change-Id: Id3e94d615d50f0673cc5e3fde77ed6748d26ebd3 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Build-Tested: build bot (Jenkins) at Tue Jan 3 02:47:29 2012, giving +1 Reviewed-By: Peter Stuge <peter(a)stuge.se> at Tue Jan 3 02:38:27 2012, giving +2 See http://review.coreboot.org/514 for details. -gerrit

1 0

Patch set updated for coreboot: 098c3a7 Add missing EOT marker.
by Jonathan A. Kollasch 03 Jan '12

03 Jan '12

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/514 -gerrit commit 098c3a7c8881934249624d28a6e1889c061d9c35 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Mon Jan 2 19:11:49 2012 -0600 Add missing EOT marker. Omitted from commit 3d1d6bb4ecb15a12f48f871c623882bee9c0c576 Change-Id: Id3e94d615d50f0673cc5e3fde77ed6748d26ebd3 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> --- util/superiotool/superiotool.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/util/superiotool/superiotool.h b/util/superiotool/superiotool.h index 5583ec5..94918b8 100644 --- a/util/superiotool/superiotool.h +++ b/util/superiotool/superiotool.h @@ -247,7 +247,7 @@ static const struct { {probe_idregs_amd, {0xaa, EOT}}, #endif {probe_idregs_serverengines, {0x2e, EOT}}, - {probe_idregs_infineon, {0x2e, 0x4e}}, + {probe_idregs_infineon, {0x2e, 0x4e, EOT}}, }; /** Table of functions to print out supported Super I/O chips. */

1 0

New patch to review for coreboot: 39a4861 Fix omission of EOT maker from commit 3d1d6bb4ecb15a12f48f871c623882bee9c0c576
by Jonathan A. Kollasch 03 Jan '12

03 Jan '12

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/514 -gerrit commit 39a4861b8725618182c5e1f662d56c55ba6cb9b8 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Mon Jan 2 19:11:49 2012 -0600 Fix omission of EOT maker from commit 3d1d6bb4ecb15a12f48f871c623882bee9c0c576 Change-Id: Id3e94d615d50f0673cc5e3fde77ed6748d26ebd3 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> --- util/superiotool/superiotool.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/util/superiotool/superiotool.h b/util/superiotool/superiotool.h index 5583ec5..94918b8 100644 --- a/util/superiotool/superiotool.h +++ b/util/superiotool/superiotool.h @@ -247,7 +247,7 @@ static const struct { {probe_idregs_amd, {0xaa, EOT}}, #endif {probe_idregs_serverengines, {0x2e, EOT}}, - {probe_idregs_infineon, {0x2e, 0x4e}}, + {probe_idregs_infineon, {0x2e, 0x4e, EOT}}, }; /** Table of functions to print out supported Super I/O chips. */

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Patch merged into coreboot/master: 1ba80c2 F14 mainboard: mptable update
by gerrit＠coreboot.org 02 Jan '12

02 Jan '12

the following patch was just integrated into master: commit 1ba80c2a084e3403fc7ce06c487e0a97316b668e Author: Kerry Sheh <shekairui(a)gmail.com> Date: Thu Dec 22 12:18:26 2011 +0800 F14 mainboard: mptable update Add GNB internal graphic interrupt, correct southbridge hd audio device interrupt. and remove the dead code already commented out. south_station, union_station, inagua, persimmon and e350m1 mainboard are included herein. Change-Id: Ic7618d80e0432ed0e22d1c16e1adb8ba6cea2e59 Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Build-Tested: build bot (Jenkins) at Thu Dec 22 04:56:30 2011, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Mon Jan 2 23:12:57 2012, giving +2 See http://review.coreboot.org/451 for details. -gerrit

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Patch merged into coreboot/master: 42bde27 F14 mainboard: update acpi interrupt routing in pic and apic mode
by gerrit＠coreboot.org 02 Jan '12

02 Jan '12

the following patch was just integrated into master: commit 42bde27e1474bd45ef0d727ef7a874f1eebfd3ab Author: Kerry Sheh <shekairui(a)gmail.com> Date: Thu Dec 22 12:18:37 2011 +0800 F14 mainboard: update acpi interrupt routing in pic and apic mode Add interrupt routing for APU GNB internal Graphic and HD audio device, and other pcie bridge device in GNB. south_station, union_station, inagua, persimmon and e350m1 mainboard are included herein. Change-Id: I4b6e0fce8d34637c03de8ebfdadea008c98e193b Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Build-Tested: build bot (Jenkins) at Thu Dec 22 04:46:42 2011, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Mon Jan 2 23:10:04 2012, giving +2 See http://review.coreboot.org/452 for details. -gerrit

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please suggest
by marty 02 Jan '12

02 Jan '12

I wish to use coreboot for a firewall design. I need to have iptables/modules/and drop policy all loaded before networking is enabled. I can do the rest from disk. I will need 2 slots for Ethernet cards. I need 2G RAM capability. I prefer a 3.x version Linux kernel. From what I see, most BIOS chips seem a bit small for this. I don't need high-end hardware; domestic stuff is preferred. Definately no Realtec 8169 however... Gaa... Can someone please suggest a board(s) that might suit my needs, and is well supported by coreboot? Thank you, Marty B.

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Trac reminder: list of new ticket(s)
by coreboot tracker 02 Jan '12

02 Jan '12

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coreboot January 2012