coreboot April 2011

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Happy Bunny Day!
by Joseph Smith 24 Apr '11

24 Apr '11

Happy Bunny Day Everyone! -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

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Differencies between AMD microcodes
by David Santamaría Rogado 22 Apr '11

22 Apr '11

I'm trying to bring up support for Gigabyte GA-MA785GM-US2H. Actually there is GA-MA78GM-US2H and GA-MA785GMT-UD2H that are similar. GA-MA785GM-US2H only differs from GA-MA785GMT-UD2H that it's DDR2 and AM2+ instead of DDR· and AM3, so, i copy the folder ma785gmt to ma785gm and started to change places where appear as am3 to am2r2 and ddr3 to ddr2. To finish I look the differencies between GA-MA78GM-US2H and GA-MA785GMT-UD2H and I see that config AMD_UCODE_PATCH_FILE of GA-MA78GM-US2H is mc_patch_01000095.h and GA-MA785GMT-UD2H is mc_patch_010000b6.h. I don't know what to apply for GA-MA785GM-US2H, if *95.h is used when the socket is am2+ and *b6.h when it's am3 I have to use *95.h, but, if *95.h is used when the chipset is 780 and *b6.h when it's 785 I have to use *b6.h. So the question is what it's the difference between the two mcs and which one should I use for a 785g chipset am2+ motherboard? Thanks in advance.

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[commit] r6543 - trunk/util/superiotool
by repository service 22 Apr '11

22 Apr '11

Author: stepan Date: Sat Apr 23 01:12:40 2011 New Revision: 6543 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6543 Log: Add (partly) support for Nuvoton NCT6776F Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/superiotool/nuvoton.c trunk/util/superiotool/superiotool.h Modified: trunk/util/superiotool/nuvoton.c ============================================================================== --- trunk/util/superiotool/nuvoton.c Sat Apr 23 01:10:35 2011 (r6542) +++ trunk/util/superiotool/nuvoton.c Sat Apr 23 01:12:40 2011 (r6543) @@ -66,13 +66,201 @@ {EOT}}}, {0x1a, "WPCM450", { {EOT}}}, + {0xc332, "NCT6776F (B)", { + {NOLDN, NULL, + {0x10,0x11,0x13,0x14,0x16,0x17,0x18,0x19,0x1a, + 0x1b,0x1c,0x1d,0x1e,0x1f,0x20,0x21,0x22,0x23, + 0x24,0x25,0x26,0x27,0x28,0x2a,0x2b,0x2c,0x2d, + 0x2e,0x2f,EOT}, + {0xff,0xff,0x00,0x00,0xff,0xff,0xff,0xff,0xf0, + 0x78,0x00,0x00,0xff,0xff,0xc3,0x32,0xff,0x00, + 0x64,0x00,MISC,0x00,0x00,0xc0,0x00,0x81,0x00, + 0x00,MISC,EOT}}, + {0x00, "FDC", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4, + 0xf5,EOT}, + {0x01,0x03,0xf0,0x06,0x02,0x0e,0x00,0xff,0x00, + 0x00,EOT}}, + {0x01, "Parallel Port", + {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, + {0x01,0x03,0x78,0x07,0x04,0x3f,EOT}}, + {0x02, "UART A", + {0x30,0x60,0x61,0x70,0xf0,0xf2,EOT}, + {0x01,0x03,0xf8,0x04,0x00,0x00,EOT}}, + {0x03, "UART B, IR", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,EOT}, + {0x01,0x02,0xf8,0x03,0x00,0x00,0x00,EOT}}, + {0x05, "Keyboard Controller", + {0x30,0x60,0x61,0x62,0x63,0x70,0x72,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x83,EOT}}, + {0x06, "CIR", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,0xf3,EOT}, + {0x00,0x00,0x00,0x00,0x08,0x09,0x32,0x00,EOT}}, + {0x07, "GPIO6, GPIO7, GPIO8, GPIO9", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, + 0xe8,0xe9,0xea,0xeb,0xec,0xed,0xee,0xf4,0xf5, + 0xf6,0xf7,0xf8,EOT}, + {0x03,0xff,0x00,0x00,0x00,0xef,0x00,0x00,0x00, + 0xff,0x00,0x00,0x00,0x00,0x00,0x00,0xff,0x00, + 0x00,0x00,0x00,EOT}}, + {0x08, "WDT1, GPIO0, GPIO1, GPIOA", + {0x30,0x60,0x61,0xe0,0xe1,0xe2,0xe3,0xe4,0xf0, + 0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,EOT}, + {0x02,0x00,0x00,0xff,0x00,0x00,0x00,0xef,0xff, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x09, "GPIO2, GPIO3, GPIO4, GPIO5", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, + 0xe8,0xe9,0xea,0xeb,0xee,0xf0,0xf1,0xf2,0xf4, + 0xf5,0xf6,0xf7,0xfe,EOT}, + {0x04,0xdf,0x00,0x00,0x00,0xff,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0xff,0x00,0x00,0xff, + 0x00,0x00,0x00,0x00,EOT}}, + {0x0a, "ACPI", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe9, + 0xee,0xf0,0xf2,0xf3,0xf4,0xf6,0xf7,0xfe,EOT}, + {0x01,0x00,0x00,0x00,0x00,0x02,0x1c,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0xc0,0x00,EOT}}, + {0x0b, "Hardware Monitor, Front Panel LED", + {0x30,0x60,0x61,0x62,0x63,0x70,0xe0,0xe1,0xe2, + 0xf0,0xf1,0xf2,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa, + EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x7f,0x7f,0xff, + 0x00,0x00,0x00,0x10,0x00,0x87,0x47,0x00,0x00, + EOT}}, + {0x0d, "VID", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe9,0xee, + 0xef,0xf0,0xf4,0xf5,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x88, + 0x00,0x00,0x00,0x00,EOT}}, + {0x0e, "CIR WAKE-UP", + {0x30,0x60,0x61,0x70,EOT}, + {0x00,0x00,0x00,0x00,EOT}}, + {0x0f, "GPIO Push-Pull or Open-drain", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8, + 0xe9,0xf0,0xf1,0xf2,EOT}, + {0xff,0xdf,0xff,0xfe,0xf6,0xff,0xff,0xd3,0xff, + 0x9f,0x00,0x00,0x00,EOT}}, + {0x14, "SVID", + {0xe0,0xe1,0xe3,0xe4,EOT}, + {0x00,0x80,0x00,0x00,EOT}}, + {0x16, "Deep Sleep", + {0x30,0xe0,0xe1,0xe2,EOT}, + {0x20,0x20,0x04,0x05,EOT}}, + {0x17, "GPIOA", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,EOT}, + {0x01,0x00,0x00,0x00,0x01,0x00,EOT}}, + {EOT}}}, + {0xc333, "NCT6776F (C)", { + {NOLDN, NULL, + {0x10,0x11,0x13,0x14,0x16,0x17,0x18,0x19,0x1a, + 0x1b,0x1c,0x1d,0x1e,0x1f,0x20,0x21,0x22,0x23, + 0x24,0x25,0x26,0x27,0x28,0x2a,0x2b,0x2c,0x2d, + 0x2e,0x2f,EOT}, + {0xff,0xff,0x00,0x00,0xff,0xff,0xff,0xff,0xf0, + 0x78,0x00,0x00,0xff,0xff,0xc3,0x33,0xff,0x00, + 0x64,0x00,MISC,0x00,0x00,0xc0,0x00,0x81,0x00, + 0x00,MISC,EOT}}, + {0x00, "FDC", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4, + 0xf5,EOT}, + {0x01,0x03,0xf0,0x06,0x02,0x0e,0x00,0xff,0x00, + 0x00,EOT}}, + {0x01, "Parallel Port", + {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, + {0x01,0x03,0x78,0x07,0x04,0x3f,EOT}}, + {0x02, "UART A", + {0x30,0x60,0x61,0x70,0xf0,0xf2,EOT}, + {0x01,0x03,0xf8,0x04,0x00,0x00,EOT}}, + {0x03, "UART B, IR", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,EOT}, + {0x01,0x02,0xf8,0x03,0x00,0x00,0x00,EOT}}, + {0x05, "Keyboard Controller", + {0x30,0x60,0x61,0x62,0x63,0x70,0x72,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x83,EOT}}, + {0x06, "CIR", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,0xf3,EOT}, + {0x00,0x00,0x00,0x00,0x08,0x09,0x32,0x00,EOT}}, + {0x07, "GPIO6, GPIO7, GPIO8, GPIO9", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, + 0xe8,0xe9,0xea,0xeb,0xec,0xed,0xee,0xf4,0xf5, + 0xf6,0xf7,0xf8,EOT}, + {0x03,0xff,0x00,0x00,0x00,0xef,0x00,0x00,0x00, + 0xff,0x00,0x00,0x00,0x00,0x00,0x00,0xff,0x00, + 0x00,0x00,0x00,EOT}}, + {0x08, "WDT1, GPIO0, GPIO1, GPIOA", + {0x30,0x60,0x61,0xe0,0xe1,0xe2,0xe3,0xe4,0xf0, + 0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,EOT}, + {0x02,0x00,0x00,0xff,0x00,0x00,0x00,0xef,0xff, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x09, "GPIO2, GPIO3, GPIO4, GPIO5", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, + 0xe8,0xe9,0xea,0xeb,0xee,0xf0,0xf1,0xf2,0xf4, + 0xf5,0xf6,0xf7,0xfe,EOT}, + {0x04,0xdf,0x00,0x00,0x00,0xff,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0xff,0x00,0x00,0xff, + 0x00,0x00,0x00,0x00,EOT}}, + {0x0a, "ACPI", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe9, + 0xee,0xf0,0xf2,0xf3,0xf4,0xf6,0xf7,0xfe,EOT}, + {0x01,0x00,0x00,0x00,0x00,0x02,0x1c,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0xc0,0x00,EOT}}, + {0x0b, "Hardware Monitor, Front Panel LED", + {0x30,0x60,0x61,0x62,0x63,0x70,0xe0,0xe1,0xe2, + 0xf0,0xf1,0xf2,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa, + EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x7f,0x7f,0xff, + 0x00,0x00,0x00,0x10,0x00,0x87,0x47,0x00,0x00, + EOT}}, + {0x0d, "VID", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe9,0xee, + 0xef,0xf0,0xf4,0xf5,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x88, + 0x00,0x00,0x00,0x00,EOT}}, + {0x0e, "CIR WAKE-UP", + {0x30,0x60,0x61,0x70,EOT}, + {0x00,0x00,0x00,0x00,EOT}}, + {0x0f, "GPIO Push-Pull or Open-drain", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8, + 0xe9,0xf0,0xf1,0xf2,EOT}, + {0xff,0xdf,0xff,0xfe,0xf6,0xff,0xff,0xd3,0xff, + 0x9f,0x00,0x00,0x00,EOT}}, + {0x14, "SVID", + {0xe0,0xe1,0xe3,0xe4,EOT}, + {0x00,0x80,0x00,0x00,EOT}}, + {0x16, "Deep Sleep", + {0x30,0xe0,0xe1,0xe2,EOT}, + {0x20,0x20,0x04,0x05,EOT}}, + {0x17, "GPIOA", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,EOT}, + {0x01,0x00,0x00,0x00,0x01,0x00,EOT}}, + {EOT}}}, {EOT} }; void probe_idregs_nuvoton(uint16_t port) { uint8_t sid, srid; - uint8_t chip_id = 0, chip_rev = 0; + uint16_t chip_id = 0; + uint8_t chip_rev = 0; + + /* Probe for the 16bit IDs first to avoid collisions */ + probing_for("Nuvoton", "", port); + enter_conf_mode_winbond_fintek_ite_8787(port); + chip_id = (regval(port, DEVICE_ID_REG) << 8) | + regval(port, DEVICE_ID_REG + 1); + + exit_conf_mode_winbond_fintek_ite_8787(port); + + if (!superio_unknown(reg_table, chip_id)) { + printf("Found Nuvoton %s (id=0x%02x) at 0x%x\n", + get_superio_name(reg_table, chip_id), chip_id, port); + chip_found = 1; + dump_superio("Nuvoton", reg_table, port, chip_id, LDN_SEL); + return; + } + + if (verbose) + printf(NOTFOUND "chip_id=0x%04x\n", chip_id); probing_for("Nuvoton", "(sid=0xfc) ", port); Modified: trunk/util/superiotool/superiotool.h ============================================================================== --- trunk/util/superiotool/superiotool.h Sat Apr 23 01:10:35 2011 (r6542) +++ trunk/util/superiotool/superiotool.h Sat Apr 23 01:12:40 2011 (r6543) @@ -230,7 +230,7 @@ {probe_idregs_nsc, {0x2e, 0x4e, 0x15c, 0x164e, EOT}}, /* I/O pairs on Nuvoton EC chips can be configured by firmware in * addition to the following hardware strapping options. */ - {probe_idregs_nuvoton, {0x164e, 0x2e, EOT}}, + {probe_idregs_nuvoton, {0x164e, 0x2e, 0x4e, EOT}}, {probe_idregs_smsc, {0x2e, 0x4e, 0x162e, 0x164e, 0x3f0, 0x370, EOT}}, {probe_idregs_winbond, {0x2e, 0x4e, 0x3f0, 0x370, 0x250, EOT}}, #ifdef PCI_SUPPORT

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[commit] r6542 - trunk/util/superiotool
by repository service 22 Apr '11

22 Apr '11

Author: stepan Date: Sat Apr 23 01:10:35 2011 New Revision: 6542 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6542 Log: cosmetic changes to superiotool's nuvoton code Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Modified: trunk/util/superiotool/nuvoton.c Modified: trunk/util/superiotool/nuvoton.c ============================================================================== --- trunk/util/superiotool/nuvoton.c Sat Apr 23 00:26:04 2011 (r6541) +++ trunk/util/superiotool/nuvoton.c Sat Apr 23 01:10:35 2011 (r6542) @@ -29,7 +29,7 @@ {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, - {0xFC,0x11,RSVD,RSVD,RSVD,0x00,0x00,MISC,0x00, + {0xfc,0x11,RSVD,RSVD,RSVD,0x00,0x00,MISC,0x00, 0x04,RSVD,RSVD,RSVD,0x00,RSVD,RSVD,EOT}}, {0x03, "CIR Port (CIRP)", /* where supported */ {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, @@ -99,7 +99,6 @@ printf("Found Nuvoton %s (id=0x%02x, rev=0x%02x) at 0x%x\n", get_superio_name(reg_table, sid), chip_id, chip_rev, port); chip_found = 1; - dump_superio("Nuvoton", reg_table, port, sid, LDN_SEL); }

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[PATCH] superiotool support for nuvoton nct6776f
by Stefan Reinauer 22 Apr '11

22 Apr '11

See patch

2 1

[commit] r6541 - trunk/src/lib
by repository service 22 Apr '11

22 Apr '11

Author: ruik Date: Sat Apr 23 00:26:04 2011 New Revision: 6541 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6541 Log: Fix of fix copy and paste errors in ne2k.c (r6512 by stepan) Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Rudolf Marek <r.marek(a)assembler.cz> Modified: trunk/src/lib/ne2k.c Modified: trunk/src/lib/ne2k.c ============================================================================== --- trunk/src/lib/ne2k.c Fri Apr 22 04:32:03 2011 (r6540) +++ trunk/src/lib/ne2k.c Sat Apr 23 00:26:04 2011 (r6541) @@ -453,7 +453,7 @@ }; static const struct pci_driver ne2k_driver __pci_driver = { - .ops = &si_sata_ops, + .ops = &ne2k_ops, .vendor = 0x10ec, .device = 0x8029, };

1 0

coreboot hackaton in Prague
by Rudolf Marek 22 Apr '11

22 Apr '11

Hi all, I think it is time to remind the coreboot hackaton in Prague which will take place last weekend at the end of May (27,28,29) There is still a http://doodle.com/2n4h3gcugwvs6c9k poll if others wants to join in. The even will take place in Prague, Czech Republic. Most likely at the university building in city centre. The accommodation could be arranged at the dormitory or in any other hotel/hostel. Now a bit to a programme and this is where you all can jump in! I think we could also do a short Prague sightseeing/social events too ;) Thanks, Rudolf

2 1

[PATCH] Add subsystem callbacks for VIA
by Rudolf Marek 22 Apr '11

22 Apr '11

Hi all, Following patch adds subsystem callbacks for VT8237x and VT890 family of chipsets. Tested only partially because the device on/off is done in strange way not using the devicetree, which I might address in the future. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Thanks, Rudolf

2 1

[PATCH 1/4] ADVANSUS a785e-i Mainboard support
by She, Kerry 22 Apr '11

22 Apr '11

Hello, ADVANSUS a785e-i Mainboard support RS880(RS785E)+SB820 platform Signed-off-by: Kerry She <Kerry.she(a)amd.com> Regards, Kerry She < kerry.she(a)amd.com> Tel: 86-10-6280-1415 Mobile: 86 - 152 1018 2083

2 1

[commit] r6540 - trunk/src/lib
by repository service 21 Apr '11

21 Apr '11

Author: stepan Date: Fri Apr 22 04:32:03 2011 New Revision: 6540 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6540 Log: fix typo ttys0_index -> b_index Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Modified: trunk/src/lib/uart8250.c Modified: trunk/src/lib/uart8250.c ============================================================================== --- trunk/src/lib/uart8250.c Fri Apr 22 04:17:26 2011 (r6539) +++ trunk/src/lib/uart8250.c Fri Apr 22 04:32:03 2011 (r6540) @@ -101,7 +101,7 @@ #if defined(__PRE_RAM__) b_index = read_option(CMOS_VSTART_baud_rate, CMOS_VLEN_baud_rate, 0); b_index &= 7; - div = divisor[ttys0_index]; + div = divisor[b_index]; #else if (get_option(&b_index, "baud_rate") == 0) { div = divisor[b_index];

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coreboot April 2011