coreboot April 2011

coreboot@coreboot.org

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229 discussions

Sun Ultra 40 M2
by Thom Lauret 27 Apr '11

27 Apr '11

Hey all, I know the Sun Ultra 40 has a coreboot image available but is anyone working on the Sun Ultra 40 M2 ? Sun / Oracle's latest BIOS for this unit will not support quad or six core (or dual threaded) Opterons. The chipset is definitely capable however. A BIOS with a microcode update would substantially enhance this workstation, going from the current 2x dual core, single threaded / 4 way maximum to a 2x six core, dual threaded / 24 way system. Thank You Thom

2 1

[commit] r6548 - trunk/src/mainboard/lenovo/x60
by repository service 27 Apr '11

27 Apr '11

Author: svens Date: Wed Apr 27 21:48:05 2011 New Revision: 6548 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6548 Log: X60: enable Ultrabay if device is plugged in Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/mainboard/lenovo/x60/Makefile.inc trunk/src/mainboard/lenovo/x60/devicetree.cb trunk/src/mainboard/lenovo/x60/dock.c trunk/src/mainboard/lenovo/x60/dock.h trunk/src/mainboard/lenovo/x60/mainboard.c Modified: trunk/src/mainboard/lenovo/x60/Makefile.inc ============================================================================== --- trunk/src/mainboard/lenovo/x60/Makefile.inc Wed Apr 27 21:47:49 2011 (r6547) +++ trunk/src/mainboard/lenovo/x60/Makefile.inc Wed Apr 27 21:48:05 2011 (r6548) @@ -19,3 +19,4 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c dock.c romstage-y += dock.c +ramstage-y += dock.c Modified: trunk/src/mainboard/lenovo/x60/devicetree.cb ============================================================================== --- trunk/src/mainboard/lenovo/x60/devicetree.cb Wed Apr 27 21:47:49 2011 (r6547) +++ trunk/src/mainboard/lenovo/x60/devicetree.cb Wed Apr 27 21:48:05 2011 (r6548) @@ -156,7 +156,7 @@ end end end - device pci 1f.1 off # IDE + device pci 1f.1 on # IDE subsystemid 0x17aa 0x200c end device pci 1f.2 on # SATA Modified: trunk/src/mainboard/lenovo/x60/dock.c ============================================================================== --- trunk/src/mainboard/lenovo/x60/dock.c Wed Apr 27 21:47:49 2011 (r6547) +++ trunk/src/mainboard/lenovo/x60/dock.c Wed Apr 27 21:48:05 2011 (r6548) @@ -247,3 +247,8 @@ { return !((inb(DEFAULT_GPIOBASE + 0x0c) >> 13) & 1); } + +int dock_ultrabay_device_present(void) +{ + return inb(0x1621) & 0x02 ? 0 : 1; +} Modified: trunk/src/mainboard/lenovo/x60/dock.h ============================================================================== --- trunk/src/mainboard/lenovo/x60/dock.h Wed Apr 27 21:47:49 2011 (r6547) +++ trunk/src/mainboard/lenovo/x60/dock.h Wed Apr 27 21:48:05 2011 (r6548) @@ -5,4 +5,5 @@ extern void dock_disconnect(void); extern int dock_present(void); extern int dlpc_init(void); +extern int dock_ultrabay_device_present(void); #endif Modified: trunk/src/mainboard/lenovo/x60/mainboard.c ============================================================================== --- trunk/src/mainboard/lenovo/x60/mainboard.c Wed Apr 27 21:47:49 2011 (r6547) +++ trunk/src/mainboard/lenovo/x60/mainboard.c Wed Apr 27 21:48:05 2011 (r6548) @@ -34,10 +34,11 @@ #include <ec/acpi/ec.h> #include <ec/lenovo/h8/h8.h> #include <northbridge/intel/i945/i945.h> +#include "dock.h" static void mainboard_enable(device_t dev) { - device_t dev0; + device_t dev0, idedev; /* enable Audio */ h8_set_audio_mute(0); @@ -46,6 +47,19 @@ dev0 = dev_find_slot(0, PCI_DEVFN(0,0)); if (dev0 && pci_read_config32(dev0, SKPAD) == 0xcafed00d) ec_write(0x0c, 0xc7); + + idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1)); + if (idedev && idedev->chip_info && dock_ultrabay_device_present()) { + struct southbridge_intel_i82801gx_config *config = idedev->chip_info; + config->ide_enable_primary = 1; + /* enable Ultrabay power */ + outb(inb(0x1628) | 0x01, 0x1628); + ec_write(0x0c, 0x84); + } else { + /* disable Ultrabay power */ + outb(inb(0x1628) & ~0x01, 0x1628); + ec_write(0x0c, 0x04); + } } struct chip_operations mainboard_ops = {

1 0

[commit] r6547 - trunk/src/mainboard/lenovo/t60
by repository service 27 Apr '11

27 Apr '11

Author: svens Date: Wed Apr 27 21:47:49 2011 New Revision: 6547 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6547 Log: T60: enable Ultrabay if device is plugged in Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/mainboard/lenovo/t60/devicetree.cb trunk/src/mainboard/lenovo/t60/mainboard.c Modified: trunk/src/mainboard/lenovo/t60/devicetree.cb ============================================================================== --- trunk/src/mainboard/lenovo/t60/devicetree.cb Wed Apr 27 21:47:42 2011 (r6546) +++ trunk/src/mainboard/lenovo/t60/devicetree.cb Wed Apr 27 21:47:49 2011 (r6547) @@ -180,7 +180,7 @@ end end end - device pci 1f.1 off # IDE + device pci 1f.1 on # IDE subsystemid 0x17aa 0x200c end device pci 1f.2 on # SATA Modified: trunk/src/mainboard/lenovo/t60/mainboard.c ============================================================================== --- trunk/src/mainboard/lenovo/t60/mainboard.c Wed Apr 27 21:47:42 2011 (r6546) +++ trunk/src/mainboard/lenovo/t60/mainboard.c Wed Apr 27 21:47:49 2011 (r6547) @@ -38,7 +38,7 @@ static void mainboard_enable(device_t dev) { - device_t dev0; + device_t dev0, idedev; int touchpad; /* enable Audio */ @@ -53,6 +53,17 @@ touchpad = 1; pmh7_touchpad_enable(touchpad); + + idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1)); + if (idedev && idedev->chip_info && h8_ultrabay_device_present()) { + struct southbridge_intel_i82801gx_config *config = idedev->chip_info; + config->ide_enable_primary = 1; + pmh7_ultrabay_power_enable(1); + ec_write(0x0c, 0x84); + } else { + pmh7_ultrabay_power_enable(0); + ec_write(0x0c, 0x04); + } } struct chip_operations mainboard_ops = {

1 0

[commit] r6546 - trunk/src/ec/lenovo/pmh7
by repository service 27 Apr '11

27 Apr '11

Author: svens Date: Wed Apr 27 21:47:42 2011 New Revision: 6546 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6546 Log: Lenovo PMH7: add pmh7_ultrabay_power_enable() Can be used to enable/disable Ultrabay power on Thinkpads who control that with the PMH7. (i.e. T60) Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/ec/lenovo/pmh7/pmh7.c trunk/src/ec/lenovo/pmh7/pmh7.h Modified: trunk/src/ec/lenovo/pmh7/pmh7.c ============================================================================== --- trunk/src/ec/lenovo/pmh7/pmh7.c Wed Apr 27 21:47:28 2011 (r6545) +++ trunk/src/ec/lenovo/pmh7/pmh7.c Wed Apr 27 21:47:42 2011 (r6546) @@ -49,6 +49,15 @@ else pmh7_register_set_bit(0x51, 2); } + +void pmh7_ultrabay_power_enable(int onoff) +{ + if (onoff) + pmh7_register_clear_bit(0x62, 0); + else + pmh7_register_set_bit(0x62, 0); +} + void pmh7_register_set_bit(int reg, int bit) { char val; Modified: trunk/src/ec/lenovo/pmh7/pmh7.h ============================================================================== --- trunk/src/ec/lenovo/pmh7/pmh7.h Wed Apr 27 21:47:28 2011 (r6545) +++ trunk/src/ec/lenovo/pmh7/pmh7.h Wed Apr 27 21:47:42 2011 (r6546) @@ -34,4 +34,5 @@ void pmh7_backlight_enable(int onoff); void pmh7_dock_event_enable(int onoff); void pmh7_touchpad_enable(int onoff); +void pmh7_ultrabay_power_enable(int onoff); #endif

1 0

[commit] r6545 - trunk/src/ec/lenovo/h8
by repository service 27 Apr '11

27 Apr '11

Author: svens Date: Wed Apr 27 21:47:28 2011 New Revision: 6545 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6545 Log: Lenovo H8: add h8_ultrabay_device_present() returns 1 if a CDROM/HDD device is plugging in the ultrabay. Return 0 if there's a battery or superio extensions plugged in. Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/ec/lenovo/h8/h8.c trunk/src/ec/lenovo/h8/h8.h Modified: trunk/src/ec/lenovo/h8/h8.c ============================================================================== --- trunk/src/ec/lenovo/h8/h8.c Wed Apr 27 01:47:04 2011 (r6544) +++ trunk/src/ec/lenovo/h8/h8.c Wed Apr 27 21:47:28 2011 (r6545) @@ -87,6 +87,11 @@ } +int h8_ultrabay_device_present(void) +{ + return ec_read(H8_STATUS1) & 0x5 ? 0 : 1; +} + static void h8_enable(device_t dev) { struct ec_lenovo_h8_config *conf = dev->chip_info; Modified: trunk/src/ec/lenovo/h8/h8.h ============================================================================== --- trunk/src/ec/lenovo/h8/h8.h Wed Apr 27 01:47:04 2011 (r6544) +++ trunk/src/ec/lenovo/h8/h8.h Wed Apr 27 21:47:28 2011 (r6545) @@ -25,6 +25,7 @@ void h8_set_audio_mute(int on); void h8_enable_event(int event); void h8_disable_event(int event); +int h8_ultrabay_device_present(void); /* EC registers */ #define H8_CONFIG0 0x00 @@ -102,6 +103,10 @@ #define H8_EVENT_FN_PRESS 0x39 +#define H8_STATUS0 0x46 +#define H8_STATUS1 0x47 +#define H8_STATUS2 0x48 + #define H8_EVENT_BAT0 0x4a #define H8_EVENT_BAT0_STATE 0x4b

1 0

[PATCH] Enable Ultrabay and IDE interface if Ultrabay device is present
by Sven Schnelle 27 Apr '11

27 Apr '11

this small patch series enable the Ultrabay found in T60 and X60 Laptops. The X60 is a bit more ugly as the T60 because the X60 ultrabase notifies the system over some GPIO Lines about Ultrabay state, while the T60 uses PMH7 and the EC for status information. I'm not sure if everyone likes modifying chip_info in the dev tree, so if anyone has a better solution please give me a hint. Happy corebooting with Ultrabay devices, Sven.

2 5

[commit] r6544 - in trunk/src: . arch/x86/boot arch/x86/lib console cpu/x86/smm drivers drivers/oxford drivers/oxford/oxpcie include include/boot lib
by repository service 26 Apr '11

26 Apr '11

Author: stepan Date: Wed Apr 27 01:47:04 2011 New Revision: 6544 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6544 Log: Add support for memory mapped UARTs to coreboot and add the OXPCIe952 as an example. This newer version reflects the recent changes to further simplify the console code and partly gets rid of some hacks in the previous version. Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Acked-by: Peter Stuge <peter(a)stuge.se> Added: trunk/src/console/uart8250mem_console.c trunk/src/drivers/oxford/ trunk/src/drivers/oxford/Kconfig trunk/src/drivers/oxford/Makefile.inc trunk/src/drivers/oxford/oxpcie/ trunk/src/drivers/oxford/oxpcie/Kconfig trunk/src/drivers/oxford/oxpcie/Makefile.inc trunk/src/drivers/oxford/oxpcie/oxpcie.c trunk/src/drivers/oxford/oxpcie/oxpcie_early.c trunk/src/lib/uart8250mem.c Modified: trunk/src/Kconfig trunk/src/arch/x86/boot/coreboot_table.c trunk/src/arch/x86/lib/romstage_console.c trunk/src/console/Kconfig trunk/src/console/Makefile.inc trunk/src/console/console.c trunk/src/cpu/x86/smm/smiutil.c trunk/src/drivers/Kconfig trunk/src/drivers/Makefile.inc trunk/src/include/boot/coreboot_tables.h trunk/src/include/uart8250.h trunk/src/lib/Makefile.inc Modified: trunk/src/Kconfig ============================================================================== --- trunk/src/Kconfig Sat Apr 23 01:12:40 2011 (r6543) +++ trunk/src/Kconfig Wed Apr 27 01:47:04 2011 (r6544) @@ -159,6 +159,15 @@ source src/console/Kconfig +# This should default to N and be set by SuperI/O drivers that have an UART +config HAVE_UART_IO_MAPPED + bool + default y + +config HAVE_UART_MEMORY_MAPPED + bool + default n + config HAVE_ACPI_RESUME bool default n Modified: trunk/src/arch/x86/boot/coreboot_table.c ============================================================================== --- trunk/src/arch/x86/boot/coreboot_table.c Sat Apr 23 01:12:40 2011 (r6543) +++ trunk/src/arch/x86/boot/coreboot_table.c Wed Apr 27 01:47:04 2011 (r6544) @@ -135,6 +135,9 @@ #if CONFIG_CONSOLE_SERIAL8250 add_console(header, LB_TAG_CONSOLE_SERIAL8250); #endif +#if CONFIG_CONSOLE_SERIAL8250MEM + add_console(header, LB_TAG_CONSOLE_SERIAL8250MEM); +#endif #if CONFIG_CONSOLE_LOGBUF add_console(header, LB_TAG_CONSOLE_LOGBUF); #endif Modified: trunk/src/arch/x86/lib/romstage_console.c ============================================================================== --- trunk/src/arch/x86/lib/romstage_console.c Sat Apr 23 01:12:40 2011 (r6543) +++ trunk/src/arch/x86/lib/romstage_console.c Wed Apr 27 01:47:04 2011 (r6544) @@ -19,7 +19,7 @@ #include <console/console.h> #include <console/vtxprintf.h> -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM #include <uart8250.h> #endif #if CONFIG_USBDEBUG @@ -34,6 +34,9 @@ if (byte == '\n') console_tx_byte('\r'); +#if CONFIG_CONSOLE_SERIAL8250MEM + uart8250_mem_tx_byte(CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte); +#endif #if CONFIG_CONSOLE_SERIAL8250 uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); #endif Modified: trunk/src/console/Kconfig ============================================================================== --- trunk/src/console/Kconfig Sat Apr 23 01:12:40 2011 (r6543) +++ trunk/src/console/Kconfig Wed Apr 27 01:47:04 2011 (r6544) @@ -2,9 +2,16 @@ # TODO: Rename to SERIAL_CONSOLE once Kconfig transition is complete. config CONSOLE_SERIAL8250 bool "Serial port console output" + depends on HAVE_UART_IO_MAPPED default y help - Send coreboot debug output to a serial port console. + Send coreboot debug output to an I/O mapped serial port console. + +config CONSOLE_SERIAL8250MEM + bool "Serial port console output (memory mapped)" + depends on HAVE_UART_MEMORY_MAPPED + help + Send coreboot debug output to a memory mapped serial port console. choice prompt "Serial port" @@ -43,7 +50,7 @@ choice prompt "Baud rate" default CONSOLE_SERIAL_115200 - depends on CONSOLE_SERIAL8250 + depends on CONSOLE_SERIAL8250 || CONSOLE_SERIAL8250MEM config CONSOLE_SERIAL_115200 bool "115200" @@ -82,7 +89,7 @@ config TTYS0_LCS int default 3 - depends on CONSOLE_SERIAL8250 + depends on CONSOLE_SERIAL8250 || CONSOLE_SERIAL8250MEM # Use "select HAVE_USBDEBUG" on southbridges which have Debug Port code. config HAVE_USBDEBUG Modified: trunk/src/console/Makefile.inc ============================================================================== --- trunk/src/console/Makefile.inc Sat Apr 23 01:12:40 2011 (r6543) +++ trunk/src/console/Makefile.inc Wed Apr 27 01:47:04 2011 (r6544) @@ -14,6 +14,7 @@ romstage-y += die.c driver-$(CONFIG_CONSOLE_SERIAL8250) += uart8250_console.c +driver-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem_console.c driver-$(CONFIG_USBDEBUG) += usbdebug_console.c driver-$(CONFIG_CONSOLE_LOGBUF) += logbuf_console.c driver-$(CONFIG_CONSOLE_NE2K) += ne2k_console.c Modified: trunk/src/console/console.c ============================================================================== --- trunk/src/console/console.c Sat Apr 23 01:12:40 2011 (r6543) +++ trunk/src/console/console.c Wed Apr 27 01:47:04 2011 (r6544) @@ -22,7 +22,7 @@ #include <arch/hlt.h> #include <arch/io.h> -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM #include <uart8250.h> #endif @@ -106,6 +106,9 @@ #if CONFIG_CONSOLE_SERIAL8250 uart_init(); #endif +#if CONFIG_DRIVERS_OXFORD_OXPCIE && CONFIG_CONSOLE_SERIAL8250MEM + oxford_init(); +#endif #if CONFIG_CONSOLE_NE2K ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT); #endif Added: trunk/src/console/uart8250mem_console.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/console/uart8250mem_console.c Wed Apr 27 01:47:04 2011 (r6544) @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Eric Biederman + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <uart8250.h> +#include <pc80/mc146818rtc.h> + +static u32 uart_bar = 0; + +static void uartmem_init(void) +{ + uart_bar = uart_mem_init(); +} + +static void uartmem_tx_byte(unsigned char data) +{ + if (!uart_bar) + return; + + uart8250_mem_tx_byte(uart_bar, data); +} + +static unsigned char uartmem_rx_byte(void) +{ + if (!uart_bar) + return 0; + + return uart8250_mem_rx_byte(uart_bar); +} + +static int uartmem_tst_byte(void) +{ + if (!uart_bar) + return 0; + + return uart8250_mem_can_rx_byte(uart_bar); +} + +static const struct console_driver uart8250mem_console __console = { + .init = uartmem_init, + .tx_byte = uartmem_tx_byte, + .rx_byte = uartmem_rx_byte, + .tst_byte = uartmem_tst_byte, +}; Modified: trunk/src/cpu/x86/smm/smiutil.c ============================================================================== --- trunk/src/cpu/x86/smm/smiutil.c Sat Apr 23 01:12:40 2011 (r6543) +++ trunk/src/cpu/x86/smm/smiutil.c Wed Apr 27 01:47:04 2011 (r6544) @@ -26,7 +26,7 @@ #include <console/console.h> #include <console/vtxprintf.h> -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM #include <uart8250.h> #endif #if CONFIG_USBDEBUG @@ -36,6 +36,10 @@ #include <console/ne2k.h> #endif +#if CONFIG_CONSOLE_SERIAL8250MEM +static u32 serial8250mem_base_address = 0; +#endif + void console_tx_flush(void) { // the tx_byte functions take care of the flush. @@ -47,6 +51,10 @@ if (byte == '\n') console_tx_byte('\r'); +#if CONFIG_CONSOLE_SERIAL8250MEM + if (serial8250mem_base_address) + uart8250_mem_tx_byte(serial8250mem_base_address, byte); +#endif #if CONFIG_CONSOLE_SERIAL8250 uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); #endif @@ -65,6 +73,9 @@ #if CONFIG_CONSOLE_SERIAL8250 uart_init(); #endif +#if CONFIG_CONSOLE_SERIAL8250MEM + serial8250mem_base_address = uart_mem_init(); +#endif #else console_loglevel = 1; #endif Modified: trunk/src/drivers/Kconfig ============================================================================== --- trunk/src/drivers/Kconfig Sat Apr 23 01:12:40 2011 (r6543) +++ trunk/src/drivers/Kconfig Wed Apr 27 01:47:04 2011 (r6544) @@ -22,6 +22,7 @@ source src/drivers/emulation/Kconfig source src/drivers/generic/Kconfig source src/drivers/i2c/Kconfig +source src/drivers/oxford/Kconfig source src/drivers/sil/Kconfig source src/drivers/trident/Kconfig Modified: trunk/src/drivers/Makefile.inc ============================================================================== --- trunk/src/drivers/Makefile.inc Sat Apr 23 01:12:40 2011 (r6543) +++ trunk/src/drivers/Makefile.inc Wed Apr 27 01:47:04 2011 (r6544) @@ -22,6 +22,7 @@ subdirs-y += emulation subdirs-y += generic subdirs-y += i2c +subdirs-y += oxford subdirs-y += sil subdirs-y += trident Added: trunk/src/drivers/oxford/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/drivers/oxford/Kconfig Wed Apr 27 01:47:04 2011 (r6544) @@ -0,0 +1 @@ +source src/drivers/oxford/oxpcie/Kconfig Added: trunk/src/drivers/oxford/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/drivers/oxford/Makefile.inc Wed Apr 27 01:47:04 2011 (r6544) @@ -0,0 +1 @@ +subdirs-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie Added: trunk/src/drivers/oxford/oxpcie/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/drivers/oxford/oxpcie/Kconfig Wed Apr 27 01:47:04 2011 (r6544) @@ -0,0 +1,68 @@ +config DRIVERS_OXFORD_OXPCIE + bool "Oxford OXPCIe952" + default n + select HAVE_UART_MEMORY_MAPPED + help + Support for Oxford OXPCIe952 serial port PCIe cards. + Currently only devices with the vendor ID 0x1415 and device ID + 0xc158 will work. + NOTE: Right now you have to set the base address of your OXPCIe952 + card to exactly the value that the device allocator would set them + later on, or serial console functionality will stop as soon as the + resource allocator assigns a new base address to the device. + +config OXFORD_OXPCIE_BRIDGE_BUS + hex "OXPCIe's PCIe bridge bus number" + default 0x0 + depends on DRIVERS_OXFORD_OXPCIE + help + While coreboot is executing code from ROM, the coreboot resource + allocator has not been running yet. Hence PCI devices living behind + a bridge are not yet visible to the system. In order to use an + OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge + that controls the OXPCIe952 controller first. + +config OXFORD_OXPCIE_BRIDGE_DEVICE + hex "OXPCIe's PCIe bridge device number" + default 0x1c + depends on DRIVERS_OXFORD_OXPCIE + help + While coreboot is executing code from ROM, the coreboot resource + allocator has not been running yet. Hence PCI devices living behind + a bridge are not yet visible to the system. In order to use an + OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge + that controls the OXPCIe952 controller first. + +config OXFORD_OXPCIE_BRIDGE_FUNCTION + hex "OXPCIe's PCIe bridge function number" + default 0x2 + depends on DRIVERS_OXFORD_OXPCIE + help + While coreboot is executing code from ROM, the coreboot resource + allocator has not been running yet. Hence PCI devices living behind + a bridge are not yet visible to the system. In order to use an + OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge + that controls the OXPCIe952 controller first. + +config OXFORD_OXPCIE_BRIDGE_SUBORDINATE + hex "OXPCIe's PCIe bridge subordinate bus" + default 0x3 + depends on DRIVERS_OXFORD_OXPCIE + help + While coreboot is executing code from ROM, the coreboot resource + allocator has not been running yet. Hence PCI devices living behind + a bridge are not yet visible to the system. In order to use an + OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge + that controls the OXPCIe952 controller first. + +config OXFORD_OXPCIE_BASE_ADDRESS + hex "Base address for rom stage console" + default 0xe0400000 + depends on DRIVERS_OXFORD_OXPCIE + help + While coreboot is executing code from ROM, the coreboot resource + allocator has not been running yet. Hence PCI devices living behind + a bridge are not yet visible to the system. In order to use an + OXPCIe952 based PCIe card, coreboot has to set up a temporary address + for the OXPCIe952 controller. + Added: trunk/src/drivers/oxford/oxpcie/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/drivers/oxford/oxpcie/Makefile.inc Wed Apr 27 01:47:04 2011 (r6544) @@ -0,0 +1,3 @@ +driver-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie.c + +romstage-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie_early.c Added: trunk/src/drivers/oxford/oxpcie/oxpcie.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/drivers/oxford/oxpcie/oxpcie.c Wed Apr 27 01:47:04 2011 (r6544) @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <console/console.h> +#include <arch/io.h> +#include <uart8250.h> + +static void oxford_oxpcie_enable(device_t dev) +{ + printk(BIOS_DEBUG, "Initializing Oxford OXPCIe952\n"); + + struct resource *res = find_resource(dev, 0x10); + if (!res) { + printk(BIOS_WARNING, "OXPCIe952: No UART resource found.\n"); + return; + } + + printk(BIOS_DEBUG, "OXPCIe952: Class=%x Revision ID=%x\n", + (read32(res->base) >> 8), (read32(res->base) & 0xff)); + printk(BIOS_DEBUG, "OXPCIe952: %d UARTs detected.\n", + (read32(res->base + 4) & 3)); +} + +static struct device_operations oxford_oxpcie_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = oxford_oxpcie_enable, + .scan_bus = 0, +}; + +static const struct pci_driver oxford_oxpcie_driver __pci_driver = { + .ops = &oxford_oxpcie_ops, + .vendor = 0x1415, + .device = 0xc158, +}; Added: trunk/src/drivers/oxford/oxpcie/oxpcie_early.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/drivers/oxford/oxpcie/oxpcie_early.c Wed Apr 27 01:47:04 2011 (r6544) @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <uart8250.h> +#include <device/pci_def.h> + +#define PCIE_BRIDGE \ + PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_BUS, \ + CONFIG_OXFORD_OXPCIE_BRIDGE_DEVICE, \ + CONFIG_OXFORD_OXPCIE_BRIDGE_FUNCTION) + +#define OXPCIE_DEVICE \ + PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 0) + +void oxford_init(void) +{ + u16 reg16; + + /* First we reset the secondary bus */ + reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL); + reg16 |= (1 << 6); /* SRESET */ + pci_write_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL, reg16); + + /* Assume we don't have to wait here forever */ + + /* Read back and clear reset bit. */ + reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL); + reg16 &= ~(1 << 6); /* SRESET */ + pci_write_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL, reg16); + + /* Set up subordinate bus number */ + pci_write_config8(PCIE_BRIDGE, PCI_SECONDARY_BUS, 0x00); + pci_write_config8(PCIE_BRIDGE, PCI_SUBORDINATE_BUS, 0x00); + pci_write_config8(PCIE_BRIDGE, PCI_SECONDARY_BUS, + CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE); + pci_write_config8(PCIE_BRIDGE, PCI_SUBORDINATE_BUS, + CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE); + + /* Memory window for the OXPCIe952 card */ + // XXX is the calculation of base and limit corect? + pci_write_config32(PCIE_BRIDGE, PCI_MEMORY_BASE, + ((CONFIG_OXFORD_OXPCIE_BASE_ADDRESS & 0xffff0000) | + ((CONFIG_OXFORD_OXPCIE_BASE_ADDRESS >> 16) & 0xff00))); + + /* Enable memory access through bridge */ + reg16 = pci_read_config16(PCIE_BRIDGE, PCI_COMMAND); + reg16 |= PCI_COMMAND_MEMORY; + pci_write_config16(PCIE_BRIDGE, PCI_COMMAND, reg16); + + // FIXME Add a timeout or this will hang forever if + // no device is in the slot. + u32 id = 0; + while ((id == 0) || (id == 0xffffffff)) + id = pci_read_config32(OXPCIE_DEVICE, PCI_VENDOR_ID); + + /* Setup base address on device */ + pci_write_config32(OXPCIE_DEVICE, PCI_BASE_ADDRESS_0, + CONFIG_OXFORD_OXPCIE_BASE_ADDRESS); + + /* Enable memory on device */ + reg16 = pci_read_config16(OXPCIE_DEVICE, PCI_COMMAND); + reg16 |= PCI_COMMAND_MEMORY; + pci_write_config16(OXPCIE_DEVICE, PCI_COMMAND, reg16); + + /* Now the UART initialization */ + u32 uart0_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; + + uart8250_mem_init(uart0_base, (4000000 / CONFIG_TTYS0_BAUD)); +} + Modified: trunk/src/include/boot/coreboot_tables.h ============================================================================== --- trunk/src/include/boot/coreboot_tables.h Sat Apr 23 01:12:40 2011 (r6543) +++ trunk/src/include/boot/coreboot_tables.h Wed Apr 27 01:47:04 2011 (r6544) @@ -163,6 +163,7 @@ #define LB_TAG_CONSOLE_LOGBUF 3 #define LB_TAG_CONSOLE_SROM 4 // OBSOLETE #define LB_TAG_CONSOLE_EHCI 5 +#define LB_TAG_CONSOLE_SERIAL8250MEM 6 #define LB_TAG_FORWARD 0x0011 struct lb_forward { Modified: trunk/src/include/uart8250.h ============================================================================== --- trunk/src/include/uart8250.h Sat Apr 23 01:12:40 2011 (r6543) +++ trunk/src/include/uart8250.h Wed Apr 27 01:47:04 2011 (r6544) @@ -124,6 +124,7 @@ #define UART_MSR_DCTS 0x01 /* Delta CTS */ #define UART_SCR 0x07 +#define UART_SPR 0x07 #ifndef __ROMCC__ @@ -136,6 +137,17 @@ */ void uart8250_init(unsigned base_port, unsigned divisor); void uart_init(void); + +/* and the same for memory mapped uarts */ +unsigned char uart8250_mem_rx_byte(unsigned base_port); +int uart8250_mem_can_rx_byte(unsigned base_port); +void uart8250_mem_tx_byte(unsigned base_port, unsigned char data); +void uart8250_mem_init(unsigned base_port, unsigned divisor); +u32 uart_mem_init(void); + +/* and special init for OXPCIe based cards */ +void oxford_init(void); + #endif #endif /* UART8250_H */ Modified: trunk/src/lib/Makefile.inc ============================================================================== --- trunk/src/lib/Makefile.inc Sat Apr 23 01:12:40 2011 (r6543) +++ trunk/src/lib/Makefile.inc Wed Apr 27 01:47:04 2011 (r6544) @@ -9,6 +9,7 @@ romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c romstage-$(CONFIG_HAVE_ACPI_RESUME) += cbmem.c romstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c +romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c romstage-$(CONFIG_CONSOLE_NE2K) += compute_ip_checksum.c romstage-$(CONFIG_USBDEBUG) += usbdebug.c @@ -29,6 +30,7 @@ ramstage-y += clog2.c ramstage-y += cbmem.c ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c +ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c ramstage-$(CONFIG_USBDEBUG) += usbdebug.c ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c @@ -36,5 +38,6 @@ smm-y += memcpy.c smm-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c +smm-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c $(obj)/lib/version.ramstage.o : $(obj)/build.h Added: trunk/src/lib/uart8250mem.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/lib/uart8250mem.c Wed Apr 27 01:47:04 2011 (r6544) @@ -0,0 +1,139 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Eric Biederman + * Copyright (C) 2006-2010 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <uart8250.h> +#include <pc80/mc146818rtc.h> +#if CONFIG_USE_OPTION_TABLE +#include "option_table.h" +#endif +#if !defined(__SMM__) && !defined(__PRE_RAM__) +#include <device/device.h> +#endif + +/* Should support 8250, 16450, 16550, 16550A type UARTs */ + +static inline int uart8250_mem_can_tx_byte(unsigned base_port) +{ + return read8(base_port + UART_LSR) & UART_MSR_DSR; +} + +static inline void uart8250_mem_wait_to_tx_byte(unsigned base_port) +{ + while(!uart8250_mem_can_tx_byte(base_port)) + ; +} + +static inline void uart8250_mem_wait_until_sent(unsigned base_port) +{ + while(!(read8(base_port + UART_LSR) & UART_LSR_TEMT)) + ; +} + +void uart8250_mem_tx_byte(unsigned base_port, unsigned char data) +{ + uart8250_mem_wait_to_tx_byte(base_port); + write8(base_port + UART_TBR, data); + /* Make certain the data clears the FIFOs */ + uart8250_mem_wait_until_sent(base_port); +} + +int uart8250_mem_can_rx_byte(unsigned base_port) +{ + return read8(base_port + UART_LSR) & UART_LSR_DR; +} + +unsigned char uart8250_mem_rx_byte(unsigned base_port) +{ + while(!uart8250_mem_can_rx_byte(base_port)) + ; + return read8(base_port + UART_RBR); +} + +void uart8250_mem_init(unsigned base_port, unsigned divisor) +{ + /* Disable interrupts */ + write8(base_port + UART_IER, 0x0); + /* Enable FIFOs */ + write8(base_port + UART_FCR, UART_FCR_FIFO_EN); + + /* Assert DTR and RTS so the other end is happy */ + write8(base_port + UART_MCR, UART_MCR_DTR | UART_MCR_RTS); + + /* DLAB on */ + write8(base_port + UART_LCR, UART_LCR_DLAB | CONFIG_TTYS0_LCS); + + /* Set Baud Rate Divisor. 12 ==> 115200 Baud */ + write8(base_port + UART_DLL, divisor & 0xFF); + write8(base_port + UART_DLM, (divisor >> 8) & 0xFF); + + /* Set to 3 for 8N1 */ + write8(base_port + UART_LCR, CONFIG_TTYS0_LCS); +} + +u32 uart_mem_init(void) +{ + unsigned uart_baud = CONFIG_TTYS0_BAUD; + u32 uart_bar = 0; + unsigned div; + + /* find out the correct baud rate */ +#if !defined(__SMM__) && CONFIG_USE_OPTION_TABLE + static const unsigned baud[8] = { 115200, 57600, 38400, 19200, 9600, 4800, 2400, 1200 }; + unsigned b_index = 0; +#if defined(__PRE_RAM__) + b_index = read_option(CMOS_VSTART_baud_rate, CMOS_VLEN_baud_rate, 0); + b_index &= 7; + uart_baud = baud[b_index]; +#else + if (get_option(&b_index, "baud_rate") == 0) { + uart_baud = baud[b_index]; + } +#endif +#endif + + /* Now find the UART base address and calculate the divisor */ +#if CONFIG_DRIVERS_OXFORD_OXPCIE + +#if defined(MORE_TESTING) && !defined(__SMM__) && !defined(__PRE_RAM__) + device_t dev = dev_find_device(0x1415, 0xc158, NULL); + + if (dev) { + struct resource *res = find_resource(dev, 0x10); + + if (res) { + uart_bar = res->base + 0x1000; // for 1st UART + // uart_bar = res->base + 0x2000; // for 2nd UART + } + } + + if (!uart_bar) +#endif + uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; // 1st UART + // uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x2000; // 2nd UART + + div = 4000000 / uart_baud; +#endif + + if (uart_bar) + uart8250_mem_init(uart_bar, div); + + return uart_bar; +}

1 0

Welcome coreboot 2011 GSoC students
by Marc Jones 26 Apr '11

26 Apr '11

Say hi to the four GSoC students working with coreboot this summer. Hamo, Leandro, Stefan, and Tadas. You should be seeing more from them on the mail list and in IRC. Please make them welcome. They will also be keeping us all up to date on their progress on http://blogs.coreboot.org. Marc -- http://se-eng.com

3 2

[PATCH] coreboot support for memory mapped UARTs (v2)
by Stefan Reinauer 26 Apr '11

26 Apr '11

Revised version. See patch.

2 1

Issues porting the Iwave raibowG6
by Den nis 26 Apr '11

26 Apr '11

Hi, Im trying to "port" the iwave RainbowG6 coreboot code to a platform with the same CPU (Intel Atom Z530) and chipset (Intel US15W), 1GB RAM (2 ranks, 1024 Mbits device density, x16 device width) and a winbond WPCN381U superio chip. Meanwhile the basic functionalities of Coreboot seems to works well. But when i jump to my payload everthing become quiet. I suspect that something went wrong with the tables. I have include the build process and the serial port output (debug level = SPEW). I hope someone has a tip so I can go further. Many thanks in advance! Dennis

2 1

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coreboot April 2011