coreboot April 2011

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[commit] r6539 - in trunk/src: console lib
by repository service 21 Apr '11

21 Apr '11

Author: stepan Date: Fri Apr 22 04:17:26 2011 New Revision: 6539 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6539 Log: Get rid of all but one (I/O mapped) UART init functions. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Modified: trunk/src/console/uart8250_console.c trunk/src/lib/uart8250.c Modified: trunk/src/console/uart8250_console.c ============================================================================== --- trunk/src/console/uart8250_console.c Fri Apr 22 03:45:11 2011 (r6538) +++ trunk/src/console/uart8250_console.c Fri Apr 22 04:17:26 2011 (r6539) @@ -23,20 +23,7 @@ static void ttyS0_init(void) { - static const unsigned char div[8] = { 1, 2, 3, 6, 12, 24, 48, 96 }; - int b_index = 0; - /* TODO the divisor calculation is hard coded to standard UARTs. Some - * UARTs won't work with these values. This should be a property of the - * UART used, worst case a Kconfig variable. For now live with hard - * codes as the only devices that might be different are the iWave - * iRainbowG6 and the OXPCIe952 card (and the latter is memory mapped) - */ - unsigned int divisor = 115200 / CONFIG_TTYS0_BAUD; - - if (get_option(&b_index, "baud_rate") == 0) { - divisor = div[b_index]; - } - uart8250_init(CONFIG_TTYS0_BASE, divisor); + uart_init(); } static void ttyS0_tx_byte(unsigned char data) Modified: trunk/src/lib/uart8250.c ============================================================================== --- trunk/src/lib/uart8250.c Fri Apr 22 03:45:11 2011 (r6538) +++ trunk/src/lib/uart8250.c Fri Apr 22 04:17:26 2011 (r6539) @@ -85,7 +85,6 @@ outb(CONFIG_TTYS0_LCS, base_port + UART_LCR); } -#if defined(__PRE_RAM__) || defined(__SMM__) void uart_init(void) { /* TODO the divisor calculation is hard coded to standard UARTs. Some @@ -94,16 +93,21 @@ * codes as the only devices that might be different are the iWave * iRainbowG6 and the OXPCIe952 card (and the latter is memory mapped) */ -#if CONFIG_USE_OPTION_TABLE && !defined(__SMM__) - static const unsigned char divisor[] = { 1, 2, 3, 6, 12, 24, 48, 96 }; - unsigned ttys0_div, ttys0_index; - ttys0_index = read_option(CMOS_VSTART_baud_rate, CMOS_VLEN_baud_rate, 0); - ttys0_index &= 7; - ttys0_div = divisor[ttys0_index]; + unsigned int div = (115200 / CONFIG_TTYS0_BAUD); - uart8250_init(CONFIG_TTYS0_BASE, ttys0_div); +#if !defined(__SMM__) && CONFIG_USE_OPTION_TABLE + static const unsigned char divisor[8] = { 1, 2, 3, 6, 12, 24, 48, 96 }; + unsigned b_index = 0; +#if defined(__PRE_RAM__) + b_index = read_option(CMOS_VSTART_baud_rate, CMOS_VLEN_baud_rate, 0); + b_index &= 7; + div = divisor[ttys0_index]; #else - uart8250_init(CONFIG_TTYS0_BASE, (115200 / CONFIG_TTYS0_BAUD)); + if (get_option(&b_index, "baud_rate") == 0) { + div = divisor[b_index]; + } #endif -} #endif + + uart8250_init(CONFIG_TTYS0_BASE, div); +}

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[PATCH]
by Stefan Reinauer 21 Apr '11

21 Apr '11

See patch

2 2

[commit] r6538 - in trunk/src: console include lib mainboard/iwave/iWRainbowG6
by repository service 21 Apr '11

21 Apr '11

Author: stepan Date: Fri Apr 22 03:45:11 2011 New Revision: 6538 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6538 Log: The UART divider should be calculated based on the base frequency and baudrate, not hardcoded in addition to that. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/console/uart8250_console.c trunk/src/include/uart8250.h trunk/src/lib/uart8250.c trunk/src/mainboard/iwave/iWRainbowG6/Kconfig Modified: trunk/src/console/uart8250_console.c ============================================================================== --- trunk/src/console/uart8250_console.c Thu Apr 21 23:26:58 2011 (r6537) +++ trunk/src/console/uart8250_console.c Fri Apr 22 03:45:11 2011 (r6538) @@ -25,7 +25,13 @@ { static const unsigned char div[8] = { 1, 2, 3, 6, 12, 24, 48, 96 }; int b_index = 0; - unsigned int divisor = CONFIG_TTYS0_DIV; + /* TODO the divisor calculation is hard coded to standard UARTs. Some + * UARTs won't work with these values. This should be a property of the + * UART used, worst case a Kconfig variable. For now live with hard + * codes as the only devices that might be different are the iWave + * iRainbowG6 and the OXPCIe952 card (and the latter is memory mapped) + */ + unsigned int divisor = 115200 / CONFIG_TTYS0_BAUD; if (get_option(&b_index, "baud_rate") == 0) { divisor = div[b_index]; Modified: trunk/src/include/uart8250.h ============================================================================== --- trunk/src/include/uart8250.h Thu Apr 21 23:26:58 2011 (r6537) +++ trunk/src/include/uart8250.h Fri Apr 22 03:45:11 2011 (r6538) @@ -28,13 +28,9 @@ #ifndef CONFIG_TTYS0_BAUD #define CONFIG_TTYS0_BAUD 115200 #endif - -#ifndef CONFIG_TTYS0_DIV #if ((115200%CONFIG_TTYS0_BAUD) != 0) #error Bad ttys0 baud rate #endif -#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) -#endif /* Line Control Settings */ #ifndef CONFIG_TTYS0_LCS Modified: trunk/src/lib/uart8250.c ============================================================================== --- trunk/src/lib/uart8250.c Thu Apr 21 23:26:58 2011 (r6537) +++ trunk/src/lib/uart8250.c Fri Apr 22 03:45:11 2011 (r6538) @@ -88,6 +88,12 @@ #if defined(__PRE_RAM__) || defined(__SMM__) void uart_init(void) { + /* TODO the divisor calculation is hard coded to standard UARTs. Some + * UARTs won't work with these values. This should be a property of the + * UART used, worst case a Kconfig variable. For now live with hard + * codes as the only devices that might be different are the iWave + * iRainbowG6 and the OXPCIe952 card (and the latter is memory mapped) + */ #if CONFIG_USE_OPTION_TABLE && !defined(__SMM__) static const unsigned char divisor[] = { 1, 2, 3, 6, 12, 24, 48, 96 }; unsigned ttys0_div, ttys0_index; @@ -97,7 +103,7 @@ uart8250_init(CONFIG_TTYS0_BASE, ttys0_div); #else - uart8250_init(CONFIG_TTYS0_BASE, CONFIG_TTYS0_DIV); + uart8250_init(CONFIG_TTYS0_BASE, (115200 / CONFIG_TTYS0_BAUD)); #endif } #endif Modified: trunk/src/mainboard/iwave/iWRainbowG6/Kconfig ============================================================================== --- trunk/src/mainboard/iwave/iWRainbowG6/Kconfig Thu Apr 21 23:26:58 2011 (r6537) +++ trunk/src/mainboard/iwave/iWRainbowG6/Kconfig Fri Apr 22 03:45:11 2011 (r6538) @@ -37,9 +37,7 @@ int default 10 -# WTF, is this 19200? -config TTYS0_DIV - int - default 6 +# This mainboard might have a higher clocked UART or might not be able to run +# serial output at 115200 baud endif

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what happened when power button is pressed and a machine begins to shutdown?
by Jiang Wang 21 Apr '11

21 Apr '11

Hi I am trying to understand how the power button pressing event triggers the machine to shutdown. From the ACPI spec 4.7.2.2.1, it mentioned that the power button can be implemented either as a fixed hardware or a generic hardware programming method. So, for ASUS M2V-MX SE, how the power button is implemented? I tested coreboot with Linux on M2V-MX SE. When the Linux stops at login window, pressing the power button can lead the machine to shutdown. So what are the concrete steps between the power button is pressed to the Linux begins to shutdown? Is it a AML code get executed? (but I read the M2V-MX SE dsdt source file, and didn't find anything related to power button.) Will the event go to the BIOS first? Then go to the OS? Or it is completely handled by OS? The problem I try to solve is to find out whether BIOS can get the button event before the OS and do something without OS. Also, for the power button override event, it is completely handled by hardware, right? Is it possible to trigger this event from the BIOS? My questions may seem to be a little bit strange. Feel free to let me know, If you still not clear about the questions. Thanks. Regards, Jiang

2 1

[commit] r6537 - in trunk/src: arch/x86 boot cpu/amd/model_gx2 cpu/amd/model_lx southbridge/amd/rs780
by repository service 21 Apr '11

21 Apr '11

Author: stepan Date: Thu Apr 21 23:26:58 2011 New Revision: 6537 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6537 Log: more ifdef -> if fixes. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Modified: trunk/src/arch/x86/Kconfig trunk/src/boot/selfboot.c trunk/src/cpu/amd/model_gx2/syspreinit.c trunk/src/cpu/amd/model_lx/syspreinit.c trunk/src/southbridge/amd/rs780/early_setup.c Modified: trunk/src/arch/x86/Kconfig ============================================================================== --- trunk/src/arch/x86/Kconfig Thu Apr 21 22:45:45 2011 (r6536) +++ trunk/src/arch/x86/Kconfig Thu Apr 21 23:26:58 2011 (r6537) @@ -91,4 +91,12 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT string +config BIG_ENDIAN + bool + default n + +config LITTLE_ENDIAN + bool + default !BIG_ENDIAN + endmenu Modified: trunk/src/boot/selfboot.c ============================================================================== --- trunk/src/boot/selfboot.c Thu Apr 21 22:45:45 2011 (r6536) +++ trunk/src/boot/selfboot.c Thu Apr 21 23:26:58 2011 (r6537) @@ -30,7 +30,7 @@ #include <cbfs.h> #include <lib.h> -#ifndef CONFIG_BIG_ENDIAN +#if !CONFIG_BIG_ENDIAN #define ntohl(x) ( ((x&0xff)<<24) | ((x&0xff00)<<8) | \ ((x&0xff0000) >> 8) | ((x&0xff000000) >> 24) ) #else @@ -477,7 +477,7 @@ return 0; break; } -#if CONFIG_COMPRESSED_PAYLOAD_NRV2B==1 +#if CONFIG_COMPRESSED_PAYLOAD_NRV2B case CBFS_COMPRESS_NRV2B: { printk(BIOS_DEBUG, "using NRV2B\n"); unsigned long unrv2b(u8 *src, u8 *dst, unsigned long *ilen_p); Modified: trunk/src/cpu/amd/model_gx2/syspreinit.c ============================================================================== --- trunk/src/cpu/amd/model_gx2/syspreinit.c Thu Apr 21 22:45:45 2011 (r6536) +++ trunk/src/cpu/amd/model_gx2/syspreinit.c Thu Apr 21 23:26:58 2011 (r6537) @@ -13,7 +13,7 @@ void SystemPreInit(void) { /* they want a jump ... */ -#ifndef CONFIG_CACHE_AS_RAM +#if !CONFIG_CACHE_AS_RAM __asm__ __volatile__("jmp .+2\ninvd\njmp .+2\n"); #endif StartTimer1(); Modified: trunk/src/cpu/amd/model_lx/syspreinit.c ============================================================================== --- trunk/src/cpu/amd/model_lx/syspreinit.c Thu Apr 21 22:45:45 2011 (r6536) +++ trunk/src/cpu/amd/model_lx/syspreinit.c Thu Apr 21 23:26:58 2011 (r6537) @@ -39,7 +39,7 @@ { /* they want a jump ... */ -#ifndef CONFIG_CACHE_AS_RAM +#if !CONFIG_CACHE_AS_RAM __asm__ __volatile__("jmp .+2\ninvd\njmp .+2\n"); #endif StartTimer1(); Modified: trunk/src/southbridge/amd/rs780/early_setup.c ============================================================================== --- trunk/src/southbridge/amd/rs780/early_setup.c Thu Apr 21 22:45:45 2011 (r6536) +++ trunk/src/southbridge/amd/rs780/early_setup.c Thu Apr 21 23:26:58 2011 (r6537) @@ -17,10 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef CONFIG_NORTHBRIDGE_AMD_AMDFAM10 -#define CONFIG_NORTHBRIDGE_AMD_AMDFAM10 0 -#endif - #include "rev.h" #define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */

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[commit] r6536 - in trunk/src: arch/x86/lib console cpu/amd/car cpu/intel/car cpu/intel/model_106cx cpu/intel/model_6ex cpu/intel/model_6fx cpu/via/car devices/oprom devices/oprom/yabel devices/opr...
by repository service 21 Apr '11

21 Apr '11

Author: stepan Date: Thu Apr 21 22:45:45 2011 New Revision: 6536 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6536 Log: more ifdef -> if fixes Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Modified: trunk/src/arch/x86/lib/exception.c trunk/src/arch/x86/lib/ioapic.c trunk/src/console/post.c trunk/src/cpu/amd/car/cache_as_ram.inc trunk/src/cpu/intel/car/cache_as_ram.inc trunk/src/cpu/intel/model_106cx/cache_as_ram.inc trunk/src/cpu/intel/model_6ex/cache_as_ram.inc trunk/src/cpu/intel/model_6fx/cache_as_ram.inc trunk/src/cpu/via/car/cache_as_ram.inc trunk/src/devices/oprom/x86.c trunk/src/devices/oprom/yabel/biosemu.c trunk/src/devices/oprom/yabel/compat/functions.c trunk/src/devices/oprom/yabel/debug.h trunk/src/devices/oprom/yabel/device.h trunk/src/include/cpu/cpu.h trunk/src/include/cpu/x86/mtrr.h trunk/src/include/lib.h trunk/src/lib/fallback_boot.c trunk/src/northbridge/amd/amdk8/raminit_f.c trunk/src/northbridge/via/cn700/raminit.c trunk/src/northbridge/via/vx800/early_smbus.c trunk/src/pc80/i8254.c trunk/src/southbridge/amd/sb700/early_setup.c trunk/src/southbridge/amd/sb700/lpc.c trunk/src/southbridge/amd/sb700/sata.c Modified: trunk/src/arch/x86/lib/exception.c ============================================================================== --- trunk/src/arch/x86/lib/exception.c Thu Apr 21 22:24:43 2011 (r6535) +++ trunk/src/arch/x86/lib/exception.c Thu Apr 21 22:45:45 2011 (r6536) @@ -1,7 +1,7 @@ #include <console/console.h> #include <string.h> -#if defined(CONFIG_GDB_STUB) && CONFIG_GDB_STUB == 1 +#if CONFIG_GDB_STUB /* BUFMAX defines the maximum number of characters in inbound/outbound buffers. * At least NUM_REGBYTES*2 are needed for register packets Modified: trunk/src/arch/x86/lib/ioapic.c ============================================================================== --- trunk/src/arch/x86/lib/ioapic.c Thu Apr 21 22:24:43 2011 (r6535) +++ trunk/src/arch/x86/lib/ioapic.c Thu Apr 21 22:45:45 2011 (r6536) @@ -91,7 +91,7 @@ // XXX this decision should probably be made elsewhere, and // it's the C3, not the EPIA this depends on. -#if defined(CONFIG_EPIA_VT8237R_INIT) && CONFIG_EPIA_VT8237R_INIT +#if CONFIG_EPIA_VT8237R_INIT #define IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS #else #define IOAPIC_INTERRUPTS_ON_FSB Modified: trunk/src/console/post.c ============================================================================== --- trunk/src/console/post.c Thu Apr 21 22:24:43 2011 (r6535) +++ trunk/src/console/post.c Thu Apr 21 22:45:45 2011 (r6536) @@ -26,8 +26,8 @@ void post_code(uint8_t value) { -#if !defined(CONFIG_NO_POST) || CONFIG_NO_POST==0 -#if CONFIG_CONSOLE_POST==1 +#if !CONFIG_NO_POST +#if CONFIG_CONSOLE_POST print_emerg("POST: 0x"); print_emerg_hex8(value); print_emerg("\n"); Modified: trunk/src/cpu/amd/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/amd/car/cache_as_ram.inc Thu Apr 21 22:24:43 2011 (r6535) +++ trunk/src/cpu/amd/car/cache_as_ram.inc Thu Apr 21 22:45:45 2011 (r6536) @@ -281,7 +281,7 @@ #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) -#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK +#if CONFIG_TINY_BOOTBLOCK #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE #else #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE Modified: trunk/src/cpu/intel/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/car/cache_as_ram.inc Thu Apr 21 22:24:43 2011 (r6535) +++ trunk/src/cpu/intel/car/cache_as_ram.inc Thu Apr 21 22:45:45 2011 (r6536) @@ -231,7 +231,7 @@ #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) -#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK +#if CONFIG_TINY_BOOTBLOCK #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE #else #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE Modified: trunk/src/cpu/intel/model_106cx/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_106cx/cache_as_ram.inc Thu Apr 21 22:24:43 2011 (r6535) +++ trunk/src/cpu/intel/model_106cx/cache_as_ram.inc Thu Apr 21 22:45:45 2011 (r6536) @@ -102,7 +102,7 @@ /* Enable cache for our code in Flash because we do XIP here */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx -#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK +#if CONFIG_TINY_BOOTBLOCK #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE #else #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE @@ -128,7 +128,7 @@ movl %eax, %cr0 /* Set up the stack pointer. */ -#if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1) +#if CONFIG_USBDEBUG /* Leave some space for the struct ehci_debug_info. */ movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax #else Modified: trunk/src/cpu/intel/model_6ex/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_6ex/cache_as_ram.inc Thu Apr 21 22:24:43 2011 (r6535) +++ trunk/src/cpu/intel/model_6ex/cache_as_ram.inc Thu Apr 21 22:45:45 2011 (r6536) @@ -102,7 +102,7 @@ /* Enable cache for our code in Flash because we do XIP here */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx -#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK +#if CONFIG_TINY_BOOTBLOCK #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE #else #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE @@ -128,7 +128,7 @@ movl %eax, %cr0 /* Set up the stack pointer. */ -#if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1) +#if CONFIG_USBDEBUG /* Leave some space for the struct ehci_debug_info. */ movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax #else Modified: trunk/src/cpu/intel/model_6fx/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_6fx/cache_as_ram.inc Thu Apr 21 22:24:43 2011 (r6535) +++ trunk/src/cpu/intel/model_6fx/cache_as_ram.inc Thu Apr 21 22:45:45 2011 (r6536) @@ -109,7 +109,7 @@ /* Enable cache for our code in Flash because we do XIP here */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx -#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK +#if CONFIG_TINY_BOOTBLOCK #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE #else #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE @@ -135,7 +135,7 @@ movl %eax, %cr0 /* Set up the stack pointer. */ -#if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1) +#if CONFIG_USBDEBUG /* Leave some space for the struct ehci_debug_info. */ movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax #else Modified: trunk/src/cpu/via/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/via/car/cache_as_ram.inc Thu Apr 21 22:24:43 2011 (r6535) +++ trunk/src/cpu/via/car/cache_as_ram.inc Thu Apr 21 22:45:45 2011 (r6536) @@ -110,7 +110,7 @@ movl $(~(CacheSize - 1) | MTRRphysMaskValid), %eax wrmsr -#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK +#if CONFIG_TINY_BOOTBLOCK #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE #else #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE Modified: trunk/src/devices/oprom/x86.c ============================================================================== --- trunk/src/devices/oprom/x86.c Thu Apr 21 22:24:43 2011 (r6535) +++ trunk/src/devices/oprom/x86.c Thu Apr 21 22:45:45 2011 (r6536) @@ -296,7 +296,7 @@ printk(BIOS_DEBUG, "... Option ROM returned.\n"); } -#if defined(CONFIG_GEODE_VSA) && CONFIG_GEODE_VSA +#if CONFIG_GEODE_VSA #include <cpu/amd/lxdef.h> #include <cpu/amd/vr.h> #include <cbfs.h> Modified: trunk/src/devices/oprom/yabel/biosemu.c ============================================================================== --- trunk/src/devices/oprom/yabel/biosemu.c Thu Apr 21 22:24:43 2011 (r6535) +++ trunk/src/devices/oprom/yabel/biosemu.c Thu Apr 21 22:45:45 2011 (r6536) @@ -58,37 +58,37 @@ int i = 0; #if CONFIG_X86EMU_DEBUG debug_flags = 0; -#if defined(CONFIG_X86EMU_DEBUG_JMP) && CONFIG_X86EMU_DEBUG_JMP +#if CONFIG_X86EMU_DEBUG_JMP debug_flags |= DEBUG_JMP; #endif -#if defined(CONFIG_X86EMU_DEBUG_TRACE) && CONFIG_X86EMU_DEBUG_TRACE +#if CONFIG_X86EMU_DEBUG_TRACE debug_flags |= DEBUG_TRACE_X86EMU; #endif -#if defined(CONFIG_X86EMU_DEBUG_PNP) && CONFIG_X86EMU_DEBUG_PNP +#if CONFIG_X86EMU_DEBUG_PNP debug_flags |= DEBUG_PNP; #endif -#if defined(CONFIG_X86EMU_DEBUG_DISK) && CONFIG_X86EMU_DEBUG_DISK +#if CONFIG_X86EMU_DEBUG_DISK debug_flags |= DEBUG_DISK; #endif -#if defined(CONFIG_X86EMU_DEBUG_PMM) && CONFIG_X86EMU_DEBUG_PMM +#if CONFIG_X86EMU_DEBUG_PMM debug_flags |= DEBUG_PMM; #endif -#if defined(CONFIG_X86EMU_DEBUG_VBE) && CONFIG_X86EMU_DEBUG_VBE +#if CONFIG_X86EMU_DEBUG_VBE debug_flags |= DEBUG_VBE; #endif -#if defined(CONFIG_X86EMU_DEBUG_INT10) && CONFIG_X86EMU_DEBUG_INT10 +#if CONFIG_X86EMU_DEBUG_INT10 debug_flags |= DEBUG_PRINT_INT10; #endif -#if defined(CONFIG_X86EMU_DEBUG_INTERRUPTS) && CONFIG_X86EMU_DEBUG_INTERRUPTS +#if CONFIG_X86EMU_DEBUG_INTERRUPTS debug_flags |= DEBUG_INTR; #endif -#if defined(CONFIG_X86EMU_DEBUG_CHECK_VMEM_ACCESS) && CONFIG_X86EMU_DEBUG_CHECK_VMEM_ACCESS +#if CONFIG_X86EMU_DEBUG_CHECK_VMEM_ACCESS debug_flags |= DEBUG_CHECK_VMEM_ACCESS; #endif -#if defined(CONFIG_X86EMU_DEBUG_MEM) && CONFIG_X86EMU_DEBUG_MEM +#if CONFIG_X86EMU_DEBUG_MEM debug_flags |= DEBUG_MEM; #endif -#if defined(CONFIG_X86EMU_DEBUG_IO) && CONFIG_X86EMU_DEBUG_IO +#if CONFIG_X86EMU_DEBUG_IO debug_flags |= DEBUG_IO; #endif @@ -309,7 +309,7 @@ * some boot device status in AX (see PNP BIOS Spec Section 3.3 */ DEBUG_PRINTF_CS_IP("Option ROM Exit Status: %04x\n", M.x86.R_AX); -#if defined(CONFIG_X86EMU_DEBUG) && CONFIG_X86EMU_DEBUG +#if CONFIG_X86EMU_DEBUG DEBUG_PRINTF("Exit Status Decode:\n"); if (M.x86.R_AX & 0x100) { // bit 8 DEBUG_PRINTF Modified: trunk/src/devices/oprom/yabel/compat/functions.c ============================================================================== --- trunk/src/devices/oprom/yabel/compat/functions.c Thu Apr 21 22:24:43 2011 (r6535) +++ trunk/src/devices/oprom/yabel/compat/functions.c Thu Apr 21 22:45:45 2011 (r6536) @@ -23,8 +23,8 @@ #define VMEM_SIZE (1024 * 1024) /* 1 MB */ -#if !defined(CONFIG_YABEL_DIRECTHW) || (!CONFIG_YABEL_DIRECTHW) -#ifdef CONFIG_YABEL_VIRTMEM_LOCATION +#if !CONFIG_YABEL_DIRECTHW +#if CONFIG_YABEL_VIRTMEM_LOCATION u8* vmem = (u8 *) CONFIG_YABEL_VIRTMEM_LOCATION; #else u8* vmem = (u8 *) (16*1024*1024); /* default to 16MB */ Modified: trunk/src/devices/oprom/yabel/debug.h ============================================================================== --- trunk/src/devices/oprom/yabel/debug.h Thu Apr 21 22:24:43 2011 (r6535) +++ trunk/src/devices/oprom/yabel/debug.h Thu Apr 21 22:45:45 2011 (r6536) @@ -66,7 +66,7 @@ // set to enable tracing of JMPs in x86emu #define DEBUG_JMP 0x2000 -#if defined(CONFIG_X86EMU_DEBUG) && CONFIG_X86EMU_DEBUG +#if CONFIG_X86EMU_DEBUG #define CHECK_DBG(_flag) if (debug_flags & _flag) Modified: trunk/src/devices/oprom/yabel/device.h ============================================================================== --- trunk/src/devices/oprom/yabel/device.h Thu Apr 21 22:24:43 2011 (r6535) +++ trunk/src/devices/oprom/yabel/device.h Thu Apr 21 22:45:45 2011 (r6536) @@ -62,7 +62,7 @@ typedef struct { u8 bus; u8 devfn; -#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL struct device* dev; #else u64 puid; @@ -84,7 +84,7 @@ } biosemu_device_t; typedef struct { -#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL unsigned long info; #else u8 info; Modified: trunk/src/include/cpu/cpu.h ============================================================================== --- trunk/src/include/cpu/cpu.h Thu Apr 21 22:24:43 2011 (r6535) +++ trunk/src/include/cpu/cpu.h Thu Apr 21 22:45:45 2011 (r6536) @@ -9,7 +9,7 @@ void initialize_cpus(struct bus *cpu_bus); void secondary_cpu_init(void); -#if !defined(CONFIG_WAIT_BEFORE_CPUS_INIT) || CONFIG_WAIT_BEFORE_CPUS_INIT==0 +#if !CONFIG_WAIT_BEFORE_CPUS_INIT #define cpus_ready_for_init() do {} while(0) #else void cpus_ready_for_init(void); Modified: trunk/src/include/cpu/x86/mtrr.h ============================================================================== --- trunk/src/include/cpu/x86/mtrr.h Thu Apr 21 22:24:43 2011 (r6535) +++ trunk/src/include/cpu/x86/mtrr.h Thu Apr 21 22:45:45 2011 (r6536) @@ -69,7 +69,7 @@ #if !defined (__ASSEMBLER__) #if defined(CONFIG_XIP_ROM_SIZE) -# if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK +# if CONFIG_TINY_BOOTBLOCK extern unsigned long AUTO_XIP_ROM_BASE; # define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE # else Modified: trunk/src/include/lib.h ============================================================================== --- trunk/src/include/lib.h Thu Apr 21 22:24:43 2011 (r6535) +++ trunk/src/include/lib.h Thu Apr 21 22:45:45 2011 (r6536) @@ -40,7 +40,7 @@ void quick_ram_check(void); /* Defined in romstage.c */ -#if defined(CONFIG_CPU_AMD_LX) && CONFIG_CPU_AMD_LX +#if CONFIG_CPU_AMD_LX void cache_as_ram_main(void); #else void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); Modified: trunk/src/lib/fallback_boot.c ============================================================================== --- trunk/src/lib/fallback_boot.c Thu Apr 21 22:24:43 2011 (r6535) +++ trunk/src/lib/fallback_boot.c Thu Apr 21 22:45:45 2011 (r6536) @@ -28,7 +28,7 @@ void boot_successful(void) { -#if defined(CONFIG_BOOTSPLASH) && CONFIG_BOOTSPLASH && !CONFIG_COREBOOT_KEEP_FRAMEBUFFER +#if CONFIG_BOOTSPLASH && !CONFIG_COREBOOT_KEEP_FRAMEBUFFER void vbe_textmode_console(void); vbe_textmode_console(); Modified: trunk/src/northbridge/amd/amdk8/raminit_f.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit_f.c Thu Apr 21 22:24:43 2011 (r6535) +++ trunk/src/northbridge/amd/amdk8/raminit_f.c Thu Apr 21 22:45:45 2011 (r6536) @@ -1111,7 +1111,7 @@ if (read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) == 0) return 0; #else -#if !defined(CONFIG_INTERLEAVE_CHIP_SELECTS) || (CONFIG_INTERLEAVE_CHIP_SELECTS == 0) +#if !CONFIG_INTERLEAVE_CHIP_SELECTS return 0; #endif #endif @@ -2379,7 +2379,7 @@ dcl &= ~DCL_DimmEccEn; } #else // CMOS_VSTART_ECC_memory not defined -#if defined(CONFIG_ECC_MEMORY) && (CONFIG_ECC_MEMORY == 0) +#if !CONFIG_ECC_MEMORY dcl &= ~DCL_DimmEccEn; #endif #endif Modified: trunk/src/northbridge/via/cn700/raminit.c ============================================================================== --- trunk/src/northbridge/via/cn700/raminit.c Thu Apr 21 22:24:43 2011 (r6535) +++ trunk/src/northbridge/via/cn700/raminit.c Thu Apr 21 22:45:45 2011 (r6536) @@ -24,7 +24,7 @@ #include <delay.h> #include "cn700.h" -#ifdef CONFIG_DEBUG_RAM_SETUP +#if CONFIG_DEBUG_RAM_SETUP #define PRINT_DEBUG_MEM(x) print_debug(x) #define PRINT_DEBUG_MEM_HEX8(x) print_debug_hex8(x) #define PRINT_DEBUG_MEM_HEX16(x) print_debug_hex16(x) Modified: trunk/src/northbridge/via/vx800/early_smbus.c ============================================================================== --- trunk/src/northbridge/via/vx800/early_smbus.c Thu Apr 21 22:24:43 2011 (r6535) +++ trunk/src/northbridge/via/vx800/early_smbus.c Thu Apr 21 22:45:45 2011 (r6536) @@ -49,7 +49,7 @@ #define SMBUS_DELAY() outb(0x80, 0x80) -#ifdef CONFIG_DEBUG_SMBUS +#if CONFIG_DEBUG_SMBUS #define PRINT_DEBUG(x) print_debug(x) #define PRINT_DEBUG_HEX16(x) print_debug_hex16(x) #else Modified: trunk/src/pc80/i8254.c ============================================================================== --- trunk/src/pc80/i8254.c Thu Apr 21 22:24:43 2011 (r6535) +++ trunk/src/pc80/i8254.c Thu Apr 21 22:45:45 2011 (r6536) @@ -35,7 +35,7 @@ outb(0x12, TIMER1_PORT); } -#ifdef CONFIG_UDELAY_TIMER2 +#if CONFIG_UDELAY_TIMER2 static void load_timer2(unsigned int ticks) { /* Set up the timer gate, turn off the speaker */ Modified: trunk/src/southbridge/amd/sb700/early_setup.c ============================================================================== --- trunk/src/southbridge/amd/sb700/early_setup.c Thu Apr 21 22:24:43 2011 (r6535) +++ trunk/src/southbridge/amd/sb700/early_setup.c Thu Apr 21 22:45:45 2011 (r6536) @@ -149,7 +149,7 @@ reg32 |= 1 << 20; pci_write_config32(dev, 0x64, reg32); -#ifdef CONFIG_SOUTHBRIDGE_AMD_SP5100 +#if CONFIG_SOUTHBRIDGE_AMD_SP5100 post_code(0x66); dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ reg8 = pci_read_config8(dev, 0xBB); @@ -163,7 +163,7 @@ // XXX Serial port decode on LPC is hardcoded to 0x3f8 reg8 = pci_read_config8(dev, 0x44); reg8 |= 1 << 6; -#ifdef CONFIG_SOUTHBRIDGE_AMD_SP5100 +#if CONFIG_SOUTHBRIDGE_AMD_SP5100 #if CONFIG_TTYS0_BASE == 0x2f8 reg8 |= 1 << 7; #endif @@ -369,7 +369,7 @@ { device_t dev; u8 byte; -#ifdef CONFIG_SOUTHBRIDGE_AMD_SP5100 +#if CONFIG_SOUTHBRIDGE_AMD_SP5100 u32 dword; #endif @@ -505,7 +505,7 @@ /* Enable PCIB_DUAL_EN_UP will fix potential problem with PCI cards. */ pci_write_config8(dev, 0x50, 0x01); -#ifdef CONFIG_SOUTHBRIDGE_AMD_SP5100 +#if CONFIG_SOUTHBRIDGE_AMD_SP5100 /* SP5100 default SATA mode is RAID5 MODE */ dev = pci_locate_device(PCI_ID(0x1002, 0x4393), 0); /* Set SATA Operation Mode, Set to IDE mode */ Modified: trunk/src/southbridge/amd/sb700/lpc.c ============================================================================== --- trunk/src/southbridge/amd/sb700/lpc.c Thu Apr 21 22:24:43 2011 (r6535) +++ trunk/src/southbridge/amd/sb700/lpc.c Thu Apr 21 22:45:45 2011 (r6536) @@ -63,7 +63,7 @@ /* Disable LPC MSI Capability */ byte = pci_read_config8(dev, 0x78); byte &= ~(1 << 1); -#ifdef CONFIG_SOUTHBRIDGE_AMD_SP5100 +#if CONFIG_SOUTHBRIDGE_AMD_SP5100 /* Disable FlowContrl, Always service the request from Host * whenever there is a request from Host pending */ Modified: trunk/src/southbridge/amd/sb700/sata.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sata.c Thu Apr 21 22:24:43 2011 (r6535) +++ trunk/src/southbridge/amd/sb700/sata.c Thu Apr 21 22:45:45 2011 (r6536) @@ -190,7 +190,7 @@ byte |= 7 << 0; pci_write_config8(dev, 0x4, byte); -#ifdef CONFIG_SOUTHBRIDGE_AMD_SP5100 +#if CONFIG_SOUTHBRIDGE_AMD_SP5100 /* Master Latency Timer */ pci_write_config32(dev, 0xC, 0x00004000); #endif

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[commit] r6535 - in trunk/src: . arch/x86/boot arch/x86/include/arch devices devices/oprom/yabel include/cpu/x86 mainboard/kontron/986lcd-m northbridge/intel/i82830 northbridge/intel/i945 southbrid...
by repository service 21 Apr '11

21 Apr '11

Author: stepan Date: Thu Apr 21 22:24:43 2011 New Revision: 6535 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6535 Log: some ifdef --> if fixes Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Modified: trunk/src/Kconfig.deprecated_options trunk/src/arch/x86/boot/coreboot_table.c trunk/src/arch/x86/include/arch/interrupt.h trunk/src/devices/oprom/yabel/device.c trunk/src/devices/oprom/yabel/interrupt.c trunk/src/devices/oprom/yabel/io.c trunk/src/devices/oprom/yabel/mem.c trunk/src/devices/pci_rom.c trunk/src/devices/pciexp_device.c trunk/src/include/cpu/x86/mtrr.h trunk/src/mainboard/kontron/986lcd-m/mainboard.c trunk/src/northbridge/intel/i82830/smihandler.c trunk/src/northbridge/intel/i82830/vga.c trunk/src/northbridge/intel/i945/raminit.c trunk/src/southbridge/via/k8t890/early_car.c trunk/src/southbridge/via/vt8237r/lpc.c trunk/src/superio/ite/it8716f/it8716f.h trunk/src/superio/ite/it8716f/superio.c Modified: trunk/src/Kconfig.deprecated_options ============================================================================== --- trunk/src/Kconfig.deprecated_options Thu Apr 21 00:23:56 2011 (r6534) +++ trunk/src/Kconfig.deprecated_options Thu Apr 21 22:24:43 2011 (r6535) @@ -51,4 +51,14 @@ this option, then you can say N here to speed up boot time. Otherwise say Y. +# This was a config option for a long time, but it never showed up in Kconfig. +# It should go away and "tuning" should always be enabled when PCIe is there, +# or it should be more fine grained (ie. Enable PCIe ASPM) +config PCIE_TUNING + bool + default n + help + This variable enables certain PCIe optimizations. Right now it's + only ASPM and it's untested. + endmenu Modified: trunk/src/arch/x86/boot/coreboot_table.c ============================================================================== --- trunk/src/arch/x86/boot/coreboot_table.c Thu Apr 21 00:23:56 2011 (r6534) +++ trunk/src/arch/x86/boot/coreboot_table.c Thu Apr 21 22:24:43 2011 (r6535) @@ -145,7 +145,7 @@ static void lb_framebuffer(struct lb_header *header) { -#if defined(CONFIG_BOOTSPLASH) && CONFIG_BOOTSPLASH && CONFIG_COREBOOT_KEEP_FRAMEBUFFER +#if CONFIG_BOOTSPLASH && CONFIG_COREBOOT_KEEP_FRAMEBUFFER void fill_lb_framebuffer(struct lb_framebuffer *framebuffer); struct lb_framebuffer *framebuffer; Modified: trunk/src/arch/x86/include/arch/interrupt.h ============================================================================== --- trunk/src/arch/x86/include/arch/interrupt.h Thu Apr 21 00:23:56 2011 (r6534) +++ trunk/src/arch/x86/include/arch/interrupt.h Thu Apr 21 22:24:43 2011 (r6535) @@ -22,7 +22,7 @@ #include "registers.h" /* setup interrupt handlers for mainboard */ -#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE +#if CONFIG_PCI_OPTION_ROM_RUN_REALMODE extern void mainboard_interrupt_handlers(int intXX, void *intXX_func); #else static inline void mainboard_interrupt_handlers(int intXX, void *intXX_func) { } Modified: trunk/src/devices/oprom/yabel/device.c ============================================================================== --- trunk/src/devices/oprom/yabel/device.c Thu Apr 21 00:23:56 2011 (r6534) +++ trunk/src/devices/oprom/yabel/device.c Thu Apr 21 22:24:43 2011 (r6535) @@ -37,7 +37,7 @@ u64 size; } __attribute__ ((__packed__)) assigned_address_t; -#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL /* coreboot version */ static void @@ -110,7 +110,7 @@ } // store last entry index of translate_address_array taa_last_entry = taa_index - 1; -#if defined(CONFIG_X86EMU_DEBUG) && CONFIG_X86EMU_DEBUG +#if CONFIG_X86EMU_DEBUG //dump translate_address_array printf("translate_address_array: \n"); translate_address_t ta; @@ -194,7 +194,7 @@ } // store last entry index of translate_address_array taa_last_entry = taa_index - 1; -#if defined(CONFIG_X86EMU_DEBUG) && CONFIG_X86EMU_DEBUG +#if CONFIG_X86EMU_DEBUG //dump translate_address_array printf("translate_address_array: \n"); translate_address_t ta; @@ -226,7 +226,7 @@ translate_address_array[taa_index].address_offset = 0; } -#ifndef CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if !CONFIG_PCI_OPTION_ROM_RUN_YABEL // to simulate accesses to legacy VGA Memory (0xA0000-0xBFFFF) // we look for the first prefetchable memory BAR, if no prefetchable BAR found, // we use the first memory BAR @@ -288,7 +288,7 @@ { u32 pci_config_0; -#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL pci_config_0 = pci_read_config32(bios_device.dev, 0x0); #else pci_config_0 = @@ -350,7 +350,7 @@ memcpy(&pci_ds, (void *) (rom_base_addr + pci_ds_offset), sizeof(pci_ds)); clr_ci(); -#if defined(CONFIG_X86EMU_DEBUG) && CONFIG_X86EMU_DEBUG +#if CONFIG_X86EMU_DEBUG DEBUG_PRINTF("PCI Data Structure @%lx:\n", rom_base_addr + pci_ds_offset); dump((void *) &pci_ds, sizeof(pci_ds)); @@ -412,7 +412,7 @@ DEBUG_PRINTF("%s\n", __func__); memset(&bios_device, 0, sizeof(bios_device)); -#ifndef CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if !CONFIG_PCI_OPTION_ROM_RUN_YABEL bios_device.ihandle = of_open(device_name); if (bios_device.ihandle == 0) { DEBUG_PRINTF("%s is no valid device!\n", device_name); @@ -423,7 +423,7 @@ bios_device.dev = device; #endif biosemu_dev_get_addr_info(); -#ifndef CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if !CONFIG_PCI_OPTION_ROM_RUN_YABEL biosemu_dev_find_vmem_addr(); biosemu_dev_get_puid(); #endif @@ -440,7 +440,7 @@ { int i = 0; translate_address_t ta; -#ifndef CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if !CONFIG_PCI_OPTION_ROM_RUN_YABEL /* we dont need this hack for coreboot... we can access legacy areas */ //check if it is an access to legacy VGA Mem... if it is, map the address //to the vmem BAR and then translate it... Modified: trunk/src/devices/oprom/yabel/interrupt.c ============================================================================== --- trunk/src/devices/oprom/yabel/interrupt.c Thu Apr 21 00:23:56 2011 (r6534) +++ trunk/src/devices/oprom/yabel/interrupt.c Thu Apr 21 22:24:43 2011 (r6535) @@ -24,7 +24,7 @@ #include <x86emu/x86emu.h> #include "../x86emu/prim_ops.h" -#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL #include <device/pci.h> #include <device/pci_ops.h> #endif @@ -343,7 +343,7 @@ DEBUG_PRINTF_INTR("%s(): function: %x: PCI Find Device\n", __func__, M.x86.R_AX); /* FixME: support SI != 0 */ -#if defined(CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES) && CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES==1 +#if CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES dev = dev_find_device(M.x86.R_DX, M.x86.R_CX, 0); if (dev != 0) { DEBUG_PRINTF_INTR @@ -384,7 +384,7 @@ offs = M.x86.R_DI; DEBUG_PRINTF_INTR("%s(): function: %x: PCI Config Read from device: bus: %02x, devfn: %02x, offset: %02x\n", __func__, M.x86.R_AX, bus, devfn, offs); -#if defined(CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES) && CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES==1 +#if CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES dev = dev_find_slot(bus, devfn); DEBUG_PRINTF_INTR("%s(): function: %x: dev_find_slot() returned: %s\n", __func__, M.x86.R_AX, dev_path(dev)); @@ -408,7 +408,7 @@ switch (M.x86.R_AX) { case 0xb108: M.x86.R_CL = -#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL pci_read_config8(dev, offs); #else (u8) rtas_pci_config_read(bios_device. @@ -423,7 +423,7 @@ break; case 0xb109: M.x86.R_CX = -#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL pci_read_config16(dev, offs); #else (u16) rtas_pci_config_read(bios_device. @@ -438,7 +438,7 @@ break; case 0xb10a: M.x86.R_ECX = -#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL pci_read_config32(dev, offs); #else (u32) rtas_pci_config_read(bios_device. @@ -476,7 +476,7 @@ } else { switch (M.x86.R_AX) { case 0xb10b: -#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL pci_write_config8(bios_device.dev, offs, M.x86.R_CL); #else rtas_pci_config_write(bios_device.puid, 1, bus, @@ -488,7 +488,7 @@ M.x86.R_CL); break; case 0xb10c: -#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL pci_write_config16(bios_device.dev, offs, M.x86.R_CX); #else rtas_pci_config_write(bios_device.puid, 2, bus, @@ -500,7 +500,7 @@ M.x86.R_CX); break; case 0xb10d: -#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL pci_write_config32(bios_device.dev, offs, M.x86.R_ECX); #else rtas_pci_config_write(bios_device.puid, 4, bus, @@ -576,8 +576,9 @@ int_handled = 1; break; case PMM_INT_NUM: - /* the selfdefined PMM INT number, this is called by the code in PMM struct, it - * is handled by pmm_handleInt() + /* The self-defined PMM INT number, this is called by + * the code in PMM struct, and it is handled by + * pmm_handleInt() */ pmm_handleInt(); int_handled = 1; Modified: trunk/src/devices/oprom/yabel/io.c ============================================================================== --- trunk/src/devices/oprom/yabel/io.c Thu Apr 21 00:23:56 2011 (r6534) +++ trunk/src/devices/oprom/yabel/io.c Thu Apr 21 22:24:43 2011 (r6535) @@ -19,13 +19,13 @@ #include <x86emu/x86emu.h> #include "io.h" -#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL #include <device/pci.h> #include <device/pci_ops.h> #include <device/resource.h> #endif -#ifdef CONFIG_ARCH_X86 +#if CONFIG_ARCH_X86 #include <arch/io.h> #else // these are not used, only needed for linking, must be overridden using X86emu_setupPioFuncs @@ -76,7 +76,7 @@ } #endif -#if defined(CONFIG_YABEL_DIRECTHW) && (CONFIG_YABEL_DIRECTHW == 1) +#if CONFIG_YABEL_DIRECTHW u8 my_inb(X86EMU_pioAddr addr) { u8 val; @@ -455,7 +455,7 @@ offs += (addr - 0xCFC); // if addr is not 0xcfc, the offset is moved accordingly DEBUG_PRINTF_INTR("%s(): PCI Config Read from device: bus: %02x, devfn: %02x, offset: %02x\n", __func__, bus, devfn, offs); -#if defined(CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES) && CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES==1 +#if CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES dev = dev_find_slot(bus, devfn); DEBUG_PRINTF_INTR("%s(): dev_find_slot() returned: %s\n", __func__, dev_path(dev)); @@ -475,7 +475,7 @@ HALT_SYS(); return 0; } else { -#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL switch (size) { case 1: rval = pci_read_config8(dev, offs); @@ -526,7 +526,7 @@ bus, devfn >> 3, devfn & 7, offs); HALT_SYS(); } else { -#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL switch (size) { case 1: pci_write_config8(bios_device.dev, offs, val); Modified: trunk/src/devices/oprom/yabel/mem.c ============================================================================== --- trunk/src/devices/oprom/yabel/mem.c Thu Apr 21 00:23:56 2011 (r6534) +++ trunk/src/devices/oprom/yabel/mem.c Thu Apr 21 22:24:43 2011 (r6535) @@ -19,9 +19,9 @@ #include "mem.h" #include "compat/time.h" -#if !defined(CONFIG_YABEL_DIRECTHW) || (!CONFIG_YABEL_DIRECTHW) +#if !CONFIG_YABEL_DIRECTHW || !CONFIG_YABEL_DIRECTHW -#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL #include <device/resource.h> #endif Modified: trunk/src/devices/pci_rom.c ============================================================================== --- trunk/src/devices/pci_rom.c Thu Apr 21 00:23:56 2011 (r6534) +++ trunk/src/devices/pci_rom.c Thu Apr 21 22:24:43 2011 (r6535) @@ -46,7 +46,7 @@ rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS); if (rom_address == 0x00000000 || rom_address == 0xffffffff) { -#if defined(CONFIG_BOARD_EMULATION_QEMU_X86) && CONFIG_BOARD_EMULATION_QEMU_X86 +#if CONFIG_BOARD_EMULATION_QEMU_X86 if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) rom_address = 0xc0000; else Modified: trunk/src/devices/pciexp_device.c ============================================================================== --- trunk/src/devices/pciexp_device.c Thu Apr 21 00:23:56 2011 (r6534) +++ trunk/src/devices/pciexp_device.c Thu Apr 21 22:24:43 2011 (r6535) @@ -27,7 +27,7 @@ static void pciexp_tune_dev(device_t dev) { unsigned int cap; -#ifdef CONFIG_PCIE_TUNING +#if CONFIG_PCIE_TUNING u32 reg32; #endif @@ -35,7 +35,7 @@ if (!cap) return; -#ifdef CONFIG_PCIE_TUNING +#if CONFIG_PCIE_TUNING printk(BIOS_DEBUG, "PCIe: tuning %s\n", dev_path(dev)); // TODO make this depending on ASPM. Modified: trunk/src/include/cpu/x86/mtrr.h ============================================================================== --- trunk/src/include/cpu/x86/mtrr.h Thu Apr 21 00:23:56 2011 (r6534) +++ trunk/src/include/cpu/x86/mtrr.h Thu Apr 21 22:24:43 2011 (r6535) @@ -1,7 +1,6 @@ #ifndef CPU_X86_MTRR_H #define CPU_X86_MTRR_H - /* These are the region types */ #define MTRR_TYPE_UNCACHEABLE 0 #define MTRR_TYPE_WRCOMB 1 @@ -64,11 +63,10 @@ # error "CONFIG_XIP_ROM_BASE is not a multiple of CONFIG_XIP_ROM_SIZE" #endif -#if (CONFIG_RAMTOP & (CONFIG_RAMTOP -1)) != 0 +#if (CONFIG_RAMTOP & (CONFIG_RAMTOP - 1)) != 0 # error "CONFIG_RAMTOP must be a power of 2" #endif - #if !defined (__ASSEMBLER__) #if defined(CONFIG_XIP_ROM_SIZE) # if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK Modified: trunk/src/mainboard/kontron/986lcd-m/mainboard.c ============================================================================== --- trunk/src/mainboard/kontron/986lcd-m/mainboard.c Thu Apr 21 00:23:56 2011 (r6534) +++ trunk/src/mainboard/kontron/986lcd-m/mainboard.c Thu Apr 21 22:24:43 2011 (r6535) @@ -20,14 +20,14 @@ #include <types.h> #include <device/device.h> #include <console/console.h> -#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL #include <x86emu/x86emu.h> #endif #include <pc80/mc146818rtc.h> #include <arch/io.h> #include "chip.h" -#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL static int int15_handler(void) { #define BOOT_DISPLAY_DEFAULT 0 @@ -221,7 +221,7 @@ static void mainboard_enable(device_t dev) { -#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL /* Install custom int15 handler for VGA OPROM */ int15_install(); #endif Modified: trunk/src/northbridge/intel/i82830/smihandler.c ============================================================================== --- trunk/src/northbridge/intel/i82830/smihandler.c Thu Apr 21 00:23:56 2011 (r6534) +++ trunk/src/northbridge/intel/i82830/smihandler.c Thu Apr 21 22:24:43 2011 (r6535) @@ -37,7 +37,7 @@ /* If YABEL is enabled and it's not running at 0x00000000, we have to add some * offset to all our mbi object memory accesses */ -#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL && !CONFIG_YABEL_DIRECTHW +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL && !CONFIG_YABEL_DIRECTHW #define OBJ_OFFSET CONFIG_YABEL_VIRTMEM_LOCATION #else #define OBJ_OFFSET 0x00000 Modified: trunk/src/northbridge/intel/i82830/vga.c ============================================================================== --- trunk/src/northbridge/intel/i82830/vga.c Thu Apr 21 00:23:56 2011 (r6534) +++ trunk/src/northbridge/intel/i82830/vga.c Thu Apr 21 22:24:43 2011 (r6535) @@ -25,7 +25,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <cbfs.h> -#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL #include <x86emu/x86emu.h> #endif @@ -62,7 +62,7 @@ printk(BIOS_INFO, "Graphics Initialization Complete\n"); /* Enable TV-Out */ -#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL #define PIPE_A_CRT (1 << 0) #define PIPE_A_LFP (1 << 1) #define PIPE_A_TV (1 << 3) Modified: trunk/src/northbridge/intel/i945/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i945/raminit.c Thu Apr 21 00:23:56 2011 (r6534) +++ trunk/src/northbridge/intel/i945/raminit.c Thu Apr 21 22:24:43 2011 (r6535) @@ -113,7 +113,7 @@ static int memclk(void) { int offset = 0; -#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM) +#if CONFIG_NORTHBRIDGE_INTEL_I945GM offset++; #endif switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) { @@ -125,7 +125,7 @@ return -1; } -#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM) +#if CONFIG_NORTHBRIDGE_INTEL_I945GM static u16 fsbclk(void) { switch (MCHBAR32(CLKCFG) & 7) { @@ -136,7 +136,7 @@ } return 0xffff; } -#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC) +#elif CONFIG_NORTHBRIDGE_INTEL_I945GC static u16 fsbclk(void) { switch (MCHBAR32(CLKCFG) & 7) { @@ -1075,7 +1075,7 @@ return nc; } -#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM) +#if CONFIG_NORTHBRIDGE_INTEL_I945GM /* Strength multiplier tables */ static const u8 dual_channel_strength_multiplier[] = { 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, @@ -1130,7 +1130,7 @@ 0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, 0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11 }; -#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC) +#elif CONFIG_NORTHBRIDGE_INTEL_I945GC static const u8 dual_channel_strength_multiplier[] = { 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, @@ -2186,7 +2186,7 @@ /** * We add the indices according to our clocks from CLKCFG. */ -#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM) +#if CONFIG_NORTHBRIDGE_INTEL_I945GM static const u32 data_clock_crossing[] = { 0x00100401, 0x00000000, /* DDR400 FSB400 */ 0xffffffff, 0xffffffff, /* nonexistant */ @@ -2231,7 +2231,7 @@ 0xffffffff, 0xffffffff, /* nonexistant */ }; -#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC) +#elif CONFIG_NORTHBRIDGE_INTEL_I945GC /* i945 G/P */ static const u32 data_clock_crossing[] = { 0xffffffff, 0xffffffff, /* nonexistant */ @@ -2822,9 +2822,9 @@ { u8 clocks[2] = { 0, 0 }; -#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM) +#if CONFIG_NORTHBRIDGE_INTEL_I945GM #define CLOCKS_WIDTH 2 -#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC) +#elif CONFIG_NORTHBRIDGE_INTEL_I945GC #define CLOCKS_WIDTH 3 #endif if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED) Modified: trunk/src/southbridge/via/k8t890/early_car.c ============================================================================== --- trunk/src/southbridge/via/k8t890/early_car.c Thu Apr 21 00:23:56 2011 (r6534) +++ trunk/src/southbridge/via/k8t890/early_car.c Thu Apr 21 22:24:43 2011 (r6535) @@ -69,15 +69,15 @@ ldtnr = 2; } -#if defined(CONFIG_SOUTHBRIDGE_VIA_K8M800) +#if CONFIG_SOUTHBRIDGE_VIA_K8M800 print_debug("K8M800 found at LDT "); -#elif defined(CONFIG_SOUTHBRIDGE_VIA_K8T800) +#elif CONFIG_SOUTHBRIDGE_VIA_K8T800 print_debug("K8T800 found at LDT "); -#elif defined(CONFIG_SOUTHBRIDGE_VIA_K8T800PRO) +#elif CONFIG_SOUTHBRIDGE_VIA_K8T800PRO print_debug("K8T800 Pro found at LDT "); -#elif defined(CONFIG_SOUTHBRIDGE_VIA_K8M890) +#elif CONFIG_SOUTHBRIDGE_VIA_K8M890 print_debug("K8M890 found at LDT "); -#elif defined(CONFIG_SOUTHBRIDGE_VIA_K8T890) +#elif CONFIG_SOUTHBRIDGE_VIA_K8T890 print_debug("K8T890 found at LDT "); #endif print_debug_hex8(ldtnr); Modified: trunk/src/southbridge/via/vt8237r/lpc.c ============================================================================== --- trunk/src/southbridge/via/vt8237r/lpc.c Thu Apr 21 00:23:56 2011 (r6534) +++ trunk/src/southbridge/via/vt8237r/lpc.c Thu Apr 21 22:24:43 2011 (r6535) @@ -300,7 +300,7 @@ pci_write_config8(dev, 0x48, 0x0c); #else - #if defined(CONFIG_SOUTHBRIDGE_VIA_K8T800) + #if CONFIG_SOUTHBRIDGE_VIA_K8T800 /* It seems that when we pair with the K8T800, we need to disable * the A2 mask */ Modified: trunk/src/superio/ite/it8716f/it8716f.h ============================================================================== --- trunk/src/superio/ite/it8716f/it8716f.h Thu Apr 21 00:23:56 2011 (r6534) +++ trunk/src/superio/ite/it8716f/it8716f.h Thu Apr 21 22:24:43 2011 (r6535) @@ -36,7 +36,7 @@ #define IT8716F_GAME 0x09 /* GAME port */ #define IT8716F_IR 0x0a /* Consumer IR */ -#if defined(CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL) && CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL +#if CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL /* Provided by mainboard, called by IT8716F superio.c. */ void init_ec(u16 base); #endif Modified: trunk/src/superio/ite/it8716f/superio.c ============================================================================== --- trunk/src/superio/ite/it8716f/superio.c Thu Apr 21 00:23:56 2011 (r6534) +++ trunk/src/superio/ite/it8716f/superio.c Thu Apr 21 22:24:43 2011 (r6535) @@ -46,7 +46,7 @@ pnp_write_config(dev, 0x02, 0x02); } -#if !defined(CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL) || !CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL +#if !CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL static void pnp_write_index(u16 port_base, u8 reg, u8 value) { outb(reg, port_base);

1 0

Has the Seabios git server address changed
by Bao, Zheng 21 Apr '11

21 Apr '11

Hi, All, Since we can only access the code tree via a firewall, I need to give the IP address I need to access to the administrator. But the seabios git server just seems to have changed, hasn't it? Actually I am pretty sure it has and I can resolve the IP address. What I am wondering is whether it is also a temp address or a long term one. No chance it will be changed back, right? Thanks. Zheng

3 3

Dell Latitude D820
by Philippe LeCavalier 21 Apr '11

21 Apr '11

Hi All. Just joined the list to find out your opinion on whether or not I should put coreboot on my laptop. First off, what do I gain? I read it's faster but I don't really think my BIOS is slow. OR is it? Perhaps seeing is believing... Second, I've created a small txt file for reference. Felt this mail might get kinda bulky otherwise. So whatever isn't answered below hopefully is in the file. Step 1: A very brief description of your system: board vendor, board name, CPU, northbridge, southbridge, and optionally other important details. Dell Latitude D820, Intel T2500(2.0GHz) CEntrino Duo, Intel 82801,Intel Mobile 945PM, Nvidia Go 7400 256MB, Intel Pro 3945 minipci, Broadcom gigabit nic PCIe Step 2: Linux "lspci -tvnn" output for your system, generated by booting Linux via the original BIOS and runnning lspci. See attached Step 3: Super I/O chip on the mainboard (report the model numbers on the actual chip, for example "Winbond W83627HF" and/or run "superiotool -dV"). See attached Step 4: Type of BIOS device (see the question "How do I identify the BIOS chip on my mainboard?" below). Please send us the output of "flashrom -V" see attached Step 5: URL to the mainboard specifications page (optional). http://www.dell.com/downloads/global/products/latit/en/spec_latit_d820_en.p… Step 6: Any other relevant information you can provide I'm running Deb Wheezy with GRUB2 -- Thanks, Phil

5 7

[PATCH] coreboot support for memory mapped UARTs
by Stefan Reinauer 20 Apr '11

20 Apr '11

See patch.

3 3

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coreboot April 2011