coreboot April 2011

coreboot@coreboot.org

66 participants
229 discussions

[commit] r6529 - trunk/src/superio/nsc/pc87384
by repository service 20 Apr '11

20 Apr '11

Author: svens Date: Wed Apr 20 11:05:37 2011 New Revision: 6529 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6529 Log: PC87384: remove unused init function Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Acked-by: Sven Schnelle <svens(a)stackframe.org> Modified: trunk/src/superio/nsc/pc87384/superio.c Modified: trunk/src/superio/nsc/pc87384/superio.c ============================================================================== --- trunk/src/superio/nsc/pc87384/superio.c Wed Apr 20 10:58:38 2011 (r6528) +++ trunk/src/superio/nsc/pc87384/superio.c Wed Apr 20 11:05:37 2011 (r6529) @@ -30,25 +30,11 @@ #include "chip.h" #include "pc87384.h" -static void init(device_t dev) -{ - struct superio_nsc_pc87384_config *conf = dev->chip_info; - - if (!dev->enabled) - return; - - switch(dev->path.pnp.device) { - case PC87384_GPIO: - break; - } -} - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_enable, - .init = init, }; static struct pnp_info pnp_dev_info[] = {

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[commit] r6528 - in trunk/src: mainboard/nokia/ip530 southbridge/ti/pci1x2x
by repository service 20 Apr '11

20 Apr '11

Author: svens Date: Wed Apr 20 10:58:38 2011 New Revision: 6528 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6528 Log: pci1x2x: remove latency/bridge control/cacheline size settings Those settings should be handled by the generic PCI/Cardbus code, and not by the driver itself. Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Acked-by: Sven Schnelle <svens(a)stackframe.org> Modified: trunk/src/mainboard/nokia/ip530/devicetree.cb trunk/src/southbridge/ti/pci1x2x/chip.h trunk/src/southbridge/ti/pci1x2x/pci1x2x.c Modified: trunk/src/mainboard/nokia/ip530/devicetree.cb ============================================================================== --- trunk/src/mainboard/nokia/ip530/devicetree.cb Wed Apr 20 10:58:30 2011 (r6527) +++ trunk/src/mainboard/nokia/ip530/devicetree.cb Wed Apr 20 10:58:38 2011 (r6528) @@ -33,8 +33,6 @@ device pci 00.0 on subsystemid 0x13b8 0x0000 end - register "cltr" = "0x40" - register "bcr" = "0x7c0" register "scr" = "0x08449060" register "mrr" = "0x00007522" end Modified: trunk/src/southbridge/ti/pci1x2x/chip.h ============================================================================== --- trunk/src/southbridge/ti/pci1x2x/chip.h Wed Apr 20 10:58:30 2011 (r6527) +++ trunk/src/southbridge/ti/pci1x2x/chip.h Wed Apr 20 10:58:38 2011 (r6528) @@ -6,8 +6,5 @@ struct southbridge_ti_pci1x2x_config { int scr; int mrr; - int clsr; - int cltr; - int bcr; }; #endif Modified: trunk/src/southbridge/ti/pci1x2x/pci1x2x.c ============================================================================== --- trunk/src/southbridge/ti/pci1x2x/pci1x2x.c Wed Apr 20 10:58:30 2011 (r6527) +++ trunk/src/southbridge/ti/pci1x2x/pci1x2x.c Wed Apr 20 10:58:38 2011 (r6528) @@ -34,12 +34,6 @@ struct southbridge_ti_pci1x2x_config *conf = dev->chip_info; if (conf) { - /* Cache Line Size (offset 0x0C) */ - pci_write_config8(dev, 0x0C, conf->clsr); - /* CardBus latency timer (offset 0x1B) */ - pci_write_config8(dev, 0x1B, conf->cltr); - /* Bridge control (offset 0x3E) */ - pci_write_config16(dev, 0x3E, conf->bcr); /* System control (offset 0x80) */ pci_write_config32(dev, 0x80, conf->scr); /* Multifunction routing */

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[commit] r6527 - trunk/src/southbridge/ti/pci1x2x
by repository service 20 Apr '11

20 Apr '11

Author: svens Date: Wed Apr 20 10:58:30 2011 New Revision: 6527 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6527 Log: pci1x2x: use cardbus_read_resources()/cardbus_enable_resources() Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Modified: trunk/src/southbridge/ti/pci1x2x/pci1x2x.c Modified: trunk/src/southbridge/ti/pci1x2x/pci1x2x.c ============================================================================== --- trunk/src/southbridge/ti/pci1x2x/pci1x2x.c Wed Apr 20 10:58:16 2011 (r6526) +++ trunk/src/southbridge/ti/pci1x2x/pci1x2x.c Wed Apr 20 10:58:30 2011 (r6527) @@ -22,6 +22,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <device/cardbus.h> #include <console/console.h> #include <arch/io.h> #include "chip.h" @@ -65,9 +66,9 @@ }; struct device_operations southbridge_ti_pci1x2x_pciops = { - .read_resources = NULL, //pci_dev_read_resources, + .read_resources = cardbus_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, + .enable_resources = cardbus_enable_resources, .init = ti_pci1x2y_init, .scan_bus = 0, .ops_pci = &ti_pci1x2y_pci_ops,

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[commit] r6526 - in trunk/src: mainboard/nokia/ip530 southbridge/ti/pci1x2x
by repository service 20 Apr '11

20 Apr '11

Author: svens Date: Wed Apr 20 10:58:16 2011 New Revision: 6526 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6526 Log: pci1x2x: use pci_ops set_subsystem instead of custom code Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Modified: trunk/src/mainboard/nokia/ip530/devicetree.cb trunk/src/southbridge/ti/pci1x2x/pci1x2x.c Modified: trunk/src/mainboard/nokia/ip530/devicetree.cb ============================================================================== --- trunk/src/mainboard/nokia/ip530/devicetree.cb Wed Apr 20 10:58:08 2011 (r6525) +++ trunk/src/mainboard/nokia/ip530/devicetree.cb Wed Apr 20 10:58:16 2011 (r6526) @@ -31,7 +31,7 @@ device pci f.0 on chip southbridge/ti/pci1x2x device pci 00.0 on - + subsystemid 0x13b8 0x0000 end register "cltr" = "0x40" register "bcr" = "0x7c0" Modified: trunk/src/southbridge/ti/pci1x2x/pci1x2x.c ============================================================================== --- trunk/src/southbridge/ti/pci1x2x/pci1x2x.c Wed Apr 20 10:58:08 2011 (r6525) +++ trunk/src/southbridge/ti/pci1x2x/pci1x2x.c Wed Apr 20 10:58:16 2011 (r6526) @@ -23,6 +23,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <console/console.h> +#include <arch/io.h> #include "chip.h" static void ti_pci1x2y_init(struct device *dev) @@ -38,16 +39,6 @@ pci_write_config8(dev, 0x1B, conf->cltr); /* Bridge control (offset 0x3E) */ pci_write_config16(dev, 0x3E, conf->bcr); - } - /* - * Enable change sub-vendor ID. Clear the bit 5 to enable to write - * to the sub-vendor/device ids at 40 and 42. - */ - pci_write_config32(dev, 0x80, 0x10); - pci_write_config32(dev, 0x40, PCI_VENDOR_ID_NOKIA); - - if (conf) { - /* Now write the correct value for SCR. */ /* System control (offset 0x80) */ pci_write_config32(dev, 0x80, conf->scr); /* Multifunction routing */ @@ -57,12 +48,29 @@ pci_write_config8(dev, 0x92, pci_read_config8(dev, 0x92) | 0x02); } +static void ti_pci1x2y_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + /* + * Enable change sub-vendor ID. Clear the bit 5 to enable to write + * to the sub-vendor/device ids at 40 and 42. + */ + pci_write_config32(dev, 0x80, pci_read_config32(dev, 0x080) & ~0x10); + pci_write_config16(dev, 0x40, vendor); + pci_write_config16(dev, 0x42, device); + pci_write_config32(dev, 0x80, pci_read_config32(dev, 0x80) | 0x10); +} + +static struct pci_operations ti_pci1x2y_pci_ops = { + .set_subsystem = ti_pci1x2y_set_subsystem, +}; + struct device_operations southbridge_ti_pci1x2x_pciops = { .read_resources = NULL, //pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = ti_pci1x2y_init, .scan_bus = 0, + .ops_pci = &ti_pci1x2y_pci_ops, }; static const struct pci_driver ti_pci1225_driver __pci_driver = {

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[commit] r6525 - in trunk/src: include/device southbridge/ti/pci1x2x
by repository service 20 Apr '11

20 Apr '11

Author: svens Date: Wed Apr 20 10:58:08 2011 New Revision: 6525 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6525 Log: pci1x2x: add PCI1510 device IDs Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Modified: trunk/src/include/device/pci_ids.h trunk/src/southbridge/ti/pci1x2x/pci1x2x.c Modified: trunk/src/include/device/pci_ids.h ============================================================================== --- trunk/src/include/device/pci_ids.h Wed Apr 20 10:57:53 2011 (r6524) +++ trunk/src/include/device/pci_ids.h Wed Apr 20 10:58:08 2011 (r6525) @@ -737,6 +737,7 @@ #define PCI_DEVICE_ID_TI_4451 0xac42 #define PCI_DEVICE_ID_TI_1420 0xac51 #define PCI_DEVICE_ID_TI_1520 0xac55 +#define PCI_DEVICE_ID_TI_1510 0xac56 #define PCI_VENDOR_ID_SONY 0x104d #define PCI_DEVICE_ID_SONY_CXD3222 0x8039 Modified: trunk/src/southbridge/ti/pci1x2x/pci1x2x.c ============================================================================== --- trunk/src/southbridge/ti/pci1x2x/pci1x2x.c Wed Apr 20 10:57:53 2011 (r6524) +++ trunk/src/southbridge/ti/pci1x2x/pci1x2x.c Wed Apr 20 10:58:08 2011 (r6525) @@ -77,6 +77,12 @@ .device = PCI_DEVICE_ID_TI_1420, }; +static const struct pci_driver ti_pci1510_driver __pci_driver = { + .ops = &southbridge_ti_pci1x2x_pciops, + .vendor = PCI_VENDOR_ID_TI, + .device = PCI_DEVICE_ID_TI_1510, +}; + static const struct pci_driver ti_pci1520_driver __pci_driver = { .ops = &southbridge_ti_pci1x2x_pciops, .vendor = PCI_VENDOR_ID_TI,

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[commit] r6524 - in trunk/src: mainboard/nokia/ip530 southbridge/ti/pci1x2x
by repository service 20 Apr '11

20 Apr '11

Author: svens Date: Wed Apr 20 10:57:53 2011 New Revision: 6524 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6524 Log: pci1x2x: use devicetree register configuration Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Added: trunk/src/southbridge/ti/pci1x2x/chip.h Modified: trunk/src/mainboard/nokia/ip530/Kconfig trunk/src/mainboard/nokia/ip530/devicetree.cb trunk/src/southbridge/ti/pci1x2x/pci1x2x.c Modified: trunk/src/mainboard/nokia/ip530/Kconfig ============================================================================== --- trunk/src/mainboard/nokia/ip530/Kconfig Wed Apr 20 03:08:25 2011 (r6523) +++ trunk/src/mainboard/nokia/ip530/Kconfig Wed Apr 20 10:57:53 2011 (r6524) @@ -45,29 +45,4 @@ int default 22 -## Configuration for the PCMCIA-Cardbus controller. -config TI_PCMCIA_CARDBUS_CMDR - hex - default 0x0107 - -config TI_PCMCIA_CARDBUS_CLSR - hex - default 0x00 - -config TI_PCMCIA_CARDBUS_CLTR - hex - default 0x40 - -config TI_PCMCIA_CARDBUS_BCR - hex - default 0x07C0 - -config TI_PCMCIA_CARDBUS_SCR - hex - default 0x08449060 - -config TI_PCMCIA_CARDBUS_MRR - hex - default 0x00007522 - endif # BOARD_NOKIA_IP530 Modified: trunk/src/mainboard/nokia/ip530/devicetree.cb ============================================================================== --- trunk/src/mainboard/nokia/ip530/devicetree.cb Wed Apr 20 03:08:25 2011 (r6523) +++ trunk/src/mainboard/nokia/ip530/devicetree.cb Wed Apr 20 10:57:53 2011 (r6524) @@ -28,6 +28,17 @@ device pci 0.0 on end # Host bridge device pci 1.0 on end # PCI/AGP bridge chip southbridge/intel/i82371eb # Southbridge + device pci f.0 on + chip southbridge/ti/pci1x2x + device pci 00.0 on + + end + register "cltr" = "0x40" + register "bcr" = "0x7c0" + register "scr" = "0x08449060" + register "mrr" = "0x00007522" + end + end device pci 7.0 on # ISA bridge chip superio/smsc/smscsuperio # Super I/O (SMSC FDC37B787) device pnp 3f0.0 off end # Floppy (No connector) Added: trunk/src/southbridge/ti/pci1x2x/chip.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/ti/pci1x2x/chip.h Wed Apr 20 10:57:53 2011 (r6524) @@ -0,0 +1,13 @@ +#ifndef SOUTHBRIDGE_TI_PCI1X2X_H +#define SOUTHBRIDGE_TI_PCI1X2X_H + +extern struct chip_operations southbridge_ti_pci1x2x_ops; + +struct southbridge_ti_pci1x2x_config { + int scr; + int mrr; + int clsr; + int cltr; + int bcr; +}; +#endif Modified: trunk/src/southbridge/ti/pci1x2x/pci1x2x.c ============================================================================== --- trunk/src/southbridge/ti/pci1x2x/pci1x2x.c Wed Apr 20 03:08:25 2011 (r6523) +++ trunk/src/southbridge/ti/pci1x2x/pci1x2x.c Wed Apr 20 10:57:53 2011 (r6524) @@ -23,44 +23,41 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <console/console.h> - -#if (!defined(CONFIG_TI_PCMCIA_CARDBUS_CMDR) || \ - !defined(CONFIG_TI_PCMCIA_CARDBUS_CLSR) || \ - !defined(CONFIG_TI_PCMCIA_CARDBUS_CLTR) || \ - !defined(CONFIG_TI_PCMCIA_CARDBUS_BCR) || \ - !defined(CONFIG_TI_PCMCIA_CARDBUS_SCR) || \ - !defined(CONFIG_TI_PCMCIA_CARDBUS_MRR)) -#error "you must supply these values in your mainboard-specific Kconfig file" -#endif +#include "chip.h" static void ti_pci1x2y_init(struct device *dev) { + printk(BIOS_INFO, "Init of Texas Instruments PCI1x2x PCMCIA/CardBus controller\n"); + struct southbridge_ti_pci1x2x_config *conf = dev->chip_info; - /* Command (offset 04) */ - pci_write_config16(dev, 0x04, CONFIG_TI_PCMCIA_CARDBUS_CMDR); - /* Cache Line Size (offset 0x0C) */ - pci_write_config8(dev, 0x0C, CONFIG_TI_PCMCIA_CARDBUS_CLSR); - /* CardBus latency timer (offset 0x1B) */ - pci_write_config8(dev, 0x1B, CONFIG_TI_PCMCIA_CARDBUS_CLTR); - /* Bridge control (offset 0x3E) */ - pci_write_config16(dev, 0x3E, CONFIG_TI_PCMCIA_CARDBUS_BCR); + if (conf) { + /* Cache Line Size (offset 0x0C) */ + pci_write_config8(dev, 0x0C, conf->clsr); + /* CardBus latency timer (offset 0x1B) */ + pci_write_config8(dev, 0x1B, conf->cltr); + /* Bridge control (offset 0x3E) */ + pci_write_config16(dev, 0x3E, conf->bcr); + } /* * Enable change sub-vendor ID. Clear the bit 5 to enable to write * to the sub-vendor/device ids at 40 and 42. */ pci_write_config32(dev, 0x80, 0x10); pci_write_config32(dev, 0x40, PCI_VENDOR_ID_NOKIA); - /* Now write the correct value for SCR. */ - /* System control (offset 0x80) */ - pci_write_config32(dev, 0x80, CONFIG_TI_PCMCIA_CARDBUS_SCR); - /* Multifunction routing */ - pci_write_config32(dev, 0x8C, CONFIG_TI_PCMCIA_CARDBUS_MRR); + + if (conf) { + /* Now write the correct value for SCR. */ + /* System control (offset 0x80) */ + pci_write_config32(dev, 0x80, conf->scr); + /* Multifunction routing */ + pci_write_config32(dev, 0x8C, conf->mrr); + } /* Set the device control register (0x92) accordingly. */ pci_write_config8(dev, 0x92, pci_read_config8(dev, 0x92) | 0x02); } -static struct device_operations ti_pci1x2y_ops = { +struct device_operations southbridge_ti_pci1x2x_pciops = { .read_resources = NULL, //pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, @@ -69,19 +66,23 @@ }; static const struct pci_driver ti_pci1225_driver __pci_driver = { - .ops = &ti_pci1x2y_ops, + .ops = &southbridge_ti_pci1x2x_pciops, .vendor = PCI_VENDOR_ID_TI, .device = PCI_DEVICE_ID_TI_1225, }; static const struct pci_driver ti_pci1420_driver __pci_driver = { - .ops = &ti_pci1x2y_ops, + .ops = &southbridge_ti_pci1x2x_pciops, .vendor = PCI_VENDOR_ID_TI, .device = PCI_DEVICE_ID_TI_1420, }; static const struct pci_driver ti_pci1520_driver __pci_driver = { - .ops = &ti_pci1x2y_ops, + .ops = &southbridge_ti_pci1x2x_pciops, .vendor = PCI_VENDOR_ID_TI, .device = PCI_DEVICE_ID_TI_1520, }; + +struct chip_operations southbridge_ti_pci1x2x_ops = { + CHIP_NAME("TI PCI1x2x Cardbus controller") +};

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Failed to launch windows 7 and two more questions ...
by Boris Shpoungin 20 Apr '11

20 Apr '11

We are considering to use coreboot for our developing board. I downloaded latest version of coreboot + seabios and compiled it for emulation. I tried to launch windows 7 in qemu with coreboot bios and got the following error: "Windows failed to load because the firmware (BIOS) is not ACPI compatible" Status: 0xc0000225 Can anyone clarify why I get this error and what i did wrong? Two more questions: Could you recommend any manual which describe coreboot porting process to new not supported platform? Does it exist at all? Could you provide rough effort estimate to port coreboot to new unsupported platform? Thank you.

3 4

build service results for r6522
by repository service 20 Apr '11

20 Apr '11

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 6522 to the coreboot repository. This caused the following changes: Change Log: fix boards that still had some uart init remainders Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build Log: Compilation of lenovo:x60 has been fixed Compilation of via:epia-cn has been fixed Compilation of via:epia-m has been fixed Compilation of via:vt8454c has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r6523 - in trunk/src: include lib southbridge/via/vt82c686
by repository service 20 Apr '11

20 Apr '11

Author: stepan Date: Wed Apr 20 03:08:25 2011 New Revision: 6523 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6523 Log: drop dead uart init code. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Modified: trunk/src/include/uart8250.h trunk/src/lib/uart8250.c trunk/src/southbridge/via/vt82c686/chip.h Modified: trunk/src/include/uart8250.h ============================================================================== --- trunk/src/include/uart8250.h Wed Apr 20 03:03:58 2011 (r6522) +++ trunk/src/include/uart8250.h Wed Apr 20 03:08:25 2011 (r6523) @@ -131,11 +131,6 @@ #ifndef __ROMCC__ -// Can't we just drop this? It seems silly. -struct uart8250 { - unsigned int baud; -}; - unsigned char uart8250_rx_byte(unsigned base_port); int uart8250_can_rx_byte(unsigned base_port); void uart8250_tx_byte(unsigned base_port, unsigned char data); @@ -144,7 +139,6 @@ * have three different sets of uart code, so it's an improvement. */ void uart8250_init(unsigned base_port, unsigned divisor); -void init_uart8250(unsigned base_port, struct uart8250 *uart); void uart_init(void); #endif Modified: trunk/src/lib/uart8250.c ============================================================================== --- trunk/src/lib/uart8250.c Wed Apr 20 03:03:58 2011 (r6522) +++ trunk/src/lib/uart8250.c Wed Apr 20 03:08:25 2011 (r6523) @@ -86,23 +86,6 @@ outb(CONFIG_TTYS0_LCS, base_port + UART_LCR); } -#ifndef __ROMCC__ -/* Initialize a generic uart */ -void init_uart8250(unsigned base_port, struct uart8250 *uart) -{ - int divisor = uart->baud ? (115200/uart->baud) : 1; - - if (base_port == CONFIG_TTYS0_BASE) { - /* Don't reinitialize the console serial port, - * This is espeically nasty in SMP. - * NOTE: The first invocation thus always needs to be - */ - return; - } - uart8250_init(base_port, divisor); -} -#endif - #if defined(__PRE_RAM__) || defined(__SMM__) void uart_init(void) { Modified: trunk/src/southbridge/via/vt82c686/chip.h ============================================================================== --- trunk/src/southbridge/via/vt82c686/chip.h Wed Apr 20 03:03:58 2011 (r6522) +++ trunk/src/southbridge/via/vt82c686/chip.h Wed Apr 20 03:08:25 2011 (r6523) @@ -28,7 +28,6 @@ extern struct chip_operations superio_via_vt82c686_ops; struct superio_via_vt82c686_config { - struct uart8250 com1, com2; struct pc_keyboard keyboard; };

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[commit] r6522 - in trunk/src/superio: nsc/pc87382 via/vt1211
by repository service 20 Apr '11

20 Apr '11

Author: stepan Date: Wed Apr 20 03:03:58 2011 New Revision: 6522 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6522 Log: fix boards that still had some uart init remainders Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Modified: trunk/src/superio/nsc/pc87382/superio.c trunk/src/superio/via/vt1211/vt1211.c Modified: trunk/src/superio/nsc/pc87382/superio.c ============================================================================== --- trunk/src/superio/nsc/pc87382/superio.c Tue Apr 19 23:33:40 2011 (r6521) +++ trunk/src/superio/nsc/pc87382/superio.c Wed Apr 20 03:03:58 2011 (r6522) @@ -32,8 +32,6 @@ static void init(device_t dev) { - struct superio_nsc_pc87382_config *conf = dev->chip_info; - if (!dev->enabled) return; Modified: trunk/src/superio/via/vt1211/vt1211.c ============================================================================== --- trunk/src/superio/via/vt1211/vt1211.c Tue Apr 19 23:33:40 2011 (r6521) +++ trunk/src/superio/via/vt1211/vt1211.c Wed Apr 20 03:03:58 2011 (r6522) @@ -93,21 +93,12 @@ static void vt1211_init(struct device *dev) { - struct superio_via_vt1211_config *conf = dev->chip_info; struct resource *res0; if (!dev->enabled) return; switch (dev->path.pnp.device) { - case VT1211_SP1: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com1); - break; - case VT1211_SP2: - res0 = find_resource(dev, PNP_IDX_IO0); - init_uart8250(res0->base, &conf->com2); - break; case VT1211_HWM: res0 = find_resource(dev, PNP_IDX_IO0); init_hwm(res0->base);

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coreboot April 2011