coreboot February 2011

coreboot@coreboot.org

52 participants
283 discussions

[commit] r6401 - in trunk/src: cpu/amd/model_10xxx northbridge/amd/amdht northbridge/amd/amdmct/wrappers
by repository service 27 Feb '11

27 Feb '11

Author: mjones Date: Mon Feb 28 04:02:40 2011 New Revision: 6401 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6401 Log: Improving BKDG implementation of P-states, CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. Factor out some common expressions. Add an error message when coreboots hangs waiting for a pstate that never comes (it happened to me), and throw some paranoia at it for good mesure. If I understood BKDG fam10 CPUs never need a software initiated vid transition, because the hardware knows what to do when you just request a Pstate change if the cpu is properly configured. In fact unifying a little what PVI and SVI do was better for my board (SVI). So I drop transitionVid, which I didn't understand either (why did it have a case for PVI if it is never called for PVI ? Why did the PVI case distinguigh cpu or nb when PVI is theoretically single voltage plane ? ). Signed-off-by: Xavi Drudis Ferran <xdrudis(a)tinet.cat> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c trunk/src/northbridge/amd/amdht/AsPsDefs.h trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 03:36:15 2011 (r6400) +++ trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 04:02:40 2011 (r6401) @@ -67,13 +67,13 @@ } static void setVSRamp(device_t dev) { - /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSRampTime] - * If this field accepts 8 values between 10 and 500 us why - * does page 324 say "BIOS should set this field to 001b." + /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSRampTime] + * If this field accepts 8 values between 10 and 500 us why + * does page 324 say "BIOS should set this field to 001b." * (20 us) ? * Shouldn't it depend on the voltage regulators, mainboard - * or something ? - */ + * or something ? + */ u32 dword; dword = pci_read_config32(dev, 0xd8); dword &= VSRAMP_MASK; @@ -180,18 +180,18 @@ } static u32 nb_clk_did(int node, u32 cpuRev,u8 procPkg) { - u8 link0isGen3 = 0; + u8 link0isGen3 = 0; u8 offset; if (AMD_CpuFindCapability(node, 0, &offset)) { link0isGen3 = (AMD_checkLinkType(node, 0, offset) & HTPHY_LINKTYPE_HT3 ); } - /* FIXME: NB_CLKDID should be 101b for AMD_DA_C2 in package - S1g3 in link Gen3 mode, but I don't know how to tell - package S1g3 from S1g4 */ - if ((cpuRev & AMD_DA_C2) && (procPkg & AMD_PKGTYPE_S1gX) + /* FIXME: NB_CLKDID should be 101b for AMD_DA_C2 in package + S1g3 in link Gen3 mode, but I don't know how to tell + package S1g3 from S1g4 */ + if ((cpuRev & AMD_DA_C2) && (procPkg & AMD_PKGTYPE_S1gX) && link0isGen3) { - return 5 ; /* divide clk by 128*/ - } else { + return 5 ; /* divide clk by 128*/ + } else { return 4 ; /* divide clk by 16 */ } } @@ -200,29 +200,29 @@ static u32 power_up_down(int node, u8 procPkg) { u32 dword=0; /* from CPU rev guide #41322 rev 3.74 June 2010 Table 26 */ - u8 singleLinkFlag = ((procPkg == AMD_PKGTYPE_AM3_2r2) - || (procPkg == AMD_PKGTYPE_S1gX) + u8 singleLinkFlag = ((procPkg == AMD_PKGTYPE_AM3_2r2) + || (procPkg == AMD_PKGTYPE_S1gX) || (procPkg == AMD_PKGTYPE_ASB2)); if (singleLinkFlag) { - /* + /* * PowerStepUp=01000b - 50nS * PowerStepDown=01000b - 50ns */ dword |= PW_STP_UP50 | PW_STP_DN50; } else { - u32 dispRefModeEn = (pci_read_config32(NODE_PCI(node,0),0x68) >> 24) & 1; + u32 dispRefModeEn = (pci_read_config32(NODE_PCI(node,0),0x68) >> 24) & 1; u32 isocEn = 0; - int j; + int j; for(j=0 ; (j<4) && (!isocEn) ; j++ ) { u8 offset; if (AMD_CpuFindCapability(node, j, &offset)) { isocEn = (pci_read_config32(NODE_PCI(node,0),offset+4) >>12) & 1; } - } + } if (dispRefModeEn || isocEn) { - dword |= PW_STP_UP50 | PW_STP_DN50 ; + dword |= PW_STP_UP50 | PW_STP_DN50 ; } else { /* get number of cores for PowerStepUp & PowerStepDown in server 1 core - 400nS - 0000b @@ -247,17 +247,17 @@ } } } - return dword; + return dword; } -static void config_clk_power_ctrl_reg0(int node, u32 cpuRev, u8 procPkg) { +static void config_clk_power_ctrl_reg0(int node, u32 cpuRev, u8 procPkg) { device_t dev = NODE_PCI(node, 3); /* Program fields in Clock Power/Control register0 (F3xD4) */ /* set F3xD4 Clock Power/Timing Control 0 Register * NbClkDidApplyAll=1b - * NbClkDid=100b or 101b + * NbClkDid=100b or 101b * PowerStepUp= "platform dependent" * PowerStepDown= "platform dependent" * LinkPllLink=01b @@ -275,7 +275,7 @@ } -static void config_power_ctrl_misc_reg(device_t dev,u32 cpuRev, u8 procPkg) { +static void config_power_ctrl_misc_reg(device_t dev,u32 cpuRev, u8 procPkg) { /* check PVI/SVI */ u32 dword = pci_read_config32(dev, 0xA0); @@ -302,10 +302,10 @@ dword = dtemp; } /* set the rest of A0 since we're at it... */ - - if (cpuRev & (AMD_DA_Cx | AMD_RB_C3 )) { + + if (cpuRev & (AMD_DA_Cx | AMD_RB_C3 )) { dword |= NB_PSTATE_FORCE_ON; - } // else should we clear it ? + } // else should we clear it ? if ((procPkg == AMD_PKGTYPE_G34) || (procPkg == AMD_PKGTYPE_C32) ) { @@ -320,41 +320,41 @@ #endif pci_write_config32(dev, 0xA0, dword); } - + static void config_nb_syn_ptr_adj(device_t dev, u32 cpuRev) { /* Note the following settings are additional from the ported * function setFidVidRegs() */ - /* adjust FIFO between nb and core clocks to max allowed - values (min latency) */ + /* adjust FIFO between nb and core clocks to max allowed + values (min latency) */ u32 nbPstate = pci_read_config32(dev,0x1f0) & NB_PSTATE_MASK; u8 nbSynPtrAdj; if ((cpuRev & (AMD_DR_Bx|AMD_DA_Cx) ) - || ( (cpuRev & AMD_RB_C3) && (nbPstate!=0))) { - nbSynPtrAdj = 5; + || ( (cpuRev & AMD_RB_C3) && (nbPstate!=0))) { + nbSynPtrAdj = 5; } else { nbSynPtrAdj = 6; } u32 dword = pci_read_config32(dev, 0xDc); dword &= ~ NB_SYN_PTR_ADJ_MASK; - dword |= nbSynPtrAdj << NB_SYN_PTR_ADJ_POS; + dword |= nbSynPtrAdj << NB_SYN_PTR_ADJ_POS; /* NbsynPtrAdj set to 5 or 6 per BKDG (needs reset) */ pci_write_config32(dev, 0xdc, dword); } static void config_acpi_pwr_state_ctrl_regs(device_t dev, u32 cpuRev, u8 procPkg) { - /* step 1, chapter 2.4.2.6 of AMD Fam 10 BKDG #31116 Rev 3.48 22.4.2010 */ + /* step 1, chapter 2.4.2.6 of AMD Fam 10 BKDG #31116 Rev 3.48 22.4.2010 */ u32 dword; u32 c1= 1; if (cpuRev & (AMD_DR_Bx)) { // will coreboot ever enable cache scrubbing ? // if it does, will it be enough to check the current state - // or should we configure for what we'll set up later ? + // or should we configure for what we'll set up later ? dword = pci_read_config32(dev, 0x58); u32 scrubbingCache = dword & ( (0x1F << 16) // DCacheScrub - | (0x1F << 8) ); // L2Scrub + | (0x1F << 8) ); // L2Scrub if (scrubbingCache) { c1 = 0x80; } else { @@ -368,7 +368,7 @@ c1 = 0x80; } } - dword = (c1 << 24) | (0xE641E6); + dword = (c1 << 24) | (0xE641E6); pci_write_config32(dev, 0x84, dword); @@ -377,25 +377,25 @@ assertion time, then { If ASB2 && SVI then smaf001 = F6h else smaf001=87h. } else ... I hardly know what it means or how to check it from here, so I bluntly assume it is false and code here the else, -which is easier */ +which is easier */ u32 smaf001 = 0xE6; if (cpuRev & AMD_DR_Bx ) { smaf001 = 0xA6; } else { #if CONFIG_SVI_HIGH_FREQ - if (cpuRev & (AMD_RB_C3 | AMD_DA_C3)) { - smaf001 = 0xF6; + if (cpuRev & (AMD_RB_C3 | AMD_DA_C3)) { + smaf001 = 0xF6; } #endif } u32 fidvidChange = 0; if (((cpuRev & AMD_DA_Cx) && (procPkg & AMD_PKGTYPE_S1gX)) - || (cpuRev & AMD_RB_C3) ) { + || (cpuRev & AMD_RB_C3) ) { fidvidChange=0x0B; - } - dword = (0xE6 << 24) | (fidvidChange << 16) - | (smaf001 << 8) | 0x81; + } + dword = (0xE6 << 24) | (fidvidChange << 16) + | (smaf001 << 8) | 0x81; pci_write_config32(dev, 0x80, dword); } @@ -423,7 +423,7 @@ config_clk_power_ctrl_reg0(i,cpuRev,procPkg); - config_power_ctrl_misc_reg(dev,cpuRev,procPkg); + config_power_ctrl_misc_reg(dev,cpuRev,procPkg); config_nb_syn_ptr_adj(dev,cpuRev); config_acpi_pwr_state_ctrl_regs(dev,cpuRev,procPkg); @@ -443,6 +443,62 @@ } } +static void waitCurrentPstate(u32 target_pstate){ + msr_t initial_msr = rdmsr(TSC_MSR); + msr_t pstate_msr = rdmsr(CUR_PSTATE_MSR); + msr_t tsc_msr; + u8 timedout ; + + /* paranoia ? I fear when we run fixPsNbVidBeforeWR we can enter a + * P1 that is a copy of P0, therefore has the same NB DID but the + * TSC will count twice per tick, so we have to wait for twice the + * count to achieve the desired timeout. But I'm likely to + * misunderstand this... + */ + u32 corrected_timeout = ( (pstate_msr.lo==1) + && (!(rdmsr(0xC0010065).lo & NB_DID_M_ON)) ) ? + WAIT_PSTATE_TIMEOUT*2 : WAIT_PSTATE_TIMEOUT ; + msr_t timeout; + + timeout.lo = initial_msr.lo + corrected_timeout ; + timeout.hi = initial_msr.hi; + if ( (((u32)0xffffffff) - initial_msr.lo) < corrected_timeout ) { + timeout.hi++; + } + + // assuming TSC ticks at 1.25 ns per tick (800 MHz) + do { + pstate_msr = rdmsr(CUR_PSTATE_MSR); + tsc_msr = rdmsr(TSC_MSR); + timedout = (tsc_msr.hi > timeout.hi) + || ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo )); + } while ( (pstate_msr.lo != target_pstate) && (! timedout) ) ; + + if (pstate_msr.lo != target_pstate) { + msr_t limit_msr = rdmsr(0xc0010061); + printk(BIOS_ERR, "*** Time out waiting for P-state %01x. Current P-state %01x P-state current limit MSRC001_0061=%02x\n", target_pstate, pstate_msr.lo, limit_msr.lo); + + do { // should we just go on instead ? + pstate_msr = rdmsr(CUR_PSTATE_MSR); + } while ( pstate_msr.lo != target_pstate ) ; + } +} + +static void set_pstate(u32 nonBoostedPState) { + msr_t msr; + + // Transition P0 for calling core. + msr = rdmsr(0xC0010062); + + msr.lo = nonBoostedPState; + wrmsr(0xC0010062, msr); + + /* Wait for P0 to set. */ + waitCurrentPstate(nonBoostedPState); +} + + + static void UpdateSinglePlaneNbVid(void) { @@ -468,157 +524,62 @@ } } -static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid) -{ - msr_t msr; - u8 startup_pstate; - - /* This function sets NbVid before the warm reset. - * Get StartupPstate from MSRC001_0071. - * Read Pstate register pionted by [StartupPstate]. - * and copy its content to P0 and P1 registers. - * Copy newNbVid to P0[NbVid]. - * transition to P1 on all cores, - * then transition to P0 on core 0. - * Wait for MSRC001_0063[CurPstate] = 000b on core 0. - */ +static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid, u32 dev, u8 pviMode) + { + msr_t msr; + u8 startup_pstate; + + /* This function sets NbVid before the warm reset. + * Get StartupPstate from MSRC001_0071. + * Read Pstate register pointed by [StartupPstate]. + * and copy its content to P0 and P1 registers. + * Copy newNbVid to P0[NbVid]. + * transition to P1 on all cores, + * then transition to P0 on core 0. + * Wait for MSRC001_0063[CurPstate] = 000b on core 0. + * see BKDG rev 3.48 2.4.2.9.1 BIOS NB COF and VID Configuration + * for SVI and Single-Plane PVI Systems + */ - msr = rdmsr(0xc0010071); + msr = rdmsr(0xc0010071); startup_pstate = (msr.hi >> (32 - 32)) & 0x07; - /* Copy startup pstate to P1 and P0 MSRs. Set the maxvid for this node in P0. - * Then transition to P1 for corex and P0 for core0. - * These setting will be cleared by the warm reset + /* Copy startup pstate to P1 and P0 MSRs. Set the maxvid for + * this node in P0. Then transition to P1 for corex and P0 + * for core0. These setting will be cleared by the warm reset */ msr = rdmsr(0xC0010064 + startup_pstate); wrmsr(0xC0010065, msr); wrmsr(0xC0010064, msr); + /* missing step 2 from BDKG , F3xDC[PstateMaxVal] = + * max(1,F3xDC[PstateMaxVal] ) because it would take + * synchronization between cores and we don't think + * PstatMaxVal is going to be 0 on cold reset anyway ? + */ + if ( ! (pci_read_config32(dev, 0xDC) & (~ PS_MAX_VAL_MASK)) ) { + printk(BIOS_ERR,"F3xDC[PstateMaxVal] is zero. Northbridge voltage setting will fail. fixPsNbVidBeforeWR in fidvid.c needs fixing. See AMD # 31116 rev 3.48 BKDG 2.4.2.9.1 \n"); + }; + msr.lo &= ~0xFE000000; // clear nbvid - msr.lo |= newNbVid << 25; + msr.lo |= (newNbVid << 25); wrmsr(0xC0010064, msr); - UpdateSinglePlaneNbVid(); + if (pviMode) { /* single plane*/ + UpdateSinglePlaneNbVid(); + } // Transition to P1 for all APs and P0 for core0. - msr = rdmsr(0xC0010062); - msr.lo = (msr.lo & ~0x07) | 1; - wrmsr(0xC0010062, msr); - - // Wait for P1 to set. - do { - msr = rdmsr(0xC0010063); - } while (msr.lo != 1); + set_pstate(1); if (coreid == 0) { - msr.lo = msr.lo & ~0x07; - wrmsr(0xC0010062, msr); - // Wait for P0 to set. - do { - msr = rdmsr(0xC0010063); - } while (msr.lo != 0); - } -} + set_pstate(0); + } -static void coreDelay(void) -{ - u32 saved; - u32 hi, lo, msr; - u32 cycles; - - /* delay ~40us - This seems like a hack to me... - It would be nice to have a central delay function. */ - - cycles = 8000 << 3; /* x8 (number of 1.25ns ticks) */ - - msr = 0x10; /* TSC */ - _RDMSR(msr, &lo, &hi); - saved = lo; - do { - _RDMSR(msr, &lo, &hi); - } while (lo - saved < cycles); -} - -static void transitionVid(u32 targetVid, u8 dev, u8 isNb) -{ - u32 currentVid, dtemp; - msr_t msr; - u8 vsTimecode; - u16 timeTable[8] = { 10, 20, 30, 40, 60, 100, 200, 500 }; - int vsTime; - - /* This function steps or slam the Nb VID to the target VID. - * It uses VSRampTime for [SlamVidMode]=0 ([PviMode]=1) - * or VSSlamTime for [SlamVidMode]=1 ([PviMode]=0)to time period. + /* missing step 7 (restore PstateMax to 0 if needed) because + * we skipped step 2 */ - /* get the current VID */ - msr = rdmsr(0xC0010071); - if (isNb) - currentVid = (msr.lo >> NB_VID_POS) & BIT_MASK_7; - else - currentVid = (msr.lo >> CPU_VID_POS) & BIT_MASK_7; - - /* Read MSRC001_0070 COFVID Control Register */ - msr = rdmsr(0xC0010070); - - /* check PVI/SPI */ - dtemp = pci_read_config32(dev, 0xA0); - if (dtemp & PVI_MODE) { /* PVI, step VID */ - if (currentVid < targetVid) { - while (currentVid < targetVid) { - currentVid++; - if (isNb) - msr.lo = (msr.lo & NB_VID_MASK_OFF) | (currentVid << NB_VID_POS); - else - msr.lo = (msr.lo & CPU_VID_MASK_OFF) | (currentVid << CPU_VID_POS); - wrmsr(0xC0010070, msr); - - /* read F3xD8[VSRampTime] */ - dtemp = pci_read_config32(dev, 0xD8); - vsTimecode = (u8) ((dtemp >> VS_RAMP_T) & 0x7); - vsTime = (int)timeTable[vsTimecode]; - do { - coreDelay(); - vsTime -= 40; - } while (vsTime > 0); - } - } else if (currentVid > targetVid) { - while (currentVid > targetVid) { - currentVid--; - if (isNb) - msr.lo = (msr.lo & NB_VID_MASK_OFF) | (currentVid << NB_VID_POS); - else - msr.lo = (msr.lo & CPU_VID_MASK_OFF) | (currentVid << CPU_VID_POS); - wrmsr(0xC0010070, msr); - - /* read F3xD8[VSRampTime] */ - dtemp = pci_read_config32(dev, 0xD8); - vsTimecode = (u8) ((dtemp >> VS_RAMP_T) & 0x7); - vsTime = (int)timeTable[vsTimecode]; - do { - coreDelay(); - vsTime -= 40; - } while (vsTime > 0); - } - } - } else { /* SVI, slam VID */ - if (isNb) - msr.lo = (msr.lo & NB_VID_MASK_OFF) | (targetVid << NB_VID_POS); - else - msr.lo = (msr.lo & CPU_VID_MASK_OFF) | (targetVid << CPU_VID_POS); - wrmsr(0xC0010070, msr); - - /* read F3xD8[VSRampTime] */ - dtemp = pci_read_config32(dev, 0xD8); - vsTimecode = (u8) ((dtemp >> VS_RAMP_T) & 0x7); - vsTime = (int)timeTable[vsTimecode]; - do { - coreDelay(); - vsTime -= 40; - } while (vsTime > 0); - } } static u32 needs_NB_COF_VID_update(void) @@ -633,8 +594,8 @@ for (i = 0; i < nodes; i++) { u32 cpuRev = mctGetLogicalCPUID(i) ; u32 nbCofVidUpdateDefined = (cpuRev & (AMD_FAM10_LT_D)); - if (nbCofVidUpdateDefined - && (pci_read_config32(NODE_PCI(i, 3), 0x1FC) + if (nbCofVidUpdateDefined + && (pci_read_config32(NODE_PCI(i, 3), 0x1FC) & NB_COF_VID_UPDATE_MASK)) { nb_cof_vid_update = 1; break; @@ -647,31 +608,29 @@ { device_t dev; u32 vid_max; - u32 fid_max=0; + u32 fid_max = 0; u8 nb_cof_vid_update = needs_NB_COF_VID_update(); u8 pvimode; u32 reg1fc; /* Steps 1-6 of BIOS NB COF and VID Configuration - * for SVI and Single-Plane PVI Systems. + * for SVI and Single-Plane PVI Systems. BKDG 2.4.2.9 #31116 rev 3.48 */ dev = NODE_PCI(nodeid, 3); - pvimode = (pci_read_config32(dev, 0xA0) >> 8) & 1; + pvimode = pci_read_config32(dev, PW_CTL_MISC) & PVI_MODE; reg1fc = pci_read_config32(dev, 0x1FC); if (nb_cof_vid_update) { - if (pvimode) { - vid_max = (reg1fc >> 7) & 0x7F; - fid_max = (reg1fc >> 2) & 0x1F; - - /* write newNbVid to P-state Reg's NbVid always if NbVidUpdatedAll=1 */ - fixPsNbVidBeforeWR(vid_max, coreid); - } else { /* SVI */ - vid_max = ((reg1fc >> 7) & 0x7F) - ((reg1fc >> 17) & 0x1F); - fid_max = ((reg1fc >> 2) & 0x1F) + ((reg1fc >> 14) & 0x7); - transitionVid(vid_max, dev, IS_NB); + vid_max = (reg1fc & SINGLE_PLANE_NB_VID_MASK ) >> SINGLE_PLANE_NB_VID_SHIFT ; + fid_max = (reg1fc & SINGLE_PLANE_NB_FID_MASK ) >> SINGLE_PLANE_NB_FID_SHIFT ; + + if (!pvimode) { /* SVI, dual power plane */ + vid_max = vid_max - ((reg1fc & DUAL_PLANE_NB_VID_OFF_MASK ) >> DUAL_PLANE_NB_VID_SHIFT ); + fid_max = fid_max + ((reg1fc & DUAL_PLANE_NB_FID_OFF_MASK ) >> DUAL_PLANE_NB_FID_SHIFT ); } + /* write newNbVid to P-state Reg's NbVid always if NbVidUpdatedAll=1 */ + fixPsNbVidBeforeWR(vid_max, coreid,dev,pvimode); /* fid setup is handled by the BSP at the end. */ @@ -691,7 +650,7 @@ printk(BIOS_DEBUG, "FIDVID on AP: %02x\n", apicid); - send = init_fidvid_core(nodeid,coreid); + send = init_fidvid_core(nodeid,coreid); send |= (apicid << 24); // ap apicid // Send signal to BSP about this AP max fid @@ -812,21 +771,6 @@ } while (msr.lo != StartupPstate); } -static void set_p0(void) -{ - msr_t msr; - - // Transition P0 for calling core. - msr = rdmsr(0xC0010062); - msr.lo = (msr.lo & ~0x07); - wrmsr(0xC0010062, msr); - - /* Wait for P0 to set. */ - do { - msr = rdmsr(0xC0010063); - } while (msr.lo != 0); -} - static void finalPstateChange(void) { /* Enble P0 on all cores for best performance. @@ -834,7 +778,7 @@ * It is safe since they will be in C1 halt * most of the time anyway. */ - set_p0(); + set_pstate(0); } static void init_fidvid_stage2(u32 apicid, u32 nodeid) Modified: trunk/src/northbridge/amd/amdht/AsPsDefs.h ============================================================================== --- trunk/src/northbridge/amd/amdht/AsPsDefs.h Mon Feb 28 03:36:15 2011 (r6400) +++ trunk/src/northbridge/amd/amdht/AsPsDefs.h Mon Feb 28 04:02:40 2011 (r6401) @@ -231,6 +231,16 @@ /* F3x1FC Product Information Register */ #define NB_COF_VID_UPDATE_MASK 1 /* for CPU rev <= C */ +#define SINGLE_PLANE_NB_FID_MASK 0x007c/* for CPU rev <= C */ +#define SINGLE_PLANE_NB_FID_SHIFT 2/* for CPU rev <= C */ +#define SINGLE_PLANE_NB_VID_MASK 0x3f80/* for CPU rev <= C */ +#define SINGLE_PLANE_NB_VID_SHIFT 7/* for CPU rev <= C */ + +#define DUAL_PLANE_NB_FID_OFF_MASK 0x001c000/* for CPU rev <= C */ +#define DUAL_PLANE_NB_FID_SHIFT 14/* for CPU rev <= C */ +#define DUAL_PLANE_NB_VID_OFF_MASK 0x3e0000/* for CPU rev <= C */ +#define DUAL_PLANE_NB_VID_SHIFT 17/* for CPU rev <= C */ + #define NM_PS_REG 5 /* number of P-state MSR registers */ @@ -266,4 +276,9 @@ #define GH_REV_A2 0x4 /* GH Rev A2 logical ID, Upper half */ +#define TSC_MSR 0x10 +#define CUR_PSTATE_MSR 0xc0010063 + +#define WAIT_PSTATE_TIMEOUT 80000000 /* 0.1 s , unit : 1.25 ns */ + #endif Modified: trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c Mon Feb 28 03:36:15 2011 (r6400) +++ trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c Mon Feb 28 04:02:40 2011 (r6401) @@ -339,9 +339,6 @@ { } -static void coreDelay (void); - - #if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */ /* Erratum 350 */ static void vErrata350(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) @@ -408,10 +405,10 @@ static void vErratum372(struct DCTStatStruc *pDCTstat) { msr_t msr = rdmsr(NB_CFG_MSR); - + int nbPstate1supported = ! (msr.hi && (1 << (NB_GfxNbPstateDis -32))) ; - // is this the right way to check for NB pstate 1 or DDR3-1333 ? + // is this the right way to check for NB pstate 1 or DDR3-1333 ? if (((pDCTstat->PresetmaxFreq==1333)||(nbPstate1supported)) &&(!pDCTstat->GangedMode)) { /* DisableCf8ExtCfg */ @@ -423,14 +420,14 @@ static void vErratum414(struct DCTStatStruc *pDCTstat) { int dct=0; - for(; dct < 2 ; dct++) + for(; dct < 2 ; dct++) { - int dRAMConfigHi = Get_NB32(pDCTstat->dev_dct,0x94 + (0x100 * dct)); + int dRAMConfigHi = Get_NB32(pDCTstat->dev_dct,0x94 + (0x100 * dct)); int powerDown = dRAMConfigHi && (1 << PowerDownEn ) ; int ddr3 = dRAMConfigHi && (1 << Ddr3Mode ) ; int dRAMMRS = Get_NB32(pDCTstat->dev_dct,0x84 + (0x100 * dct)); int pchgPDModeSel = dRAMMRS && (1 << PchgPDModeSel ) ; - if (powerDown && ddr3 && pchgPDModeSel ) + if (powerDown && ddr3 && pchgPDModeSel ) { Set_NB32(pDCTstat->dev_dct,0x84 + (0x100 * dct), dRAMMRS & ~(1 << PchgPDModeSel) ); }

1 0

[patch] Kino serial was being disabled in PNP init.
by Marc Jones 27 Feb '11

27 Feb '11

Kino devicetree.cb SIO PNP devices were not matched up with the actual SIO. This fixes the serial device being disabled during PNP init. Signed-off-by: Marc Jones <marcj303(a)gmail.com> -- http://se-eng.com

2 2

[commit] r6400 - trunk/src/mainboard/iei/kino-780am2-fam10
by repository service 27 Feb '11

27 Feb '11

Author: mjones Date: Mon Feb 28 03:36:15 2011 New Revision: 6400 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6400 Log: Kino devicetree.cb SIO PNP devices were not matched up with the actual SIO. This fixes the serial device being disabled during PNP init. Signed-off-by: Marc Jones <marcj303(a)gmail.com> Acked-by: Scott Duplichan <scott(a)notabs.org> Modified: trunk/src/mainboard/iei/kino-780am2-fam10/devicetree.cb Modified: trunk/src/mainboard/iei/kino-780am2-fam10/devicetree.cb ============================================================================== --- trunk/src/mainboard/iei/kino-780am2-fam10/devicetree.cb Mon Feb 28 03:33:59 2011 (r6399) +++ trunk/src/mainboard/iei/kino-780am2-fam10/devicetree.cb Mon Feb 28 03:36:15 2011 (r6400) @@ -51,32 +51,10 @@ device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x439d chip superio/fintek/f71859 - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 + device pnp 2e.3 on # Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 off end # EC - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end end #SIO end #LPC device pci 14.4 on end # PCI 0x4384

1 0

[commit] r6399 - in trunk/src: cpu/amd/model_10xxx northbridge/amd/amdht northbridge/amd/amdmct
by repository service 27 Feb '11

27 Feb '11

Author: mjones Date: Mon Feb 28 03:33:59 2011 New Revision: 6399 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6399 Log: Improving BKDG implementation of P-states, CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. Contemplate the possibility of nbCofVidUpdate not being defined, trying to get closer to BKDG Signed-off-by: Xavi Drudis Ferran <xdrudis(a)tinet.cat> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c trunk/src/northbridge/amd/amdht/AsPsDefs.h trunk/src/northbridge/amd/amdmct/amddefs.h Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 01:31:24 2011 (r6398) +++ trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 03:33:59 2011 (r6399) @@ -631,7 +631,11 @@ nodes = get_nodes(); nb_cof_vid_update = 0; for (i = 0; i < nodes; i++) { - if (pci_read_config32(NODE_PCI(i, 3), 0x1FC) & 1) { + u32 cpuRev = mctGetLogicalCPUID(i) ; + u32 nbCofVidUpdateDefined = (cpuRev & (AMD_FAM10_LT_D)); + if (nbCofVidUpdateDefined + && (pci_read_config32(NODE_PCI(i, 3), 0x1FC) + & NB_COF_VID_UPDATE_MASK)) { nb_cof_vid_update = 1; break; } Modified: trunk/src/northbridge/amd/amdht/AsPsDefs.h ============================================================================== --- trunk/src/northbridge/amd/amdht/AsPsDefs.h Mon Feb 28 01:31:24 2011 (r6398) +++ trunk/src/northbridge/amd/amdht/AsPsDefs.h Mon Feb 28 03:33:59 2011 (r6399) @@ -229,6 +229,8 @@ /* F3x1F0 Product Information Register */ #define NB_PSTATE_MASK 0x00070000 /* NbPstate for CPU rev C3 */ +/* F3x1FC Product Information Register */ +#define NB_COF_VID_UPDATE_MASK 1 /* for CPU rev <= C */ #define NM_PS_REG 5 /* number of P-state MSR registers */ Modified: trunk/src/northbridge/amd/amdmct/amddefs.h ============================================================================== --- trunk/src/northbridge/amd/amdmct/amddefs.h Mon Feb 28 01:31:24 2011 (r6398) +++ trunk/src/northbridge/amd/amdmct/amddefs.h Mon Feb 28 03:33:59 2011 (r6399) @@ -63,6 +63,7 @@ #define AMD_DR_GT_B0 (AMD_DR_ALL & ~(AMD_DR_B0)) #define AMD_DR_ALL (AMD_DR_Bx) #define AMD_FAM10_ALL (AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 ) +#define AMD_FAM10_LT_D (AMD_FAM10_ALL & ~(AMD_HY_D0)) #define AMD_FAM10_GT_B0 (AMD_FAM10_ALL & ~(AMD_DR_B0)) #define AMD_DA_Cx (AMD_DA_C2 | AMD_DA_C3) #define AMD_DR_Cx (AMD_RB_C2 | AMD_RB_C3 | AMD_DA_Cx)

1 0

about Intel calpella board(I3+QM57)
by zxy__1127 27 Feb '11

27 Feb '11

Hello, I have worked on this board two weeks,now it can print from serial port, and stop at ddr3 initialling in file romstage.c. I found it difficult to deal with it. Is there anyone working on it? thanks! 2011-02-28 zxy__1127

1 0

[commit] r6398 - trunk/src/cpu/amd/model_10xxx
by repository service 27 Feb '11

27 Feb '11

Author: mjones Date: Mon Feb 28 01:31:24 2011 New Revision: 6398 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6398 Log: Improving BKDG implementation of P-states, CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. Configuration of F3x[84:80] was hardcoded for rev B. I change that for some code that checks for revision and configures according to BKDG. Unfinished but hopefully better than it was. Signed-off-by: Xavi Drudis Ferran <xdrudis(a)tinet.cat> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 01:24:21 2011 (r6397) +++ trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 01:31:24 2011 (r6398) @@ -343,11 +343,59 @@ pci_write_config32(dev, 0xdc, dword); } -static void config_acpi_pwr_state_ctrl_regs(device_t dev) { - /* Rev B settings - FIXME: support other revs. */ - u32 dword = 0xA0E641E6; +static void config_acpi_pwr_state_ctrl_regs(device_t dev, u32 cpuRev, u8 procPkg) { + /* step 1, chapter 2.4.2.6 of AMD Fam 10 BKDG #31116 Rev 3.48 22.4.2010 */ + u32 dword; + u32 c1= 1; + if (cpuRev & (AMD_DR_Bx)) { + // will coreboot ever enable cache scrubbing ? + // if it does, will it be enough to check the current state + // or should we configure for what we'll set up later ? + dword = pci_read_config32(dev, 0x58); + u32 scrubbingCache = dword & + ( (0x1F << 16) // DCacheScrub + | (0x1F << 8) ); // L2Scrub + if (scrubbingCache) { + c1 = 0x80; + } else { + c1 = 0xA0; + } + } else { // rev C or later + // same doubt as cache scrubbing: ok to check current state ? + dword = pci_read_config32(dev, 0xDC); + u32 cacheFlushOnHalt = dword & (7 << 16); + if (!cacheFlushOnHalt) { + c1 = 0x80; + } + } + dword = (c1 << 24) | (0xE641E6); pci_write_config32(dev, 0x84, dword); - dword = 0xE600A681; + + + /* FIXME: BKDG Table 100 says if the link is at a Gen1 +frequency and the chipset does not support a 10us minimum LDTSTOP +assertion time, then { If ASB2 && SVI then smaf001 = F6h else +smaf001=87h. } else ... I hardly know what it means or how to check +it from here, so I bluntly assume it is false and code here the else, +which is easier */ + + u32 smaf001 = 0xE6; + if (cpuRev & AMD_DR_Bx ) { + smaf001 = 0xA6; + } else { + #if CONFIG_SVI_HIGH_FREQ + if (cpuRev & (AMD_RB_C3 | AMD_DA_C3)) { + smaf001 = 0xF6; + } + #endif + } + u32 fidvidChange = 0; + if (((cpuRev & AMD_DA_Cx) && (procPkg & AMD_PKGTYPE_S1gX)) + || (cpuRev & AMD_RB_C3) ) { + fidvidChange=0x0B; + } + dword = (0xE6 << 24) | (fidvidChange << 16) + | (smaf001 << 8) | 0x81; pci_write_config32(dev, 0x80, dword); } @@ -378,7 +426,7 @@ config_power_ctrl_misc_reg(dev,cpuRev,procPkg); config_nb_syn_ptr_adj(dev,cpuRev); - config_acpi_pwr_state_ctrl_regs(dev); + config_acpi_pwr_state_ctrl_regs(dev,cpuRev,procPkg); dword = pci_read_config32(dev, 0x80); printk(BIOS_DEBUG, " F3x80: %08x \n", dword);

1 0

[commit] r6397 - in trunk/src: cpu/amd/model_10xxx northbridge/amd/amdht
by repository service 27 Feb '11

27 Feb '11

Author: mjones Date: Mon Feb 28 01:24:21 2011 New Revision: 6397 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6397 Log: Improving BKDG implementation of P-states, CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. BKDG says nbSynPtrAdj may also be 6 sometimes. Signed-off-by: Xavi Drudis Ferran <xdrudis(a)tinet.cat> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c trunk/src/northbridge/amd/amdht/AsPsDefs.h Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 01:18:43 2011 (r6396) +++ trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 01:24:21 2011 (r6397) @@ -321,14 +321,26 @@ pci_write_config32(dev, 0xA0, dword); } -static void config_nb_syn_ptr_adj(device_t dev) { +static void config_nb_syn_ptr_adj(device_t dev, u32 cpuRev) { /* Note the following settings are additional from the ported * function setFidVidRegs() */ + /* adjust FIFO between nb and core clocks to max allowed + values (min latency) */ + u32 nbPstate = pci_read_config32(dev,0x1f0) & NB_PSTATE_MASK; + u8 nbSynPtrAdj; + if ((cpuRev & (AMD_DR_Bx|AMD_DA_Cx) ) + || ( (cpuRev & AMD_RB_C3) && (nbPstate!=0))) { + nbSynPtrAdj = 5; + } else { + nbSynPtrAdj = 6; + } + u32 dword = pci_read_config32(dev, 0xDc); - dword |= 0x5 << 12; /* NbsynPtrAdj set to 0x5 per BKDG (needs reset) */ + dword &= ~ NB_SYN_PTR_ADJ_MASK; + dword |= nbSynPtrAdj << NB_SYN_PTR_ADJ_POS; + /* NbsynPtrAdj set to 5 or 6 per BKDG (needs reset) */ pci_write_config32(dev, 0xdc, dword); - } static void config_acpi_pwr_state_ctrl_regs(device_t dev) { @@ -364,7 +376,7 @@ config_clk_power_ctrl_reg0(i,cpuRev,procPkg); config_power_ctrl_misc_reg(dev,cpuRev,procPkg); - config_nb_syn_ptr_adj(dev); + config_nb_syn_ptr_adj(dev,cpuRev); config_acpi_pwr_state_ctrl_regs(dev); Modified: trunk/src/northbridge/amd/amdht/AsPsDefs.h ============================================================================== --- trunk/src/northbridge/amd/amdht/AsPsDefs.h Mon Feb 28 01:18:43 2011 (r6396) +++ trunk/src/northbridge/amd/amdht/AsPsDefs.h Mon Feb 28 01:24:21 2011 (r6397) @@ -181,6 +181,8 @@ #define CPTC2 0xdc /* Clock Power/Timing Control2 Register*/ #define PS_MAX_VAL_POS 8 /* PstateMaxValue bit shift */ #define PS_MAX_VAL_MASK 0xfffff8ff /* PstateMaxValue Mask off */ +#define NB_SYN_PTR_ADJ_POS 12 /* NbsynPtrAdj bit shift */ +#define NB_SYN_PTR_ADJ_MASK (0x7 << NB_SYN_PTR_ADJ_POS) /* NbsynPtrAdj bit mask */ #define PRCT_INFO 0x1fc /* Product Info Register */ #define UNI_NB_FID_BIT 2 /* UniNbFid bit position */ @@ -224,6 +226,10 @@ /* F4x1F4 Northbridge P-state spec register */ #define NB_PS_SPEC_REG 0x1f4 /* Nb PS spec reg */ +/* F3x1F0 Product Information Register */ +#define NB_PSTATE_MASK 0x00070000 /* NbPstate for CPU rev C3 */ + + #define NM_PS_REG 5 /* number of P-state MSR registers */ /* sFidVidInit.outFlags defines */

1 0

[commit] r6396 - in trunk/src: cpu/amd/model_10xxx northbridge/amd/amdfam10 northbridge/amd/amdht northbridge/amd/amdmct
by repository service 27 Feb '11

27 Feb '11

Author: mjones Date: Mon Feb 28 01:18:43 2011 New Revision: 6396 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6396 Log: Improving BKDG implementation of P-states, CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. I didn't understand quite why it did that iwth F3xA0 (Power Control Misc Register) so I moved Pll Lock time to rules in defaults.h and reimplemented F3xA0 programming. A later patch will remove a part I don't know what's mean to do. Signed-off-by: Xavi Drudis Ferran <xdrudis(a)tinet.cat> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/cpu/amd/model_10xxx/defaults.h trunk/src/cpu/amd/model_10xxx/fidvid.c trunk/src/northbridge/amd/amdfam10/Kconfig trunk/src/northbridge/amd/amdht/AsPsDefs.h trunk/src/northbridge/amd/amdmct/amddefs.h Modified: trunk/src/cpu/amd/model_10xxx/defaults.h ============================================================================== --- trunk/src/cpu/amd/model_10xxx/defaults.h Mon Feb 28 01:10:37 2011 (r6395) +++ trunk/src/cpu/amd/model_10xxx/defaults.h Mon Feb 28 01:18:43 2011 (r6396) @@ -68,7 +68,7 @@ 1 << 24, 0x00000000, 1 << 24, 0x00000000 }, /* Erratum #261 [DIS_PIGGY_BACK_SCRUB]=1 */ - { LS_CFG, AMD_FAM10_GT_B0, AMD_PTYPE_ALL, + { LS_CFG, AMD_DR_GT_B0, AMD_PTYPE_ALL, 0 << 1, 0x00000000, 1 << 1, 0x00000000 }, /* IDX_MATCH_ALL=0 */ @@ -261,8 +261,11 @@ { 3, 0xA0, AMD_FAM10_ALL, AMD_PTYPE_MOB | AMD_PTYPE_DSK, 0x00000080, 0x00000080 }, /* [7] PSIVidEnable */ - { 3, 0xA0, AMD_FAM10_ALL, AMD_PTYPE_ALL, - 0x00001800, 0x000003800 }, /* [13:11] PllLockTime = 3 */ + { 3, 0xA0, AMD_DR_Bx, AMD_PTYPE_ALL, + 0x00002800, 0x000003800 }, /* [13:11] PllLockTime = 5 */ + + { 3, 0xA0, (AMD_FAM10_ALL & ~(AMD_DR_Bx)), AMD_PTYPE_ALL, + 0x00000800, 0x000003800 }, /* [13:11] PllLockTime = 1 */ /* Reported Temp Control Register */ { 3, 0xA4, AMD_FAM10_ALL, AMD_PTYPE_ALL, Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 01:10:37 2011 (r6395) +++ trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 01:18:43 2011 (r6396) @@ -275,19 +275,18 @@ } -static void config_power_ctrl_misc_reg(device_t dev) { +static void config_power_ctrl_misc_reg(device_t dev,u32 cpuRev, u8 procPkg) { /* check PVI/SVI */ u32 dword = pci_read_config32(dev, 0xA0); + + /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xA0[VSSlamVidMod] */ + /* PllLockTime and PsiVidEn set in ruleset in defaults.h */ if (dword & PVI_MODE) { /* PVI */ /* set slamVidMode to 0 for PVI */ - dword &= VID_SLAM_OFF | PLLLOCK_OFF; - dword |= PLLLOCK_DFT_L; - pci_write_config32(dev, 0xA0, dword); + dword &= VID_SLAM_OFF ; } else { /* SVI */ /* set slamVidMode to 1 for SVI */ - dword &= PLLLOCK_OFF; - dword |= PLLLOCK_DFT_L | VID_SLAM_ON; - pci_write_config32(dev, 0xA0, dword); + dword |= VID_SLAM_ON; u32 dtemp = dword; @@ -299,7 +298,27 @@ else dword &= PWR_PLN_OFF; pci_write_config32(dev, 0xD8, dword); + + dword = dtemp; + } + /* set the rest of A0 since we're at it... */ + + if (cpuRev & (AMD_DA_Cx | AMD_RB_C3 )) { + dword |= NB_PSTATE_FORCE_ON; + } // else should we clear it ? + + + if ((procPkg == AMD_PKGTYPE_G34) || (procPkg == AMD_PKGTYPE_C32) ) { + dword |= BP_INS_TRI_EN_ON ; } + + /* TODO: look into C1E state and F3xA0[IdleExitEn]*/ + #if CONFIG_SVI_HIGH_FREQ + if (cpuRev & AMD_FAM10_C3) { + dword |= SVI_HIGH_FREQ_ON; + } + #endif + pci_write_config32(dev, 0xA0, dword); } static void config_nb_syn_ptr_adj(device_t dev) { @@ -344,8 +363,7 @@ config_clk_power_ctrl_reg0(i,cpuRev,procPkg); - config_power_ctrl_misc_reg(dev); - + config_power_ctrl_misc_reg(dev,cpuRev,procPkg); config_nb_syn_ptr_adj(dev); config_acpi_pwr_state_ctrl_regs(dev); Modified: trunk/src/northbridge/amd/amdfam10/Kconfig ============================================================================== --- trunk/src/northbridge/amd/amdfam10/Kconfig Mon Feb 28 01:10:37 2011 (r6395) +++ trunk/src/northbridge/amd/amdfam10/Kconfig Mon Feb 28 01:18:43 2011 (r6396) @@ -112,4 +112,12 @@ endif endif +config SVI_HIGH_FREQ + bool + default n + depends on NORTHBRIDGE_AMD_AMDFAM10 + help + Select this for boards with a Voltage Regulator able to operate + at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3. + source src/northbridge/amd/amdfam10/root_complex/Kconfig Modified: trunk/src/northbridge/amd/amdht/AsPsDefs.h ============================================================================== --- trunk/src/northbridge/amd/amdht/AsPsDefs.h Mon Feb 28 01:10:37 2011 (r6395) +++ trunk/src/northbridge/amd/amdht/AsPsDefs.h Mon Feb 28 01:18:43 2011 (r6396) @@ -198,11 +198,19 @@ #define PVI_MODE 0x100 /* PviMode bit mask */ #define VID_SLAM_OFF 0x0dfffffff /* set VidSlamMode OFF */ #define VID_SLAM_ON 0x020000000 /* set VidSlamMode ON */ +#define NB_PSTATE_FORCE_ON 0x010000000 /* set Northbridge P-state + force on next LDTSTOP + assertion on, in F3xA0 */ +#define BP_INS_TRI_EN_ON 0x00004000 /* breakpoint pins tristate + enable in F3xA0 */ #define PLLLOCK_OFF 0x0ffffc7ff /* PllLockTime Mask OFF */ #define PLLLOCK_DFT 0x00001800 /* PllLockTime default value = 011b */ #define PLLLOCK_DFT_L 0x00002800 /* PllLockTime long value = 101b */ -/* P-state Specification register base in PCI sapce */ +#define SVI_HIGH_FREQ_ON 0x00000200 /* F3xA0[SviHighFreqSel] for + 3.4 MHz SVI in rev. C3 */ + +/* P-state Specification register base in PCI space */ #define PS_SPEC_REG 0x1e0 /* PS Spec register base address */ #define PCI_REG_LEN 4 /* PCI register length */ #define NB_DID_MASK 0x10000 /* NbDid bit mask */ Modified: trunk/src/northbridge/amd/amdmct/amddefs.h ============================================================================== --- trunk/src/northbridge/amd/amdmct/amddefs.h Mon Feb 28 01:10:37 2011 (r6395) +++ trunk/src/northbridge/amd/amdmct/amddefs.h Mon Feb 28 01:18:43 2011 (r6396) @@ -64,7 +64,9 @@ #define AMD_DR_ALL (AMD_DR_Bx) #define AMD_FAM10_ALL (AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 ) #define AMD_FAM10_GT_B0 (AMD_FAM10_ALL & ~(AMD_DR_B0)) -#define AMD_DR_Cx (AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3) +#define AMD_DA_Cx (AMD_DA_C2 | AMD_DA_C3) +#define AMD_DR_Cx (AMD_RB_C2 | AMD_RB_C3 | AMD_DA_Cx) +#define AMD_FAM10_C3 (AMD_RB_C3 | AMD_DA_C3) #define AMD_DR_Dx (AMD_HY_D0) #define AMD_DRBH_Cx (AMD_DR_Cx | AMD_HY_D0 ) #define AMD_DRBA23_RBC2 (AMD_DR_BA | AMD_DR_B2 | AMD_DR_B3 | AMD_RB_C2 )

1 0

[commit] r6395 - in trunk/src: cpu/amd/model_10xxx northbridge/amd/amdfam10 northbridge/amd/amdht northbridge/amd/amdmct
by repository service 27 Feb '11

27 Feb '11

Author: mjones Date: Mon Feb 28 01:10:37 2011 New Revision: 6395 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6395 Log: Improving BKDG implementation of P-states, CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. Bring F3xD4 (Clock/Power Control Register 0) more in line with BKDG i more cases. It requires looking at the CPU package type so I add a function for that (in the wrong place?) and some new constants Signed-off-by: Xavi Drudis Ferran <xdrudis(a)tinet.cat> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c trunk/src/northbridge/amd/amdht/AsPsDefs.h trunk/src/northbridge/amd/amdmct/amddefs.h Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 01:00:51 2011 (r6394) +++ trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 01:10:37 2011 (r6395) @@ -179,16 +179,51 @@ pci_write_config32(dev, 0xd8, dtemp); } -static u32 power_up_down(int node) { +static u32 nb_clk_did(int node, u32 cpuRev,u8 procPkg) { + u8 link0isGen3 = 0; + u8 offset; + if (AMD_CpuFindCapability(node, 0, &offset)) { + link0isGen3 = (AMD_checkLinkType(node, 0, offset) & HTPHY_LINKTYPE_HT3 ); + } + /* FIXME: NB_CLKDID should be 101b for AMD_DA_C2 in package + S1g3 in link Gen3 mode, but I don't know how to tell + package S1g3 from S1g4 */ + if ((cpuRev & AMD_DA_C2) && (procPkg & AMD_PKGTYPE_S1gX) + && link0isGen3) { + return 5 ; /* divide clk by 128*/ + } else { + return 4 ; /* divide clk by 16 */ + } +} + + +static u32 power_up_down(int node, u8 procPkg) { u32 dword=0; - /* check platform type */ - if (!(get_platform_type() & AMD_PTYPE_SVR)) { - /* For non-server platform - * PowerStepUp=01000b - 50nS - * PowerStepDown=01000b - 50ns - */ - dword |= PW_STP_UP50 | PW_STP_DN50 ; + /* from CPU rev guide #41322 rev 3.74 June 2010 Table 26 */ + u8 singleLinkFlag = ((procPkg == AMD_PKGTYPE_AM3_2r2) + || (procPkg == AMD_PKGTYPE_S1gX) + || (procPkg == AMD_PKGTYPE_ASB2)); + + if (singleLinkFlag) { + /* + * PowerStepUp=01000b - 50nS + * PowerStepDown=01000b - 50ns + */ + dword |= PW_STP_UP50 | PW_STP_DN50; } else { + u32 dispRefModeEn = (pci_read_config32(NODE_PCI(node,0),0x68) >> 24) & 1; + u32 isocEn = 0; + int j; + for(j=0 ; (j<4) && (!isocEn) ; j++ ) { + u8 offset; + if (AMD_CpuFindCapability(node, j, &offset)) { + isocEn = (pci_read_config32(NODE_PCI(node,0),offset+4) >>12) & 1; + } + } + + if (dispRefModeEn || isocEn) { + dword |= PW_STP_UP50 | PW_STP_DN50 ; + } else { /* get number of cores for PowerStepUp & PowerStepDown in server 1 core - 400nS - 0000b 2 cores - 200nS - 0010b @@ -210,28 +245,31 @@ dword |= PW_STP_UP100 | PW_STP_DN100; break; } + } } return dword; } -static void config_clk_power_ctrl_reg0(int node) { +static void config_clk_power_ctrl_reg0(int node, u32 cpuRev, u8 procPkg) { device_t dev = NODE_PCI(node, 3); - /* Program fields in Clock Power/Control register0 (F3xD4) */ /* set F3xD4 Clock Power/Timing Control 0 Register * NbClkDidApplyAll=1b - * NbClkDid=100b + * NbClkDid=100b or 101b * PowerStepUp= "platform dependent" * PowerStepDown= "platform dependent" * LinkPllLink=01b - * ClkRampHystSel=HW default + * ClkRampHystCtl=HW default + * ClkRampHystSel=1111b */ u32 dword= pci_read_config32(dev, 0xd4); dword &= CPTC0_MASK; - dword |= NB_CLKDID_ALL | NB_CLKDID | LNK_PLL_LOCK; /* per BKDG */ - dword |= power_up_down(node); + dword |= NB_CLKDID_ALL | LNK_PLL_LOCK | CLK_RAMP_HYST_SEL_VAL; + dword |= (nb_clk_did(node,cpuRev,procPkg) << NB_CLKDID_SHIFT); + + dword |= power_up_down(node, procPkg); pci_write_config32(dev, 0xd4, dword); @@ -296,13 +334,15 @@ for (i = 0; i < nodes; i++) { printk(BIOS_DEBUG, "Prep FID/VID Node:%02x \n", i); dev = NODE_PCI(i, 3); + u32 cpuRev = mctGetLogicalCPUID(0xFF) ; + u8 procPkg = mctGetProcessorPackageType(); setVSRamp(dev); /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSSlamTime] */ /* Figure out the value for VsSlamTime and program it */ recalculateVsSlamTimeSettingOnCorePre(dev); - config_clk_power_ctrl_reg0(i); + config_clk_power_ctrl_reg0(i,cpuRev,procPkg); config_power_ctrl_misc_reg(dev); Modified: trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c Mon Feb 28 01:00:51 2011 (r6394) +++ trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c Mon Feb 28 01:10:37 2011 (r6395) @@ -214,6 +214,11 @@ return ret; } +static u8 mctGetProcessorPackageType(void) { + /* FIXME: I guess this belongs wherever mctGetLogicalCPUID ends up ? */ + u32 BrandId = cpuid_ebx(0x80000001); + return (u8)((BrandId >> 28) & 0x0F); +} static void raminit_amdmct(struct sys_info *sysinfo) { Modified: trunk/src/northbridge/amd/amdht/AsPsDefs.h ============================================================================== --- trunk/src/northbridge/amd/amdht/AsPsDefs.h Mon Feb 28 01:00:51 2011 (r6394) +++ trunk/src/northbridge/amd/amdht/AsPsDefs.h Mon Feb 28 01:10:37 2011 (r6395) @@ -111,6 +111,7 @@ #define NB_FID_EN 0x20 /* NbFidEn bit ON */ #define NB_CLKDID_ALL 0x80000000 /* NbClkDidApplyAll bit ON */ #define NB_CLKDID 0x40000000 /* NbClkDid value set by BIOS */ +#define NB_CLKDID_SHIFT 28 /* NbClkDid bit shift */ #define PW_STP_UP50 0x08000000 /* PowerStepUp 50nS(1000b) */ #define PW_STP_DN50 0x00800000 /* PowerStepDown 50nS (1000b)*/ #define PW_STP_UP100 0x03000000 /* PowerStepUp 100nS(0011b) */ @@ -119,6 +120,11 @@ #define PW_STP_DN200 0x00200000 /* PowerStepDown 200nS (0010b)*/ #define PW_STP_UP400 0x00000000 /* PowerStepUp 400nS(0000b) */ #define PW_STP_DN400 0x00000000 /* PowerStepDown 400nS (0000b)*/ +#define CLK_RAMP_HYST_SEL_VAL 0x00000f00 /* value mask for clock ramp + hysteresis select. BIOS + should program + F3xC4[ClkRampHystSel] to + 1111b */ #define LNK_PLL_LOCK 0x00010000 /* LnkPllLock value set (01b) by BIOS */ Modified: trunk/src/northbridge/amd/amdmct/amddefs.h ============================================================================== --- trunk/src/northbridge/amd/amdmct/amddefs.h Mon Feb 28 01:00:51 2011 (r6394) +++ trunk/src/northbridge/amd/amdmct/amddefs.h Mon Feb 28 01:10:37 2011 (r6395) @@ -134,3 +134,13 @@ #define DC_CFG 0xC0011022 #define BU_CFG 0xC0011023 #define BU_CFG2 0xC001102A + +/* + * Processor package types + */ +#define AMD_PKGTYPE_FrX_1207 0 +#define AMD_PKGTYPE_AM3_2r2 1 +#define AMD_PKGTYPE_S1gX 2 +#define AMD_PKGTYPE_G34 3 +#define AMD_PKGTYPE_ASB2 4 +#define AMD_PKGTYPE_C32 5

1 0

[commit] r6394 - trunk/src/cpu/amd/model_10xxx
by repository service 27 Feb '11

27 Feb '11

Author: mjones Date: Mon Feb 28 01:00:51 2011 New Revision: 6394 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6394 Log: Prepare for next patches (Improving BKDG implementation of P-states, CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode). No change of behaviour intended. Refactor FAM10 fidvid . Factor out the decision whether to update northbridge frequency and voltage because there was the same code in 3 places and so we can later modify it in one place. Signed-off-by: Xavi Drudis Ferran <xdrudis(a)tinet.cat> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 00:58:34 2011 (r6393) +++ trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 01:00:51 2011 (r6394) @@ -280,7 +280,6 @@ pci_write_config32(dev, 0x84, dword); dword = 0xE600A681; pci_write_config32(dev, 0x80, dword); - } static void prep_fid_change(void) @@ -522,24 +521,19 @@ return nb_cof_vid_update; } -static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid) +static u32 init_fidvid_core(u32 nodeid, u32 coreid) { device_t dev; u32 vid_max; - u32 fid_max; + u32 fid_max=0; u8 nb_cof_vid_update = needs_NB_COF_VID_update(); u8 pvimode; u32 reg1fc; - u32 send; - - printk(BIOS_DEBUG, "FIDVID on AP: %02x\n", apicid); /* Steps 1-6 of BIOS NB COF and VID Configuration * for SVI and Single-Plane PVI Systems. */ - - dev = NODE_PCI(nodeid, 3); pvimode = (pci_read_config32(dev, 0xA0) >> 8) & 1; reg1fc = pci_read_config32(dev, 0x1FC); @@ -565,7 +559,17 @@ UpdateSinglePlaneNbVid(); } - send = (nb_cof_vid_update << 16) | (fid_max << 8); + return ((nb_cof_vid_update << 16) | (fid_max << 8)); + +} + +static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid) +{ + u32 send; + + printk(BIOS_DEBUG, "FIDVID on AP: %02x\n", apicid); + + send = init_fidvid_core(nodeid,coreid); send |= (apicid << 24); // ap apicid // Send signal to BSP about this AP max fid @@ -783,48 +787,15 @@ u32 i; #endif struct fidvid_st fv; - device_t dev; - u32 vid_max; - u32 fid_max=0; - u8 nb_cof_vid_update = needs_NB_COF_VID_update(); - u32 reg1fc; - u8 pvimode; printk(BIOS_DEBUG, "FIDVID on BSP, APIC_id: %02x\n", bsp_apicid); - /* FIXME: The first half of this function is nearly the same as - * init_fidvid_bsp() and the code could be combined. - */ /* Steps 1-6 of BIOS NB COF and VID Configuration * for SVI and Single-Plane PVI Systems. */ - dev = NODE_PCI(0, 3); - pvimode = (pci_read_config32(dev, 0xA0) >> 8) & 1; - reg1fc = pci_read_config32(dev, 0x1FC); - - if (nb_cof_vid_update) { - if (pvimode) { - vid_max = (reg1fc >> 7) & 0x7F; - fid_max = (reg1fc >> 2) & 0x1F; - - /* write newNbVid to P-state Reg's NbVid always if NbVidUpdatedAll=1 */ - fixPsNbVidBeforeWR(vid_max, 0); - } else { /* SVI */ - vid_max = ((reg1fc >> 7) & 0x7F) - ((reg1fc >> 17) & 0x1F); - fid_max = ((reg1fc >> 2) & 0x1F) + ((reg1fc >> 14) & 0x7); - transitionVid(vid_max, dev, IS_NB); - } - - /* fid setup is handled by the BSP at the end. */ - - } else { /* ! nb_cof_vid_update */ - /* Use max values */ - if (pvimode) - UpdateSinglePlaneNbVid(); - } + fv.common_fid = init_fidvid_core(0,0); - fv.common_fid = (nb_cof_vid_update << 16) | (fid_max << 8); print_debug_fv("BSP fid = ", fv.common_fid); #if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST && !CONFIG_SET_FIDVID_CORE0_ONLY

1 0

← Newer
1
2
3
4
5
6
7
8
9
...
29
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot February 2011