coreboot February 2011

coreboot@coreboot.org

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Issue mainboard asus a8n-e
by ors 06 Mar '11

06 Mar '11

Author: raby71 Date: Mon Feb 28 22:00 2011 last Revision: 6380 hi all I try to work my board (asus a8n-e) with coreboot. I compiled coreboot with a debian 5.07 installation. After flashing the bios-chip with flashrom, the system starts, also the monitor until to boot-promt (or payload terminal) but is not possible to type anything with keyboard (usb or ps/2) to monitor, simply: i'm not able to take further actions. I compiled coreboot with payloads filo grub2 and seabios, but i have in all my tries the same effect. Can everyone help me? I have also the coreboot.log here. I got them with a serial-null-modem cable. Terminal ready coreboot-4.0-r- Sat Feb 26 16:25:25 CST 2011 starting... Enabling routing table for node 00 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done core0 started: started ap apicid: SBLink=00 NC node|link=00 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x35 pos=0x52, unfiltered freq_cap=0x807f pos=0x52, filtered freq_cap=0x7f freq_cap1=0x35, freq_cap2=0x7f dev1 old_freq=0x5, freq=0x5, needs_reset=0x0 dev2 old_freq=0x5, freq=0x5, needs_reset=0x0 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 SMBus controller enabled Ram1.00 setting up CPU00 northbridge registers done. Ram2.00 Enabling dual channel memory Unbuffered 166Mhz Interleaved RAM end at 0x00100000 kB Lower RAM end at 0x00100000 kB Ram3 Initializing memory: done Handling memory hole at 0x00300000 (default) Ram4 v_esp=000cfdb8 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Loading image. Check CBFS header at fffffcfe magic is 4f524243 Found CBFS header at fffffcfe Check cmos_layout.bin CBFS: follow chain: fff80000 + 28 + 6f3 + align -> fff80740 Check fallback/romstage CBFS: follow chain: fff80740 + 38 + 7eca + align -> fff88680 Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x100000 (245760 bytes), entry @ 0x100000 Stage: done loading. Jumping to image. coreboot-4.0-r- Sat Feb 26 16:25:25 CST 2011 booting... Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 0 PNP: 002e.3: enabled 1 PNP: 002e.4: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 1 PNP: 002e.7: enabled 1 PNP: 002e.8: enabled 1 PNP: 002e.9: enabled 1 PNP: 002e.a: enabled 0 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:04.0: enabled 1 PCI: 00:04.1: enabled 0 PCI: 00:06.0: enabled 1 PCI: 00:07.0: enabled 1 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:0a.0: enabled 1 PCI: 00:0b.0: enabled 1 PCI: 00:0c.0: enabled 1 PCI: 00:0d.0: enabled 1 PCI: 00:0e.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 Compare with tree... Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 0 PNP: 002e.3: enabled 1 PNP: 002e.4: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 1 PNP: 002e.7: enabled 1 PNP: 002e.8: enabled 1 PNP: 002e.9: enabled 1 PNP: 002e.a: enabled 0 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:04.0: enabled 1 PCI: 00:04.1: enabled 0 PCI: 00:06.0: enabled 1 PCI: 00:07.0: enabled 1 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:0a.0: enabled 1 PCI: 00:0b.0: enabled 1 PCI: 00:0c.0: enabled 1 PCI: 00:0d.0: enabled 1 PCI: 00:0e.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 scan_static_bus for Root Device APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 scanning... PCI: 00:18.3 siblings=0 Found Rev E or Rev F later single core CPU: APIC: 00 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:18.0 [1022/1100] bus ops PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled PCI: Using configuration type 1 PCI: 00:00.0 [10de/005e] ops PCI: 00:00.0 [10de/005e] enabled Capability: type 0x08 @ 0x44 flags: 0x01e0 PCI: 00:00.0 count: 000f static_count: 000f PCI: 00:00.0 [10de/005e] enabled next_unitid: 000f PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [10de/005e] enabled PCI: 00:01.0 [10de/0050] bus ops PCI: 00:01.0 [10de/0050] enabled PCI: 00:01.1 [10de/0052] bus ops PCI: 00:01.1 [10de/0052] enabled PCI: 00:02.0 [10de/005a] ops PCI: 00:02.0 [10de/005a] enabled PCI: 00:02.1 [10de/005b] ops PCI: 00:02.1 [10de/005b] enabled PCI: 00:04.0 [10de/0059] ops PCI: 00:04.0 [10de/0059] enabled PCI: 00:04.1 [10de/0058] ops PCI: 00:04.1 [10de/0058] disabled PCI: 00:06.0 [10de/0053] ops PCI: 00:06.0 [10de/0053] enabled PCI: 00:07.0 [10de/0054] ops PCI: 00:07.0 [10de/0054] enabled PCI: 00:08.0 [10de/0055] ops PCI: 00:08.0 [10de/0055] enabled PCI: 00:09.0 [10de/005c] bus ops PCI: 00:09.0 [10de/005c] enabled PCI: 00:0a.0 [10de/0057] ops PCI: 00:0a.0 [10de/0057] enabled PCI: 00:0b.0 [10de/005d] bus ops PCI: 00:0b.0 [10de/005d] enabled PCI: 00:0c.0 [10de/005d] bus ops PCI: 00:0c.0 [10de/005d] enabled PCI: 00:0d.0 [10de/005d] bus ops PCI: 00:0d.0 [10de/005d] enabled PCI: 00:0e.0 [10de/005d] bus ops PCI: 00:0e.0 [10de/005d] enabled scan_static_bus for PCI: 00:01.0 PNP: 002e.0 enabled PNP: 002e.1 enabled PNP: 002e.2 disabled PNP: 002e.3 enabled PNP: 002e.4 enabled PNP: 002e.5 enabled PNP: 002e.6 enabled PNP: 002e.7 enabled PNP: 002e.8 enabled PNP: 002e.9 enabled PNP: 002e.a disabled scan_static_bus for PCI: 00:01.0 done scan_static_bus for PCI: 00:01.1 scan_static_bus for PCI: 00:01.1 done do_pci_scan_bridge for PCI: 00:09.0 PCI: pci_scan_bus for bus 01 PCI: 01:06.0 [10de/002c] enabled PCI: pci_scan_bus returning with max=001 do_pci_scan_bridge returns max 1 do_pci_scan_bridge for PCI: 00:0b.0 PCI: pci_scan_bus for bus 02 PCI: pci_scan_bus returning with max=002 do_pci_scan_bridge returns max 2 do_pci_scan_bridge for PCI: 00:0c.0 PCI: pci_scan_bus for bus 03 PCI: pci_scan_bus returning with max=003 do_pci_scan_bridge returns max 3 do_pci_scan_bridge for PCI: 00:0d.0 PCI: pci_scan_bus for bus 04 PCI: pci_scan_bus returning with max=004 do_pci_scan_bridge returns max 4 do_pci_scan_bridge for PCI: 00:0e.0 PCI: pci_scan_bus for bus 05 PCI: pci_scan_bus returning with max=005 do_pci_scan_bridge returns max 5 PCI: pci_scan_bus returning with max=005 PCI: pci_scan_bus returning with max=005 PCI_DOMAIN: 0000 passpw: enabled scan_static_bus for Root Device done done Setting up VGA for PCI: 01:06.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:09.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 APIC_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC_CLUSTER: 0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 VGA: PCI: 00:18.0 (aka node 0) link 0 has VGA device PCI: 00:18.0 read_resources bus 0 link: 0 PCI: 00:01.0 read_resources bus 0 link: 0 PCI: 00:01.0 read_resources bus 0 link: 0 done PCI: 00:09.0 read_resources bus 1 link: 0 PCI: 00:09.0 read_resources bus 1 link: 0 done PCI: 00:0b.0 read_resources bus 2 link: 0 PCI: 00:0b.0 read_resources bus 2 link: 0 done PCI: 00:0c.0 read_resources bus 3 link: 0 PCI: 00:0c.0 read_resources bus 3 link: 0 done PCI: 00:0d.0 read_resources bus 4 link: 0 PCI: 00:0d.0 read_resources bus 4 link: 0 done PCI: 00:0e.0 read_resources bus 5 link: 0 PCI: 00:0e.0 read_resources bus 5 link: 0 done PCI: 00:18.0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:18.0 child on link 0 PCI: 00:00.0 PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 0 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 2 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80200 index 1 PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit ffffffff flags c0000200 index 4 PCI: 00:00.0 PCI: 00:01.0 child on link 0 PNP: 002e.0 PCI: 00:01.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 10 PCI: 00:01.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 60 PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 64 PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 68 PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:01.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit fff flags c0000100 index 60 PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 002e.1 PNP: 002e.1 resource base 3f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60 PNP: 002e.1 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.2 PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60 PNP: 002e.2 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.3 PNP: 002e.3 resource base 378 size 4 align 2 gran 2 limit fff flags c0000100 index 60 PNP: 002e.3 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 002e.4 PNP: 002e.4 resource base 290 size 8 align 3 gran 3 limit fff flags c0000100 index 60 PNP: 002e.4 resource base 0 size 8 align 3 gran 3 limit fff flags c0000100 index 62 PNP: 002e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60 PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62 PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 resource base 2 size 0 align 0 gran 0 limit 0 flags c0000400 index 71 PNP: 002e.6 PNP: 002e.6 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.6 resource base 2 size 0 align 0 gran 0 limit 0 flags c0000400 index 71 PNP: 002e.7 PNP: 002e.7 resource base 800 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60 PNP: 002e.7 resource base 0 size 0 align 0 gran 0 limit 0 flags c0000100 index 25 PNP: 002e.7 resource base 2540 size 0 align 0 gran 0 limit 0 flags c0000100 index 27 PNP: 002e.7 resource base 2100 size 0 align 0 gran 0 limit 0 flags c0000100 index b2 PNP: 002e.7 resource base 100 size 0 align 0 gran 0 limit 0 flags c0000100 index ba PNP: 002e.7 resource base 0 size 0 align 0 gran 0 limit 0 flags c0000100 index c0 PNP: 002e.7 resource base 2540 size 0 align 0 gran 0 limit 0 flags c0000100 index c2 PNP: 002e.7 resource base 0 size 0 align 0 gran 0 limit 0 flags c0000100 index c8 PNP: 002e.7 resource base 500 size 0 align 0 gran 0 limit 0 flags c0000100 index ca PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62 PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 64 PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.8 PNP: 002e.8 resource base 300 size 8 align 3 gran 3 limit fff flags c0000100 index 60 PNP: 002e.8 resource base a size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.9 PNP: 002e.9 resource base 201 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60 PNP: 002e.a PNP: 002e.a resource base 310 size 8 align 3 gran 3 limit fff flags c0000100 index 60 PNP: 002e.a resource base b size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PCI: 00:01.1 PCI: 00:01.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 10 PCI: 00:01.1 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20 PCI: 00:01.1 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 24 PCI: 00:02.0 PCI: 00:02.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:02.1 PCI: 00:02.1 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 PCI: 00:04.0 PCI: 00:04.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10 PCI: 00:04.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 14 PCI: 00:04.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 18 PCI: 00:04.1 PCI: 00:06.0 PCI: 00:06.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:07.0 PCI: 00:07.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:07.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:07.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:07.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:07.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:07.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 24 PCI: 00:08.0 PCI: 00:08.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:08.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:08.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:08.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:08.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 24 PCI: 00:09.0 child on link 0 PCI: 01:06.0 PCI: 00:09.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24 PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 01:06.0 PCI: 01:06.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 10 PCI: 01:06.0 resource base 0 size 2000000 align 25 gran 25 limit ffffffff flags 1200 index 14 PCI: 01:06.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 PCI: 00:0a.0 PCI: 00:0a.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:0a.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 14 PCI: 00:0b.0 PCI: 00:0b.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:0b.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:0b.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:0c.0 PCI: 00:0c.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:0d.0 PCI: 00:0d.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:0e.0 PCI: 00:0e.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:0e.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:0e.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94 PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:09.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:09.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:0b.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:0b.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:0c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:0c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:0d.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:0d.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:0e.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:0e.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:01.0 60 * [0x0 - 0xff] io PCI: 00:01.0 64 * [0x400 - 0x4ff] io PCI: 00:01.0 68 * [0x800 - 0x8ff] io PCI: 00:04.0 10 * [0xc00 - 0xcff] io PCI: 00:04.0 14 * [0x1000 - 0x10ff] io PCI: 00:01.0 10 * [0x1400 - 0x147f] io PCI: 00:01.1 20 * [0x1480 - 0x14bf] io PCI: 00:01.1 24 * [0x14c0 - 0x14ff] io PCI: 00:01.1 10 * [0x1800 - 0x181f] io PCI: 00:06.0 20 * [0x1820 - 0x182f] io PCI: 00:07.0 20 * [0x1830 - 0x183f] io PCI: 00:08.0 20 * [0x1840 - 0x184f] io PNP: 002e.7 62 * [0x1850 - 0x1857] io PNP: 002e.7 64 * [0x1858 - 0x185f] io PCI: 00:07.0 10 * [0x1860 - 0x1867] io PCI: 00:07.0 18 * [0x1868 - 0x186f] io PCI: 00:08.0 10 * [0x1870 - 0x1877] io PCI: 00:08.0 18 * [0x1878 - 0x187f] io PCI: 00:0a.0 14 * [0x1880 - 0x1887] io PCI: 00:07.0 14 * [0x1888 - 0x188b] io PCI: 00:07.0 1c * [0x188c - 0x188f] io PCI: 00:08.0 14 * [0x1890 - 0x1893] io PCI: 00:08.0 1c * [0x1894 - 0x1897] io PCI: 00:18.0 compute_resources_io: base: 1898 size: 2000 align: 12 gran: 12 limit: fff done PCI: 00:18.0 00 * [0x0 - 0x1fff] io PCI_DOMAIN: 0000 compute_resources_io: base: 2000 size: 2000 align: 12 gran: 0 limit: fff done PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:09.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:06.0 14 * [0x0 - 0x1ffffff] prefmem PCI: 00:09.0 compute_resources_prefmem: base: 2000000 size: 2000000 align: 25 gran: 20 limit: ffffffff done PCI: 00:0b.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:0b.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:0c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:0c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:0d.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:0d.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:0e.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:0e.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:09.0 24 * [0x0 - 0x1ffffff] prefmem PCI: 00:18.0 compute_resources_prefmem: base: 2000000 size: 2000000 align: 25 gran: 20 limit: ffffffff done PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:09.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:06.0 10 * [0x0 - 0xffffff] mem PCI: 01:06.0 30 * [0x1000000 - 0x100ffff] mem PCI: 00:09.0 compute_resources_mem: base: 1010000 size: 1100000 align: 24 gran: 20 limit: ffffffff done PCI: 00:0b.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:0b.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:0c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:0c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:0d.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:0d.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:0e.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:0e.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:09.0 20 * [0x0 - 0x10fffff] mem PCI: 00:01.0 14 * [0x1100000 - 0x1100fff] mem PCI: 00:02.0 10 * [0x1101000 - 0x1101fff] mem PCI: 00:04.0 18 * [0x1102000 - 0x1102fff] mem PCI: 00:07.0 24 * [0x1103000 - 0x1103fff] mem PCI: 00:08.0 24 * [0x1104000 - 0x1104fff] mem PCI: 00:0a.0 10 * [0x1105000 - 0x1105fff] mem PCI: 00:02.1 10 * [0x1106000 - 0x11060ff] mem PCI: 00:18.0 compute_resources_mem: base: 1106100 size: 1200000 align: 24 gran: 20 limit: ffffffff done PCI: 00:18.3 94 * [0x0 - 0x3ffffff] mem PCI: 00:18.0 02 * [0x4000000 - 0x5ffffff] prefmem PCI: 00:18.0 01 * [0x6000000 - 0x71fffff] mem PCI_DOMAIN: 0000 compute_resources_mem: base: 7200000 size: 7200000 align: 26 gran: 0 limit: ffffffff done avoid_fixed_resources: PCI_DOMAIN: 0000 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 00000fff avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI_DOMAIN: 0000 constrain_resources: PCI: 00:18.0 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:01.0 constrain_resources: PNP: 002e.0 constrain_resources: PNP: 002e.1 constrain_resources: PNP: 002e.3 constrain_resources: PNP: 002e.4 constrain_resources: PNP: 002e.5 skipping PNP: 002e.5@71 fixed resource, size=0! constrain_resources: PNP: 002e.6 skipping PNP: 002e.6@71 fixed resource, size=0! constrain_resources: PNP: 002e.7 skipping PNP: 002e.7@25 fixed resource, size=0! skipping PNP: 002e.7@27 fixed resource, size=0! skipping PNP: 002e.7@b2 fixed resource, size=0! skipping PNP: 002e.7@ba fixed resource, size=0! skipping PNP: 002e.7@c0 fixed resource, size=0! skipping PNP: 002e.7@c2 fixed resource, size=0! skipping PNP: 002e.7@c8 fixed resource, size=0! skipping PNP: 002e.7@ca fixed resource, size=0! constrain_resources: PNP: 002e.8 constrain_resources: PNP: 002e.9 constrain_resources: PCI: 00:01.1 constrain_resources: PCI: 00:02.0 constrain_resources: PCI: 00:02.1 constrain_resources: PCI: 00:04.0 constrain_resources: PCI: 00:06.0 constrain_resources: PCI: 00:07.0 constrain_resources: PCI: 00:08.0 constrain_resources: PCI: 00:09.0 constrain_resources: PCI: 01:06.0 constrain_resources: PCI: 00:0a.0 constrain_resources: PCI: 00:0b.0 constrain_resources: PCI: 00:0c.0 constrain_resources: PCI: 00:0d.0 constrain_resources: PCI: 00:0e.0 constrain_resources: PCI: 00:18.1 constrain_resources: PCI: 00:18.2 constrain_resources: PCI: 00:18.3 avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 00000fff lim->base 00000065 lim->limit 00000200 avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff lim->base 000c0000 lim->limit febfffff Setting resources... PCI_DOMAIN: 0000 allocate_resources_io: base:65 size:2000 align:12 gran:0 limit:200 !! Resource didn't fit !! aligned base 1000 size 2000 limit 200 2fff needs to be <= 200 (limit) PCI: 00:18.0 00 * [0x0 - 0x1fff] io PCI: 00:18.0 00 * [0x0 - 0x1fff] io PCI_DOMAIN: 0000 allocate_resources_io: next_base: 65 size: 2000 align: 12 gran: 0 done PCI: 00:18.0 allocate_resources_io: base:0 size:2000 align:12 gran:12 limit:200 Assigned: PCI: 00:01.0 60 * [0x0 - 0xff] io !! Resource didn't fit !! aligned base 400 size 100 limit 200 4ff needs to be <= 200 (limit) PCI: 00:01.0 64 * [0x400 - 0x4ff] io PCI: 00:01.0 64 * [0x400 - 0x4ff] io !! Resource didn't fit !! aligned base 400 size 100 limit 200 4ff needs to be <= 200 (limit) PCI: 00:01.0 68 * [0x800 - 0x8ff] io PCI: 00:01.0 68 * [0x800 - 0x8ff] io !! Resource didn't fit !! aligned base 400 size 100 limit 200 4ff needs to be <= 200 (limit) PCI: 00:04.0 10 * [0xc00 - 0xcff] io PCI: 00:04.0 10 * [0xc00 - 0xcff] io !! Resource didn't fit !! aligned base 400 size 100 limit 200 4ff needs to be <= 200 (limit) PCI: 00:04.0 14 * [0x1000 - 0x10ff] io PCI: 00:04.0 14 * [0x1000 - 0x10ff] io !! Resource didn't fit !! aligned base 400 size 80 limit 200 47f needs to be <= 200 (limit) PCI: 00:01.0 10 * [0x1400 - 0x147f] io PCI: 00:01.0 10 * [0x1400 - 0x147f] io !! Resource didn't fit !! aligned base 400 size 40 limit 200 43f needs to be <= 200 (limit) PCI: 00:01.1 20 * [0x1480 - 0x14bf] io PCI: 00:01.1 20 * [0x1480 - 0x14bf] io !! Resource didn't fit !! aligned base 400 size 40 limit 200 43f needs to be <= 200 (limit) PCI: 00:01.1 24 * [0x14c0 - 0x14ff] io PCI: 00:01.1 24 * [0x14c0 - 0x14ff] io !! Resource didn't fit !! aligned base 400 size 20 limit 200 41f needs to be <= 200 (limit) PCI: 00:01.1 10 * [0x1800 - 0x181f] io PCI: 00:01.1 10 * [0x1800 - 0x181f] io !! Resource didn't fit !! aligned base 400 size 10 limit 200 40f needs to be <= 200 (limit) PCI: 00:06.0 20 * [0x1820 - 0x182f] io PCI: 00:06.0 20 * [0x1820 - 0x182f] io !! Resource didn't fit !! aligned base 400 size 10 limit 200 40f needs to be <= 200 (limit) PCI: 00:07.0 20 * [0x1830 - 0x183f] io PCI: 00:07.0 20 * [0x1830 - 0x183f] io !! Resource didn't fit !! aligned base 400 size 10 limit 200 40f needs to be <= 200 (limit) PCI: 00:08.0 20 * [0x1840 - 0x184f] io PCI: 00:08.0 20 * [0x1840 - 0x184f] io !! Resource didn't fit !! aligned base 400 size 8 limit 200 407 needs to be <= 200 (limit) PNP: 002e.7 62 * [0x1850 - 0x1857] io PNP: 002e.7 62 * [0x1850 - 0x1857] io !! Resource didn't fit !! aligned base 400 size 8 limit 200 407 needs to be <= 200 (limit) PNP: 002e.7 64 * [0x1858 - 0x185f] io PNP: 002e.7 64 * [0x1858 - 0x185f] io !! Resource didn't fit !! aligned base 400 size 8 limit 200 407 needs to be <= 200 (limit) PCI: 00:07.0 10 * [0x1860 - 0x1867] io PCI: 00:07.0 10 * [0x1860 - 0x1867] io !! Resource didn't fit !! aligned base 400 size 8 limit 200 407 needs to be <= 200 (limit) PCI: 00:07.0 18 * [0x1868 - 0x186f] io PCI: 00:07.0 18 * [0x1868 - 0x186f] io !! Resource didn't fit !! aligned base 400 size 8 limit 200 407 needs to be <= 200 (limit) PCI: 00:08.0 10 * [0x1870 - 0x1877] io PCI: 00:08.0 10 * [0x1870 - 0x1877] io !! Resource didn't fit !! aligned base 400 size 8 limit 200 407 needs to be <= 200 (limit) PCI: 00:08.0 18 * [0x1878 - 0x187f] io PCI: 00:08.0 18 * [0x1878 - 0x187f] io !! Resource didn't fit !! aligned base 400 size 8 limit 200 407 needs to be <= 200 (limit) PCI: 00:0a.0 14 * [0x1880 - 0x1887] io PCI: 00:0a.0 14 * [0x1880 - 0x1887] io !! Resource didn't fit !! aligned base 400 size 4 limit 200 403 needs to be <= 200 (limit) PCI: 00:07.0 14 * [0x1888 - 0x188b] io PCI: 00:07.0 14 * [0x1888 - 0x188b] io !! Resource didn't fit !! aligned base 400 size 4 limit 200 403 needs to be <= 200 (limit) PCI: 00:07.0 1c * [0x188c - 0x188f] io PCI: 00:07.0 1c * [0x188c - 0x188f] io !! Resource didn't fit !! aligned base 400 size 4 limit 200 403 needs to be <= 200 (limit) PCI: 00:08.0 14 * [0x1890 - 0x1893] io PCI: 00:08.0 14 * [0x1890 - 0x1893] io !! Resource didn't fit !! aligned base 400 size 4 limit 200 403 needs to be <= 200 (limit) PCI: 00:08.0 1c * [0x1894 - 0x1897] io PCI: 00:08.0 1c * [0x1894 - 0x1897] io PCI: 00:18.0 allocate_resources_io: next_base: 400 size: 2000 align: 12 gran: 12 done PCI: 00:09.0 allocate_resources_io: base:200 size:0 align:12 gran:12 limit:200 PCI: 00:09.0 allocate_resources_io: next_base: 200 size: 0 align: 12 gran: 12 done PCI: 00:0b.0 allocate_resources_io: base:200 size:0 align:12 gran:12 limit:200 PCI: 00:0b.0 allocate_resources_io: next_base: 200 size: 0 align: 12 gran: 12 done PCI: 00:0c.0 allocate_resources_io: base:200 size:0 align:12 gran:12 limit:200 PCI: 00:0c.0 allocate_resources_io: next_base: 200 size: 0 align: 12 gran: 12 done PCI: 00:0d.0 allocate_resources_io: base:200 size:0 align:12 gran:12 limit:200 PCI: 00:0d.0 allocate_resources_io: next_base: 200 size: 0 align: 12 gran: 12 done PCI: 00:0e.0 allocate_resources_io: base:200 size:0 align:12 gran:12 limit:200 PCI: 00:0e.0 allocate_resources_io: next_base: 200 size: 0 align: 12 gran: 12 done PCI_DOMAIN: 0000 allocate_resources_mem: base:f4000000 size:7200000 align:26 gran:0 limit:febfffff Assigned: PCI: 00:18.3 94 * [0xf4000000 - 0xf7ffffff] mem Assigned: PCI: 00:18.0 02 * [0xf8000000 - 0xf9ffffff] prefmem Assigned: PCI: 00:18.0 01 * [0xfa000000 - 0xfb1fffff] mem PCI_DOMAIN: 0000 allocate_resources_mem: next_base: fb200000 size: 7200000 align: 26 gran: 0 done PCI: 00:18.0 allocate_resources_prefmem: base:f8000000 size:2000000 align:25 gran:20 limit:febfffff Assigned: PCI: 00:09.0 24 * [0xf8000000 - 0xf9ffffff] prefmem PCI: 00:18.0 allocate_resources_prefmem: next_base: fa000000 size: 2000000 align: 25 gran: 20 done PCI: 00:09.0 allocate_resources_prefmem: base:f8000000 size:2000000 align:25 gran:20 limit:febfffff Assigned: PCI: 01:06.0 14 * [0xf8000000 - 0xf9ffffff] prefmem PCI: 00:09.0 allocate_resources_prefmem: next_base: fa000000 size: 2000000 align: 25 gran: 20 done PCI: 00:0b.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:0b.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:0c.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:0c.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:0d.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:0d.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:0e.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:0e.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:18.0 allocate_resources_mem: base:fa000000 size:1200000 align:24 gran:20 limit:febfffff Assigned: PCI: 00:09.0 20 * [0xfa000000 - 0xfb0fffff] mem Assigned: PCI: 00:01.0 14 * [0xfb100000 - 0xfb100fff] mem Assigned: PCI: 00:02.0 10 * [0xfb101000 - 0xfb101fff] mem Assigned: PCI: 00:04.0 18 * [0xfb102000 - 0xfb102fff] mem Assigned: PCI: 00:07.0 24 * [0xfb103000 - 0xfb103fff] mem Assigned: PCI: 00:08.0 24 * [0xfb104000 - 0xfb104fff] mem Assigned: PCI: 00:0a.0 10 * [0xfb105000 - 0xfb105fff] mem Assigned: PCI: 00:02.1 10 * [0xfb106000 - 0xfb1060ff] mem PCI: 00:18.0 allocate_resources_mem: next_base: fb106100 size: 1200000 align: 24 gran: 20 done PCI: 00:09.0 allocate_resources_mem: base:fa000000 size:1100000 align:24 gran:20 limit:febfffff Assigned: PCI: 01:06.0 10 * [0xfa000000 - 0xfaffffff] mem Assigned: PCI: 01:06.0 30 * [0xfb000000 - 0xfb00ffff] mem PCI: 00:09.0 allocate_resources_mem: next_base: fb010000 size: 1100000 align: 24 gran: 20 done PCI: 00:0b.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:0b.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:0c.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:0c.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:0d.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:0d.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:0e.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:0e.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 0: mmio_basek=003d0000, basek=00000300, limitk=00100000 PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 amdk8_set_resource, enabling legacy VGA IO forwarding for PCI: 00:18.0 link 0x0 FATAL: stdin closed picocom v1.4 port is : /dev/ttyS0 flowcontrol : none baudrate is : 115200 parity is : none databits are : 8 escape is : C-a noinit is : no noreset is : no nolock is : no send_cmd is : ascii_xfr -s -v -l10 receive_cmd is : rz -vv

2 1

[PATCH] Move cmos.default handling to bootblock
by Patrick Georgi 04 Mar '11

04 Mar '11

The cmos.default code wasn't actually used so far, due to an oversight when forward-porting this feature from an old branch. - Extend walkcbfs' use by factoring out the stage handling into C code. - New sanitize_cmos() function that looks if CMOS data is invalid and cmos.default exists and if so overwrites CMOS with cmos.default data. - Use sanitize_cmos() in both bootblock implementations. - Drop the need to reboot after writing CMOS: CMOS wasn't used so far, so we can go on without a reboot. - Remove the restriction that cmos.default only works on CAR boards. - Always build in cmos.default support on boards that USE_OPTION_TABLE. Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> It's abuild tested and boot tested with emulation/qemu-x86. With this patch CMOS recovery only works on bootblock enabled boards/chipsets. Consider this an incentive to implement bootblock support where necessary :-) --- src/arch/x86/Kconfig | 6 ----- src/arch/x86/Makefile.bootblock.inc | 2 +- src/arch/x86/include/bootblock_common.h | 34 ++++++++++++++++++++++++++++-- src/arch/x86/init/bootblock_normal.c | 4 +++ src/arch/x86/init/bootblock_simple.c | 5 ++++ src/arch/x86/lib/walkcbfs.S | 10 +-------- src/pc80/mc146818rtc_early.c | 28 ------------------------- 7 files changed, 42 insertions(+), 47 deletions(-)

5 8

Re: [coreboot] [PATCH] SECC Pentium 2/3 users are gonna love this
by Keith Hui 02 Mar '11

02 Mar '11

> > Please don't gzip patches, it lowers the chance of someone reviewing > them to zero ;-) I figured if we're coding at this level, gzip won't be a hurdle. I announced it up front, didn't I? :p > > There is 65x microcode in the model_67x directory, and it's not split up > into single files as for the other CPUs. > The microcodes are static and are not supposed to change, our CPU drivers are grouped by family, and the microcodes are going to be included one after another in one place anyway even when made separate, so why have 5 files for 5 microcodes in the 67x family for example when one will do? Of course I retained the comments therein that marks the microcodes and the processors they're intended for. To put things in perspective, the microcode data we get from Intel has hundreds of them all in one file. > + if (cpuid_res.ebx != 0x756e6547 || cpuid_res.edx != 0x49656e69 || > cpuid_res.ecx != 0x6c65746e) { > + printk(BIOS_INFO, "Not 'GenuineIntel' Processor"); > + return 0; > + } > > This is not necessary. When model_6**_init() is executed, it's clear > already that this is an intel cpu. I'm not sure if the check for choosing the CPU driver to execute is on these CPUID signatures, or through some other fields. This check is carried from v1. I agree we can take a chance and take it out; we'll revisit when something breaks. :D > > +/* if (signature & 0x1000) { > + printk(BIOS_DEBUG,"Overdrive chip no L2 cache configuration\n"); > + return 0; > + } > + > + if (signature < 0x630 || signature >= 0x680) { > + printk(BIOS_DEBUG,"L2 cache on CPUID %x does not require > configuration\n", signature); > + return 0; > + }*/ > > I think this code should just be dropped That may change when (IF) we manage to get coreboot on a socket 8 board on which a Pentium II OverDrive processor sits. Again this piece is from the original code from v1. I agree the second signature check is not needed. > > Is it generally possible to move p6_configure_l2_cache to a generic > place, maybe to cpu/x86/cache ? > > +/*--- End L2 init code from corebbot v1 ---*/ > > I think this kind of comment is not needed. > That's a marker to help preserve my sanity. :-p > +static inline void strcpy(char *dst, char *src) > +{ > + while (*src) *dst++ = *src++; > +} > > I know I am the idiot who introduced this in a model_xxx_init.c file, > but maybe we should move it to lib/strcpy.c ? Well, 63x and 67x don't even need this; they don't support the processor brand string that 6bx do. Same with the fill_processor_name() function. I'll just take them out entirely. > > +static struct cpu_device_id cpu_table[] = { > + { X86_VENDOR_INTEL, 0x0650 }, > + { X86_VENDOR_INTEL, 0x0651 }, > + { X86_VENDOR_INTEL, 0x0652 }, > + { X86_VENDOR_INTEL, 0x0653 }, > + { X86_VENDOR_INTEL, 0x0671 }, > + { X86_VENDOR_INTEL, 0x0672 }, > + { X86_VENDOR_INTEL, 0x0673 }, > + { 0, 0 }, > +}; > > Instead of using a common driver, can two drivers use a common set of > shared functions instead? > It's already partially done. src/cpu/intel/model_67x/l2_cache.c (new in this patch) is linked in by model_65x driver too. Next prime suspect: fill_processor_name() in 6bx and a few other CPU models I'm no expert of. But 65x and 67x really are so similar that one driver can do both. Now is our end goal here to spin off model_63x/65x/66x/67x/68x/6ax/6bx all into their own CPU drivers when most of what's being done is duplicating code from model_6xx which is what they collectively once were? What's the rationale behind this need for split? I think a split should only be done when different initialization sequence are needed, eg. the special L2 initialization sequence for these SECC P6s. Same with motherboard models. When P2B-LS support matures I'd probably use the same directory for P2B-L and P2B-S support. They share the same circuit board anyway, and a -LS can emulate both by moving two jumpers. > +ifeq ($(CONFIG_USE_DCACHE_RAM),y) > +cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc > +endif > > This will break all targets except the ones you worked on. > I read this and thought, "I gotta run abuild." So I did. The errors I saw all seems to be k8/k10 targets and/or ACPI related. Even the entire P2B family that is in the tree passed abuild with this patch applied. Oh they haven't been migrated to CAR yet. Thanks Keith

6 19

[PATCH] Proposal for dealing with superio *.c includes
by Alex G. 02 Mar '11

02 Mar '11

Hi guys! I present a proposal for dealing with the annoying: #include "superio/vendor/model/early_serial.c" present in virtually all romstage.c files. The steps are as follows: 1) Declare a generic prototype: superio_enable_early_serial(); 2) Remove #include */early_serial.c from romstage 3) add a romstage-$(CONFIG_THIS_SUPERIO) += early_serial.c to the superio's Makefile.inc 4) Include the generic "superio/early_serial.h" definition in romstage.c 5) Include the superio specific header in romstage.c 6) Done I'm demonstrating this with the fintek/f81865f superio, and the amd/persimmon board. Besides discussion, this patch is also intended for inclusion. See patch for more details.

3 5

[PATCH] Add K8T800, K8T800Pro*, and K8M800* support
by Alex G. 02 Mar '11

02 Mar '11

Find attached a new version of my previous patch for the K8T800. In my previous patch, I was worried that the .tblpointer could contain incorrect values. I have hexdumped the image for the A8V-E SE (K8T8900 chipset), and it contains the correct values. The same applies to the board I'm porting (with K8T800 chipset). I remember someone on IRC asking about the previous patch for the K8T800. I've added the PCI ID for the K8M800 VGA controller to the K8M890 driver, so the VGA might work (TM) on the K8M800. The code for the K8T800 works. The reason I'm not also putting up a patch for the ASUS K8V-X SE is that IRQs are not (yet) working well for this board. Alex *These northbridges have not been tested.

5 10

[PATCH] outb(* 0x80) to post_code()
by Alex G. 02 Mar '11

02 Mar '11

Applies to fresh svn.......................[OK] abuild run......................................[OK] See patch. Alex

3 14

coreboot certified hardware
by Carl-Daniel Hailfinger 02 Mar '11

02 Mar '11

Hi, I wonder if we want to establish something like the "Designed for Windows XP" or "Yes it runs with Netware" certificates? It would certainly be a nice marketing aid for vendors, and at the same time it would promote coreboot visibility. If there is interest in such an idea, we will have to decide which criteria have to be fulfilled to get such a certificate, and if the certificate has an expiry date and/or is bound to a specific svn revision. Off the top of my head, I can think of the following criteria: - coreboot+SeaBIOS works well enough to boot $ENTERPRISE_LINUX, $ENDUSER_LINUX and Windows 7 (Vista and XP as well?) - Nvidia and ATI graphics drivers (both free and closed) work if booted with a coreboot+SeaBIOS image? - Frequency scaling and the various suspend methods work - Soft poweroff works - IRQ routing and all PCI/PCIe/AGP/whatever slots work - Legacy ports (if present) work - Fans work well enough (temperature-based scaling if present in the "normal" BIOS) - Source for a working coreboot image (including the Kconfig settings for the board, and possibly NVRAM settings?) is available for free without NDA - Board port merged into coreboot svn - SeaBIOS source code is available - SeaBIOS code is merged into SeaBIOS git - flashrom works on the board (no lockdown) or there is a way to boot unlocked and run flashrom for your image of choice - At least some serial output (coreboot version) if a serial port (header) is present, otherwise... USB Debug? Floppy? LPC bus? POST card on port 82h? Did I forget something? Are some criteria useless? What would Jane User expect from a normal mainboard if she didn't know coreboot was running? Regards, Carl-Daniel -- http://www.hailfinger.org/

11 25

[RFC] Converting W83977TF early serial from included to linked
by Keith Hui 28 Feb '11

28 Feb '11

Hi all, In my pipeline is something more infrastructural, something different from what I usually do - I am converting early serial code for Winbond W83977TF from code included in romstage to compiled unit to be linked into romstage. 13 boards use this superio, some apparently still not converted to CAR (including one Intel server board). I have yet to complete running abuild on my change. Should I let it break when I submit it for review given earlier buzz suggesting we leave non-CAR boards behind? The reason I'm doing this is I want to do this for ITE IT8705F, which happens to have no board using it at the moment, but I want to test this approach on a board that I can boot test right now. Enter the P2B-LS and W83977TF. If this proof of concept works, we can start this conversion one superio at a time and nail down one more goal of the infrastructure refactoring. Thoughts and comments? Thanks Keith

2 1

[PATCH] add functions to set Subsystem Vendor/Device to rl5c746
by Sven Schnelle 28 Feb '11

28 Feb '11

Hi List, this patch adds functions to set the Subsystem Vendor/Device ID fields on Ricoh RL5C746. Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Index: src/southbridge/ricoh/rl5c476/rl5c476.c =================================================================== --- src/southbridge/ricoh/rl5c476/rl5c476.c (revision 6374) +++ src/southbridge/ricoh/rl5c476/rl5c476.c (working copy) @@ -198,12 +198,29 @@ } +static void rl5c476_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + int miscreg = pci_read_config16(dev, 0x82); + /* Enable subsystem id register writes */ + pci_write_config16(dev, 0x82, miscreg | 0x40); + + pci_write_config16(dev, 0x40, vendor); + pci_write_config16(dev, 0x42, device); + /* restore original contents */ + pci_write_config16(dev, 0x82, miscreg); +} + +static struct pci_operations rl5c476_pci_ops = { + .set_subsystem = rl5c476_set_subsystem, +}; + static struct device_operations ricoh_rl5c476_ops = { .read_resources = rl5c476_read_resources, .set_resources = rl5c476_set_resources, .enable_resources = cardbus_enable_resources, .init = rl5c476_init, .scan_bus = pci_scan_bridge, + .ops_pci = &rl5c476_pci_ops, }; static const struct pci_driver ricoh_rl5c476_driver __pci_driver = {

3 4

[commit] r6412 - trunk/src/southbridge/ricoh/rl5c476
by repository service 28 Feb '11

28 Feb '11

Author: svens Date: Mon Feb 28 19:09:58 2011 New Revision: 6412 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6412 Log: add functions to set Subsystem Vendor/Device to rl5c746 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/southbridge/ricoh/rl5c476/rl5c476.c Modified: trunk/src/southbridge/ricoh/rl5c476/rl5c476.c ============================================================================== --- trunk/src/southbridge/ricoh/rl5c476/rl5c476.c Mon Feb 28 04:59:34 2011 (r6411) +++ trunk/src/southbridge/ricoh/rl5c476/rl5c476.c Mon Feb 28 19:09:58 2011 (r6412) @@ -198,12 +198,29 @@ } +static void rl5c476_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + u16 miscreg = pci_read_config16(dev, 0x82); + /* Enable subsystem id register writes */ + pci_write_config16(dev, 0x82, miscreg | 0x40); + + pci_write_config16(dev, 0x40, vendor); + pci_write_config16(dev, 0x42, device); + /* restore original contents */ + pci_write_config16(dev, 0x82, miscreg); +} + +static struct pci_operations rl5c476_pci_ops = { + .set_subsystem = rl5c476_set_subsystem, +}; + static struct device_operations ricoh_rl5c476_ops = { .read_resources = rl5c476_read_resources, .set_resources = rl5c476_set_resources, .enable_resources = cardbus_enable_resources, .init = rl5c476_init, .scan_bus = pci_scan_bridge, + .ops_pci = &rl5c476_pci_ops, }; static const struct pci_driver ricoh_rl5c476_driver __pci_driver = {

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coreboot February 2011