Oskar Enoksson wrote:
> Myles Watson wrote:
>
>>> I think Myles was right, there is a i2c mux in this server that somehow
>>> multiplexes DIMM devices on the i2c bus. I was able to guess which i2c
>>> ports contain the DIMM info, and which port is the mux, then added the
>>> mux to devicetree.cb and the DIMM ports under it. Now I'm able to use
>>> memory from both CPU's, at least for the combination of DIMM's I have
>>> (2x2x1GB and 2x2x512MB).
>>>
>>>
>> I'm glad it worked out!
>>
>>
>>> So I'm basically able to use these servers now. I would love to have
>>> ACPI and Cool'nQuiet of course, perhaps I'll try to do that later.
>>>
>>> Thanks very much for all help! If you want me to commit the new
>>> mainboard to your svn repository let me know.
>>>
>>>
>> Yes, please. If you'll send your latest patch with a Signed-off-by: line,
>> I'll take it from there.
>>
>> Thanks,
>> Myles
>>
>>
> I hope this file is the way you want it. I did "svn cp
> src/mainboard/tyan/s2881 src/mainboard/hp/dl145_g1" and then modified
> the files, then "svn diff src/mainboard" so I assume you should do the
> same svn cp operation, then apply my patch, then commit to retain the
> original files' history.
>
I have fixed several problems and now it boots reliably for both and
older dual Opteron 248 server and an upgraded dual Opteron 280 server.
memtest86+ doesn't work, but according to another mailinglist thread
memtest cannot handle tables in high memory, so that seems to be a
memtest issue.
Attached is a cleaned-up patch. Thanks to Myles and others for excellent
help and support. I hope someone finds the result useful.
Adds RS740 HT and internal graphics PCI ids.
Adds support for RS740 in RS690 code (some of the fam10 code from RS780).
Adds support for ECS A740GM-M.
This definitely needs more patches and fine-tuning.
Only tested on RS740.
Signed-off-by: Ivaylo Valkov <ivaylo(a)e-valkov.org>
---
Hello all,
And thank you for all the work you have done so far.
This is kind of long e-mail, so for the impatient - with these patches I
am able to initialize the RS740 chipset on the ECS A740GM-M motherboard and
boot GNU/Linux (with Xorg), but the code definitely needs more fine-tuning
and patching.
All my hardware died recently, so I bought two identical ECS A740GM-M
[1] replacement boards with AMD RS740/740G chipset as an opportunity to
help the coreboot project gather some information. The requested
information for flashrom and the RS740 chipset is attached. One thing
led to another and I've gone a lot further - the board seems usable.
Flashrom works on the board. The flash chip is recognised as MX25L8005,
but it is actually [2] MX25L8006. [3] In spite of that I was able to
flash it and boot the proprietary BIOS and coreboot. I've experienced
some CMOS checksum errors with the proprietary BIOS after flashing, but
everything worked fine after setting the date. This does not happen
always and I can't see a pattern when it does. Should I post the
flashrom related information on the flashrom mailing list?
With flashrom working and the information on this list (and few other
places) that the RS740 is RS690 with new graphics I decided to test the
RS690 code on the board. So, after nearly a month of cut-and-paste from
mahogany_fam10 and dmb690t, new code in RS690, borrowed from RS780, ACPI
from mahogany_fam10 for the board and some modifications I ended up
with something usable. The CPU is Sempron 140 (AM3/AM2+ socket).
I have some basic and blurry understanding of the boot process. I do not
know why exactly all that I've done worked. It is fair to say that I
have read almost zero documentation. All was achieved only by reading
the available code and observing the logic. Maybe it wasn't the smartest
and safest thing to do, but worth it.
So carefully review the code. Some of it is there so I could build. It
might be irrelevant. Patches are attached.
I used a cmos.layout from mahogany_fam10 to build, but images with
enabled CONFIG_USE_OPTION_TABLE (use CMOS/NVRAM values instead of hard
coded ones) in menuconfig do not boot at all - not even single serial
line of output. With recent changes and the move of CMOS to CBFS I can't
build with that option.
I am able to boot GNU/Linux. USB, network, sound, ATA and SATA are
working. PCI worked with external graphic and network card. PCIe is not
tested.
The master and stable releases of SeaBIOS hang when there is a USB mouse
connected after printing "USB mouse initialized". USB works fine under
GNU/Linux.
HT is initialized to 200MHz. The lspci output (also attached) after
coreboot loads, shows that 1.6GHz link frequency is possible. The
documented limit for RS690 is 1GHz. The RS780 code is implemented
differently, so it has k8 and fam10 support. Do you think it will be
possible to use something from RS780 code? I am not confident and
competent to make the changes myself, but I am willing to test patches
(any).
The lspci output for the board with coreboot running differs(in
places). I think it is ACPI and devicetree.cb related. Don't know how to
fix it right now.
After coreboot initializes the board, the CPU has two states - 1.9 GHz
and 2.7GHz. With proprietary BIOS the CPU can do two more - 1.5GHz and
800MHz. That is ACPI issue, righ? Before adding ACPI the only possible
frequency was 2.7GHz.
The code that prints the CPU revision (in get_cpu_revision) is taken
from RS780. I think it prints (only that!) wrong revision - "K8_10"
instead of "Fam 10". It seems it should be "eax <= 0x100fff" instead of
"eax <= 0x100f00", but as I've said I didn't read enough documentation.
I've extracted a VGA BIOS image from the proprietary BIOS and the
internal graphics card worked. Both DVI and VGA connectors work. Xorg
loads, but if the resolution is higher than or equal to 1024x768 the
screen flickers and I see horizontal lines. [4] When the display is
refreshed (key press, mouse move, by programs) it is awful. [5] For
lower resolutions it is not noticeable or even missing. This is tested
on deblobed Linux-libre kernel only, and the drivers do not load the
binary-blob firmware for 3D acceleration.
Is it possible to initialize the internal graphics on RS690/RS740 from
coreboot code and use VGA BIOS image from SeaBIOS? Like it is done for
the M2V-MX SE board? Yes I know it uses VIA chipset and it has
documentation. I guess what I am asking is, is it there enough
documentation released by AMD to make it work. I've hacked a PCI header
for the VGA BIOS image from SeaBIOS, so it can be loaded by coreboot
(vendor/device ID complains). The ROM is loaded, but SeaBIOS hangs. Not
that I was expecting to just work.
There are microcode patches for some CPUs that are non-free binary-blobs
(examine their license headers). Is it possible to make loading such
microcode configurable? I am unable to build the fam10 code without a
microcode filename. I understand that AMD (and other companies) might
not want to release such information for various reasons, but I prefer
to use "crippled" CPU instead of non-free microcode, when I am running
free software BIOS. Do I really need them for Sempron anyway? It works
without them. Didn't notice any difference in performance with them. Not
that the current state of the board can be used for measuring
performance. The work-around I am using right now is zero-filled
microcode patch file in the board directory, that does nothing.
Images of the board and the chips can be found on my "web site" [6].
I've copied the copyright notices from files that had such and I've used
code from. For the rest I've put a comment pointing to the file I've
borrowed from. Hope that is the right way to do it. Unfortunately the
code I used restricts me to GPLv2 only, I prefer GPLv2(or later). What
is the policy on GPLv3 (or later) code for that matter? Just thinking
for possible future contributions.
P.S. This is a lot of information (and issues). If anything has to go in
the issue tracker I will do it.
[1] http://www.ecs.com.tw/ECSWebSite/Product/Product_Detail.aspx?CategoryID=1&D…
[2] http://e-valkov.org/coreboot/ecs-a740gm-m-bios-chip.jpg
[3] http://www.mxic.com.tw/QuickPlace/hq/PageLibrary4825740B00298A3B.nsf/h_Inde…
[4] http://e-valkov.org/coreboot/video-card-1.ogv
[5] http://e-valkov.org/coreboot/video-card-2.ogv
[6] http://e-valkov.org/coreboot/
Hi All,
I wanted to build a new Desktop workstation with currently available
CPU and motherboard that is supported by Coreboot bios, I have
searched few links for it
e.g.
Ubuntu-certified hardware http://www.ubuntu.com/certification/
Zareason http://zareason.com/shop/home.php
AMD Processors - Recommended Motherboards
http://products.amd.com/pages/recommendedmbfilter.aspx?AspxAutoDetectCookie…
But these site mention hardware where gnu/linux could run easily, but
they do not inform about coreboot bios compatibility.
And checked
http://www.coreboot.org/Supported_Motherboards for searching suitable
motherboard, seen coreboot related video in youtube.
But I did not found here new Intel and AMD cpu for motherboards in
Desktop/Workstation section (except Laptop)
mentioned for e.g.
Intel Core 7i
Intel Core 3i and similar AMD's latest.
So finally I like to know do these newer CPU's any motherboard going
to be supported in near future, So I will purchase that motherboard.
I want to find it out as it will be difficult to change hardware than
software later. Please suggest which CPU/motherboard combination is
good with coreboot.
--
Regards,
-sharad
Hi,
I've attempted to use the rs780 and sb800 code on a AM3 870 + SB850
board. Raminit seems to go okay, as does the first bits of ramstage.
However, ramstage fails after the first two passes through
rs780_enable(). It stalls in get_vid_did() reading PCI config space
of device 2 (or 4). Also, the rs780 HT init code thinks the link should
run at 200MHz, maybe that's related.
I'm aware that this code wasn't exactly intended for the 870,
but maybe someone has some hints of what to try next.
Jonathan Kollasch
Hi all,
Would someone be interrested if I write something about microcoded CPUs
controllers? Like the classic uCode ROM + ALU + Regs + IO unit?
Thanks,
Rudolf
Stefan mentioned that he knows several people who he has worked with in the
area, and we're thinking it would be fun to get everyone together for a day
of hacking on Coreboot and related projects such as Flashrom and SeaBIOS.
So, I'd like to invite everyone to Google's beautiful campus in Mountain
View for a day of Coreboot hacking, board porting, BIOS flashing, etc. We'll
set a tentative date for Saturday the 29th of this month from noon 'till
8pm. We also have FlexyICE ROMulators and Dediprog SPI flash programmers so
folks can worry less about bricking their system. Maybe Stefan can whip up a
tutorial for newbies if there is particular interest in a specific area.
If this sounds like something you'd like to participate in, please fill out
the registration form at the URL below. It will help us to ensure we have
adequate facilities reserved, equipment ready, visitor badges printed, and
technically prepared for the topics of interest. We'll also send
confirmation with detailed instructions on how to find the building /
conference room to those who register.
Registration form:
https://spreadsheets.google.com/viewform?formkey=dGRab2s1VHRKNzRDX19pTVVrTj…
--
David Hendricks (dhendrix)
Systems Software Engineer, Google Inc.
This is the most up-to-date patch on a board I have been struggling with
for over a month now I am posting this patch for both discussion and
inclusion.
The good part is we get to linux. The bad part is that linux gets bored
of waiting for the IRQs. The IRQs do not seem to work, at least, they
partially do not work.
This board is on loan from a friend, and I will have to give it back in
a few days. If I can't get it to work, I'd at least like my work to be
available for the next person who may want to get this model running.
The first obvious sign of something going wrong is the keyboard not
responding in SeaBIOS. Later, linux tells us:
"..TIMER: vector=0x30 apic1=0 pin1=2 apic2=0 pin2=0
..MP-BIOS bug: 8254 timer not connected to IO-APIC
...trying to set up timer (IRQ0) through the 8259A ...
..... (found apic 0 pin 0) ...
...... works."
message from linux.
This indicates to me that linux is setting up the timer as IRQ0 through
the i8259A, through the IOAPIC pin 0 as ExtInt, and to the LAPIC lint0
as ExtInt.
The mfg BIOS sets it up through the IOAPIC pin2, and it works.
We later see the i8259 IMR= fffa, which means IRQ0 (timer) and
IRQ2(cascade) are unmasked.
In the mfg BIOS, the IMR = fffb, which means that only IRQ2 is unmasked,
so the timer should be set up through the IOAPIC pin 2.
Under coreboot, linux finally says
ata3: lost interrupt (Status 0x58)
and dies.
Well, maybe it's just the IOAPIC acting up, so let's put a "noapic" in
the kernel arguments and see what happens. IRQs still do not work and
linux stops at the same error message.
The fact that the IOAPIC is accepting IRQ0 from the PIC means that the
IOAPIC should at least work as a VirtualWire, but the fact that
interrupts still do not work in "noapic" mode indicates the opposite. Is
it the IOAPIC acting up, or the i8259?
Maybe I'm looking at the problem from the wrong perspective. I'd
appreciate any suggestions or hints to get this board corebooting.
I'm also attaching the boot log from both coreboot and the mfg BIOS for
a more complete reference.
Alex
