Hi,
I've attempted to use the rs780 and sb800 code on a AM3 870 + SB850 board. Raminit seems to go okay, as does the first bits of ramstage. However, ramstage fails after the first two passes through rs780_enable(). It stalls in get_vid_did() reading PCI config space of device 2 (or 4). Also, the rs780 HT init code thinks the link should run at 200MHz, maybe that's related.
I'm aware that this code wasn't exactly intended for the 870, but maybe someone has some hints of what to try next.
Jonathan Kollasch
The attached patch gets coreboot going on the ASRock E350M1 board. This is an AMD family 14h Fusion board I bought for US $120, including processor. The video option rom is from the supplied UEFI BIOS.
The patch modifies the persimmon project and is for development use, not for commit. With this patch it can boot DOS from a SATA drive. It can also boot WinPE from a USB flash drive. I was unable to get Windows setup to run.
The board has a socketed SPI flash BIOS chip and a serial port header. The SIO is Nuvoton NCT5572D. Using coreboot's existing Winbond w83627hf is a good enough match to at least get the serial port and keyboard going.
Here are pictures of the board: http://notabs.org/pictures/ASRock-E350M1/
Thanks, Scott
Scott Duplichan wrote:
The attached patch gets coreboot going on the ASRock E350M1 board. This is an AMD family 14h Fusion board I bought for US $120, including processor. The video option rom is from the supplied UEFI BIOS.
The patch modifies the persimmon project and is for development use, not for commit.
What would you like to add functionally before commiting?
//Peter
-----Original Message----- From: coreboot-bounces@coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Peter Stuge Sent: Wednesday, February 23, 2011 10:15 PM To: coreboot@coreboot.org Subject: Re: [coreboot] Coreboot for AMD Fusion family 14h: ASRock E350M1
Scott Duplichan wrote:
The attached patch gets coreboot going on the ASRock E350M1 board. This is an AMD family 14h Fusion board I bought for US $120, including processor. The video option rom is from the supplied UEFI BIOS.
The patch modifies the persimmon project and is for development use, not for commit.
]What would you like to add functionally before commiting?
I guess the main thing to do before a commit is to branch persimmon and make an asrock e350m1 project. I suspect the functionality, while not ideal, is similar to that of persimmon. I will try to make a proper patch... Thanks, Scott
//Peter
Scott Duplichan wrote:
The patch modifies the persimmon project and is for development use, not for commit.
]What would you like to add functionally before commiting?
I guess the main thing to do before a commit is to branch persimmon and make an asrock e350m1 project. I suspect the functionality, while not ideal, is similar to that of persimmon. I will try to make a proper patch...
Great! Use svn cp to create the directory, then put your changes in there, and then svn diff should create the corresponding small patch that you sent already. I'm happy to ack. This looks like a nice board for a media center system.
//Peter
Peter wrote:
]Great! Use svn cp to create the directory, then put your changes in ]there, and then svn diff should create the corresponding small patch ]that you sent already. I'm happy to ack. This looks like a nice board ]for a media center system. ] ]//Peter
Thanks Peter. I accidentally did the 'svn cp' step interactively instead of by patch. The attached patch completes the work of converting AMD Persimmon into ASRock E350M1.
ASRock E350M1 is built from a branch of AMD Persimmon with these changes:
1) Replace SMSC KBC1100 with Winbond w83627hf. 2) Change the SPD address of the second DIMM slot. 3) Cosmetic changes.
A video option rom needs to be added to support the built-in uma graphics.
Thanks, Scott
Index: src/mainboard/asrock/e350m1/acpi/ssdt2.asl =================================================================== --- src/mainboard/asrock/e350m1/acpi/ssdt2.asl (revision 6375) +++ src/mainboard/asrock/e350m1/acpi/ssdt2.asl (working copy) @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440) +DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-FAM14", "AMDACPI", 100925440) { Scope (_SB) { Index: src/mainboard/asrock/e350m1/acpi/ssdt3.asl =================================================================== --- src/mainboard/asrock/e350m1/acpi/ssdt3.asl (revision 6375) +++ src/mainboard/asrock/e350m1/acpi/ssdt3.asl (working copy) @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440) +DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-FAM14", "AMDACPI", 100925440) { Scope (_SB) { Index: src/mainboard/asrock/e350m1/acpi/ssdt4.asl =================================================================== --- src/mainboard/asrock/e350m1/acpi/ssdt4.asl (revision 6375) +++ src/mainboard/asrock/e350m1/acpi/ssdt4.asl (working copy) @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440) +DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-FAM14", "AMDACPI", 100925440) { Scope (_SB) { Index: src/mainboard/asrock/e350m1/acpi/ssdt5.asl =================================================================== --- src/mainboard/asrock/e350m1/acpi/ssdt5.asl (revision 6375) +++ src/mainboard/asrock/e350m1/acpi/ssdt5.asl (working copy) @@ -18,7 +18,7 @@ */
-DefinitionBlock ("SSDT5.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440) +DefinitionBlock ("SSDT5.aml", "SSDT", 1, "AMD-FAM14", "AMDACPI", 100925440) { Scope (_SB) { Index: src/mainboard/asrock/e350m1/devicetree.cb =================================================================== --- src/mainboard/asrock/e350m1/devicetree.cb (revision 6375) +++ src/mainboard/asrock/e350m1/devicetree.cb (working copy) @@ -55,30 +55,46 @@ device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x439d - chip superio/fintek/f81865f - device pnp 4e.0 off # Floppy + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 4e.3 off end # Parallel Port - device pnp 4e.4 off end # Hardware Monitor - device pnp 4e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 end - device pnp 4e.6 off end # GPIO - device pnp 4e.a off end # PME - device pnp 4e.10 on # COM1 + device pnp 2e.2 on # Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 4e.11 off # COM2 + device pnp 2e.3 off # Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - end # f81865f + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end end #LPC device pci 14.4 on end # PCI 0x4384 device pci 14.5 on end # USB 2 Index: src/mainboard/asrock/e350m1/dimmSpd.c =================================================================== --- src/mainboard/asrock/e350m1/dimmSpd.c (revision 6375) +++ src/mainboard/asrock/e350m1/dimmSpd.c (working copy) @@ -34,8 +34,8 @@ { // socket 0 { - {0xA0, 0xA2}, // channel 0 dimms - {0xA4, 0xA8}, // channel 1 dimms + {0xA0, 0xA4}, // channel 0 dimms + {0x00, 0x00}, // channel 1 dimms }, // socket 1 { Index: src/mainboard/asrock/e350m1/dsdt.asl =================================================================== --- src/mainboard/asrock/e350m1/dsdt.asl (revision 6375) +++ src/mainboard/asrock/e350m1/dsdt.asl (working copy) @@ -23,7 +23,7 @@ "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "AMD ", /* OEMID */ - "PERSIMMO", /* TABLE ID */ + "E350M1 ", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ Index: src/mainboard/asrock/e350m1/Kconfig =================================================================== --- src/mainboard/asrock/e350m1/Kconfig (revision 6375) +++ src/mainboard/asrock/e350m1/Kconfig (working copy) @@ -17,7 +17,7 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA #
-if BOARD_AMD_PERSIMMON +if BOARD_ASROCK_E350M1
config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -28,7 +28,7 @@ select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14_ROOT_COMPLEX select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800 - select SUPERIO_FINTEK_F81865F + select SUPERIO_WINBOND_W83627HF select BOARD_HAS_FADT select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE @@ -56,7 +56,7 @@
config MAINBOARD_DIR string - default amd/persimmon + default asrock/e350m1
config APIC_ID_OFFSET hex @@ -64,7 +64,7 @@
config MAINBOARD_PART_NUMBER string - default "Persimmon" + default "e350m1"
config HW_MEM_HOLE_SIZEK hex @@ -132,16 +132,16 @@
config SIO_PORT hex - default 0x4e + default 0x2e
config ONBOARD_VGA_IS_PRIMARY bool default y
-#define CONFIG_VGA_BIOS_ID "1002,9804" +#define CONFIG_VGA_BIOS_ID "1002,9802" config VGA_BIOS_ID string - default "1002,9804" + default "1002,9802"
config DRIVERS_PS2_KEYBOARD bool @@ -151,5 +151,5 @@ bool default n
-endif # BOARD_AMD_PERSIMMON +endif # BOARD_ASROCK_E350M1
Index: src/mainboard/asrock/e350m1/mainboard.c =================================================================== --- src/mainboard/asrock/e350m1/mainboard.c (revision 6375) +++ src/mainboard/asrock/e350m1/mainboard.c (working copy) @@ -49,11 +49,11 @@ uint64_t uma_memory_base, uma_memory_size;
/************************************************* -* enable the dedicated function in persimmon board. +* enable the dedicated function in e350m1 board. *************************************************/ -static void persimmon_enable(device_t dev) +static void e350m1_enable(device_t dev) { - printk(BIOS_INFO, "Mainboard Persimmon Enable. dev=0x%p\n", dev); + printk(BIOS_INFO, "Mainboard E350M1 Enable. dev=0x%p\n", dev); #if (CONFIG_GFXUMA == 1) msr_t msr, msr2; uint32_t sys_mem; @@ -110,6 +110,6 @@ return 0; } struct chip_operations mainboard_ops = { - CHIP_NAME("AMD PERSIMMON Mainboard") - .enable_dev = persimmon_enable, + CHIP_NAME("ASRock E350M1 Mainboard") + .enable_dev = e350m1_enable, }; Index: src/mainboard/asrock/e350m1/romstage.c =================================================================== --- src/mainboard/asrock/e350m1/romstage.c (revision 6375) +++ src/mainboard/asrock/e350m1/romstage.c (working copy) @@ -31,16 +31,16 @@ #include <console/loglevel.h> #include "agesawrapper.h" #include "cpu/x86/bist.h" -#include "superio/fintek/f81865f/f81865f_early_serial.c" +#include "superio/winbond/w83627hf/early_serial.c" #include "cpu/x86/lapic/boot_cpu.c" #include "pc80/i8254.c" +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #include "pc80/i8259.c" #include "SbEarly.h" #include "SBPLATFORM.h"
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
-#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -52,7 +52,7 @@ sb_poweron_init();
post_code(0x31); - f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); } Index: src/mainboard/asrock/Kconfig =================================================================== --- src/mainboard/asrock/Kconfig (revision 6375) +++ src/mainboard/asrock/Kconfig (working copy) @@ -23,10 +23,12 @@
config BOARD_ASROCK_939A785GMH bool "939A785GMH/128M" +config BOARD_ASROCK_E350M1 + bool "E350M1"
endchoice
-source "src/mainboard/asrock/939a785gmh/Kconfig" +source "src/mainboard/asrock/e350m1/Kconfig"
config MAINBOARD_VENDOR string
Scott Duplichan wrote:
I accidentally did the 'svn cp' step interactively instead of by patch. The attached patch completes the work of converting AMD Persimmon into ASRock E350M1.
Good stuff. Some simple comments, then I'll ack.
A video option rom needs to be added to support the built-in uma graphics.
Does the default filename match what was extracted from factory EFI?
+++ src/mainboard/asrock/e350m1/dsdt.asl (working copy) @@ -23,7 +23,7 @@ "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "AMD ", /* OEMID */
- "PERSIMMO", /* TABLE ID */
- "E350M1 ", /* TABLE ID */
Also change AMD?
+++ src/mainboard/asrock/e350m1/Kconfig (working copy)
..
@@ -64,7 +64,7 @@
config MAINBOARD_PART_NUMBER string
default "Persimmon"
default "e350m1"
I think this should be uppercase.
-#define CONFIG_VGA_BIOS_ID "1002,9804" +#define CONFIG_VGA_BIOS_ID "1002,9802"
Why have this comment at all? Better just remove it.
+++ src/mainboard/asrock/e350m1/mainboard.c (working copy)
..
- printk(BIOS_INFO, "Mainboard Persimmon Enable. dev=0x%p\n", dev);
- printk(BIOS_INFO, "Mainboard E350M1 Enable. dev=0x%p\n", dev);
Please change to: "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable." ..
@@ -110,6 +110,6 @@ return 0; } struct chip_operations mainboard_ops = {
- CHIP_NAME("AMD PERSIMMON Mainboard")
- .enable_dev = persimmon_enable,
- CHIP_NAME("ASRock E350M1 Mainboard")
- .enable_dev = e350m1_enable,
Same here. CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
+++ src/mainboard/asrock/e350m1/romstage.c (working copy)
..
@@ -52,7 +52,7 @@ sb_poweron_init();
post_code(0x31);
- f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
Whitespace?
//Peter
Peter wrote:
]Scott Duplichan wrote: ]> I accidentally did the 'svn cp' step interactively instead of by ]> patch. The attached patch completes the work of converting AMD ]> Persimmon into ASRock E350M1. ] ]Good stuff. Some simple comments, then I'll ack. ] ]> A video option rom needs to be added to support the built-in uma ]> graphics. ] ]Does the default filename match what was extracted from factory EFI?
I do not know of a way to recover the original filename of the extracted video BIOS. After booting the factory BIOS, I saved physical memory range C0000-CFFFF to a file with a made up name.
+++ src/mainboard/asrock/e350m1/dsdt.asl (working copy) @@ -23,7 +23,7 @@ "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "AMD ", /* OEMID */
- "PERSIMMO", /* TABLE ID */
- "E350M1 ", /* TABLE ID */
]Also change AMD? Thanks for pointing this out, I changed it. In the revised patch, I also changed it in mptable.c
+++ src/mainboard/asrock/e350m1/Kconfig (working copy)
..
@@ -64,7 +64,7 @@
config MAINBOARD_PART_NUMBER string
default "Persimmon"
default "e350m1"
]I think this should be uppercase. Agree, I revised it.
-#define CONFIG_VGA_BIOS_ID "1002,9804" +#define CONFIG_VGA_BIOS_ID "1002,9802"
]Why have this comment at all? Better just remove it. Good point, I removed it.
+++ src/mainboard/asrock/e350m1/mainboard.c (working copy)
..
- printk(BIOS_INFO, "Mainboard Persimmon Enable. dev=0x%p\n", dev);
- printk(BIOS_INFO, "Mainboard E350M1 Enable. dev=0x%p\n", dev);
]Please change to: "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable." .. Good idea.
@@ -110,6 +110,6 @@ return 0; } struct chip_operations mainboard_ops = {
- CHIP_NAME("AMD PERSIMMON Mainboard")
- .enable_dev = persimmon_enable,
- CHIP_NAME("ASRock E350M1 Mainboard")
- .enable_dev = e350m1_enable,
]Same here. ]CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") Thanks.
+++ src/mainboard/asrock/e350m1/romstage.c (working copy)
..
@@ -52,7 +52,7 @@ sb_poweron_init();
post_code(0x31);
- f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
]Whitespace? Oops, I fixed it.
//Peter
Index: src/mainboard/asrock/e350m1/acpi/ssdt2.asl =================================================================== --- src/mainboard/asrock/e350m1/acpi/ssdt2.asl (revision 6375) +++ src/mainboard/asrock/e350m1/acpi/ssdt2.asl (working copy) @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440) +DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-FAM14", "AMDACPI", 100925440) { Scope (_SB) { Index: src/mainboard/asrock/e350m1/acpi/ssdt3.asl =================================================================== --- src/mainboard/asrock/e350m1/acpi/ssdt3.asl (revision 6375) +++ src/mainboard/asrock/e350m1/acpi/ssdt3.asl (working copy) @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440) +DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-FAM14", "AMDACPI", 100925440) { Scope (_SB) { Index: src/mainboard/asrock/e350m1/acpi/ssdt4.asl =================================================================== --- src/mainboard/asrock/e350m1/acpi/ssdt4.asl (revision 6375) +++ src/mainboard/asrock/e350m1/acpi/ssdt4.asl (working copy) @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440) +DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-FAM14", "AMDACPI", 100925440) { Scope (_SB) { Index: src/mainboard/asrock/e350m1/acpi/ssdt5.asl =================================================================== --- src/mainboard/asrock/e350m1/acpi/ssdt5.asl (revision 6375) +++ src/mainboard/asrock/e350m1/acpi/ssdt5.asl (working copy) @@ -18,7 +18,7 @@ */
-DefinitionBlock ("SSDT5.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440) +DefinitionBlock ("SSDT5.aml", "SSDT", 1, "AMD-FAM14", "AMDACPI", 100925440) { Scope (_SB) { Index: src/mainboard/asrock/e350m1/devicetree.cb =================================================================== --- src/mainboard/asrock/e350m1/devicetree.cb (revision 6375) +++ src/mainboard/asrock/e350m1/devicetree.cb (working copy) @@ -55,30 +55,46 @@ device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x439d - chip superio/fintek/f81865f - device pnp 4e.0 off # Floppy + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 4e.3 off end # Parallel Port - device pnp 4e.4 off end # Hardware Monitor - device pnp 4e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 end - device pnp 4e.6 off end # GPIO - device pnp 4e.a off end # PME - device pnp 4e.10 on # COM1 + device pnp 2e.2 on # Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 4e.11 off # COM2 + device pnp 2e.3 off # Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - end # f81865f + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end end #LPC device pci 14.4 on end # PCI 0x4384 device pci 14.5 on end # USB 2 Index: src/mainboard/asrock/e350m1/dimmSpd.c =================================================================== --- src/mainboard/asrock/e350m1/dimmSpd.c (revision 6375) +++ src/mainboard/asrock/e350m1/dimmSpd.c (working copy) @@ -34,8 +34,8 @@ { // socket 0 { - {0xA0, 0xA2}, // channel 0 dimms - {0xA4, 0xA8}, // channel 1 dimms + {0xA0, 0xA4}, // channel 0 dimms + {0x00, 0x00}, // channel 1 dimms }, // socket 1 { Index: src/mainboard/asrock/e350m1/dsdt.asl =================================================================== --- src/mainboard/asrock/e350m1/dsdt.asl (revision 6375) +++ src/mainboard/asrock/e350m1/dsdt.asl (working copy) @@ -22,8 +22,8 @@ "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "AMD ", /* OEMID */ - "PERSIMMO", /* TABLE ID */ + "ASROCK", /* OEMID */ + "E350M1 ", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ Index: src/mainboard/asrock/e350m1/Kconfig =================================================================== --- src/mainboard/asrock/e350m1/Kconfig (revision 6375) +++ src/mainboard/asrock/e350m1/Kconfig (working copy) @@ -17,7 +17,7 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA #
-if BOARD_AMD_PERSIMMON +if BOARD_ASROCK_E350M1
config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -28,7 +28,7 @@ select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14_ROOT_COMPLEX select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800 - select SUPERIO_FINTEK_F81865F + select SUPERIO_WINBOND_W83627HF select BOARD_HAS_FADT select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE @@ -56,7 +56,7 @@
config MAINBOARD_DIR string - default amd/persimmon + default asrock/e350m1
config APIC_ID_OFFSET hex @@ -64,7 +64,7 @@
config MAINBOARD_PART_NUMBER string - default "Persimmon" + default "E350M1"
config HW_MEM_HOLE_SIZEK hex @@ -132,16 +132,15 @@
config SIO_PORT hex - default 0x4e + default 0x2e
config ONBOARD_VGA_IS_PRIMARY bool default y
-#define CONFIG_VGA_BIOS_ID "1002,9804" config VGA_BIOS_ID string - default "1002,9804" + default "1002,9802"
config DRIVERS_PS2_KEYBOARD bool @@ -151,5 +150,5 @@ bool default n
-endif # BOARD_AMD_PERSIMMON +endif # BOARD_ASROCK_E350M1
Index: src/mainboard/asrock/e350m1/mainboard.c =================================================================== --- src/mainboard/asrock/e350m1/mainboard.c (revision 6375) +++ src/mainboard/asrock/e350m1/mainboard.c (working copy) @@ -49,11 +49,11 @@ uint64_t uma_memory_base, uma_memory_size;
/************************************************* -* enable the dedicated function in persimmon board. +* enable the dedicated function in e350m1 board. *************************************************/ -static void persimmon_enable(device_t dev) +static void e350m1_enable(device_t dev) { - printk(BIOS_INFO, "Mainboard Persimmon Enable. dev=0x%p\n", dev); + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); #if (CONFIG_GFXUMA == 1) msr_t msr, msr2; uint32_t sys_mem; @@ -110,6 +110,6 @@ return 0; } struct chip_operations mainboard_ops = { - CHIP_NAME("AMD PERSIMMON Mainboard") - .enable_dev = persimmon_enable, + CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") + .enable_dev = e350m1_enable, }; Index: src/mainboard/asrock/e350m1/mptable.c =================================================================== --- src/mainboard/asrock/e350m1/mptable.c (revision 6375) +++ src/mainboard/asrock/e350m1/mptable.c (working copy) @@ -50,7 +50,7 @@ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LAPIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); + memcpy(mc->mpc_oem, "ASROCK ", 8);
smp_write_processors(mc);
Index: src/mainboard/asrock/e350m1/romstage.c =================================================================== --- src/mainboard/asrock/e350m1/romstage.c (revision 6375) +++ src/mainboard/asrock/e350m1/romstage.c (working copy) @@ -31,16 +31,16 @@ #include <console/loglevel.h> #include "agesawrapper.h" #include "cpu/x86/bist.h" -#include "superio/fintek/f81865f/f81865f_early_serial.c" +#include "superio/winbond/w83627hf/early_serial.c" #include "cpu/x86/lapic/boot_cpu.c" #include "pc80/i8254.c" +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #include "pc80/i8259.c" #include "SbEarly.h" #include "SBPLATFORM.h"
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
-#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -52,7 +52,7 @@ sb_poweron_init();
post_code(0x31); - f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); } Index: src/mainboard/asrock/Kconfig =================================================================== --- src/mainboard/asrock/Kconfig (revision 6380) +++ src/mainboard/asrock/Kconfig (working copy) @@ -23,10 +23,12 @@
config BOARD_ASROCK_939A785GMH bool "939A785GMH/128M" +config BOARD_ASROCK_E350M1 + bool "E350M1"
endchoice
-source "src/mainboard/asrock/939a785gmh/Kconfig" +source "src/mainboard/asrock/e350m1/Kconfig"
config MAINBOARD_VENDOR string
Scott Duplichan wrote:
]> A video option rom needs to be added to support the built-in uma ]> graphics. ] ]Does the default filename match what was extracted from factory EFI?
I do not know of a way to recover the original filename of the extracted video BIOS. After booting the factory BIOS, I saved physical memory range C0000-CFFFF to a file with a made up name.
Ahh! And that worked? It doesn't always. The original filename would be discovered by using bios_extract or another similar tool on the factory firmware image. That also doesn't work always, but it's worth a try.
+++ src/mainboard/asrock/e350m1/dsdt.asl (working copy) @@ -23,7 +23,7 @@ "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "AMD ", /* OEMID */
- "PERSIMMO", /* TABLE ID */
- "E350M1 ", /* TABLE ID */
]Also change AMD? Thanks for pointing this out, I changed it. In the revised patch, I also changed it in mptable.c
Nice catch!
+++ src/mainboard/asrock/e350m1/mainboard.c (working copy)
..
@@ -110,6 +110,6 @@ return 0; } struct chip_operations mainboard_ops = {
- CHIP_NAME("AMD PERSIMMON Mainboard")
- .enable_dev = persimmon_enable,
- CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
- .enable_dev = e350m1_enable,
Some whitespace on the CHIP_NAME line seems off. After that and if you find something out about the VGA BIOS filename it's
Acked-by: Peter Stuge peter@stuge.se
Peter wrote:
]Scott Duplichan wrote: ]> ]> A video option rom needs to be added to support the built-in uma ]> ]> graphics. ]> ] ]> ]Does the default filename match what was extracted from factory EFI? ]> ]> I do not know of a way to recover the original filename of the ]> extracted video BIOS. After booting the factory BIOS, I saved ]> physical memory range C0000-CFFFF to a file with a made up name.
]Ahh! And that worked? It doesn't always. The original filename would ]be discovered by using bios_extract or another similar tool on the ]factory firmware image. That also doesn't work always, but it's worth ]a try.
I tried AMIBCP.exe. That is the only tool I have for AMI Aptio UEFI BIOS. It displays lots of strings, but no filenames. Wonderful UEFI uses GUIDs internally for option rom tracking.
]> > +++ src/mainboard/asrock/e350m1/dsdt.asl (working copy) ]> > @@ -23,7 +23,7 @@ ]> > "DSDT", /* Signature */ ]> > 0x02, /* DSDT Revision, needs to be 2 for 64bit */ ]> > "AMD ", /* OEMID */ ]> > - "PERSIMMO", /* TABLE ID */ ]> > + "E350M1 ", /* TABLE ID */ ]> ]> ]Also change AMD? ]> Thanks for pointing this out, I changed it. ]> In the revised patch, I also changed it in mptable.c ] ]Nice catch!
]> +++ src/mainboard/asrock/e350m1/mainboard.c (working copy) ].. ]> @@ -110,6 +110,6 @@ ]> return 0; ]> } ]> struct chip_operations mainboard_ops = { ]> - CHIP_NAME("AMD PERSIMMON Mainboard") ]> - .enable_dev = persimmon_enable, ]> + CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") ]> + .enable_dev = e350m1_enable, ] ]Some whitespace on the CHIP_NAME line seems off. After that and if ]you find something out about the VGA BIOS filename it's
Oops, got it.
Acked-by: Peter Stuge peter@stuge.se
On 02/24/11 13:48, Scott Duplichan wrote:
Peter wrote:
]Scott Duplichan wrote: ]> ]> A video option rom needs to be added to support the built-in uma ]> ]> graphics. ]> ] ]> ]Does the default filename match what was extracted from factory EFI? ]> ]> I do not know of a way to recover the original filename of the ]> extracted video BIOS. After booting the factory BIOS, I saved ]> physical memory range C0000-CFFFF to a file with a made up name.
]Ahh! And that worked? It doesn't always. The original filename would ]be discovered by using bios_extract or another similar tool on the ]factory firmware image. That also doesn't work always, but it's worth ]a try.
I tried AMIBCP.exe. That is the only tool I have for AMI Aptio UEFI BIOS. It displays lots of strings, but no filenames. Wonderful UEFI uses GUIDs internally for option rom tracking.
this EFI bios is using the CSM module so it can use the traditional vBIOS. are there any plans to support this new GOP model they (the EFI guys) are trying to push?
]> > +++ src/mainboard/asrock/e350m1/dsdt.asl (working copy) ]> > @@ -23,7 +23,7 @@ ]> > "DSDT", /* Signature */ ]> > 0x02, /* DSDT Revision, needs to be 2 for 64bit */ ]> > "AMD ", /* OEMID */ ]> > - "PERSIMMO", /* TABLE ID */ ]> > + "E350M1 ", /* TABLE ID */ ]> ]> ]Also change AMD? ]> Thanks for pointing this out, I changed it. ]> In the revised patch, I also changed it in mptable.c ] ]Nice catch!
]> +++ src/mainboard/asrock/e350m1/mainboard.c (working copy) ].. ]> @@ -110,6 +110,6 @@ ]> return 0; ]> } ]> struct chip_operations mainboard_ops = { ]> - CHIP_NAME("AMD PERSIMMON Mainboard") ]> - .enable_dev = persimmon_enable, ]> + CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") ]> + .enable_dev = e350m1_enable, ] ]Some whitespace on the CHIP_NAME line seems off. After that and if ]you find something out about the VGA BIOS filename it's
Oops, got it.
Acked-by: Peter Stugepeter@stuge.se
Anish Patel wrote:
]this EFI bios is using the CSM module so it can use the traditional vBIOS. ]are there any plans to support this new GOP model they (the EFI guys) ]are trying to push?
I like the idea of replacing a 16-bit binary module with 32-bit source code. But I think the use of EFI GOP is still quite limited. All of the UEFI BIOS I have seen from AMI, Insyde, and Phoenix still use CSM to execute the old legacy 16-bit video option rom. The only EFI BIOS I know of that executes video code natively is Apple. Native video code execution probably contributes to Apple's fast boot time. The problem for us is getting the needed source code from the video manufacturer.
Thanks, Scott
On 03/10/11 13:36, Scott Duplichan wrote:
Anish Patel wrote:
]this EFI bios is using the CSM module so it can use the traditional vBIOS. ]are there any plans to support this new GOP model they (the EFI guys) ]are trying to push?
I like the idea of replacing a 16-bit binary module with 32-bit source code. But I think the use of EFI GOP is still quite limited. All of the UEFI BIOS I have seen from AMI, Insyde, and Phoenix still use CSM to execute the old legacy 16-bit video option rom. The only EFI BIOS I know of that executes video code natively is Apple. Native video code execution probably contributes to Apple's fast boot time. The problem for us is getting the needed source code from the video manufacturer.
Thanks, Scott
Well Intel lets you get to their GOP module with IMGD/EMGD for certain products. They also have this EPOG thingy for their BLDK thing they just built. which apparently is also going to be released for their other procs too.
Anish Patel wrote:
]are there any plans to support this new GOP model they (the EFI ]guys) are trying to push?
I like the idea of replacing a 16-bit binary module with 32-bit source code.
..
Well Intel lets you get to their GOP module with IMGD/EMGD for certain products. They also have this EPOG thingy for their BLDK thing they just built.
Great. Please send a patch that you have made sure is legal.
which apparently is also going to be released for their other procs too.
Great. Please send patches for those too!
//Peter
Any chance to move the SSDTs to the northbridge/southbridge/cpu directory instead of having them live under mainboard?
* Scott Duplichan scott@notabs.org [110224 07:05]:
Index: src/mainboard/asrock/e350m1/acpi/ssdt2.asl
--- src/mainboard/asrock/e350m1/acpi/ssdt2.asl (revision 6375) +++ src/mainboard/asrock/e350m1/acpi/ssdt2.asl (working copy) @@ -17,7 +17,7 @@
- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440) +DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-FAM14", "AMDACPI", 100925440) { Scope (_SB) { Index: src/mainboard/asrock/e350m1/acpi/ssdt3.asl =================================================================== --- src/mainboard/asrock/e350m1/acpi/ssdt3.asl (revision 6375) +++ src/mainboard/asrock/e350m1/acpi/ssdt3.asl (working copy) @@ -17,7 +17,7 @@
- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440) +DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-FAM14", "AMDACPI", 100925440) { Scope (_SB) { Index: src/mainboard/asrock/e350m1/acpi/ssdt4.asl =================================================================== --- src/mainboard/asrock/e350m1/acpi/ssdt4.asl (revision 6375) +++ src/mainboard/asrock/e350m1/acpi/ssdt4.asl (working copy) @@ -17,7 +17,7 @@
- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440) +DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-FAM14", "AMDACPI", 100925440) { Scope (_SB) { Index: src/mainboard/asrock/e350m1/acpi/ssdt5.asl =================================================================== --- src/mainboard/asrock/e350m1/acpi/ssdt5.asl (revision 6375) +++ src/mainboard/asrock/e350m1/acpi/ssdt5.asl (working copy) @@ -18,7 +18,7 @@ */
-DefinitionBlock ("SSDT5.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440) +DefinitionBlock ("SSDT5.aml", "SSDT", 1, "AMD-FAM14", "AMDACPI", 100925440) { Scope (_SB) {
Stefan Reinauer wrote:
]Any chance to move the SSDTs to the northbridge/southbridge/cpu ]directory instead of having them live under mainboard?
It looks like SSDT2,3,4,5 are never used and can be removed from this project.
Thanks, Scott {
Am Donnerstag, den 24.02.2011, 05:34 +0100 schrieb Peter Stuge:
Scott Duplichan wrote:
These are really great news.
[…]
This looks like a nice board for a media center system.
Indeed. There are some reviews available of this board [1][2].
Unfortunately in Germany all the online shops seem to be out of stock [3]. The board would cost around 90 €.
Thanks,
Paul
[1] http://www.fudzilla.com/reviews/item/21897-asrock-e350m1-brazos-review/21897... [2] http://www.tomshardware.com/reviews/asrock-e350m1-amd-brazos-zacate-apu,2840... [3] http://www.preistrend.de/Preisvergleich_ASRock_E350M1__x7249770B04777704.htm...
* Scott Duplichan scott@notabs.org [110224 05:03]:
The attached patch gets coreboot going on the ASRock E350M1 board. This is an AMD family 14h Fusion board I bought for US $120, including processor. The video option rom is from the supplied UEFI BIOS.
The patch modifies the persimmon project and is for development use, not for commit. With this patch it can boot DOS from a SATA drive. It can also boot WinPE from a USB flash drive. I was unable to get Windows setup to run.
The board has a socketed SPI flash BIOS chip and a serial port header. The SIO is Nuvoton NCT5572D. Using coreboot's existing Winbond w83627hf is a good enough match to at least get the serial port and keyboard going.
Here are pictures of the board: http://notabs.org/pictures/ASRock-E350M1/
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
if CONFIG_SIO_PORT is defined in Kconfig (why?) we could as well use it in romstage.c. Is there a chance to remove it from Kconfig instead?
Stefan Reinauer wrote:
]> +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
]if CONFIG_SIO_PORT is defined in Kconfig (why?) we could as well use it ]in romstage.c. Is there a chance to remove it from Kconfig instead?
Certainly the two occurrences of 2e is not ideal. This change works:
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +#define SERIAL_DEV PNP_DEV(CONFIG_SIO_PORT, W83627HF_SP1)
I believe most SIOs have a strap option for 4e, so presumably this address needs to be project selectable by some method. Phoenix legacy BIOS actually figures it out at runtime. That method seems dangerous to me and makes stepping through the code tedious.
If we remove it from kconfig, would it just be local to romstage.c? I suppose this would be a separate patch, given the number of projects affected.
Thanks, Scott
* Scott Duplichan scott@notabs.org [110225 02:02]:
Stefan Reinauer wrote:
]> +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
]if CONFIG_SIO_PORT is defined in Kconfig (why?) we could as well use it ]in romstage.c. Is there a chance to remove it from Kconfig instead?
Certainly the two occurrences of 2e is not ideal. This change works:
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +#define SERIAL_DEV PNP_DEV(CONFIG_SIO_PORT, W83627HF_SP1)
That would work. Or leave the first version and we try to get rid of the Kconfig variable later on...
Anyways Acked-by: Stefan Reinauer stefan.reinauer@coreboot.org
I believe most SIOs have a strap option for 4e, so presumably this address needs to be project selectable by some method. Phoenix legacy BIOS actually figures it out at runtime. That method seems dangerous to me and makes stepping through the code tedious.
You can certainly detect where it lives and what kind of device it is (though I have not seen Phoenix do that during runtime on intel systems, according to SerialICE) .. The one thing I think you can not probe is how the ports are wired up (i.e. if you have two Super I/O chips, is the one serial port connected to the first or second chip)
If we remove it from kconfig, would it just be local to romstage.c? I suppose this would be a separate patch, given the number of projects affected.
There's always at least another occurence in devicetree.cb. But that is not used in romstage, only in ramstage.
Maybe it is time to think about extending the devicetree.cb so it can be used by romstage, too? But that's for another mail.
On 02/24/2011 04:14 AM, Jonathan A. Kollasch wrote:
Hi,
I've attempted to use the rs780 and sb800 code on a AM3 870 + SB850 board. Raminit seems to go okay, as does the first bits of ramstage. However, ramstage fails after the first two passes through rs780_enable(). It stalls in get_vid_did() reading PCI config space of device 2 (or 4). Also, the rs780 HT init code thinks the link should run at 200MHz, maybe that's related.
I'm aware that this code wasn't exactly intended for the 870, but maybe someone has some hints of what to try next.
Output output output output from the serial port. Please. :)
Alex
Dear Jonathan,
Am Donnerstag, den 24.02.2011, 02:14 +0000 schrieb Jonathan A. Kollasch:
I've attempted to use the rs780 and sb800 code on a AM3 870 + SB850 board.
what is the model number?
[…]
Good luck with the port!
Thanks,
Paul
On Thu, Feb 24, 2011 at 02:14:07AM +0000, Jonathan A. Kollasch wrote:
Hi,
I've attempted to use the rs780 and sb800 code on a AM3 870 + SB850 board. Raminit seems to go okay, as does the first bits of ramstage. However, ramstage fails after the first two passes through rs780_enable(). It stalls in get_vid_did() reading PCI config space of device 2 (or 4). Also, the rs780 HT init code thinks the link should run at 200MHz, maybe that's related.
Attached is the diff, and console output there from. (Mainboard directory is a svn cp of bimini_fam10.)
Jonathan Kollasch
On Thu, Feb 24, 2011 at 7:23 AM, Jonathan A. Kollasch jakllsch@kollasch.net wrote:
On Thu, Feb 24, 2011 at 02:14:07AM +0000, Jonathan A. Kollasch wrote:
Hi,
I've attempted to use the rs780 and sb800 code on a AM3 870 + SB850 board. Raminit seems to go okay, as does the first bits of ramstage. However, ramstage fails after the first two passes through rs780_enable(). It stalls in get_vid_did() reading PCI config space of device 2 (or 4). Also, the rs780 HT init code thinks the link should run at 200MHz, maybe that's related.
Attached is the diff, and console output there from. (Mainboard directory is a svn cp of bimini_fam10.)
rs780_htinit cpu_ht_freq=0. rs780_htinit: HT1 mode
It looks it had problems getting the HT frequency from the CPU. Both sides have to agree on what is capable. You may need to look at the CPU HT code for a hint on why it reports what it does to the SB.
Marc
-----Original Message----- From: coreboot-bounces@coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Marc Jones Sent: Thursday, February 24, 2011 10:45 AM To: Jonathan A. Kollasch Cc: coreboot@coreboot.org Subject: Re: [coreboot] 870 attempt
On Thu, Feb 24, 2011 at 7:23 AM, Jonathan A. Kollasch jakllsch@kollasch.net wrote:
On Thu, Feb 24, 2011 at 02:14:07AM +0000, Jonathan A. Kollasch wrote:
Hi,
I've attempted to use the rs780 and sb800 code on a AM3 870 + SB850 board. Raminit seems to go okay, as does the first bits of ramstage. However, ramstage fails after the first two passes through rs780_enable(). It stalls in get_vid_did() reading PCI config space of device 2 (or 4). Also, the rs780 HT init code thinks the link should run at 200MHz, maybe that's related.
Attached is the diff, and console output there from. (Mainboard directory is a svn cp of bimini_fam10.)
rs780_htinit cpu_ht_freq=0. rs780_htinit: HT1 mode
]It looks it had problems getting the HT frequency from the CPU. Both ]sides have to agree on what is capable. You may need to look at the ]CPU HT code for a hint on why it reports what it does to the SB. ] ]Marc
Also remember that the family 10h swap list problem still exists. There are some old patches and discussion that might be useful. Here is an example:
http://www.mail-archive.com/coreboot@coreboot.org/msg27356.html
On Thu, Feb 24, 2011 at 11:07:04AM -0600, Scott Duplichan wrote:
-----Original Message----- From: coreboot-bounces@coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Marc Jones Sent: Thursday, February 24, 2011 10:45 AM To: Jonathan A. Kollasch Cc: coreboot@coreboot.org Subject: Re: [coreboot] 870 attempt
On Thu, Feb 24, 2011 at 7:23 AM, Jonathan A. Kollasch jakllsch@kollasch.net wrote:
On Thu, Feb 24, 2011 at 02:14:07AM +0000, Jonathan A. Kollasch wrote:
Hi,
I've attempted to use the rs780 and sb800 code on a AM3 870 + SB850 board. Raminit seems to go okay, as does the first bits of ramstage. However, ramstage fails after the first two passes through rs780_enable(). It stalls in get_vid_did() reading PCI config space of device 2 (or 4). Also, the rs780 HT init code thinks the link should run at 200MHz, maybe that's related.
Attached is the diff, and console output there from. (Mainboard directory is a svn cp of bimini_fam10.)
rs780_htinit cpu_ht_freq=0. rs780_htinit: HT1 mode
]It looks it had problems getting the HT frequency from the CPU. Both ]sides have to agree on what is capable. You may need to look at the ]CPU HT code for a hint on why it reports what it does to the SB. ] ]Marc
Also remember that the family 10h swap list problem still exists. There are some old patches and discussion that might be useful. Here is an example:
http://www.mail-archive.com/coreboot@coreboot.org/msg27356.html
That seems to let it detect HT3 before warm reset, and the warm reset succeeded, something that didn't happen when I attempted to force HT3. Unfortunately that didn't also fix the stall on config space access.
Jonathan Kollasch
Jonathan A. Kollasch wrote:
]That seems to let it detect HT3 before warm reset, and the warm ]reset succeeded, something that didn't happen when I attempted to ]force HT3. Unfortunately that didn't also fix the stall on ]config space access. ] ] Jonathan Kollasch
You could try disabling device 2 and 4 in devicetree.cb as a way to see what other problems remain. I suppose you might need device 2 for a graphics card. It might be possible that some action is needed to turn on clocks or slot power.
I also noticed the last line of rs780_ht.c references PCI device ID 9600 (PCI_DEVICE_ID_AMD_RS780_HT). Not sure if revising that is important.
Thanks, Scott
* Scott Duplichan scott@notabs.org [110224 18:07]:
-----Original Message----- From: coreboot-bounces@coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Marc Jones Sent: Thursday, February 24, 2011 10:45 AM To: Jonathan A. Kollasch Cc: coreboot@coreboot.org Subject: Re: [coreboot] 870 attempt
On Thu, Feb 24, 2011 at 7:23 AM, Jonathan A. Kollasch jakllsch@kollasch.net wrote:
On Thu, Feb 24, 2011 at 02:14:07AM +0000, Jonathan A. Kollasch wrote:
Hi,
I've attempted to use the rs780 and sb800 code on a AM3 870 + SB850 board. Raminit seems to go okay, as does the first bits of ramstage. However, ramstage fails after the first two passes through rs780_enable(). It stalls in get_vid_did() reading PCI config space of device 2 (or 4). Also, the rs780 HT init code thinks the link should run at 200MHz, maybe that's related.
Attached is the diff, and console output there from. (Mainboard directory is a svn cp of bimini_fam10.)
rs780_htinit cpu_ht_freq=0. rs780_htinit: HT1 mode
]It looks it had problems getting the HT frequency from the CPU. Both ]sides have to agree on what is capable. You may need to look at the ]CPU HT code for a hint on why it reports what it does to the SB. ] ]Marc
Also remember that the family 10h swap list problem still exists. There are some old patches and discussion that might be useful. Here is an example:
http://www.mail-archive.com/coreboot@coreboot.org/msg27356.html
Acked-by: Stefan Reinauer stefan.reinauer@coreboot.org
]> Also remember that the family 10h swap list problem still exists. ]> There are some old patches and discussion that might be useful. ]> Here is an example: ]> ]> http://www.mail-archive.com/coreboot@coreboot.org/msg27356.html ] ] Acked-by: Stefan Reinauer stefan.reinauer@coreboot.org
Thanks Stefen, rev 6439. Thanks, Scott
On Thu, Feb 24, 2011 at 02:14:07AM +0000, Jonathan A. Kollasch wrote:
Hi,
I've attempted to use the rs780 and sb800 code on a AM3 870 + SB850 board. Raminit seems to go okay, as does the first bits of ramstage. However, ramstage fails after the first two passes through rs780_enable(). It stalls in get_vid_did() reading PCI config space of device 2 (or 4). Also, the rs780 HT init code thinks the link should run at 200MHz, maybe that's related.
I'm aware that this code wasn't exactly intended for the 870, but maybe someone has some hints of what to try next.
This turned out to be GLOBAL_RESET_GFX and GLOBAL_RESET_GPPSB being set. I now get to the payload, but no SATA drives are detected, also, some of the PCIe x1 ports (onboard and slots) aren't quite right yet ...
Jonathan Kollasch
On Sun, Feb 27, 2011 at 11:41:11PM +0000, Jonathan A. Kollasch wrote:
On Thu, Feb 24, 2011 at 02:14:07AM +0000, Jonathan A. Kollasch wrote:
Hi,
I've attempted to use the rs780 and sb800 code on a AM3 870 + SB850 board. Raminit seems to go okay, as does the first bits of ramstage. However, ramstage fails after the first two passes through rs780_enable(). It stalls in get_vid_did() reading PCI config space of device 2 (or 4). Also, the rs780 HT init code thinks the link should run at 200MHz, maybe that's related.
This turned out to be GLOBAL_RESET_GFX and GLOBAL_RESET_GPPSB being set. I now get to the payload, but no SATA drives are detected, also, some of the PCIe x1 ports (onboard and slots) aren't quite right yet ...
Well seen.
In fact I was having the same exact symptoms as you, and your solution has helped me, thank you all. With Scott Duplichan's patch I got HT3, and with the attached patch (to rev.6458) I can get FILO to load linux. (but linux won't boot). But this patch can't be checked in, it's just an experiment. In fact I'm not sure of how to do it properly.
Funny enough I don't have a rs870 or sb850 . I have a sb710 and a rx780/rx790 on an ASUS M4A77TD-PRO . But the same solution works as with rs870. Maybe my rx780 was a rs870 that didn't pass QC and had its GPU disabled ?
Anyway, apparently Jonathan board and mine need to clear the GLOBAL_RESET_GFX and GLOBAL_RESET_GPPSB (which are 1 on boot). In my case I need to do this before any pci_locate_device call is made. Otherwise it hangs. I was using a patch[1] that eliminated all early pci_locate_device calls and hardcoded bus,device,function and that got me past romstage, but it still hanged in ramstage in pci enable, and clearing the resets fixes it, so it's better to clear them soon and not hardcode bdf. This means I need it in the bootblock, between the FAM10 northbridge bootblock code and the SB700 southbridge code. But I guess it would be good to do it in any rs780 family southbridge, whatever the sb. So what would be the proper way ?
1- change src/arch/x86/init/bootblock_simple.c so that it calls a "middlebridge_init" between bootblock_northbridge_init(); and bootblock_southbridge_init(); and have it empty always except for rs780 ? Too invasive ?
2- put a function in rs780/early_init.c to clear the resets and call it from the beginning of roomstage.c for boards which need it ? Then I would have to hardcode bdf in sb700/bootblock.c to avoid pci_locate_device before romstage.
3.- add a call to sb700/bootblock.c to a function that is empty for all but rs780 family chips ?
4.- call some form of weak function from src/arch/x86/init/bootblock_simple.c that does nothing by default but any board can override ? (in a specific C file, I guess, since it'll have to be linked to the bootblock).
5.- have some kconfig magic replace src/arch/x86/init/bootblock_simple.c with some board or southbridge or something specific code ?
6+ .- ... others ?
in any case, if the rs780 reset bits are cleared in bootblock (i.e. we don't choose option 2), I'd need to add some code for set_nbmisc_enable_bits which I think is not in the bootblock now (this code is in bootblock.c in the illustrative patch I'm attaching). This code is already duplicated in southbridge/amd/rs780/cmn.c and southbridge/amd/rs780/early_setup.c so I hesitate to make a third copy in the bootblock.
1.- should it be separated into a link file to have it in one place and include or link it in the three places where it is needed ?
2.- should the entire rs780/early_setup.c be linked in the bootblock (does it need to be tiny?).
In any case, does anyone have any idea on what to do to get linux to boot ?. I've tried to initialise the sb710 in AHCI mode but then filo won't find the disk (might have been done it wrong, I don't have the patch here). I've tried to fix a little sata.c and pcie.c (see patch) but I'm not sure it helps.
The kernel hangs after the message pci 0000:00:11.0: set SATA to AHCI mode With the original BIOS it continues with pci 0000:00:12.0: reg 10: [mem 0xf7ffe000-0xf7ffefff] (12 is USB) With the original BIOS and passing acpi=off to the kernel, linux boots but 2 USB ports don't work (the kernel complains of the loading ehci too late). So maybe it's something in OHCI initialization ? Or maybe I need to look into ACPI (I thought it wasn't needed, so I left the tilapia code).
I'm attaching the patch, also a patch for the mainboard (copied from tilapia_fam10, I never looked into acpi and the mptable utility complains of extended table hosed, so I left the mptable.c identical to tilapia or other boards), the boot log and an lspci output, and a dmesg with the original BIOS and acpi=off in the kernel command line. Maybe somebody has any idea... I may have even less spare time from now until august to look at this...
Thank you.
[1] http://www.coreboot.org/pipermail/coreboot/2010-August/059899.html
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Alex G. -
Anish Patel -
Jonathan A. Kollasch -
Marc Jones -
Paul Menzel -
Peter Stuge -
Scott Duplichan -
Stefan Reinauer -
xdrudis