coreboot-4.0-r6375:6378M- Thu Feb 24 08:03:37 CST 2011 starting... BSP Family_Model: 00100f43 *sysinfo range: [000cc000,000cf360] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: equivalent rev id = 0x1043, current patch id = 0x00000000 microcode: patch id to apply = 0x010000b6 microcode: updated to patch id = 0x010000b6 success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify() event class: 02 event: 2005 data: 05 00 00 00 01 AMD_CB_EventNotify() event class: 05 event: 2006 data: 04 00 00 ff Exit amd_ht_init() cpuSetAMDPCI 00 done Prep FID/VID Node:00 F3x80: e600a681 F3x84: a0e641e6 F3xD4: c8810f24 F3xD8: 03001716 F3xDC: 00005336 core0 started: start_other_cores() init node: 00 cores: 03 Start other core - nodeid: 00 cores: 03 started ap apicid: cccoororerexe:xx :: ------- --{ {{ AAAPPPIIICICCDIIDD === 01002 3 N ONNOODDDEEEIIDID D = = =0 00000 C COCORORERIEEDII DD= == 00102}3} }- -------- * mAimmPcii cc0rrr1ooosccctoooadddreeet::e : de e qeq uq*iuu viiAavvPlaa ellnee0tnn2 ttsr trraeeervt vvi ediid dd *== = A0 0Px0 1xx00113400344s,33t,,a rccctuuuerrdrrr ere ne tnn ttp rpspaa7at8tct0chc_h he i aidird d = l =y=0 _ x0s00xex0t000u000p00(000)000000 000 0 0g e t _cpum_immicrireccovrrc oooEccAoodXdde=ee::: 0 pxppa1at0atc0tchfch 4h i3 d.ii ddt ttoCoo P aU ap apppRplpeylvl y y= i =s=0 0K0xx8x0_01011010000000.000 0b0 b6bf66a m 1m0immcii_rccoorrpcootcciooomdddieeez:::a tuuipupodpdnada(ta)ett dee ddt rsttooo 7 p8pa0pat_atcpthocc rhhi_ iiidndd i =t== 0 00xxx000101100000000000b6bb6 6 s s bsus8cu0ucc0cec_ceeessasssrs l y _ scpecutcpSupueput(SSA)eeM ttD AAMsMMSbDDR8MM 0SS0RR_ d edvoi ddcnoeeons ne_ e p i noiriinn_tiii_tnft_ii_ftdfi(vi)idd dvv _iiaddsp__b(aa8spp0((0tss_atdgtaeeagv1gei)ec 11ea))sp iaa_pppciioicrdci_:ii ddn0::i1 t 00( 32)F I :DFF IISVDMIDVBDVIu IDsoD n D ooeAnnP v:AAi PPc::e0 ,1 00 32B D F:0-20-0 SMBus controller enabled, sb revision is A12 sb800_devices_por_init(): IDE Device, BDF:0-20-1 sb800_devices_por_init(): LPC Device, BDF:0-20-3 sb800_devices_por_init(): P2P Bridge, BDF:0-20-4 sb800_devices_por_init(): SATA Device, BDF:0-18-0 Begin FIDVID MSR 0xc0010071 0x30bc00d3 0x40036c40 FIDVID on BSP, APIC_id: 00 BSP fid = 10600 Wait for AP stage 1: ap_apicid = 1 readback = 1010601 common_fid(packed) = 10600 Wait for AP stage 1: ap_apicid = 2 readback = 2010601 common_fid(packed) = 10600 Wait for AP stage 1: ap_apicid = 3 readback = 3010601 common_fid(packed) = 10600 common_fid = 10600 FID Change Node:00, F3xD4: c8810f26 End FIDVIDMSR 0xc0010071 0x30bc00d3 0x40036c40 rs780_htinit cpu_ht_freq=0. rs780_htinit: HT1 mode ...WARM RESET... coreboot-4.0-r6375:6378M- Thu Feb 24 08:03:37 CST 2011 starting... BSP Family_Model: 00100f43 *sysinfo range: [000cc000,000cf360] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: equivalent rev id = 0x1043, current patch id = 0x00000000 microcode: patch id to apply = 0x010000b6 microcode: updated to patch id = 0x010000b6 success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify() event class: 02 event: 2005 data: 05 00 00 00 01 AMD_CB_EventNotify() event class: 05 event: 2006 data: 04 00 00 ff Exit amd_ht_init() cpuSetAMDPCI 00 done Prep FID/VID Node:00 F3x80: e600a681 F3x84: a0e641e6 F3xD4: c8810f26 F3xD8: 03001716 F3xDC: 00005336 core0 started: start_other_cores() init node: 00 cores: 03 Start other core - nodeid: 00 cores: 03 started ap apicid: ccocoorrereex:xx:: - ------ -- { {{ AAPAPPIICICCIIDIDD = == 010023 N NONOODEDDEEIIDIDD = == 00000 0C COCOORRREIEEIDI DD = == 0 0013}2}} ------- -- * miAmmciiPc rcorr0o1cosoccootdaeddeer:t :: eedqeeqq u iuuvii*v avlaaAlPelnee n0tn tt2 srterreeavr vv itdeiidd d = = *= 00xA0Pxx110 100044334s33,,, tca ccurrtuurrreedrr eennt n tt p appratatstcc7hh8c0h ii_ eidd adr == l=0y 00xx_0sx0000e0t00u00000p0(00000)0 000 0g e t_cpmmum_iiiccrcerrroovo cccoooEdAddeeeX:=::0 ppxp1aaatt0t0ccchhhf 4 iii3d.dd tt toooCP aaUap pppppRlellyyyv ===i s 000 xxKx800011_110000000.00000 0 bbb666f a m 1mmmi0ii_cccrrorpooocctcioooddmdeiee:::z a uuutpippdddoanaattt(ee)e ddd tttrsooo 7 8pppaa0a_tttccpcohhh r i_iidddi n ===i t 000 xx x000111000000000000bbb666 sssbs8uuucc0cc0cceee_sesssssa r l y _ scccepptpuuuuSSpS(eeett)t AAAMMM DsDDMMMbS8SS0RRR 0 _dev idddcooeosnnnee_ep o riii_nninniiittti_t__fff(i)ii dddvv vsiiiddbd8___ss0st0ttaaa_gdggeeee2v22i aacaepppiisic_cciipioddd::r:_ 00i0n213 i t (): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A12 sb800_devices_por_init(): IDE Device, BDF:0-20-1 sb800_devices_por_init(): LPC Device, BDF:0-20-3 sb800_devices_por_init(): P2P Bridge, BDF:0-20-4 sb800_devices_por_init(): SATA Device, BDF:0-18-0 Begin FIDVID MSR 0xc0010071 0x30bc00d3 0x40033440 End FIDVIDMSR 0xc0010071 0x30bc00d3 0x4000340e rs780_htinit cpu_ht_freq=0. rs780_htinit: HT1 mode fill_mem_ctrl() raminit_amdmct() raminit_amdmct begin: DIMMPresence: DIMMValid=f DIMMPresence: DIMMPresent=f DIMMPresence: RegDIMMPresent=0 DIMMPresence: DimmECCPresent=0 DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=0 DIMMPresence: Dimmx8Present=f DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=f DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=4 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=2 DIMMPresence: DATAload[1]=4 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=2 DIMMPresence: Status 1000 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTInit_D: mct_DIMMPresence Done SPDCalcWidth: Status 1000 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done SPDGetTCL_D: DIMMCASL 4 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 1000 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done AutoCycTiming: Status 1000 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent f SPDSetBanks: Status 1000 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = ffffff StitchMemory: Status 1000 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 1000 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 2a06 AutoConfig_D: DramTimingLo: 90092 AutoConfig_D: DramConfigMisc: 0 AutoConfig_D: DramConfigMisc2: 0 AutoConfig_D: DramConfigLo: 10000 AutoConfig_D: DramConfigHi: f48000b AutoConfig: Status 1000 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D DCTInit_D: mct_DIMMPresence Done SPDCalcWidth: Status 1000 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming: Status 1000 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent f SPDSetBanks: Status 1000 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1fffffe StitchMemory: Status 1000 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 1000 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 2a06 AutoConfig_D: DramTimingLo: 90092 AutoConfig_D: DramConfigMisc: 0 AutoConfig_D: DramConfigMisc2: 0 AutoConfig_D: DramConfigLo: 10000 AutoConfig_D: DramConfigHi: f48000b AutoConfig: Status 1000 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D mctAutoInitMCT_D: SyncDCTsReady_D mctAutoInitMCT_D: HTMemMapInit_D Node: 00 base: 00 limit: 1ffffff BottomIO: e00000 Node: 00 base: 03 limit: 21fffff Node: 01 base: 00 limit: 00 Node: 02 base: 00 limit: 00 Node: 03 base: 00 limit: 00 Node: 04 base: 00 limit: 00 Node: 05 base: 00 limit: 00 Node: 06 base: 00 limit: 00 Node: 07 base: 00 limit: 00 mctAutoInitMCT_D: CPUMemTyping_D CPUMemTyping: Cache32bTOP:e00000 CPUMemTyping: Bottom32bIO:e00000 CPUMemTyping: Bottom40bIO:2200000 mctAutoInitMCT_D: DQSTiming_D TrainRcvrEn: Status 1100 TrainRcvrEn: ErrStatus 0 TrainRcvrEn: ErrCode 0 TrainRcvrEn: Done TrainDQSRdWrPos: Status 1100 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 0 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 1100 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 0 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 1100 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 0 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 1100 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 0 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done mctAutoInitMCT_D: UMAMemTyping_D mctAutoInitMCT_D: :OtherTiming InterleaveNodes_D: Status 1100 InterleaveNodes_D: ErrStatus 0 InterleaveNodes_D: ErrCode 0 InterleaveNodes_D: Done InterleaveChannels_D: Node 0 InterleaveChannels_D: Status 1100 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 1 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 2 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 3 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 4 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 5 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 6 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 7 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Done mctAutoInitMCT_D: ECCInit_D All Done raminit_amdmct end: v_esp=000cbf48 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Loading image. Check CBFS header at fffffcae magic is 4f524243 Found CBFS header at fffffcae Check cmos_layout.bin CBFS: follow chain: fff00000 + 28 + 6ef + align -> fff00740 Check fallback/romstage CBFS: follow chain: fff00740 + 38 + 1751c + align -> fff17cc0 Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x200000 (1179648 bytes), entry @ 0x200000 Stage: done loading. Jumping to image. coreboot-4.0-r6375:6378M- Thu Feb 24 08:03:37 CST 2011 booting... Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 0 PCI: 00:04.0: enabled 1 PCI: 00:05.0: enabled 0 PCI: 00:06.0: enabled 0 PCI: 00:07.0: enabled 0 PCI: 00:08.0: enabled 0 PCI: 00:09.0: enabled 1 PCI: 00:0a.0: enabled 1 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:12.2: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.2: enabled 1 PCI: 00:14.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 0 PNP: 002e.3: enabled 0 PNP: 002e.4: enabled 0 PNP: 002e.5: enabled 0 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PCI: 00:14.4: enabled 0 PCI: 00:14.5: enabled 1 PCI: 00:14.6: enabled 1 PCI: 00:15.0: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 1 PCI: 00:15.3: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:16.2: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 Compare with tree... Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 0 PCI: 00:04.0: enabled 1 PCI: 00:05.0: enabled 0 PCI: 00:06.0: enabled 0 PCI: 00:07.0: enabled 0 PCI: 00:08.0: enabled 0 PCI: 00:09.0: enabled 1 PCI: 00:0a.0: enabled 1 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:12.2: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.2: enabled 1 PCI: 00:14.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 0 PNP: 002e.3: enabled 0 PNP: 002e.4: enabled 0 PNP: 002e.5: enabled 0 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PCI: 00:14.4: enabled 0 PCI: 00:14.5: enabled 1 PCI: 00:14.6: enabled 1 PCI: 00:15.0: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 1 PCI: 00:15.3: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:16.2: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 scan_static_bus for Root Device APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 scanning... PCI: 00:18.3 siblings=3 CPU: APIC: 00 enabled CPU: APIC: 01 enabled CPU: APIC: 02 enabled CPU: APIC: 03 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:18.0 [1022/1200] bus ops PCI: 00:18.0 [1022/1200] enabled PCI: 00:18.1 [1022/1201] enabled PCI: 00:18.2 [1022/1202] enabled PCI: 00:18.3 [1022/1203] ops PCI: 00:18.3 [1022/1203] enabled PCI: 00:18.4 [1022/1204] enabled gvdPCI: Using configuration type 1 59571002 rs780_enable: dev=002198bc, VID_DID=0x59571002 Bus-0, Dev-0, Fun-0. enable_pcie_bar3() addr=e0000000,bus=0,devfn=40 gpp_sb_init nb_dev=0x0, dev=0x40, port=0x8 NB_PCI_REG04 = 6. NB_PCI_REG84 = 3000095. NB_PCI_REG4C = 52042. PCI: 00:00.0 [1002/5957] enabled Capability: type 0x08 @ 0xc4 flags: 0x0181 PCI: pci_scan_bus for bus 00 PCI: pci_scan_bus limits devfn 0 - devfn ffffffff PCI: pci_scan_bus upper limit too big. Using 0xff. gvd59571002 rs780_enable: dev=002198bc, VID_DID=0x59571002 Bus-0, Dev-0, Fun-0. enable_pcie_bar3() gpp_sb_init nb_dev=0x0, dev=0x40, port=0x8 NB_PCI_REG04 = 6. NB_PCI_REG84 = 3000095. NB_PCI_REG4C = 52042. PCI: 00:00.0 [1002/5957] enabled gvd