coreboot-4.0-r6458M Tue Mar 22 00:36:43 CET 2011 starting... BSP Family_Model: 00100f43 *sysinfo range: [000cc000,000cf360] bsp_apicid = 00 cpu_init_detectedx = 00000000 POST: 0x33 cpuSetAMDMSR done POST: 0x34 Enter amd_ht_init() Exit amd_ht_init() POST: 0x35 cpuSetAMDPCI 00 done Prep FID/VID Node:00 F3x80: e60bf681 F3x84: 80e641e6 F3xD4: c8810f24 F3xD8: 03001a15 F3xDC: 0000632e POST: 0x36 core0 started: start_other_cores() init node: 00 cores: 03 Start other core - nodeid: 00 cores: 03 POST: 0x37 started ap apicid: PPPOOOSSSTTT::: 000xxx333000 cccooorrreeexxx::: --------- {{{ AAAPPPIIICCCIIIDDD === 000321 NNNOOODDDEEEIIIDDD === 000000 CCCOOORRREEEIIIDDD === 000312}}} --------- *cccpp puuAuSSPSee ett0tAA1AMMsMDDDtMMMaSSSrRRRt ed * dddAoooPnnn eee0 2 siiintnniaiitrtt_t__feffidiidddv vvi*iid dd__A_aaPapp p((0(ss3sttstaataggageeer111t))e) d aaappp iiiccc iiiPdddO:::S T000:123 0 xFFF38IIIDDD VVVrIsIID7DD 8 o0oon_nn e AAaAPPrP::l: y 00_023s1e t up() get_cpu_rev EAX=0x100f43. CPU Rev is K8_10. fam10_optimization() rs780_por_init after rs780 early setup sb700_early_setup() sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A14 sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-18-0 sb700_pmio_por_init() Begin FIDVID MSR 0xc0010071 0x30b400f3 0x50035c40 POST: 0x39 FIDVID on BSP, APIC_id: 00 BSP fid = 10600 Wait for AP stage 1: ap_apicid = 1 readback = 1010601 common_fid(packed) = 10600 Wait for AP stage 1: ap_apicid = 2 readback = 2010601 common_fid(packed) = 10600 Wait for AP stage 1: ap_apicid = 3 readback = 3010601 common_fid(packed) = 10600 common_fid = 10600 FID Change Node:00, F3xD4: c8810f26 POST: 0x3a End FIDVIDMSR 0xc0010071 0x30b400f3 0x40005c40 rs780_htinit cpu_ht_freq=b. rs780_htinit: HT3 mode ...WARM RESET... coreboot-4.0-r6458M Tue Mar 22 00:36:43 CET 2011 starting... BSP Family_Model: 00100f43 *sysinfo range: [000cc000,000cf360] bsp_apicid = 00 cpu_init_detectedx = 00000000 POST: 0x33 cpuSetAMDMSR done POST: 0x34 Enter amd_ht_init() Exit amd_ht_init() POST: 0x35 cpuSetAMDPCI 00 done Prep FID/VID Node:00 F3x80: e60bf681 F3x84: 80e641e6 F3xD4: c8810f26 F3xD8: 03001a15 F3xDC: 0000632e POST: 0x36 core0 started: start_other_cores() init node: 00 cores: 03 Start other core - nodeid: 00 cores: 03 POST: 0x37 started ap apicid: PPPOOOSSSTTT::: 000xxx333000 cccooorrreeexxx::: --------- {{{ AAAPPPIIICCCIIIDDD === 000321 NNNOOODDDEEEIIIDDD === 000000 CCCOOORRREEEIIIDDD === 000321}}} --------- *cccppp AuuuSSPS eeett0t1AAAMMsMtDDDMMaMSSSrRtRR ed ddd*o oonnnAePee 0 ii2isnnniitiattt__r_tfffiieiddddvvv iiid*dd___ sAssttPt aaagg0g3eee22s2t aaaarpppitiiccceidiiddd: :: 0 00132PO S T: 0x38 rs780_early_setup() get_cpu_rev EAX=0x100f43. CPU Rev is K8_10. fam10_optimization() rs780_por_init after rs780 early setup sb700_early_setup() sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A14 sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-18-0 sb700_pmio_por_init() Begin FIDVID MSR 0xc0010071 0x30b400f3 0x40005c40 POST: 0x39 POST: 0x3a End FIDVIDMSR 0xc0010071 0x30b400f3 0x40003c0a rs780_htinit cpu_ht_freq=b. rs780_htinit: HT3 mode POST: 0x3b fill_mem_ctrl() POST: 0x40 dimm: 00.0: 50 00: 92 10 0b 02 03 19 00 09 03 52 01 08 0c 00 3c 00 10: 69 78 69 30 69 11 20 8c 00 05 3c 3c 00 f0 83 0d 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 10 11 01 01 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 04 cd 00 00 00 00 00 00 00 fe e2 dimm: 00.1: 51 00: 92 10 0b 02 03 19 00 09 03 52 01 08 0c 00 3c 00 10: 69 78 69 30 69 11 20 8c 00 05 3c 3c 00 f0 83 0d 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 10 11 01 01 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 04 cd 00 00 00 00 00 00 00 fe e2 dimm: 01.0: 52 00: dimm: 01.1: 53 00: smbus: 20 00: 03 00 00 00 00 00 00 00 00 00 00 00 00 00 02 ae 10: 00 00 00 00 00 00 2f a8 c0 00 00 00 00 00 0c 01 20: 01 01 01 ff ff ff ff ff ff ff ff ff ff ff ff ff 30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff b0: ff ff 09 ff ff 09 ff ff ff ff ff ff ff ff ff ff c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff smbus: 38 00: 01 00 00 00 00 50 ac 14 81 b4 08 10 7c 04 00 00 10: 01 00 00 00 00 50 ac 14 81 b4 08 10 7c 04 00 00 20: 01 00 00 00 00 50 ac 14 81 b4 08 10 7c 04 00 00 30: 01 00 00 00 00 50 ac 14 81 b4 08 10 7c 04 00 00 40: 01 00 00 00 00 50 ac 14 81 b4 08 10 7c 04 00 00 50: 01 00 00 00 00 50 ac 14 81 b4 08 10 7c 04 00 00 60: 01 00 00 00 00 50 ac 14 81 b4 08 10 7c 04 00 00 70: 01 00 00 00 00 50 ac 14 81 b4 08 10 7c 04 00 00 80: 01 00 00 00 00 50 ac 14 81 b4 08 10 7c 04 00 00 90: 01 00 00 00 00 50 ac 14 81 b4 08 10 7c 04 00 00 a0: 01 00 00 00 00 50 ac 14 81 b4 08 10 7c 04 00 00 b0: 01 00 00 00 00 50 ac 14 81 b4 08 10 7c 04 00 00 c0: 01 00 00 00 00 50 ac 14 81 b4 08 10 7c 04 00 00 d0: 01 00 00 00 00 50 ac 14 81 b4 08 10 7c 04 00 00 e0: 01 00 00 00 00 50 ac 14 81 b4 08 10 7c 04 00 00 f0: 01 00 00 00 00 50 ac 14 81 b4 08 10 7c 04 00 00 smbus: 50 00: 92 10 0b 02 03 19 00 09 03 52 01 08 0c 00 3c 00 10: 69 78 69 30 69 11 20 8c 00 05 3c 3c 00 f0 83 0d 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 10 11 01 01 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 04 cd 00 00 00 00 00 00 00 fe e2 80: 46 33 2d 31 30 36 36 36 43 4c 39 2d 34 47 42 52 90: 4c 00 00 00 04 cd 00 00 00 00 00 00 ff ff ff ff a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 smbus: 51 00: 92 10 0b 02 03 19 00 09 03 52 01 08 0c 00 3c 00 10: 69 78 69 30 69 11 20 8c 00 05 3c 3c 00 f0 83 0d 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 10 11 01 01 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 04 cd 00 00 00 00 00 00 00 fe e2 80: 46 33 2d 31 30 36 36 36 43 4c 39 2d 34 47 42 52 90: 4c 00 00 00 04 cd 00 00 00 00 00 00 ff ff ff ff a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 smbus: 69 00: 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 10: 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 20: 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 30: 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f raminit_amdmct() raminit_amdmct begin: DIMMPresence: DIMMValid=3 DIMMPresence: DIMMPresent=3 DIMMPresence: RegDIMMPresent=0 DIMMPresence: DimmECCPresent=0 DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=0 DIMMPresence: Dimmx8Present=3 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=3 DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=10 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=10 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 1000 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTInit_D: mct_DIMMPresence Done SPDCalcWidth: Status 1000 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done SPDGetTCL_D: DIMMCASL 4 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 1000 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done AutoCycTiming: Status 1000 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent 3 SPDSetBanks: Status 1000 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = ffffff StitchMemory: Status 1000 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 1000 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 2a06 AutoConfig_D: DramTimingLo: 90092 AutoConfig_D: DramConfigMisc: 0 AutoConfig_D: DramConfigMisc2: 0 AutoConfig_D: DramConfigLo: 10000 AutoConfig_D: DramConfigHi: f48000b AutoConfig: Status 1000 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D DCTInit_D: mct_DIMMPresence Done SPDCalcWidth: Status 1000 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming: Status 1000 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent 3 SPDSetBanks: Status 1000 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1fffffe StitchMemory: Status 1000 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 1000 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 2a06 AutoConfig_D: DramTimingLo: 90092 AutoConfig_D: DramConfigMisc: 0 AutoConfig_D: DramConfigMisc2: 0 AutoConfig_D: DramConfigLo: 10000 AutoConfig_D: DramConfigHi: f48000b AutoConfig: Status 1000 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D mctAutoInitMCT_D: SyncDCTsReady_D mctAutoInitMCT_D: HTMemMapInit_D Node: 00 base: 00 limit: 1ffffff BottomIO: c00000 Node: 00 base: 03 limit: 23fffff Node: 01 base: 00 limit: 00 Node: 02 base: 00 limit: 00 Node: 03 base: 00 limit: 00 Node: 04 base: 00 limit: 00 Node: 05 base: 00 limit: 00 Node: 06 base: 00 limit: 00 Node: 07 base: 00 limit: 00 mctAutoInitMCT_D: CPUMemTyping_D CPUMemTyping: Cache32bTOP:c00000 CPUMemTyping: Bottom32bIO:c00000 CPUMemTyping: Bottom40bIO:2400000 mctAutoInitMCT_D: DQSTiming_D vErrata350: dummy read vErrata350: dummy read vErrata350: dummy read vErrata350: dummy read vErrata350: dummy read vErrata350: dummy read vErrata350: dummy read vErrata350: dummy read vErrata350: step 2a vErrata350: step 2b vErrata350: step 3 vErrata350: step 4 vErrata350: step 4b vErrata350: step 5 TrainRcvrEn: Status 1100 TrainRcvrEn: ErrStatus 0 TrainRcvrEn: ErrCode 0 TrainRcvrEn: Done TrainDQSRdWrPos: Status 1100 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 0 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 1100 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 0 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 1100 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 0 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 1100 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 0 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done mctAutoInitMCT_D: UMAMemTyping_D mctAutoInitMCT_D: :OtherTiming InterleaveNodes_D: Status 1100 InterleaveNodes_D: ErrStatus 0 InterleaveNodes_D: ErrCode 0 InterleaveNodes_D: Done InterleaveChannels_D: Node 0 InterleaveChannels_D: Status 1100 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 1 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 2 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 3 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 4 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 5 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 6 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 7 InterleaveChannels_D: Status 1000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Done mctAutoInitMCT_D: ECCInit_D All Done raminit_amdmct end: POST: 0x41 POST: 0x42 *** Yes, the copy/decompress is taking a while, FIXME! v_esp=000cbf48 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Loading image. Check CBFS header at fffffb7e magic is 4f524243 Found CBFS header at fffffb7e Check cmos_layout.bin CBFS: follow chain: fff00000 + 28 + 6ef + align -> fff00740 Check fallback/romstage CBFS: follow chain: fff00740 + 38 + 177d8 + align -> fff17f80 Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x200000 (1114112 bytes), entry @ 0x200000 Stage: done loading. Jumping to image. POST: 0x80 POST: 0x39 coreboot-4.0-r6458M Tue Mar 22 00:36:43 CET 2011 booting... POST: 0x40 Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 1 PCI: 00:04.0: enabled 1 PCI: 00:05.0: enabled 0 PCI: 00:06.0: enabled 0 PCI: 00:07.0: enabled 0 PCI: 00:08.0: enabled 0 PCI: 00:09.0: enabled 0 PCI: 00:0a.0: enabled 1 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:12.1: enabled 1 PCI: 00:12.2: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.1: enabled 1 PCI: 00:13.2: enabled 1 PCI: 00:14.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 0 PNP: 002e.3: enabled 0 PNP: 002e.4: enabled 0 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 1 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PCI: 00:14.4: enabled 1 PCI: 00:14.5: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 Compare with tree... Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 1 PCI: 00:04.0: enabled 1 PCI: 00:05.0: enabled 0 PCI: 00:06.0: enabled 0 PCI: 00:07.0: enabled 0 PCI: 00:08.0: enabled 0 PCI: 00:09.0: enabled 0 PCI: 00:0a.0: enabled 1 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:12.1: enabled 1 PCI: 00:12.2: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.1: enabled 1 PCI: 00:13.2: enabled 1 PCI: 00:14.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 0 PNP: 002e.3: enabled 0 PNP: 002e.4: enabled 0 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 1 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PCI: 00:14.4: enabled 1 PCI: 00:14.5: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 Mainboard M4A77TD-PRO Enable. dev=0x002188d8 m4a77tdpro_enable, TOP MEM: msr.lo = 0xc0000000, msr.hi = 0x00000000 m4a77tdpro_enable, TOP MEM2: msr2.lo = 0x40000000, msr2.hi = 0x00000002 m4a77tdpro_enable: uma size 0x10000000, memory start 0xb0000000 PCI: Using configuration type 1 Init adt7461 end , status 0x02 fd Dev3 is not present. GFX Configuration is One x16 slot scan_static_bus for Root Device APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 scanning... malloc Enter, size 144, free_mem_ptr 00250000 malloc 00250000 PCI: 00:18.3 siblings=3 CPU: APIC: 00 enabled malloc Enter, size 72, free_mem_ptr 00250090 malloc 00250090 CPU: APIC: 01 enabled malloc Enter, size 72, free_mem_ptr 002500d8 malloc 002500d8 CPU: APIC: 02 enabled malloc Enter, size 72, free_mem_ptr 00250120 malloc 00250120 CPU: APIC: 03 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 POST: 0x24 PCI: 00:18.0 [1022/1200] bus ops PCI: 00:18.0 [1022/1200] enabled PCI: 00:18.1 [1022/1201] enabled PCI: 00:18.2 [1022/1202] enabled PCI: 00:18.3 [1022/1203] ops PCI: 00:18.3 [1022/1203] enabled PCI: 00:18.4 [1022/1204] enabled POST: 0x25 rs780_enable: dev=00218dd4, VID_DID=0x59571002 Bus-0, Dev-0, Fun-0. enable_pcie_bar3() addr=e0000000,bus=0,devfn=40 gpp_sb_init nb_dev=0x0, dev=0x40, port=0x8 NB_PCI_REG04 = 6. NB_PCI_REG84 = 3000095. NB_PCI_REG4C = 52042. PCI: 00:00.0 [1002/5957] enabled Capability: type 0x08 @ 0xc4 flags: 0x0181 PCI: pci_scan_bus for bus 00 PCI: pci_scan_bus limits devfn 0 - devfn ffffffff PCI: pci_scan_bus upper limit too big. Using 0xff. POST: 0x24 rs780_enable: dev=00218dd4, VID_DID=0x59571002 Bus-0, Dev-0, Fun-0. enable_pcie_bar3() gpp_sb_init nb_dev=0x0, dev=0x40, port=0x8 NB_PCI_REG04 = 6. NB_PCI_REG84 = 3000095. NB_PCI_REG4C = 52042. PCI: 00:00.0 [1002/5957] enabled rs780_enable: dev=00218f84, VID_DID=0x59781002 Bus-0, Dev-2,3, Fun-0. enable=1 rs780_gfx_init, nb_dev=0x00218dd4, dev=0x00218f84, port=0x2. misc 28 = 3ff57f rs780_gfx_init step5.9.12.1. rs780_gfx_init step5.9.12.3. rs780_gfx_init step5.9.12.9. rs780_gfx_init step1. device = 2 rs780_gfx_init single_port_configuration. PcieLinkTraining port=2:lc current state=a0b0f10 addr=e0000000,bus=0,devfn=10 PcieTrainPort reg=0x10000 rs780_gfx_init single_port_configuration step12. GFX Inactive Lanes = 0x0. rs780_gfx_init single_port_configuration step13. rs780_gfx_init single_port_configuration step14. Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:02.0 subordinate bus PCI Express PCI: 00:02.0 [1002/5978] enabled rs780_enable: dev=00219134, VID_DID=0xffffffff Bus-0, Dev-2,3, Fun-0. enable=1 rs780_gfx_init, nb_dev=0x00218dd4, dev=0x00219134, port=0x3. misc 28 = 3ff57f rs780_gfx_init step5.9.12.1. rs780_gfx_init step5.9.12.3. rs780_gfx_init step5.9.12.9. rs780_gfx_init step1. device = 3 Single port. Do nothing. PCI: Static device PCI: 00:03.0 not found, disabling it. rs780_enable: dev=002192e4, VID_DID=0x597a1002 Bus-0, Dev-4,5,6,7, Fun-0. enable=1 gpp_sb_init nb_dev=0x0, dev=0x20, port=0x4 PcieLinkTraining port=4:lc current state=4000102 PcieTrainPort port=0x4 result=0 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:04.0 subordinate bus PCI Express PCI: 00:04.0 [1002/597a] enabled rs780_enable: dev=002193bc, VID_DID=0x597b1002 Bus-0, Dev-4,5,6,7, Fun-0. enable=0 rs780_enable: dev=0021944c, VID_DID=0x597c1002 Bus-0, Dev-4,5,6,7, Fun-0. enable=0 rs780_enable: dev=002194dc, VID_DID=0x597d1002 Bus-0, Dev-4,5,6,7, Fun-0. enable=0 rs780_enable: dev=0021956c, VID_DID=0x59821002 Bus-0, Dev-8, Fun-0. enable=0 rs780_enable: dev=002195fc, VID_DID=0x597e1002 Bus-0, Dev-9, 10, Fun-0. enable=0 rs780_enable: dev=0021968c, VID_DID=0x597f1002 Bus-0, Dev-9, 10, Fun-0. enable=1 gpp_sb_init nb_dev=0x0, dev=0x50, port=0xa PcieLinkTraining port=a:lc current state=0 PcieTrainPort port=0xa result=0 disable_pcie_bar3() Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:0a.0 subordinate bus PCI Express PCI: 00:0a.0 [1002/597f] enabled sb700_enable() PCI: 00:11.0 [1002/4390] ops PCI: 00:11.0 [1002/4390] enabled sb700_enable() PCI: 00:12.0 [1002/4397] ops PCI: 00:12.0 [1002/4397] enabled sb700_enable() PCI: 00:12.1 [1002/4398] ops PCI: 00:12.1 [1002/4398] enabled sb700_enable() PCI: 00:12.2 [1002/4396] ops PCI: 00:12.2 [1002/4396] enabled sb700_enable() PCI: 00:13.0 [1002/4397] ops PCI: 00:13.0 [1002/4397] enabled sb700_enable() PCI: 00:13.1 [1002/4398] ops PCI: 00:13.1 [1002/4398] enabled sb700_enable() PCI: 00:13.2 [1002/4396] ops PCI: 00:13.2 [1002/4396] enabled sb700_enable() PCI: 00:14.0 [1002/4385] bus ops PCI: 00:14.0 [1002/4385] enabled sb700_enable() PCI: 00:14.1 [1002/439c] ops PCI: 00:14.1 [1002/439c] enabled sb700_enable() PCI: 00:14.2 [1002/4383] ops PCI: 00:14.2 [1002/4383] enabled sb700_enable() PCI: 00:14.3 [1002/439d] bus ops PCI: 00:14.3 [1002/439d] enabled sb700_enable() PCI: 00:14.4 [1002/4384] bus ops PCI: 00:14.4 [1002/4384] enabled sb700_enable() PCI: 00:14.5 [1002/4399] ops PCI: 00:14.5 [1002/4399] enabled malloc Enter, size 72, free_mem_ptr 00250168 malloc 00250168 PCI: 00:18.0 [1022/1200] bus ops PCI: 00:18.0 [1022/1200] enabled malloc Enter, size 72, free_mem_ptr 002501b0 malloc 002501b0 PCI: 00:18.1 [1022/1201] enabled malloc Enter, size 72, free_mem_ptr 002501f8 malloc 002501f8 PCI: 00:18.2 [1022/1202] enabled malloc Enter, size 72, free_mem_ptr 00250240 malloc 00250240 PCI: 00:18.3 [1022/1203] ops PCI: 00:18.3 [1022/1203] enabled malloc Enter, size 72, free_mem_ptr 00250288 malloc 00250288 PCI: 00:18.4 [1022/1204] enabled POST: 0x25 do_pci_scan_bridge for PCI: 00:02.0 malloc Enter, size 24, free_mem_ptr 002502d0 malloc 002502d0 PCI: pci_scan_bus for bus 01 POST: 0x24 malloc Enter, size 72, free_mem_ptr 002502e8 malloc 002502e8 PCI: 01:00.0 [10de/06e4] enabled POST: 0x25 PCI: pci_scan_bus returning with max=001 POST: 0x55 Capability: type 0x01 @ 0x60 Capability: type 0x05 @ 0x68 Capability: type 0x10 @ 0x78 do_pci_scan_bridge returns max 1 do_pci_scan_bridge for PCI: 00:04.0 malloc Enter, size 24, free_mem_ptr 00250330 malloc 00250330 PCI: pci_scan_bus for bus 02 POST: 0x24 POST: 0x25 PCI: pci_scan_bus returning with max=002 POST: 0x55 do_pci_scan_bridge returns max 2 do_pci_scan_bridge for PCI: 00:0a.0 malloc Enter, size 24, free_mem_ptr 00250348 malloc 00250348 PCI: pci_scan_bus for bus 03 POST: 0x24 POST: 0x25 PCI: pci_scan_bus returning with max=003 POST: 0x55 do_pci_scan_bridge returns max 3 scan_static_bus for PCI: 00:14.0 smbus: PCI: 00:14.0[0]->I2C: 01:50 enabled smbus: PCI: 00:14.0[0]->I2C: 01:51 enabled smbus: PCI: 00:14.0[0]->I2C: 01:52 enabled smbus: PCI: 00:14.0[0]->I2C: 01:53 enabled scan_static_bus for PCI: 00:14.0 done scan_static_bus for PCI: 00:14.3 PNP: 002e.0 disabled PNP: 002e.1 enabled PNP: 002e.2 disabled PNP: 002e.3 disabled PNP: 002e.4 disabled PNP: 002e.5 enabled PNP: 002e.6 enabled PNP: 002e.7 disabled PNP: 002e.8 disabled PNP: 002e.9 disabled PNP: 002e.a disabled scan_static_bus for PCI: 00:14.3 done do_pci_scan_bridge for PCI: 00:14.4 malloc Enter, size 24, free_mem_ptr 00250360 malloc 00250360 PCI: pci_scan_bus for bus 04 POST: 0x24 POST: 0x25 PCI: pci_scan_bus returning with max=004 POST: 0x55 do_pci_scan_bridge returns max 4 PCI: pci_scan_bus returning with max=004 POST: 0x55 PCI: pci_scan_bus returning with max=004 POST: 0x55 PCI_DOMAIN: 0000 passpw: enabled scan_static_bus for Root Device done done POST: 0x66 Setting up VGA for PCI: 01:00.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 APIC_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC: 01 missing read_resources APIC: 02 missing read_resources APIC: 03 missing read_resources APIC_CLUSTER: 0 read_resources bus 0 link: 0 done malloc Enter, size 2560, free_mem_ptr 00250378 malloc 00250378 PCI_DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:18.0 read_resources bus 0 link: 0 PCI: 00:00.0 register 1c(00000004), read-only ignoring it PCI: 00:02.0 read_resources bus 1 link: 0 PCI: 00:02.0 read_resources bus 1 link: 0 done PCI: 00:04.0 read_resources bus 2 link: 0 PCI: 00:04.0 read_resources bus 2 link: 0 done PCI: 00:0a.0 read_resources bus 3 link: 0 PCI: 00:0a.0 read_resources bus 3 link: 0 done PCI: 00:14.0 read_resources bus 1 link: 0 I2C: 01:50 missing read_resources I2C: 01:51 missing read_resources I2C: 01:52 missing read_resources I2C: 01:53 missing read_resources PCI: 00:14.0 read_resources bus 1 link: 0 done PCI: 00:14.3 read_resources bus 0 link: 0 PNP: 002e.1 missing read_resources PNP: 002e.5 missing read_resources PNP: 002e.6 missing read_resources PCI: 00:14.3 read_resources bus 0 link: 0 done PCI: 00:14.4 read_resources bus 4 link: 0 PCI: 00:14.4 read_resources bus 4 link: 0 done PCI: 00:18.0 read_resources bus 0 link: 0 done PCI: 00:18.0 read_resources bus 0 link: 1 PCI: 00:18.0 read_resources bus 0 link: 1 done PCI: 00:18.0 read_resources bus 0 link: 2 PCI: 00:18.0 read_resources bus 0 link: 2 done PCI: 00:18.0 read_resources bus 0 link: 3 PCI: 00:18.0 read_resources bus 0 link: 3 done PCI: 00:18.0 read_resources bus 0 link: 4 PCI: 00:18.0 read_resources bus 0 link: 4 done PCI: 00:18.0 read_resources bus 0 link: 5 PCI: 00:18.0 read_resources bus 0 link: 5 done PCI: 00:18.0 read_resources bus 0 link: 6 PCI: 00:18.0 read_resources bus 0 link: 6 done PCI: 00:18.0 read_resources bus 0 link: 7 PCI: 00:18.0 read_resources bus 0 link: 7 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 APIC: 01 APIC: 02 APIC: 03 PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:18.0 child on link 0 PCI: 00:00.0 PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 10d8 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 10b8 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 80200 index 10b0 PCI: 00:00.0 PCI: 00:02.0 child on link 0 PCI: 01:00.0 PCI: 00:02.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 10 PCI: 01:00.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 14 PCI: 01:00.0 resource base 0 size 2000000 align 25 gran 25 limit ffffffffffffffff flags 201 index 1c PCI: 01:00.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 24 PCI: 01:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30 PCI: 00:03.0 PCI: 00:04.0 PCI: 00:04.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:05.0 PCI: 00:06.0 PCI: 00:07.0 PCI: 00:08.0 PCI: 00:09.0 PCI: 00:0a.0 PCI: 00:0a.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:11.0 PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:11.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 24 PCI: 00:12.0 PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:12.1 PCI: 00:12.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:12.2 PCI: 00:12.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 PCI: 00:13.0 PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:13.1 PCI: 00:13.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:13.2 PCI: 00:13.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 PCI: 00:14.0 child on link 0 I2C: 01:50 PCI: 00:14.0 resource base fec00000 size 1000 align 8 gran 8 limit ffffffff flags 80000200 index 74 PCI: 00:14.0 resource base b00 size 10 align 8 gran 8 limit ffff flags 80000100 index 90 I2C: 01:50 I2C: 01:51 I2C: 01:52 I2C: 01:53 PCI: 00:14.1 PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:14.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:14.2 PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:14.3 child on link 0 PNP: 002e.0 PCI: 00:14.3 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 200 index a0 PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.0 resource base 6 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.0 resource base 2 size 0 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 002e.1 PNP: 002e.1 resource base 3f8 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.1 resource base 4 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.2 PNP: 002e.2 resource base 2f8 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.2 resource base 3 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.3 PNP: 002e.3 resource base 378 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.3 resource base 7 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.4 PNP: 002e.5 PNP: 002e.5 resource base 60 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.5 resource base 64 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 PNP: 002e.5 resource base 1 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.6 PNP: 002e.6 resource base c size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.7 PNP: 002e.8 PNP: 002e.8 resource base 300 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.8 resource base 9 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.9 PNP: 002e.9 resource base 220 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.a PCI: 00:14.4 PCI: 00:14.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24 PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:14.5 PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:18.0 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94 PCI: 00:18.4 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94 PCI: 00:18.4 PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:02.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 01:00.0 24 * [0x0 - 0x7f] io PCI: 00:02.0 compute_resources_io: base: 80 size: 1000 align: 12 gran: 12 limit: ffff done PCI: 00:04.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:04.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:0a.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:0a.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:02.0 1c * [0x0 - 0xfff] io PCI: 00:11.0 20 * [0x1000 - 0x100f] io PCI: 00:14.1 20 * [0x1010 - 0x101f] io PCI: 00:11.0 10 * [0x1020 - 0x1027] io PCI: 00:11.0 18 * [0x1028 - 0x102f] io PCI: 00:14.1 10 * [0x1030 - 0x1037] io PCI: 00:14.1 18 * [0x1038 - 0x103f] io PCI: 00:11.0 14 * [0x1040 - 0x1043] io PCI: 00:11.0 1c * [0x1044 - 0x1047] io PCI: 00:14.1 14 * [0x1048 - 0x104b] io PCI: 00:14.1 1c * [0x104c - 0x104f] io PCI: 00:18.0 compute_resources_io: base: 1050 size: 2000 align: 12 gran: 12 limit: ffff done PCI: 00:18.0 10d8 * [0x0 - 0x1fff] io PCI_DOMAIN: 0000 compute_resources_io: base: 2000 size: 2000 align: 12 gran: 0 limit: ffff done PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:02.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 01:00.0 14 * [0x0 - 0xfffffff] prefmem PCI: 00:02.0 compute_resources_prefmem: base: 10000000 size: 10000000 align: 28 gran: 20 limit: ffffffffffffffff done PCI: 00:04.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:04.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:0a.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:0a.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:02.0 24 * [0x0 - 0xfffffff] prefmem PCI: 00:18.0 compute_resources_prefmem: base: 10000000 size: 10000000 align: 28 gran: 20 limit: ffffffffff done PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:02.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:00.0 1c * [0x0 - 0x1ffffff] mem PCI: 01:00.0 10 * [0x2000000 - 0x2ffffff] mem PCI: 01:00.0 30 * [0x3000000 - 0x301ffff] mem PCI: 00:02.0 compute_resources_mem: base: 3020000 size: 3100000 align: 25 gran: 20 limit: ffffffff done PCI: 00:04.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:04.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:0a.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:0a.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:18.3 94 * [0x0 - 0x3ffffff] mem PCI: 00:02.0 20 * [0x4000000 - 0x70fffff] mem PCI: 00:14.2 10 * [0x7100000 - 0x7103fff] mem PCI: 00:12.0 10 * [0x7104000 - 0x7104fff] mem PCI: 00:12.1 10 * [0x7105000 - 0x7105fff] mem PCI: 00:13.0 10 * [0x7106000 - 0x7106fff] mem PCI: 00:13.1 10 * [0x7107000 - 0x7107fff] mem PCI: 00:14.5 10 * [0x7108000 - 0x7108fff] mem PCI: 00:11.0 24 * [0x7109000 - 0x71093ff] mem PCI: 00:12.2 10 * [0x7109400 - 0x71094ff] mem PCI: 00:13.2 10 * [0x7109500 - 0x71095ff] mem PCI: 00:14.3 a0 * [0x7109600 - 0x7109600] mem PCI: 00:18.0 compute_resources_mem: base: 7109601 size: 7200000 align: 26 gran: 20 limit: ffffffff done PCI: 00:18.0 10b8 * [0x0 - 0xfffffff] prefmem PCI: 00:18.0 10b0 * [0x10000000 - 0x171fffff] mem PCI: 00:18.3 94 * [0x18000000 - 0x1bffffff] mem PCI_DOMAIN: 0000 compute_resources_mem: base: 1c000000 size: 1c000000 align: 28 gran: 0 limit: ffffffff done avoid_fixed_resources: PCI_DOMAIN: 0000 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI_DOMAIN: 0000 constrain_resources: PCI: 00:18.0 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:02.0 constrain_resources: PCI: 01:00.0 constrain_resources: PCI: 00:04.0 constrain_resources: PCI: 00:0a.0 constrain_resources: PCI: 00:11.0 constrain_resources: PCI: 00:12.0 constrain_resources: PCI: 00:12.1 constrain_resources: PCI: 00:12.2 constrain_resources: PCI: 00:13.0 constrain_resources: PCI: 00:13.1 constrain_resources: PCI: 00:13.2 constrain_resources: PCI: 00:14.0 constrain_resources: I2C: 01:50 constrain_resources: I2C: 01:51 constrain_resources: I2C: 01:52 constrain_resources: I2C: 01:53 constrain_resources: PCI: 00:14.1 constrain_resources: PCI: 00:14.2 constrain_resources: PCI: 00:14.3 constrain_resources: PNP: 002e.1 skipping PNP: 002e.1@60 fixed resource, size=0! skipping PNP: 002e.1@70 fixed resource, size=0! constrain_resources: PNP: 002e.5 skipping PNP: 002e.5@60 fixed resource, size=0! skipping PNP: 002e.5@62 fixed resource, size=0! skipping PNP: 002e.5@70 fixed resource, size=0! constrain_resources: PNP: 002e.6 skipping PNP: 002e.6@70 fixed resource, size=0! constrain_resources: PCI: 00:14.4 constrain_resources: PCI: 00:14.5 constrain_resources: PCI: 00:18.0 constrain_resources: PCI: 00:18.1 constrain_resources: PCI: 00:18.2 constrain_resources: PCI: 00:18.3 constrain_resources: PCI: 00:18.4 constrain_resources: PCI: 00:18.1 constrain_resources: PCI: 00:18.2 constrain_resources: PCI: 00:18.3 constrain_resources: PCI: 00:18.4 avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff lim->base 00001000 lim->limit 0000ffff avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff lim->base 00000000 lim->limit dfffffff Setting resources... PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:2000 align:12 gran:0 limit:ffff Assigned: PCI: 00:18.0 10d8 * [0x1000 - 0x2fff] io PCI_DOMAIN: 0000 allocate_resources_io: next_base: 3000 size: 2000 align: 12 gran: 0 done PCI: 00:18.0 allocate_resources_io: base:1000 size:2000 align:12 gran:12 limit:ffff Assigned: PCI: 00:02.0 1c * [0x1000 - 0x1fff] io Assigned: PCI: 00:11.0 20 * [0x2000 - 0x200f] io Assigned: PCI: 00:14.1 20 * [0x2010 - 0x201f] io Assigned: PCI: 00:11.0 10 * [0x2020 - 0x2027] io Assigned: PCI: 00:11.0 18 * [0x2028 - 0x202f] io Assigned: PCI: 00:14.1 10 * [0x2030 - 0x2037] io Assigned: PCI: 00:14.1 18 * [0x2038 - 0x203f] io Assigned: PCI: 00:11.0 14 * [0x2040 - 0x2043] io Assigned: PCI: 00:11.0 1c * [0x2044 - 0x2047] io Assigned: PCI: 00:14.1 14 * [0x2048 - 0x204b] io Assigned: PCI: 00:14.1 1c * [0x204c - 0x204f] io PCI: 00:18.0 allocate_resources_io: next_base: 2050 size: 2000 align: 12 gran: 12 done PCI: 00:02.0 allocate_resources_io: base:1000 size:1000 align:12 gran:12 limit:ffff Assigned: PCI: 01:00.0 24 * [0x1000 - 0x107f] io PCI: 00:02.0 allocate_resources_io: next_base: 1080 size: 1000 align: 12 gran: 12 done PCI: 00:04.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:04.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:0a.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:0a.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:14.4 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:14.4 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI_DOMAIN: 0000 allocate_resources_mem: base:c0000000 size:1c000000 align:28 gran:0 limit:dfffffff Assigned: PCI: 00:18.0 10b8 * [0xc0000000 - 0xcfffffff] prefmem Assigned: PCI: 00:18.0 10b0 * [0xd0000000 - 0xd71fffff] mem Assigned: PCI: 00:18.3 94 * [0xd8000000 - 0xdbffffff] mem PCI_DOMAIN: 0000 allocate_resources_mem: next_base: dc000000 size: 1c000000 align: 28 gran: 0 done PCI: 00:18.0 allocate_resources_prefmem: base:c0000000 size:10000000 align:28 gran:20 limit:dfffffff Assigned: PCI: 00:02.0 24 * [0xc0000000 - 0xcfffffff] prefmem PCI: 00:18.0 allocate_resources_prefmem: next_base: d0000000 size: 10000000 align: 28 gran: 20 done PCI: 00:02.0 allocate_resources_prefmem: base:c0000000 size:10000000 align:28 gran:20 limit:dfffffff Assigned: PCI: 01:00.0 14 * [0xc0000000 - 0xcfffffff] prefmem PCI: 00:02.0 allocate_resources_prefmem: next_base: d0000000 size: 10000000 align: 28 gran: 20 done PCI: 00:04.0 allocate_resources_prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 00:04.0 allocate_resources_prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done PCI: 00:0a.0 allocate_resources_prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 00:0a.0 allocate_resources_prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done PCI: 00:14.4 allocate_resources_prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 00:14.4 allocate_resources_prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done PCI: 00:18.0 allocate_resources_mem: base:d0000000 size:7200000 align:26 gran:20 limit:dfffffff Assigned: PCI: 00:18.3 94 * [0xd0000000 - 0xd3ffffff] mem Assigned: PCI: 00:02.0 20 * [0xd4000000 - 0xd70fffff] mem Assigned: PCI: 00:14.2 10 * [0xd7100000 - 0xd7103fff] mem Assigned: PCI: 00:12.0 10 * [0xd7104000 - 0xd7104fff] mem Assigned: PCI: 00:12.1 10 * [0xd7105000 - 0xd7105fff] mem Assigned: PCI: 00:13.0 10 * [0xd7106000 - 0xd7106fff] mem Assigned: PCI: 00:13.1 10 * [0xd7107000 - 0xd7107fff] mem Assigned: PCI: 00:14.5 10 * [0xd7108000 - 0xd7108fff] mem Assigned: PCI: 00:11.0 24 * [0xd7109000 - 0xd71093ff] mem Assigned: PCI: 00:12.2 10 * [0xd7109400 - 0xd71094ff] mem Assigned: PCI: 00:13.2 10 * [0xd7109500 - 0xd71095ff] mem Assigned: PCI: 00:14.3 a0 * [0xd7109600 - 0xd7109600] mem PCI: 00:18.0 allocate_resources_mem: next_base: d7109601 size: 7200000 align: 26 gran: 20 done PCI: 00:02.0 allocate_resources_mem: base:d4000000 size:3100000 align:25 gran:20 limit:dfffffff Assigned: PCI: 01:00.0 1c * [0xd4000000 - 0xd5ffffff] mem Assigned: PCI: 01:00.0 10 * [0xd6000000 - 0xd6ffffff] mem Assigned: PCI: 01:00.0 30 * [0xd7000000 - 0xd701ffff] mem PCI: 00:02.0 allocate_resources_mem: next_base: d7020000 size: 3100000 align: 25 gran: 20 done PCI: 00:04.0 allocate_resources_mem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 00:04.0 allocate_resources_mem: next_base: dfffffff size: 0 align: 20 gran: 20 done PCI: 00:0a.0 allocate_resources_mem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 00:0a.0 allocate_resources_mem: next_base: dfffffff size: 0 align: 20 gran: 20 done PCI: 00:14.4 allocate_resources_mem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 00:14.4 allocate_resources_mem: next_base: dfffffff size: 0 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 split: 64K table at =afff0000 0: mmio_basek=00300000, basek=00400000, limitk=00900000 Adding UMA memory area PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 VGA: PCI: 00:18.0 (aka node 0) link 0 has VGA device PCI: 00:18.0 10d8 <- [0x0000001000 - 0x0000002fff] size 0x00002000 gran 0x0c io PCI: 00:18.0 10b8 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x14 prefmem PCI: 00:18.0 10b0 <- [0x00d0000000 - 0x00d71fffff] size 0x07200000 gran 0x14 mem PCI: 00:18.0 assign_resources, bus 0 link: 0 PCI: 00:02.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io PCI: 00:02.0 24 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x14 bus 01 prefmem PCI: 00:02.0 20 <- [0x00d4000000 - 0x00d70fffff] size 0x03100000 gran 0x14 bus 01 mem PCI: 00:02.0 assign_resources, bus 1 link: 0 PCI: 01:00.0 10 <- [0x00d6000000 - 0x00d6ffffff] size 0x01000000 gran 0x18 mem PCI: 01:00.0 14 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x1c prefmem64 PCI: 01:00.0 1c <- [0x00d4000000 - 0x00d5ffffff] size 0x02000000 gran 0x19 mem64 PCI: 01:00.0 24 <- [0x0000001000 - 0x000000107f] size 0x00000080 gran 0x07 io PCI: 01:00.0 30 <- [0x00d7000000 - 0x00d701ffff] size 0x00020000 gran 0x11 romem PCI: 00:02.0 assign_resources, bus 1 link: 0 PCI: 00:04.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io PCI: 00:04.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 02 prefmem PCI: 00:04.0 20 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 02 mem PCI: 00:0a.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io PCI: 00:0a.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 03 prefmem PCI: 00:0a.0 20 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 03 mem PCI: 00:11.0 10 <- [0x0000002020 - 0x0000002027] size 0x00000008 gran 0x03 io PCI: 00:11.0 14 <- [0x0000002040 - 0x0000002043] size 0x00000004 gran 0x02 io PCI: 00:11.0 18 <- [0x0000002028 - 0x000000202f] size 0x00000008 gran 0x03 io PCI: 00:11.0 1c <- [0x0000002044 - 0x0000002047] size 0x00000004 gran 0x02 io PCI: 00:11.0 20 <- [0x0000002000 - 0x000000200f] size 0x00000010 gran 0x04 io PCI: 00:11.0 24 <- [0x00d7109000 - 0x00d71093ff] size 0x00000400 gran 0x0a mem PCI: 00:12.0 10 <- [0x00d7104000 - 0x00d7104fff] size 0x00001000 gran 0x0c mem PCI: 00:12.1 10 <- [0x00d7105000 - 0x00d7105fff] size 0x00001000 gran 0x0c mem PCI: 00:12.2 10 <- [0x00d7109400 - 0x00d71094ff] size 0x00000100 gran 0x08 mem PCI: 00:13.0 10 <- [0x00d7106000 - 0x00d7106fff] size 0x00001000 gran 0x0c mem PCI: 00:13.1 10 <- [0x00d7107000 - 0x00d7107fff] size 0x00001000 gran 0x0c mem PCI: 00:13.2 10 <- [0x00d7109500 - 0x00d71095ff] size 0x00000100 gran 0x08 mem ERROR: PCI: 00:14.0 74 mem size: 0x0000001000 not assigned ERROR: PCI: 00:14.0 90 io size: 0x0000000010 not assigned PCI: 00:14.0 assign_resources, bus 1 link: 0 PCI: 00:14.0 assign_resources, bus 1 link: 0 PCI: 00:14.1 10 <- [0x0000002030 - 0x0000002037] size 0x00000008 gran 0x03 io PCI: 00:14.1 14 <- [0x0000002048 - 0x000000204b] size 0x00000004 gran 0x02 io PCI: 00:14.1 18 <- [0x0000002038 - 0x000000203f] size 0x00000008 gran 0x03 io PCI: 00:14.1 1c <- [0x000000204c - 0x000000204f] size 0x00000004 gran 0x02 io PCI: 00:14.1 20 <- [0x0000002010 - 0x000000201f] size 0x00000010 gran 0x04 io PCI: 00:14.2 10 <- [0x00d7100000 - 0x00d7103fff] size 0x00004000 gran 0x0e mem64 PCI: 00:14.3 a0 <- [0x00d7109600 - 0x00d7109600] size 0x00000001 gran 0x00 mem PCI: 00:14.3 assign_resources, bus 0 link: 0 PNP: 002e.1 missing set_resources PNP: 002e.5 missing set_resources PNP: 002e.6 missing set_resources PCI: 00:14.3 assign_resources, bus 0 link: 0 PCI: 00:14.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io PCI: 00:14.4 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 04 prefmem PCI: 00:14.4 20 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 04 mem PCI: 00:14.5 10 <- [0x00d7108000 - 0x00d7108fff] size 0x00001000 gran 0x0c mem PCI: 00:18.3 94 <- [0x00d0000000 - 0x00d3ffffff] size 0x04000000 gran 0x1a mem PCI: 00:18.3 94 <- [0x00d0000000 - 0x00d3ffffff] size 0x04000000 gran 0x1a mem PCI: 00:18.0 assign_resources, bus 0 link: 0 PCI: 00:18.3 94 <- [0x00d8000000 - 0x00dbffffff] size 0x04000000 gran 0x1a mem PCI: 00:18.3 94 <- [0x00d8000000 - 0x00dbffffff] size 0x04000000 gran 0x1a mem PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 APIC: 01 APIC: 02 APIC: 03 PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0 PCI_DOMAIN: 0000 resource base 1000 size 2000 align 12 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base c0000000 size 1c000000 align 28 gran 0 limit dfffffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10 PCI_DOMAIN: 0000 resource base c0000 size bff40000 align 0 gran 0 limit 0 flags e0004200 index 20 PCI_DOMAIN: 0000 resource base 100000000 size 130000000 align 0 gran 0 limit 0 flags e0004200 index 30 PCI_DOMAIN: 0000 resource base b0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 7 PCI: 00:18.0 child on link 0 PCI: 00:00.0 PCI: 00:18.0 resource base 1000 size 2000 align 12 gran 12 limit ffff flags 60080100 index 10d8 PCI: 00:18.0 resource base c0000000 size 10000000 align 28 gran 20 limit dfffffff flags 60081200 index 10b8 PCI: 00:18.0 resource base d0000000 size 7200000 align 26 gran 20 limit dfffffff flags 60080200 index 10b0 PCI: 00:00.0 PCI: 00:02.0 child on link 0 PCI: 01:00.0 PCI: 00:02.0 resource base 1000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:02.0 resource base c0000000 size 10000000 align 28 gran 20 limit dfffffff flags 60081202 index 24 PCI: 00:02.0 resource base d4000000 size 3100000 align 25 gran 20 limit dfffffff flags 60080202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base d6000000 size 1000000 align 24 gran 24 limit dfffffff flags 60000200 index 10 PCI: 01:00.0 resource base c0000000 size 10000000 align 28 gran 28 limit dfffffff flags 60001201 index 14 PCI: 01:00.0 resource base d4000000 size 2000000 align 25 gran 25 limit dfffffff flags 60000201 index 1c PCI: 01:00.0 resource base 1000 size 80 align 7 gran 7 limit ffff flags 60000100 index 24 PCI: 01:00.0 resource base d7000000 size 20000 align 17 gran 17 limit dfffffff flags 60002200 index 30 PCI: 00:03.0 PCI: 00:04.0 PCI: 00:04.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:04.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24 PCI: 00:04.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60080202 index 20 PCI: 00:05.0 PCI: 00:06.0 PCI: 00:07.0 PCI: 00:08.0 PCI: 00:09.0 PCI: 00:0a.0 PCI: 00:0a.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:0a.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24 PCI: 00:0a.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60080202 index 20 PCI: 00:11.0 PCI: 00:11.0 resource base 2020 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 PCI: 00:11.0 resource base 2040 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 PCI: 00:11.0 resource base 2028 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 PCI: 00:11.0 resource base 2044 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c PCI: 00:11.0 resource base 2000 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:11.0 resource base d7109000 size 400 align 10 gran 10 limit dfffffff flags 60000200 index 24 PCI: 00:12.0 PCI: 00:12.0 resource base d7104000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10 PCI: 00:12.1 PCI: 00:12.1 resource base d7105000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10 PCI: 00:12.2 PCI: 00:12.2 resource base d7109400 size 100 align 8 gran 8 limit dfffffff flags 60000200 index 10 PCI: 00:13.0 PCI: 00:13.0 resource base d7106000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10 PCI: 00:13.1 PCI: 00:13.1 resource base d7107000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10 PCI: 00:13.2 PCI: 00:13.2 resource base d7109500 size 100 align 8 gran 8 limit dfffffff flags 60000200 index 10 PCI: 00:14.0 child on link 0 I2C: 01:50 PCI: 00:14.0 resource base fec00000 size 1000 align 8 gran 8 limit ffffffff flags 80000200 index 74 PCI: 00:14.0 resource base b00 size 10 align 8 gran 8 limit ffff flags 80000100 index 90 I2C: 01:50 I2C: 01:51 I2C: 01:52 I2C: 01:53 PCI: 00:14.1 PCI: 00:14.1 resource base 2030 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 PCI: 00:14.1 resource base 2048 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 PCI: 00:14.1 resource base 2038 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 PCI: 00:14.1 resource base 204c size 4 align 2 gran 2 limit ffff flags 60000100 index 1c PCI: 00:14.1 resource base 2010 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:14.2 PCI: 00:14.2 resource base d7100000 size 4000 align 14 gran 14 limit dfffffff flags 60000201 index 10 PCI: 00:14.3 child on link 0 PNP: 002e.0 PCI: 00:14.3 resource base d7109600 size 1 align 0 gran 0 limit dfffffff flags 60000200 index a0 PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.0 resource base 6 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.0 resource base 2 size 0 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 002e.1 PNP: 002e.1 resource base 3f8 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.1 resource base 4 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.2 PNP: 002e.2 resource base 2f8 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.2 resource base 3 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.3 PNP: 002e.3 resource base 378 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.3 resource base 7 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.4 PNP: 002e.5 PNP: 002e.5 resource base 60 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.5 resource base 64 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 PNP: 002e.5 resource base 1 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.6 PNP: 002e.6 resource base c size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.7 PNP: 002e.8 PNP: 002e.8 resource base 300 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.8 resource base 9 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.9 PNP: 002e.9 resource base 220 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.a PCI: 00:14.4 PCI: 00:14.4 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:14.4 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24 PCI: 00:14.4 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60080202 index 20 PCI: 00:14.5 PCI: 00:14.5 resource base d7108000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10 PCI: 00:18.0 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base d0000000 size 4000000 align 26 gran 26 limit dfffffff flags 60000200 index 94 PCI: 00:18.4 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base d8000000 size 4000000 align 26 gran 26 limit dfffffff flags 60000200 index 94 PCI: 00:18.4 Done allocating resources. POST: 0x88 Enabling resources... PCI: 00:18.0 cmd <- 00 PCI: 00:18.1 subsystem <- 1022/3060 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 1022/3060 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 PCI: 00:18.4 subsystem <- 1022/3060 PCI: 00:18.4 cmd <- 00 PCI: 00:00.0 subsystem <- 1022/3060 PCI: 00:00.0 cmd <- 06 PCI: 00:02.0 bridge ctrl <- 000b PCI: 00:02.0 cmd <- 07 PCI: 00:04.0 bridge ctrl <- 0003 PCI: 00:04.0 cmd <- 00 PCI: 00:0a.0 bridge ctrl <- 0003 PCI: 00:0a.0 cmd <- 00 PCI: 00:11.0 cmd <- 03 PCI: 00:12.0 subsystem <- 1022/3060 PCI: 00:12.0 cmd <- 02 PCI: 00:12.1 subsystem <- 1022/3060 PCI: 00:12.1 cmd <- 02 PCI: 00:12.2 subsystem <- 1022/3060 PCI: 00:12.2 cmd <- 02 PCI: 00:13.0 subsystem <- 1022/3060 PCI: 00:13.0 cmd <- 02 PCI: 00:13.1 subsystem <- 1022/3060 PCI: 00:13.1 cmd <- 02 PCI: 00:13.2 subsystem <- 1022/3060 PCI: 00:13.2 cmd <- 02 PCI: 00:14.0 subsystem <- 1022/3060 PCI: 00:14.0 cmd <- 403 PCI: 00:14.1 subsystem <- 1022/3060 PCI: 00:14.1 cmd <- 01 PCI: 00:14.2 subsystem <- 1022/3060 PCI: 00:14.2 cmd <- 02 PCI: 00:14.3 subsystem <- 1022/3060 PCI: 00:14.3 cmd <- 0f sb700 lpc decode:PNP: 002e.1, base=0x000003f8, end=0x000003f7 sb700 lpc decode:PNP: 002e.5, base=0x00000060, end=0x0000005f sb700 lpc decode:PNP: 002e.5, base=0x00000064, end=0x00000063 PCI: 00:14.4 bridge ctrl <- 0003 PCI: 00:14.4 cmd <- 01 PCI: 00:14.5 subsystem <- 1022/3060 PCI: 00:14.5 cmd <- 02 PCI: 00:18.0 cmd <- 00 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 PCI: 00:18.4 cmd <- 00 PCI: 01:00.0 cmd <- 03 done. Initializing devices... Root Device init APIC_CLUSTER: 0 init start_eip=0x00000000, offset=0x00210000, code_size=0x0000005b Initializing CPU #0 CPU: vendor AMD device 100f43 CPU: family 10, model 04, stepping 03 nodeid = 00, coreid = 00 POST: 0x60 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole. Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB Setting variable MTRR 1, base: 8704MB, range: 256MB, type WB Setting variable MTRR 1, base: 3072MB, range: 1024MB, type UC ADDRESS_MASK_HIGH=0xffff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x00 done. POST: 0x9b CPU model: AMD Phenom(tm) II X4 910e Processor siblings = 03, CPU #0 initialized Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 1. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. Initializing CPU #1 CPU: vendor AMD device 100f43 CPU: family 10, model 04, stepping 03 nodeid = 00, coreid = 01 POST: 0x60 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole. Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB Setting variable MTRR 1, base: 8704MB, range: 256MB, type WB Setting variable MTRR 1, base: 3072MB, range: 1024MB, type UC ADDRESS_MASK_HIGH=0xffff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x01 done. POST: 0x9b CPU model: AMD Phenom(tm) II X4 910e Processor siblings = 03, CPU #1 initialized Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 2. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. Initializing CPU #2 CPU: vendor AMD device 100f43 CPU: family 10, model 04, stepping 03 nodeid = 00, coreid = 02 POST: 0x60 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole. Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB Setting variable MTRR 1, base: 8704MB, range: 256MB, type WB Setting variable MTRR 1, base: 3072MB, range: 1024MB, type UC ADDRESS_MASK_HIGH=0xffff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x02 done. POST: 0x9b CPU model: AMD Phenom(tm) II X4 910e Processor siblings = 03, CPU #2 initialized Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 3. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. Initializing CPU #3 Waiting for 1 CPUS to stop CPU: vendor AMD device 100f43 CPU: family 10, model 04, stepping 03 nodeid = 00, coreid = 03 POST: 0x60 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole. Setting variable MTRR 0, base: 0MB, range: 8192MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 1, base: 8192MB, range: 512MB, type WB Setting variable MTRR 1, base: 8704MB, range: 256MB, type WB Setting variable MTRR 1, base: 3072MB, range: 1024MB, type UC ADDRESS_MASK_HIGH=0xffff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x03 done. POST: 0x9b CPU model: AMD Phenom(tm) II X4 910e Processor siblings = 03, CPU #3 initialized All AP CPUs stopped PCI: 00:18.0 init PCI: 00:18.1 init PCI: 00:18.2 init PCI: 00:18.3 init NB: Function 3 Misc Control.. done. PCI: 00:18.4 init PCI: 00:00.0 init PCI: 00:11.0 init sata_bar0=2020 sata_bar1=2040 sata_bar2=2028 sata_bar3=2044 sata_bar4=2000 sata_bar5=d7109000 SATA port 0 status = 13 drive detection done after 0 ms Primary Master device is ready after 1 tries SATA port 1 status = 0 No Primary Slave SATA drive on Slot1 SATA port 2 status = 23 0x6=ff, 0x7=7f drive no longer selected after 0 ms, retrying init 0x6=ff, 0x7=7f drive no longer selected after 0 ms, retrying init 0x6=ff, 0x7=7f drive no longer selected after 0 ms, retrying init 0x6=ff, 0x7=7f drive no longer selected after 0 ms, retrying init 0x6=ff, 0x7=7f drive no longer selected after 0 ms, retrying init 0x6=ff, 0x7=7f drive no longer selected after 0 ms, retrying init 0x6=ff, 0x7=7f drive no longer selected after 0 ms, retrying init 0x6=ff, 0x7=7f drive no longer selected after 0 ms, retrying init 0x6=ff, 0x7=7f drive no longer selected after 0 ms, retrying init 0x6=ff, 0x7=7f drive no longer selected after 0 ms, retrying init Secondary Master device is not ready after 10 tries SATA port 3 status = 0 No Secondary Slave SATA drive on Slot3 PCI: 00:12.0 init PCI: 00:12.1 init PCI: 00:12.2 init usb2_bar0=0xd7109400 PCI: 00:13.0 init PCI: 00:13.1 init PCI: 00:13.2 init usb2_bar0=0xd7109500 PCI: 00:14.0 init sm_init(). IOAPIC: Clearing IOAPIC at 0xfec00000 IOAPIC: 23 interrupts IOAPIC: reg 0x00000000 value 0x00000000 0x00010000 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 set power on after power fail ++++++++++no set NMI+++++ RTC Init sm_init() end PCI: 00:14.1 init PCI: 00:14.2 init base = 0xd7100000 codec_mask = 01 0(th) codec viddid: 11060397 PCI: 00:14.3 init PCI: 00:14.4 init PCI: 00:14.5 init PCI: 00:18.0 init PCI: 00:18.1 init PCI: 00:18.2 init PCI: 00:18.3 init NB: Function 3 Misc Control.. done. PCI: 00:18.4 init PCI: 01:00.0 init Devices initialized Show all devs...After init. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 0 PCI: 00:04.0: enabled 1 PCI: 00:05.0: enabled 0 PCI: 00:06.0: enabled 0 PCI: 00:07.0: enabled 0 PCI: 00:08.0: enabled 0 PCI: 00:09.0: enabled 0 PCI: 00:0a.0: enabled 1 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:12.1: enabled 1 PCI: 00:12.2: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.1: enabled 1 PCI: 00:13.2: enabled 1 PCI: 00:14.0: enabled 1 I2C: 01:50: enabled 1 I2C: 01:51: enabled 1 I2C: 01:52: enabled 1 I2C: 01:53: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 0 PNP: 002e.3: enabled 0 PNP: 002e.4: enabled 0 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 1 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PCI: 00:14.4: enabled 1 PCI: 00:14.5: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 APIC: 01: enabled 1 APIC: 02: enabled 1 APIC: 03: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 01:00.0: enabled 1 POST: 0x89 Initializing CBMEM area to 0xafff0000 (65536 bytes) Adding CBMEM entry as no. 1 Moving GDT to afff0200...ok High Tables Base is afff0000. POST: 0x9a Copying Interrupt Routing Table to 0x000f0000... done. Verifying copy of Interrupt Routing Table at 0x000f0000... done Checking Interrupt Routing Table consistency... check_pirq_routing_table(): Interrupt Routing Table located at 000f0000. done. Adding CBMEM entry as no. 2 Copying Interrupt Routing Table to 0xafff0400... done. Verifying copy of Interrupt Routing Table at 0xafff0400... done Checking Interrupt Routing Table consistency... check_pirq_routing_table(): Interrupt Routing Table located at afff0400. done. PIRQ table: 336 bytes. POST: 0x9b Wrote the mp table end at: 000f0410 - 000f0544 Adding CBMEM entry as no. 3 Wrote the mp table end at: afff1410 - afff1544 MP table: 324 bytes. POST: 0x9c Adding CBMEM entry as no. 4 ACPI: Writing ACPI tables at afff2400... ACPI: * HPET at afff24c8 ACPI: added table 1/32, length now 40 ACPI: * MADT at afff2500 ACPI: added table 2/32, length now 44 ACPI: * SRAT at afff2570 SRAT: lapic cpu_index=00, node_id=00, apic_id=00 SRAT: lapic cpu_index=01, node_id=00, apic_id=01 SRAT: lapic cpu_index=02, node_id=00, apic_id=02 SRAT: lapic cpu_index=03, node_id=00, apic_id=03 set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280 set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00 set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0030 startk=00400000, sizek=004c0000 ACPI: added table 3/32, length now 48 ACPI: * SLIT at afff2658 ACPI: added table 4/32, length now 52 ACPI: * SSDT at afff2690 ACPI: added table 5/32, length now 56 ACPI: * SSDT for PState at afff2cc5 ACPI: * DSDT at afff2cc8 ACPI: * DSDT @ afff2cc8 Length 298b ACPI: * FACS at afff5658 ACPI: * FADT at afff5698 pm_base: 0x0800 ACPI: added table 6/32, length now 60 ACPI: done. ACPI tables: 13196 bytes. POST: 0x9d Adding CBMEM entry as no. 5 Writing high table forward entry at 0x00000500 Wrote coreboot table at: 00000500 - 00000518 checksum 6fde New low_table_end: 0x00000518 Now going to write high coreboot table at 0xafffe000 rom_table_end = 0xafffe000 Adjust low_table_end from 0x00000518 to 0x00001000 Adjust rom_table_end from 0xafffe000 to 0xb0000000 Adding high table area uma_memory_start=0xb0000000, uma_memory_size=0x10000000 coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-00000000affeffff: RAM 3. 00000000afff0000-00000000afffffff: CONFIGURATION TABLES 4. 00000000b0000000-00000000bfffffff: RESERVED 5. 00000000e0000000-00000000efffffff: RESERVED 6. 0000000100000000-000000022fffffff: RAM Wrote coreboot table at: afffe000 - afffe1f0 checksum e143 coreboot table: 496 bytes. POST: 0x9e POST: 0x9d Multiboot Information structure has been written. 0. FREE SPACE b0000000 00000000 1. GDT afff0200 00000200 2. IRQ TABLE afff0400 00001000 3. SMP TABLE afff1400 00001000 4. ACPI afff2400 0000bc00 5. COREBOOT afffe000 00002000 Check CBFS header at fffffb7e magic is 4f524243 Found CBFS header at fffffb7e Check cmos_layout.bin CBFS: follow chain: fff00000 + 28 + 6ef + align -> fff00740 Check fallback/romstage CBFS: follow chain: fff00740 + 38 + 177d8 + align -> fff17f80 Check fallback/coreboot_ram CBFS: follow chain: fff17f80 + 38 + d276 + align -> fff25240 Check fallback/payload Got a payload Loading segment from rom address 0xfff25278 parameter section (skipped) Loading segment from rom address 0xfff25294 data (compression=1) malloc Enter, size 36, free_mem_ptr 00250d78 malloc 00250d78 New segment dstaddr 0x100000 memsize 0x171d50 srcaddr 0xfff25318 filesize 0xe222 (cleaned up) New segment addr 0x100000 size 0x171d50 offset 0xfff25318 filesize 0xe222 Loading segment from rom address 0xfff252b0 data (compression=1) malloc Enter, size 36, free_mem_ptr 00250d9c malloc 00250d9c New segment dstaddr 0x271d50 memsize 0x48 srcaddr 0xfff3353a filesize 0x2d (cleaned up) New segment addr 0x271d50 size 0x48 offset 0xfff3353a filesize 0x2d Loading segment from rom address 0xfff252cc Entry Point 0x00100000 Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000171d50 filesz: 0x000000000000e222 lb: [0x0000000000200000, 0x0000000000310000) segment: [0x0000000000100000, 0x000000000010e222, 0x0000000000271d50) bounce: [0x00000000afcd0000, 0x00000000afcde222, 0x00000000afe41d50) Post relocation: addr: 0x00000000afcd0000 memsz: 0x0000000000171d50 filesz: 0x000000000000e222 using LZMA [ 0xafcd0000, afcf1e60, 0xafe41d50) <- fff25318 Clearing Segment: addr: 0x00000000afcf1e60 memsz: 0x000000000014fef0 dest afcd0000, end afe41d50, bouncebuffer afdd0000 move prefix around: from afcd0000, to 00100000, amount: 100000 Loading Segment: addr: 0x0000000000271d50 memsz: 0x0000000000000048 filesz: 0x000000000000002d lb: [0x0000000000200000, 0x0000000000310000) segment: [0x0000000000271d50, 0x0000000000271d7d, 0x0000000000271d98) bounce: [0x00000000afe41d50, 0x00000000afe41d7d, 0x00000000afe41d98) Post relocation: addr: 0x00000000afe41d50 memsz: 0x0000000000000048 filesz: 0x000000000000002d using LZMA [ 0xafe41d50, afe41d98, 0xafe41d98) <- fff3353a dest afe41d50, end afe41d98, bouncebuffer afdd0000 Loaded segments Jumping to boot code at 100000 POST: 0xfe entry = 0x00100000 lb_start = 0x00200000 lb_size = 0x00110000 adjust = 0xafce0000 buffer = 0xafdd0000 elf_boot_notes = 0x0021848c adjusted_boot_notes = 0xafef848c FILO version 0.6.0 (xdrudis@massagran) Sun Mar 20 10:33:25 CET 2011 00:12.2 4396:1002.2 EHCI controller root hub has 6 ports 00:12.1 4398:1002.1 OHCI controller OHCI Version 1.0 00:12.0 4397:1002.0 OHCI controller OHCI Version 1.0 00:13.2 4396:1002.2 EHCI controller root hub has 6 ports 00:13.1 4398:1002.1 OHCI controller OHCI Version 1.0 00:13.0 4397:1002.0 OHCI controller OHCI Version 1.0 00:14.5 4399:1002.5 OHCI controller OHCI Version 1.0 ERROR: No such CMOS option (boot_devices) port 2 hosts a USB2 device highspeed device device 0x152d:0x2338 is USB 2.0 (MSC) it uses SCSI transparent command set it uses Bulk-Only Transport protocol using endpoint 81 as in, 2 as out has 1 luns Waiting for device to become ready... ok. spin up. OK. Reading capacity of mass storage device. has 1953525168 blocks sized 512b menu: hda3:/boot/filo/menu.lst ERROR: No such CMOS option (boot_default) hda: LBA48 1000GB: ST31000528AS Partition 3 does not exist.Partition 3 does not exist.Could not open menu.lst file 'hda3:/boot/filo/menu.lst'. Entering command line. FILO 0.6.0 [ Minimal BASH-like line editing is supported. For the first word, TAB lists possible command completions.] FILO 0.6.0 [ Minimal BASH-like line editing is supported. For the first word, TAB lists possible command completions.] filo> root (hd0,0) FILO 0.6.0 [ Minimal BASH-like line editing is supported. For the first word, TAB lists possible command completions.] filo> root (hd0,0) filo> kernel /boot/vmlinuz-2.6.34-libre ro root=/dev/sda1 console=tty0 consol root (hd0,0) boot FILO 0.6.0 [ Minimal BASH-like line editing is supported. For the first word, TAB lists possible command completions.] filo> root (hd0,0) boot Booting 'hda1:/boot/vmlinuz-2.6.34-libre ro root=/dev/sda1 console=tty0 console =ttyS0,115200 acpi=off' Found Linux version 2.6.34-libre (xdrudis@massagran) #1 SMP PREEMPT Sun May 30 23:31:45 CEST 2010 bzImage.Loading kernel... okJumping to entry point...[ 0.000000] Initializing cgroup subsys cpuset [ 0.000000] Initializing cgroup subsys cpu [ 0.000000] Linux version 2.6.34-libre (xdrudis@massagran) (gcc version 4.3.2 (Debian 4.3.2-1.1) ) #1 SMP PREEMPT Sun May 30 23:31:45 CEST 2010 [ 0.000000] Command line: ro root=/dev/sda1 console=tty0 console=ttyS0,115200 acpi=off [ 0.000000] BIOS-provided physical RAM map: [ 0.000000] BIOS-e820: 0000000000000000 - 0000000000001000 type 16 [ 0.000000] BIOS-e820: 0000000000001000 - 00000000000a0000 (usable) [ 0.000000] BIOS-e820: 00000000000c0000 - 00000000afff0000 (usable) [ 0.000000] BIOS-e820: 00000000afff0000 - 00000000b0000000 type 16 [ 0.000000] BIOS-e820: 00000000b0000000 - 00000000c0000000 (reserved) [ 0.000000] BIOS-e820: 00000000e0000000 - 00000000f0000000 (reserved) [ 0.000000] BIOS-e820: 0000000100000000 - 0000000230000000 (usable) [ 0.000000] NX (Execute Disable) protection: active [ 0.000000] DMI not present or invalid. [ 0.000000] No AGP bridge found [ 0.000000] last_pfn = 0x230000 max_arch_pfn = 0x400000000 [ 0.000000] x86 PAT enabled: cpu 0, old 0x7040600070406, new 0x7010600070106 [ 0.000000] total RAM covered: 3072M [ 0.000000] Found optimal setting for mtrr clean up [ 0.000000] gran_size: 64K chunk_size: 64K num_reg: 2 lose cover RAM: 0G [ 0.000000] last_pfn = 0xafff0 max_arch_pfn = 0x400000000 [ 0.000000] found SMP MP-table at [ffff8800000f0400] f0400 [ 0.000000] Using GB pages for direct mapping [ 0.000000] init_memory_mapping: 0000000000000000-00000000afff0000 [ 0.000000] init_memory_mapping: 0000000100000000-0000000230000000 [ 0.000000] Zone PFN ranges: [ 0.000000] DMA 0x00000001 -> 0x00001000 [ 0.000000] DMA32 0x00001000 -> 0x00100000 [ 0.000000] Normal 0x00100000 -> 0x00230000 [ 0.000000] Movable zone start PFN for each node [ 0.000000] early_node_map[3] active PFN ranges [ 0.000000] 0: 0x00000001 -> 0x000000a0 [ 0.000000] 0: 0x00000100 -> 0x000afff0 [ 0.000000] 0: 0x00100000 -> 0x00230000 [ 0.000000] Intel MultiProcessor Specification v1.4 [ 0.000000] MPTABLE: OEM ID: ASUS [ 0.000000] MPTABLE: Product ID: M4A77TD-PRO [ 0.000000] MPTABLE: APIC at: 0xFEE00000 [ 0.000000] Processor #0 (Bootup-CPU) [ 0.000000] Processor #1 [ 0.000000] Processor #2 [ 0.000000] Processor #3 [ 0.000000] Processors: 4 [ 0.000000] SMP: Allowing 4 CPUs, 0 hotplug CPUs [ 0.000000] PM: Registered nosave memory: 00000000000a0000 - 0000000000100000 [ 0.000000] PM: Registered nosave memory: 00000000afff0000 - 00000000b0000000 [ 0.000000] PM: Registered nosave memory: 00000000b0000000 - 00000000c0000000 [ 0.000000] PM: Registered nosave memory: 00000000c0000000 - 00000000e0000000 [ 0.000000] PM: Registered nosave memory: 00000000e0000000 - 00000000f0000000 [ 0.000000] PM: Registered nosave memory: 00000000f0000000 - 0000000100000000 [ 0.000000] Allocating PCI resources starting at c0000000 (gap: c0000000:20000000) [ 0.000000] setup_percpu: NR_CPUS:4096 nr_cpumask_bits:4 nr_cpu_ids:4 nr_node_ids:1 [ 0.000000] PERCPU: Embedded 28 pages/cpu @ffff880006000000 s82472 r8192 d24024 u524288 [ 0.000000] pcpu-alloc: s82472 r8192 d24024 u524288 alloc=1*2097152 [ 0.000000] pcpu-alloc: [0] 0 1 2 3 [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 1934607 [ 0.000000] Kernel command line: ro root=/dev/sda1 console=tty0 console=ttyS0,115200 acpi=off [ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes) [ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes) [ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes) [ 0.000000] Checking aperture... [ 0.000000] No AGP bridge found [ 0.000000] Node 0: aperture @ d8000000 size 64 MB [ 0.000000] Subtract (53 early reservations) [ 0.000000] #1 [0001000000 - 0005be0d64] TEXT DATA BSS [ 0.000000] #2 [000009f000 - 00000f0400] BIOS reserved [ 0.000000] #3 [00000f0400 - 00000f0410] MP-table mpf [ 0.000000] #4 [00000f0544 - 0000100000] BIOS reserved [ 0.000000] #5 [00000f0410 - 00000f0544] MP-table mpc [ 0.000000] #6 [0000001000 - 0000003000] TRAMPOLINE [ 0.000000] #7 [0000003000 - 0000007000] ACPI WAKEUP [ 0.000000] #8 [0000008000 - 000000a000] PGTABLE [ 0.000000] #9 [000000a000 - 000000b000] PGTABLE [ 0.000000] #10 [0005be0d80 - 0005be1d80] BOOTMEM [ 0.000000] #11 [0005fe1d80 - 0005fe2320] BOOTMEM [ 0.000000] #12 [00063e3000 - 00063e4000] BOOTMEM [ 0.000000] #13 [00063e4000 - 00063e5000] BOOTMEM [ 0.000000] #14 [0006400000 - 000d000000] MEMMAP 0 [ 0.000000] #15 [0005be1d80 - 0005be1f00] BOOTMEM [ 0.000000] #16 [0005be1f00 - 0005bf9f00] BOOTMEM [ 0.000000] #17 [0005bf9f00 - 0005c11f00] BOOTMEM [ 0.000000] #18 [0005c12000 - 0005c13000] BOOTMEM [ 0.000000] #19 [0005c13000 - 0005c13188] BOOTMEM [ 0.000000] #20 [0005c11f00 - 0005c11f68] BOOTMEM [ 0.000000] #21 [0005c11f80 - 0005c11fe8] BOOTMEM [ 0.000000] #22 [0005c131c0 - 0005c13228] BOOTMEM [ 0.000000] #23 [0005c13240 - 0005c132a8] BOOTMEM [ 0.000000] #24 [0005c132c0 - 0005c13328] BOOTMEM [ 0.000000] #25 [0005c13340 - 0005c133a8] BOOTMEM [ 0.000000] #26 [0005c133c0 - 0005c13428] BOOTMEM [ 0.000000] #27 [0005c13440 - 0005c13460] BOOTMEM [ 0.000000] #28 [0005c13480 - 0005c134a0] BOOTMEM [ 0.000000] #29 [0005c134c0 - 0005c134fd] BOOTMEM [ 0.000000] #30 [0005c13500 - 0005c1353d] BOOTMEM [ 0.000000] #31 [0006000000 - 000601c000] BOOTMEM [ 0.000000] #32 [0006080000 - 000609c000] BOOTMEM [ 0.000000] #33 [0006100000 - 000611c000] BOOTMEM [ 0.000000] #34 [0006180000 - 000619c000] BOOTMEM [ 0.000000] #35 [0005c15540 - 0005c15548] BOOTMEM [ 0.000000] #36 [0005c15580 - 0005c15588] BOOTMEM [ 0.000000] #37 [0005c155c0 - 0005c155d0] BOOTMEM [ 0.000000] #38 [0005c15600 - 0005c15620] BOOTMEM [ 0.000000] #39 [0005c15640 - 0005c15770] BOOTMEM [ 0.000000] #40 [0005c15780 - 0005c157d0] BOOTMEM [ 0.000000] #41 [0005c15800 - 0005c15850] BOOTMEM [ 0.000000] #42 [0005c13540 - 0005c13740] BOOTMEM [ 0.000000] #43 [0005c13740 - 0005c13940] BOOTMEM [ 0.000000] #44 [0005c13940 - 0005c13b40] BOOTMEM [ 0.000000] #45 [0005c13b40 - 0005c13d40] BOOTMEM [ 0.000000] #46 [0005c15880 - 0005c1d880] BOOTMEM [ 0.000000] #47 [000d000000 - 000d800000] BOOTMEM [ 0.000000] #48 [000d800000 - 000dc00000] BOOTMEM [ 0.000000] #49 [000dc00000 - 0011c00000] BOOTMEM [ 0.000000] #50 [0005c1d880 - 0005c3d880] BOOTMEM [ 0.000000] #51 [0005c3d880 - 0005c7d880] BOOTMEM [ 0.000000] #52 [000000b000 - 0000013000] BOOTMEM [ 0.000000] Memory: 7596592k/9175040k available (3793k kernel code, 1311172k absent, 267276k reserved, 2741k data, 480k init) [ 0.000000] SLUB: Genslabs=13, HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1 [ 0.000000] Hierarchical RCU implementation. [ 0.000000] RCU-based detection of stalled CPUs is enabled. [ 0.000000] NR_IRQS:4352 [ 0.000000] Console: colour dummy device 80x25 [ 0.000000] console [tty0] enabled [ 0.000000] console [ttyS0] enabled [ 0.000000] Fast TSC calibration using PIT [ 0.000000] Detected 2606.461 MHz processor. [ 0.004003] Calibrating delay loop (skipped), value calculated using timer frequency.. 5212.91 BogoMIPS (lpj=2606458) [ 0.006019] Security Framework initialized [ 0.007004] SELinux: Disabled at boot. [ 0.008006] Mount-cache hash table entries: 256 [ 0.009101] Initializing cgroup subsys ns [ 0.010003] Initializing cgroup subsys cpuacct [ 0.011006] Initializing cgroup subsys devices [ 0.012004] Initializing cgroup subsys freezer [ 0.013028] CPU: Physical Processor ID: 0 [ 0.014002] CPU: Processor Core ID: 0 [ 0.015004] mce: CPU supports 6 MCE banks [ 0.016010] using C1E aware idle routine [ 0.017004] Performance Events: AMD PMU driver. [ 0.019005] ... version: 0 [ 0.020004] ... bit width: 48 [ 0.021004] ... generic registers: 4 [ 0.022004] ... value mask: 0000ffffffffffff [ 0.023001] ... max period: 00007fffffffffff [ 0.024001] ... fixed-purpose events: 0 [ 0.025001] ... event mask: 000000000000000f [ 0.026065] Setting APIC routing to flat [ 0.027005] CPU0: AMD Phenom(tm) II X4 910e Processor stepping 03 [ 0.138017] Booting Node 0, Processors #1 [ 0.215010] #2 #3 Ok. [ 0.365005] Brought up 4 CPUs [ 0.366001] Total of 4 processors activated (20850.41 BogoMIPS). [ 0.369122] regulator: core version 0.5 [ 0.370025] NET: Registered protocol family 16 [ 0.372007] TOM: 00000000d0000000 aka 3328M [ 0.373009] TOM2: 0000000230000000 aka 8960M [ 0.374025] PCI: Using configuration type 1 for base access [ 0.375007] PCI: Using configuration type 1 for extended access [ 0.379014] bio: create slab at 0 [ 0.380023] ACPI: Interpreter disabled. [ 0.381012] vgaarb: loaded [ 0.382042] SCSI subsystem initialized [ 0.383014] usbcore: registered new interface driver usbfs [ 0.384015] usbcore: registered new interface driver hub [ 0.385010] usbcore: registered new device driver usb [ 0.386015] PCI: Probing PCI hardware [ 0.388198] pci 0000:00:11.0: set SATA to AHCI mode