coreboot February 2011

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[commit] r6411 - trunk/src/cpu/amd/model_10xxx
by repository service 28 Feb '11

28 Feb '11

Author: mjones Date: Mon Feb 28 04:59:34 2011 New Revision: 6411 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6411 Log: Improving BKDG implementation of P-states, CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. I don't understand what this was doing nor find docs for these regs Maybe it was left over from some copy & paste ? Signed-off-by: Xavi Drudis Ferran <xdrudis(a)tinet.cat> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 04:56:52 2011 (r6410) +++ trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 04:59:34 2011 (r6411) @@ -16,8 +16,93 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +/* + * This file initializes the CPU cores for voltage and frequency settings + * in the different power states. + */ +/* + +checklist (functions are in this file if no source file named) +Fam10 Bios and Kernel Development Guide #31116, rev 3.48, April 22, 2010 + +2.4.2.6 Requirements for p-states + +1.- F3x[84:80] According to table 100 : prep_fid_change + +2.- COF/VID : + 2.4.2.9.1 Steps 1,3-6 and warning for 2,7 if they apply + fixPsNbVidBeforeWR(...) + 2.4.2.9.1 Step 8 enable_fid_change + We do this for all nodes, I don't understand BKDG 100% on + whether this is or isn't meant by "on the local + processor". Must be OK. + 2.4.2.9.1 Steps 9-10 (repeat 1-7 and reset) romstage.c/init_cpus ? + 2.4.2.9.1 Steps 11-12 init_fidvid_stage2 + 2.4.2.9.2 DualPlane PVI : Not supported, don't know how to detect, + needs specific circuitry. + +3.- 2.4.2.7 dualPlaneOnly(dev) + +4.- 2.4.2.8 applyBoostFIDOffset(dev) + +5.- enableNbPState1(dev) + +6.- 2.4.1.7 + a) UpdateSinglePlaneNbVid() + b) setVSRamp(), called from prep_fid_change + c) prep_fid_change + d) improperly, for lack of voltage regulator details?, + F3xA0[PsiVidEn] in defaults.h + F3xA0[PsiVid] in init_cpus.c AMD_SetupPSIVID_d (before prep_fid_change) + +7.- TODO (Core Performance Boost is only available in revision E cpus, and we + don't seem to support those yet, at least they don't have any + constant in amddefs.h ) + +8.- FIXME ? Transition to min Pstate according to 2.4.2.15.3 is required + by 2.4.2.6 after warm reset. But 2.4.2.15 states that it is not required + if the warm reset is issued by coreboot to update NbFid. So it is required + or not ? How can I tell who issued warm reset ? + Coreboot transitions to P0 instead, which is not recommended, and does + not follow 2.4.2.15.2 to do so. + +9.- TODO Requires information on current delivery capability + (depends on mainboard and maybe power supply ?). One might use a config + option with the maximum number of Ampers that the board can deliver to CPU. + +10.- [Multiprocessor] TODO 2.4.2.12 + [Uniprocessor] FIXME ? We call setPStateMaxVal() in init_fidvid_stage2, + but not sure this is what is meant by "Determine the valid set of + P-states based on enabled P-states indicated + in MSRC001_00[68:64][PstateEn]" in 2.4.2.6-10 + +11.- finalPstateChange() from init_fidvid_Stage2 (BKDG says just "may", anyway) + +12.- generate ACPI for p-states. FIXME + Needs more assesment. There's some kind of fixed support that + does not seem to depend on CPU revision or actual MSRC001_00[68:64] + as BKDG apparently requires. + http://www.coreboot.org/ACPI#CPU_Power_Management + At least for Tilapia board: + src/mainboard/<vendor>/<model>/acpi_tables.c write_acpi_tables(...) calls + acpi_add_ssdt_pstates(...) + in /src/northbridge/amd/amdfam10/amdfam10_acpi.c + which apparently copies them from static info in + src/mainboard/<vendor>/<model>/acpi/cpstate.asl + +"must also be completed" + +a.- PllLockTime set in ruleset in defaults.h + BKDG says set it "If MSRC001_00[68:64][CpuFid] is different between + any two enabled P-states", but since it does not say "only if" + I guess it is safe to do it always. + +b.- prep_fid_change(...) + + */ #if CONFIG_SET_FIDVID + #include <northbridge/amd/amdht/AsPsDefs.h> static inline void print_debug_fv(const char *str, u32 val)

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[commit] r6410 - in trunk/src: cpu/amd/model_10xxx northbridge/amd/amdht
by repository service 28 Feb '11

28 Feb '11

Author: mjones Date: Mon Feb 28 04:56:52 2011 New Revision: 6410 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6410 Log: Improving BKDG implementation of P-states, CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. I don't understand what this was doing nor find docs for these regs Maybe it was left over from some copy & paste ? Signed-off-by: Xavi Drudis Ferran <xdrudis(a)tinet.cat> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c trunk/src/cpu/amd/model_10xxx/init_cpus.c trunk/src/northbridge/amd/amdht/AsPsDefs.h Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 04:53:47 2011 (r6409) +++ trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 04:56:52 2011 (r6410) @@ -738,7 +738,7 @@ } -static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid) +static void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid) { u32 send; Modified: trunk/src/cpu/amd/model_10xxx/init_cpus.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/init_cpus.c Mon Feb 28 04:53:47 2011 (r6409) +++ trunk/src/cpu/amd/model_10xxx/init_cpus.c Mon Feb 28 04:56:52 2011 (r6410) @@ -157,7 +157,7 @@ } #if CONFIG_SET_FIDVID -static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid); +static void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid); #endif static inline __attribute__ ((always_inline)) @@ -346,8 +346,7 @@ printk(BIOS_DEBUG, "init_fidvid_ap(stage1) apicid: %02x\n", apicid); - init_fidvid_ap(bsp_apicid, apicid, id.nodeid, - id.coreid); + init_fidvid_ap(apicid, id.nodeid, id.coreid); } } #endif Modified: trunk/src/northbridge/amd/amdht/AsPsDefs.h ============================================================================== --- trunk/src/northbridge/amd/amdht/AsPsDefs.h Mon Feb 28 04:53:47 2011 (r6409) +++ trunk/src/northbridge/amd/amdht/AsPsDefs.h Mon Feb 28 04:56:52 2011 (r6410) @@ -58,7 +58,6 @@ #define PS_NB_VID_SHFT 25 /* P-state bit shift for NbVid */ #define PS_BOTH_VID_OFF 0x01ff01ff /* Mask NbVid & CpuVid */ #define PS_CPU_NB_VID_SHFT 16 /* P-state bit shift from CpuVid to NbVid */ -#define PS_NB_VID_SHFT 25 /* P-state NBVID shift */ #define PS_DIS 0x7fffffff /* disable P-state reg */ #define PS_EN 0x80000000 /* enable P-state reg */ #define PS_CPU_FID_MASK 0x03f /* MSRC001_00[68:64][CpuFid]

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[commit] r6409 - trunk/src/cpu/amd/model_10xxx
by repository service 28 Feb '11

28 Feb '11

Author: mjones Date: Mon Feb 28 04:53:47 2011 New Revision: 6409 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6409 Log: Improving BKDG implementation of P-states, CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. I don't understand what this was doing nor find docs for these regs Maybe it was left over from some copy & paste ? Signed-off-by: Xavi Drudis Ferran <xdrudis(a)tinet.cat> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 04:49:28 2011 (r6408) +++ trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 04:53:47 2011 (r6409) @@ -394,19 +394,6 @@ } else { /* SVI */ /* set slamVidMode to 1 for SVI */ dword |= VID_SLAM_ON; - - u32 dtemp = dword; - - /* Program F3xD8[PwrPlanes] according F3xA0[DulaVdd] */ - dword = pci_read_config32(dev, 0xD8); - - if (dtemp & DUAL_VDD_BIT) - dword |= PWR_PLN_ON; - else - dword &= PWR_PLN_OFF; - pci_write_config32(dev, 0xD8, dword); - - dword = dtemp; } /* set the rest of A0 since we're at it... */

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[commit] r6408 - in trunk/src: cpu/amd/model_10xxx northbridge/amd/amdht northbridge/amd/amdmct/wrappers
by repository service 28 Feb '11

28 Feb '11

Author: mjones Date: Mon Feb 28 04:49:28 2011 New Revision: 6408 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6408 Log: Improving BKDG implementation of P-states, CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. In fact I changed coreDelay before deleting the code in fidvid that called it. But there're still a couple of calls from src/northbridge/amd/amdmct/wrappers/mcti_d.c Since the comment encouraged fixing something, I parametrized it with the delay time in microseconds and paranoically tried to avoid an overflow at pathological moments. Signed-off-by: Xavi Drudis Ferran <xdrudis(a)tinet.cat> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c trunk/src/northbridge/amd/amdht/AsPsDefs.h trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 04:35:43 2011 (r6407) +++ trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 04:49:28 2011 (r6408) @@ -77,9 +77,9 @@ u32 cpuFid = msr.lo & PS_CPU_FID_MASK; cpuFid = cpuFid + asymetricBoostThisCore; msr.lo &= ~PS_CPU_FID_MASK; - msr.lo |= cpuFid ; + msr.lo |= cpuFid ; wrmsr(PS_REG_BASE , msr); - + } } @@ -104,7 +104,7 @@ } static u8 setPStateMaxVal( device_t dev ) { - u8 i,maxpstate=0; + u8 i,maxpstate=0; for (i = 0; i < NM_PS_REG; i++) { msr_t msr = rdmsr(PS_REG_BASE + i); if (msr.hi & PS_IDD_VALUE_MASK) { @@ -141,8 +141,8 @@ msr.lo=0; msr.hi=0; wrmsr(0xC0010064, rdmsr(0xC0010068) ); wrmsr(0xC0010068, msr ); - } - + } + //FIXME: CPTC2 and HTC_REG should get max per node, not per core ? u8 maxpstate = setPStateMaxVal(dev); @@ -155,15 +155,15 @@ } } -static int vidTo100uV(u8 vid) +static int vidTo100uV(u8 vid) {// returns voltage corresponding to vid in tenths of mV, i.e. hundreds of uV // BKDG #31116 rev 3.48 2.4.1.6 int voltage; if (vid >= 0x7c) { voltage = 0; } else { - voltage = (15500 - (125*vid)); - } + voltage = (15500 - (125*vid)); + } return voltage; } @@ -193,12 +193,12 @@ /* This function calculates the VsSlamTime using the range of possible * voltages instead of a hardcoded 200us. - * Note: his function is called only from prep_fid_change, - * and that from init_cpus.c finalize_node_setup() + * Note: his function is called only from prep_fid_change, + * and that from init_cpus.c finalize_node_setup() * (after set AMD MSRs and init ht ) */ - /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSSlamTime] */ + /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSSlamTime] */ /* Calculate Slam Time * Vslam = (mobileCPU?0.2:0.4)us/mV * (Vp0 - (lowest out of Vpmin or Valt)) mV * In our case, we will scale the values by 100 to avoid @@ -222,7 +222,7 @@ highVoltageVid = (u8) ((msr.lo >> PS_CPU_VID_SHFT) & 0x7F); if (!(msr.hi & 0x80000000)) { printk(BIOS_ERR,"P-state info in MSRC001_0064 is invalid !!!\n"); - highVoltageVid = (u8) ((pci_read_config32(dev, 0x1E0) + highVoltageVid = (u8) ((pci_read_config32(dev, 0x1E0) >> PS_CPU_VID_SHFT) & 0x7F); } @@ -238,13 +238,13 @@ /* Get PSmax's index */ msr = rdmsr(0xC0010061); bValue = (u8) ((msr.lo >> PS_MAX_VAL_SHFT) & BIT_MASK_3); - + /* Get PSmax's VID */ msr = rdmsr(0xC0010064 + bValue); lowVoltageVid = (u8) ((msr.lo >> PS_CPU_VID_SHFT) & 0x7F); if (!(msr.hi & 0x80000000)) { printk(BIOS_ERR,"P-state info in MSR%8x is invalid !!!\n",0xC0010064 + bValue); - lowVoltageVid = (u8) ((pci_read_config32(dev, 0x1E0+(bValue*4)) + lowVoltageVid = (u8) ((pci_read_config32(dev, 0x1E0+(bValue*4)) >> PS_CPU_VID_SHFT) & 0x7F); } @@ -266,7 +266,7 @@ if (lowVoltageVid < bValue) lowVoltageVid = bValue; - u8 mobileFlag = get_platform_type() & AMD_PTYPE_MOB; + u8 mobileFlag = get_platform_type() & AMD_PTYPE_MOB; minimumSlamTime = (mobileFlag?2:4) * (vidTo100uV(highVoltageVid) - vidTo100uV(lowVoltageVid)); /* * 0.01 us */ @@ -819,7 +819,7 @@ } -static void fixPsNbVidAfterWR(u32 newNbVid, u8 NbVidUpdatedAll,u8 pviMode) +static void fixPsNbVidAfterWR(u32 newNbVid, u8 NbVidUpdatedAll,u8 pviMode) { msr_t msr; u8 i; @@ -837,7 +837,7 @@ for (i = 0; i < 5; i++) { msr = rdmsr(0xC0010064 + i); /* NbDid (bit 22 of P-state Reg) == 0 or NbVidUpdatedAll = 1 */ - if ( (msr.hi & PS_IDD_VALUE_MASK) + if ( (msr.hi & PS_IDD_VALUE_MASK) && (msr.hi & PS_EN_MASK) &&(((msr.lo & PS_NB_DID_MASK) == 0) || NbVidUpdatedAll)) { msr.lo &= PS_NB_VID_M_OFF; @@ -855,7 +855,7 @@ /* For each core in the system, transition all cores to StartupPstate */ msr = rdmsr(0xC0010071); StartupPstate = msr.hi & 0x07; - + /* Set and wait for StartupPstate to set. */ set_pstate(StartupPstate); Modified: trunk/src/northbridge/amd/amdht/AsPsDefs.h ============================================================================== --- trunk/src/northbridge/amd/amdht/AsPsDefs.h Mon Feb 28 04:35:43 2011 (r6407) +++ trunk/src/northbridge/amd/amdht/AsPsDefs.h Mon Feb 28 04:49:28 2011 (r6408) @@ -291,7 +291,10 @@ #define TSC_MSR 0x10 #define CUR_PSTATE_MSR 0xc0010063 +#define TSC_FREQ_SEL_SHIFT 24 +#define TSC_FREQ_SEL_MASK (1 << TSC_FREQ_SEL_SHIFT) + #define WAIT_PSTATE_TIMEOUT 80000000 /* 0.1 s , unit : 1.25 ns */ #endif Modified: trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c Mon Feb 28 04:35:43 2011 (r6407) +++ trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c Mon Feb 28 04:49:28 2011 (r6408) @@ -340,6 +340,39 @@ } #if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */ +static void coreDelay(u32 microseconds) +{ + msr_t now; + msr_t end; + u32 cycles; + + /* delay ~40us + This seems like a hack to me... + It would be nice to have a central delay function. */ + + cycles = (microseconds * 100) << 3; /* x8 (number of 1.25ns ticks) */ + + if (!(rdmsr(HWCR).lo & TSC_FREQ_SEL_MASK)) { + msr_t pstate_msr = rdmsr(CUR_PSTATE_MSR); + if (!(rdmsr(0xC0010064+pstate_msr.lo).lo & NB_DID_M_ON)) { + cycles = cycles <<1; // half freq, double cycles + } + } // else should we keep p0 freq at the time of setting TSC_FREQ_SEL_MASK somewhere and check it here ? + + now = rdmsr(TSC_MSR); + // avoid overflow when called near 2^32 ticks ~ 5.3 s boundaries + if (0xffffffff - cycles >= now.lo ) { + end.hi = now.hi; + end.lo = now.lo + cycles; + } else { + end.hi = now.hi +1; // + end.lo = cycles - (1+(0xffffffff - now.lo)); + } + do { + now = rdmsr(TSC_MSR); + } while ((now.hi < end.hi) || ((now.hi == end.hi) && (now.lo < end.lo))); +} + /* Erratum 350 */ static void vErrata350(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) { @@ -385,7 +418,7 @@ print_t("vErrata350: step 3\n"); /* 3. Wait at least 300 nanoseconds. */ - coreDelay(); + coreDelay(1); print_t("vErrata350: step 4\n"); /* 4. Write 0000_0000h to register F2x[1, 0]9C_xD080F0C. */ @@ -398,7 +431,7 @@ print_t("vErrata350: step 5\n"); /* 5. Wait at least 2 microseconds. */ - coreDelay(); + coreDelay(2); }

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[commit] r6407 - trunk/src/northbridge/amd/amdht
by repository service 28 Feb '11

28 Feb '11

Author: mjones Date: Mon Feb 28 04:35:43 2011 New Revision: 6407 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6407 Log: Improving BKDG implementation of P-states, CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. bits 13 - 15 of F3xd4 (StutterScrubEn, CacheFlushImmOnAllHalt and MTC1eEn are reserved for revisions D0 and earlier, so whe should not set them to 0 in fidvid.c config_clk_power_ctrl_reg0(...), called from prep_fid_change. For revisions > D0 (when we support them) it is ok not ot clear them, because they are documented as 0 on reset. bit 12 should be left alone according to BKDG. Should I set 11:8 ClkRampHystSel to 0 in the mask too, just to indicate we're touching them ? We'll OR them to 1111 anyway... Signed-off-by: Xavi Drudis Ferran <xdrudis(a)tinet.cat> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/northbridge/amd/amdht/AsPsDefs.h Modified: trunk/src/northbridge/amd/amdht/AsPsDefs.h ============================================================================== --- trunk/src/northbridge/amd/amdht/AsPsDefs.h Mon Feb 28 04:32:23 2011 (r6406) +++ trunk/src/northbridge/amd/amdht/AsPsDefs.h Mon Feb 28 04:35:43 2011 (r6407) @@ -111,7 +111,7 @@ #define STC_PS_LMT_MASK 0x8fffffff /* StcPstateLimit mask off */ #define CPTC0 0x0d4 /* Clock Power/Timing Control0 Register*/ -#define CPTC0_MASK 0x000c0fff /* Reset mask for this register */ +#define CPTC0_MASK 0x000cffff /* Reset mask for this register */ #define CPTC0_NBFID_MASK 0xffffffe0 /* NbFid mask off for this register */ #define CPTC0_NBFID_MON 0x1f /* NbFid mask on for this register */ #define NB_FID_EN 0x20 /* NbFidEn bit ON */

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[commit] r6406 - in trunk/src: cpu/amd/model_10xxx northbridge/amd/amdht
by repository service 28 Feb '11

28 Feb '11

Author: mjones Date: Mon Feb 28 04:32:23 2011 New Revision: 6406 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6406 Log: Improving BKDG implementation of P-states, CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. Well, I understand it better like this, but maybe it's only me, part of the changes are paranoic, and the only effective change is for a factor depending on mobile or not that I can't test. Signed-off-by: Xavi Drudis Ferran <xdrudis(a)tinet.cat> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c trunk/src/northbridge/amd/amdht/AsPsDefs.h Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 04:25:07 2011 (r6405) +++ trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 04:32:23 2011 (r6406) @@ -155,6 +155,18 @@ } } +static int vidTo100uV(u8 vid) +{// returns voltage corresponding to vid in tenths of mV, i.e. hundreds of uV + // BKDG #31116 rev 3.48 2.4.1.6 + int voltage; + if (vid >= 0x7c) { + voltage = 0; + } else { + voltage = (15500 - (125*vid)); + } + return voltage; +} + static void setVSRamp(device_t dev) { /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSRampTime] * If this field accepts 8 values between 10 and 500 us why @@ -181,12 +193,14 @@ /* This function calculates the VsSlamTime using the range of possible * voltages instead of a hardcoded 200us. - * Note:This function is called from setFidVidRegs and setUserPs after - * programming a custom Pstate. + * Note: his function is called only from prep_fid_change, + * and that from init_cpus.c finalize_node_setup() + * (after set AMD MSRs and init ht ) */ + /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSSlamTime] */ /* Calculate Slam Time - * Vslam = 0.4us/mV * Vp0 - (lowest out of Vpmin or Valt) + * Vslam = (mobileCPU?0.2:0.4)us/mV * (Vp0 - (lowest out of Vpmin or Valt)) mV * In our case, we will scale the values by 100 to avoid * decimals. */ @@ -200,8 +214,17 @@ pviModeFlag = 0; /* Get P0's voltage */ + /* MSRC001_00[68:64] are not programmed yet when called from + prep_fid_change, one might use F4x1[F0:E0] instead, but + theoretically MSRC001_00[68:64] are equal to them after + reset. */ msr = rdmsr(0xC0010064); highVoltageVid = (u8) ((msr.lo >> PS_CPU_VID_SHFT) & 0x7F); + if (!(msr.hi & 0x80000000)) { + printk(BIOS_ERR,"P-state info in MSRC001_0064 is invalid !!!\n"); + highVoltageVid = (u8) ((pci_read_config32(dev, 0x1E0) + >> PS_CPU_VID_SHFT) & 0x7F); + } /* If SVI, we only care about CPU VID. * If PVI, determine the higher voltage b/t NB and CPU @@ -212,17 +235,23 @@ highVoltageVid = bValue; } - /* Get Pmin's index */ + /* Get PSmax's index */ msr = rdmsr(0xC0010061); - bValue = (u8) ((msr.lo >> PS_CUR_LIM_SHFT) & BIT_MASK_3); - - /* Get Pmin's VID */ + bValue = (u8) ((msr.lo >> PS_MAX_VAL_SHFT) & BIT_MASK_3); + + /* Get PSmax's VID */ msr = rdmsr(0xC0010064 + bValue); lowVoltageVid = (u8) ((msr.lo >> PS_CPU_VID_SHFT) & 0x7F); + if (!(msr.hi & 0x80000000)) { + printk(BIOS_ERR,"P-state info in MSR%8x is invalid !!!\n",0xC0010064 + bValue); + lowVoltageVid = (u8) ((pci_read_config32(dev, 0x1E0+(bValue*4)) + >> PS_CPU_VID_SHFT) & 0x7F); + } /* If SVI, we only care about CPU VID. * If PVI, determine the higher voltage b/t NB and CPU - */ + * BKDG 2.4.1.7 (a) + */ if (pviModeFlag) { bValue = (u8) ((msr.lo >> PS_NB_VID_SHFT) & 0x7F); if (lowVoltageVid > bValue) @@ -237,20 +266,9 @@ if (lowVoltageVid < bValue) lowVoltageVid = bValue; - /* If Vids are 7Dh - 7Fh, force 7Ch to keep calculations linear */ - if (lowVoltageVid > 0x7C) { - lowVoltageVid = 0x7C; - if (highVoltageVid > 0x7C) - highVoltageVid = 0x7C; - } - - bValue = (u8) (lowVoltageVid - highVoltageVid); + u8 mobileFlag = get_platform_type() & AMD_PTYPE_MOB; + minimumSlamTime = (mobileFlag?2:4) * (vidTo100uV(highVoltageVid) - vidTo100uV(lowVoltageVid)); /* * 0.01 us */ - /* Each Vid increment is 12.5 mV. The minimum slam time is: - * vidCodeDelta * 12.5mV * 0.4us/mV - * Scale by 100 to avoid decimals. - */ - minimumSlamTime = bValue * (125 * 4); /* Now round up to nearest register setting. * Note that if we don't find a value, we Modified: trunk/src/northbridge/amd/amdht/AsPsDefs.h ============================================================================== --- trunk/src/northbridge/amd/amdht/AsPsDefs.h Mon Feb 28 04:25:07 2011 (r6405) +++ trunk/src/northbridge/amd/amdht/AsPsDefs.h Mon Feb 28 04:32:23 2011 (r6406) @@ -25,7 +25,7 @@ #define APIC_BAR_BP 0x100 /* APIC_BAR BSP bit */ #define PS_LIM_REG 0xC0010061 /* P-state Current Limit Register */ -#define PS_CUR_LIM_SHFT 4 /* P-state Current Limit shift position */ +#define PS_MAX_VAL_SHFT 4 /* P-state Maximum Value shift position */ #define PS_CTL_REG 0xC0010062 /* P-state Control Register */ #define PS_CMD_MASK_OFF 0xfffffff8 /* P-state Control Register CMD Mask OFF */

1 0

[commit] r6405 - in trunk/src: cpu/amd/model_10xxx northbridge/amd/amdht
by repository service 28 Feb '11

28 Feb '11

Author: mjones Date: Mon Feb 28 04:25:07 2011 New Revision: 6405 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6405 Log: Improving BKDG implementation of P-states, CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. Add an untested step in BKDG 2.4.2.8. I don't have the hardware with Core Performance Boost and I think it's only available in revision E that does not even have a constant yet. Signed-off-by: Xavi Drudis Ferran <xdrudis(a)tinet.cat> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c trunk/src/northbridge/amd/amdht/AsPsDefs.h Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 04:19:17 2011 (r6404) +++ trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 04:25:07 2011 (r6405) @@ -65,6 +65,24 @@ dword); } } + +static void applyBoostFIDOffset( device_t dev ) { + // BKDG 2.4.2.8 + // revision E only, but E is apparently not supported yet, therefore untested + if ((cpuid_edx(0x80000007) & CPB_MASK) + && ((cpuid_ecx(0x80000008) & NC_MASK) ==5) ) { + u32 core = get_node_core_id_x().coreid; + u32 asymetricBoostThisCore = ((pci_read_config32(dev, 0x10C) >> (core*2))) & 3; + msr_t msr = rdmsr(PS_REG_BASE); + u32 cpuFid = msr.lo & PS_CPU_FID_MASK; + cpuFid = cpuFid + asymetricBoostThisCore; + msr.lo &= ~PS_CPU_FID_MASK; + msr.lo |= cpuFid ; + wrmsr(PS_REG_BASE , msr); + + } +} + static void enableNbPState1( device_t dev ) { u32 cpuRev = mctGetLogicalCPUID(0xFF); if (cpuRev & AMD_FAM10_C3) { @@ -872,7 +890,9 @@ pci_write_config32(dev, 0xA0, dtemp); dualPlaneOnly(dev); + applyBoostFIDOffset(dev); enableNbPState1(dev); + finalPstateChange(); /* Set TSC to tick at the P0 ndfid rate */ Modified: trunk/src/northbridge/amd/amdht/AsPsDefs.h ============================================================================== --- trunk/src/northbridge/amd/amdht/AsPsDefs.h Mon Feb 28 04:19:17 2011 (r6404) +++ trunk/src/northbridge/amd/amdht/AsPsDefs.h Mon Feb 28 04:25:07 2011 (r6405) @@ -61,6 +61,8 @@ #define PS_NB_VID_SHFT 25 /* P-state NBVID shift */ #define PS_DIS 0x7fffffff /* disable P-state reg */ #define PS_EN 0x80000000 /* enable P-state reg */ +#define PS_CPU_FID_MASK 0x03f /* MSRC001_00[68:64][CpuFid] + Core Frequency Id */ #define PS_CURDIV_SHFT 8 /* P-state Current Divisor shift position */ #define PS_CPUDID_SHIFT 6 /* P-state CPU DID shift position */ @@ -202,6 +204,8 @@ #define CPB_MASK 0x00000020 /* core performance boost. CPUID Fn8000 0007 edx */ +#define NC_MASK 0x000000FF /* number of cores - 1. CPUID + Fn8000 0008 ecx */ #define PW_CTL_MISC 0x0a0 /* Power Control Miscellaneous Register */ #define COF_VID_PROG_BIT 0x80000000 /* CofVidProg bit. 0= unfused part */ #define DUAL_VDD_BIT 0x40000000 /* DualVdd bit. */

1 0

[commit] r6404 - in trunk/src: cpu/amd/model_10xxx northbridge/amd/amdht
by repository service 28 Feb '11

28 Feb '11

Author: mjones Date: Mon Feb 28 04:19:17 2011 New Revision: 6404 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6404 Log: Improving BKDG implementation of P-states, CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. Add to init_fidvid_stage2 some step mentioned in BKDG 2.4.2.7 that was missing . Some lines are dead code now, but may handy if one day we support revison E CPUs. Signed-off-by: Xavi Drudis Ferran <xdrudis(a)tinet.cat> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c trunk/src/northbridge/amd/amdht/AsPsDefs.h Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 04:12:00 2011 (r6403) +++ trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 04:19:17 2011 (r6404) @@ -85,6 +85,58 @@ } } +static u8 setPStateMaxVal( device_t dev ) { + u8 i,maxpstate=0; + for (i = 0; i < NM_PS_REG; i++) { + msr_t msr = rdmsr(PS_REG_BASE + i); + if (msr.hi & PS_IDD_VALUE_MASK) { + msr.hi |= PS_EN_MASK ; + wrmsr(PS_REG_BASE + i, msr); + } + if (msr.hi | PS_EN_MASK) { + maxpstate = i; + } + } + //FIXME: CPTC2 and HTC_REG should get max per node, not per core ? + u32 reg = pci_read_config32(dev, CPTC2); + reg &= PS_MAX_VAL_MASK; + reg |= (maxpstate << PS_MAX_VAL_POS); + pci_write_config32(dev, CPTC2,reg); + return maxpstate; +} + +static void dualPlaneOnly( device_t dev ) { + // BKDG 2.4.2.7 + + u32 cpuRev = mctGetLogicalCPUID(0xFF); + if ((mctGetProcessorPackageType() == AMD_PKGTYPE_AM3_2r2) + && (cpuRev & AMD_DR_Cx)) { // should be rev C or rev E but there's no constant for E + if ( (pci_read_config32(dev, 0x1FC) & DUAL_PLANE_ONLY_MASK) + && (pci_read_config32(dev, 0xA0) & PVI_MODE) ){ + if (cpuid_edx(0x80000007) & CPB_MASK) { + // revision E only, but E is apparently not supported yet, therefore untested + msr_t minPstate = rdmsr(0xC0010065); + wrmsr(0xC0010065, rdmsr(0xC0010068) ); + wrmsr(0xC0010068,minPstate); + } else { + msr_t msr; + msr.lo=0; msr.hi=0; + wrmsr(0xC0010064, rdmsr(0xC0010068) ); + wrmsr(0xC0010068, msr ); + } + + //FIXME: CPTC2 and HTC_REG should get max per node, not per core ? + u8 maxpstate = setPStateMaxVal(dev); + + u32 reg = pci_read_config32(dev, HTC_REG); + reg &= HTC_PS_LMT_MASK; + reg |= (maxpstate << PS_LIMIT_POS); + pci_write_config32(dev, HTC_REG,reg); + + } + } +} + static void setVSRamp(device_t dev) { /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSRampTime] * If this field accepts 8 values between 10 and 500 us why @@ -819,6 +871,7 @@ dtemp |= PLLLOCK_DFT_L; pci_write_config32(dev, 0xA0, dtemp); + dualPlaneOnly(dev); enableNbPState1(dev); finalPstateChange(); Modified: trunk/src/northbridge/amd/amdht/AsPsDefs.h ============================================================================== --- trunk/src/northbridge/amd/amdht/AsPsDefs.h Mon Feb 28 04:12:00 2011 (r6403) +++ trunk/src/northbridge/amd/amdht/AsPsDefs.h Mon Feb 28 04:19:17 2011 (r6404) @@ -191,6 +191,7 @@ #define NB_SYN_PTR_ADJ_MASK (0x7 << NB_SYN_PTR_ADJ_POS) /* NbsynPtrAdj bit mask */ #define PRCT_INFO 0x1fc /* Product Info Register */ +#define DUAL_PLANE_ONLY_MASK 0x80000000 /* F3x1FC[DualPlaneOnly] */ #define UNI_NB_FID_BIT 2 /* UniNbFid bit position */ #define UNI_NB_VID_BIT 7 /* UniNbVid bit position */ #define SPLT_NB_FID_OFFSET 14 /* SpltNbFidOffset value bit position */ @@ -199,6 +200,8 @@ #define NB_VID_UPDATE_ALL 0x02 /* F3x1FC[NbVidUpdatedAll] bit mask */ #define C_FID_DID_M_OFF 0xfffffe00 /* mask off Core FID & DID */ +#define CPB_MASK 0x00000020 /* core performance + boost. CPUID Fn8000 0007 edx */ #define PW_CTL_MISC 0x0a0 /* Power Control Miscellaneous Register */ #define COF_VID_PROG_BIT 0x80000000 /* CofVidProg bit. 0= unfused part */ #define DUAL_VDD_BIT 0x40000000 /* DualVdd bit. */

1 0

[commit] r6403 - in trunk/src: cpu/amd/model_10xxx northbridge/amd/amdht
by repository service 28 Feb '11

28 Feb '11

Author: mjones Date: Mon Feb 28 04:12:00 2011 New Revision: 6403 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6403 Log: Improving BKDG implementation of P-states, CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. Add to init_fidvid_stage2 some step for my CPU (rev C3) mentioned in BKDG 2.4.2.6 (5) that was missing Signed-off-by: Xavi Drudis Ferran <xdrudis(a)tinet.cat> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c trunk/src/northbridge/amd/amdht/AsPsDefs.h Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 04:08:06 2011 (r6402) +++ trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 04:12:00 2011 (r6403) @@ -65,6 +65,25 @@ dword); } } +static void enableNbPState1( device_t dev ) { + u32 cpuRev = mctGetLogicalCPUID(0xFF); + if (cpuRev & AMD_FAM10_C3) { + u32 nbPState = (pci_read_config32(dev, 0x1F0) & NB_PSTATE_MASK); + if ( nbPState){ + u32 nbVid1 = (pci_read_config32(dev, 0x1F4) & NB_VID1_MASK) >> NB_VID1_SHIFT; + u32 i; + for (i = nbPState; i < NM_PS_REG; i++) { + msr_t msr = rdmsr(PS_REG_BASE + i); + if (msr.hi & PS_EN_MASK ) { + msr.hi |= NB_DID_M_ON; + msr.lo &= NB_VID_MASK_OFF; + msr.lo |= ( nbVid1 << NB_VID_POS); + wrmsr(PS_REG_BASE + i, msr); + } + } + } + } +} static void setVSRamp(device_t dev) { /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSRampTime] @@ -800,6 +819,7 @@ dtemp |= PLLLOCK_DFT_L; pci_write_config32(dev, 0xA0, dtemp); + enableNbPState1(dev); finalPstateChange(); /* Set TSC to tick at the P0 ndfid rate */ Modified: trunk/src/northbridge/amd/amdht/AsPsDefs.h ============================================================================== --- trunk/src/northbridge/amd/amdht/AsPsDefs.h Mon Feb 28 04:08:06 2011 (r6402) +++ trunk/src/northbridge/amd/amdht/AsPsDefs.h Mon Feb 28 04:12:00 2011 (r6403) @@ -153,6 +153,8 @@ #define PS_2 0x00020000 /* P-state 2 */ #define PS_CPU_DID_1 0x40 /* Cpu Did 1 */ +#define NB_VID1_MASK 0x00003f80 /* F3x1F4[NbVid1]*/ +#define NB_VID1_SHIFT 7 /* F3x1F4[NbVid1] */

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[commit] r6402 - in trunk/src: cpu/amd/model_10xxx northbridge/amd/amdht
by repository service 28 Feb '11

28 Feb '11

Author: mjones Date: Mon Feb 28 04:08:06 2011 New Revision: 6402 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6402 Log: Improving BKDG implementation of P-states, CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. Looking at BKDG the process for updating Pstate Nb vid after warn reset seemed more similar to the codethat was there fo pvi than the one for svi, so I called the pvi function passing a pvi/svi flag. I don't find documentation on why should UpdateSinglePlaneNbVid() be called in PVI, but since I can't test it, I leave it as it was. This patch showed some progress beyond fidvid in my boar,d but only sometimes, most times it just didn't work. Signed-off-by: Xavi Drudis Ferran <xdrudis(a)tinet.cat> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c trunk/src/northbridge/amd/amdht/AsPsDefs.h Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 04:02:40 2011 (r6401) +++ trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 04:08:06 2011 (r6402) @@ -712,36 +712,17 @@ } -static void updateSviPsNbVidAfterWR(u32 newNbVid) -{ - msr_t msr; - u8 i; - - /* This function copies newNbVid to NbVid bits in P-state Registers[4:0] - * for SVI mode. - */ - - for (i = 0; i < 5; i++) { - msr = rdmsr(0xC0010064 + i); - if ((msr.hi >> 31) & 1) { /* PstateEn? */ - msr.lo &= ~(0x7F << 25); - msr.lo |= (newNbVid & 0x7F) << 25; - wrmsr(0xC0010064 + i, msr); - } - } -} - - -static void fixPsNbVidAfterWR(u32 newNbVid, u8 NbVidUpdatedAll) +static void fixPsNbVidAfterWR(u32 newNbVid, u8 NbVidUpdatedAll,u8 pviMode) { msr_t msr; u8 i; u8 StartupPstate; - /* This function copies newNbVid to NbVid bits in P-state - * Registers[4:0] if its NbDid bit=0 and PstateEn bit =1 in case of - * NbVidUpdatedAll =0 or copies copies newNbVid to NbVid bits in - * P-state Registers[4:0] if its and PstateEn bit =1 in case of + /* BKDG 2.4.2.9.1 11-12 + * This function copies newNbVid to NbVid bits in P-state + * Registers[4:0] if its NbDid bit=0, and IddValue!=0 in case of + * NbVidUpdatedAll =0 or copies newNbVid to NbVid bits in + * P-state Registers[4:0] if its IddValue!=0 in case of * NbVidUpdatedAll=1. Then transition to StartPstate. */ @@ -749,26 +730,28 @@ for (i = 0; i < 5; i++) { msr = rdmsr(0xC0010064 + i); /* NbDid (bit 22 of P-state Reg) == 0 or NbVidUpdatedAll = 1 */ - if ((((msr.lo >> 22) & 1) == 0) || NbVidUpdatedAll) { - msr.lo &= ~(0x7F << 25); - msr.lo |= (newNbVid & 0x7F) << 25; + if ( (msr.hi & PS_IDD_VALUE_MASK) + && (msr.hi & PS_EN_MASK) + &&(((msr.lo & PS_NB_DID_MASK) == 0) || NbVidUpdatedAll)) { + msr.lo &= PS_NB_VID_M_OFF; + msr.lo |= (newNbVid & 0x7F) << PS_NB_VID_SHFT; wrmsr(0xC0010064 + i, msr); } } - UpdateSinglePlaneNbVid(); - + /* Not documented. Would overwrite Nb_Vids just copied + * should we just update cpu_vid or nothing at all ? + */ + if (pviMode) { //single plane + UpdateSinglePlaneNbVid(); + } /* For each core in the system, transition all cores to StartupPstate */ msr = rdmsr(0xC0010071); StartupPstate = msr.hi & 0x07; - msr = rdmsr(0xC0010062); - msr.lo = StartupPstate; - wrmsr(0xC0010062, msr); - - /* Wait for StartupPstate to set. */ - do { - msr = rdmsr(0xC0010063); - } while (msr.lo != StartupPstate); + + /* Set and wait for StartupPstate to set. */ + set_pstate(StartupPstate); + } static void finalPstateChange(void) @@ -803,15 +786,12 @@ NbVidUpdateAll = (reg1fc >> 1) & 1; if (nb_cof_vid_update) { - if (pvimode) { - nbvid = (reg1fc >> 7) & 0x7F; - /* write newNbVid to P-state Reg's NbVid if its NbDid=0 */ - fixPsNbVidAfterWR(nbvid, NbVidUpdateAll); - } else { /* SVI */ - nbvid = ((reg1fc >> 7) & 0x7F) - ((reg1fc >> 17) & 0x1F); - updateSviPsNbVidAfterWR(nbvid); + if (!pvimode) { /* SVI */ + nbvid = nbvid - ((reg1fc >> 17) & 0x1F); } - } else { /* !nb_cof_vid_update */ + /* write newNbVid to P-state Reg's NbVid if its NbDid=0 */ + fixPsNbVidAfterWR(nbvid, NbVidUpdateAll,pvimode); + } else { /* !nb_cof_vid_update */ if (pvimode) UpdateSinglePlaneNbVid(); } Modified: trunk/src/northbridge/amd/amdht/AsPsDefs.h ============================================================================== --- trunk/src/northbridge/amd/amdht/AsPsDefs.h Mon Feb 28 04:02:40 2011 (r6401) +++ trunk/src/northbridge/amd/amdht/AsPsDefs.h Mon Feb 28 04:08:06 2011 (r6402) @@ -44,6 +44,10 @@ #define PS_REG3 3 /* offset for P3 */ #define PS_REG4 4 /* offset for P4 */ +#define PS_IDD_VALUE_SHFT 0 /* IddValue: current value + field offset for msr.hi */ +#define PS_IDD_VALUE_MASK 0xFF /* IddValue: current value + field mask for msr.hi */ #define PS_PSDIS_MASK 0x7fffffff /* disable P-state register */ #define PS_EN_MASK 0x80000000 /* P-state register enable mask */ #define PS_NB_DID_MASK 0x400000 /* P-state Reg[NbDid] Mask */

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coreboot February 2011