February 2011 - coreboot - mail.coreboot.org

[commit] r6393 - trunk/src/cpu/amd/model_10xxx
by repository service Feb. 28, 2011

Feb. 28, 2011

Author: mjones Date: Mon Feb 28 00:58:34 2011 New Revision: 6393 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6393 Log: Prepare for next patches (Improving BKDG implementation of P-states, CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode). No change of behaviour intended. Refactor FAM10 fidvid . Factor out the decision whether to update northbridge frequency and voltage because there was the same code in 3 places and so we can later modify it in one place. Signed-off-by: Xavi Drudis Ferran <xdrudis(a)tinet.cat> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 00:56:00 2011 (r6392) +++ trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 00:58:34 2011 (r6393) @@ -280,6 +280,7 @@ pci_write_config32(dev, 0x84, dword); dword = 0xE600A681; pci_write_config32(dev, 0x80, dword); + } static void prep_fid_change(void) @@ -503,18 +504,33 @@ } } +static u32 needs_NB_COF_VID_update(void) +{ + u8 nb_cof_vid_update; + u8 nodes; + u8 i; + + /* If any node has nb_cof_vid_update set all nodes need an update. */ + nodes = get_nodes(); + nb_cof_vid_update = 0; + for (i = 0; i < nodes; i++) { + if (pci_read_config32(NODE_PCI(i, 3), 0x1FC) & 1) { + nb_cof_vid_update = 1; + break; + } + } + return nb_cof_vid_update; +} static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid) { device_t dev; u32 vid_max; u32 fid_max; - u8 nb_cof_vid_update; + u8 nb_cof_vid_update = needs_NB_COF_VID_update(); u8 pvimode; u32 reg1fc; u32 send; - u8 nodes; - u8 i; printk(BIOS_DEBUG, "FIDVID on AP: %02x\n", apicid); @@ -522,15 +538,7 @@ * for SVI and Single-Plane PVI Systems. */ - /* If any node has nb_cof_vid_update set all nodes need an update. */ - nodes = get_nodes(); - nb_cof_vid_update = 0; - for (i = 0; i < nodes; i++) { - if (pci_read_config32(NODE_PCI(i, 3), 0x1FC) & 1) { - nb_cof_vid_update = 1; - break; - } - } + dev = NODE_PCI(nodeid, 3); pvimode = (pci_read_config32(dev, 0xA0) >> 8) & 1; @@ -710,23 +718,13 @@ u32 reg1fc; u32 dtemp; u32 nbvid; - u8 nb_cof_vid_update; - u8 nodes; + u8 nb_cof_vid_update = needs_NB_COF_VID_update(); u8 NbVidUpdateAll; - u8 i; u8 pvimode; /* After warm reset finish the fid/vid setup for all cores. */ /* If any node has nb_cof_vid_update set all nodes need an update. */ - nodes = get_nodes(); - nb_cof_vid_update = 0; - for (i = 0; i < nodes; i++) { - if (pci_read_config32(NODE_PCI(i, 3), 0x1FC) & 1) { - nb_cof_vid_update = 1; - break; - } - } dev = NODE_PCI(nodeid, 3); pvimode = (pci_read_config32(dev, 0xA0) >> 8) & 1; @@ -788,7 +786,7 @@ device_t dev; u32 vid_max; u32 fid_max=0; - u8 nb_cof_vid_update; + u8 nb_cof_vid_update = needs_NB_COF_VID_update(); u32 reg1fc; u8 pvimode; @@ -801,15 +799,6 @@ * for SVI and Single-Plane PVI Systems. */ - /* If any node has nb_cof_vid_update set all nodes need an update. */ - nb_cof_vid_update = 0; - for (i = 0; i < nodes; i++) { - if (pci_read_config32(NODE_PCI(i, 3), 0x1FC) & 1) { - nb_cof_vid_update = 1; - break; - } - } - dev = NODE_PCI(0, 3); pvimode = (pci_read_config32(dev, 0xA0) >> 8) & 1; reg1fc = pci_read_config32(dev, 0x1FC);

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[commit] r6392 - trunk/src/cpu/amd/model_10xxx
by repository service Feb. 28, 2011

Feb. 28, 2011

Author: mjones Date: Mon Feb 28 00:56:00 2011 New Revision: 6392 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6392 Log: Prepare for next patches (Improving BKDG implementation of P-states, CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode). No change of behaviour intended. Refactor FAM10 fidvid. Factor out a little common code. Also, our earlier config_clk_power_ctrl_reg0 was still too long and it'd get longer with forthcoming patches. We now take apart F3xD4[PowerStepUp,PowerStepDown] to its own function. Signed-off-by: Xavi Drudis Ferran <xdrudis(a)tinet.cat> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 00:53:11 2011 (r6391) +++ trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 00:56:00 2011 (r6392) @@ -179,32 +179,16 @@ pci_write_config32(dev, 0xd8, dtemp); } -static void config_clk_power_ctrl_reg0(int node) { - u32 dword; - device_t dev = NODE_PCI(node, 3); - /* Program fields in Clock Power/Control register0 (F3xD4) */ - - /* set F3xD4 Clock Power/Timing Control 0 Register - * NbClkDidApplyAll=1b - * NbClkDid=100b - * PowerStepUp= "platform dependent" - * PowerStepDown= "platform dependent" - * LinkPllLink=01b - * ClkRampHystSel=HW default - */ +static u32 power_up_down(int node) { + u32 dword=0; /* check platform type */ if (!(get_platform_type() & AMD_PTYPE_SVR)) { /* For non-server platform * PowerStepUp=01000b - 50nS * PowerStepDown=01000b - 50ns */ - dword = pci_read_config32(dev, 0xd4); - dword &= CPTC0_MASK; - dword |= NB_CLKDID_ALL | NB_CLKDID | PW_STP_UP50 | PW_STP_DN50 | LNK_PLL_LOCK; /* per BKDG */ - pci_write_config32(dev, 0xd4, dword); + dword |= PW_STP_UP50 | PW_STP_DN50 ; } else { - dword = pci_read_config32(dev, 0xd4); - dword &= CPTC0_MASK; /* get number of cores for PowerStepUp & PowerStepDown in server 1 core - 400nS - 0000b 2 cores - 200nS - 0010b @@ -226,9 +210,31 @@ dword |= PW_STP_UP100 | PW_STP_DN100; break; } - dword |= NB_CLKDID_ALL | NB_CLKDID | LNK_PLL_LOCK; - pci_write_config32(dev, 0xd4, dword); } + return dword; +} + +static void config_clk_power_ctrl_reg0(int node) { + device_t dev = NODE_PCI(node, 3); + + + /* Program fields in Clock Power/Control register0 (F3xD4) */ + + /* set F3xD4 Clock Power/Timing Control 0 Register + * NbClkDidApplyAll=1b + * NbClkDid=100b + * PowerStepUp= "platform dependent" + * PowerStepDown= "platform dependent" + * LinkPllLink=01b + * ClkRampHystSel=HW default + */ + u32 dword= pci_read_config32(dev, 0xd4); + dword &= CPTC0_MASK; + dword |= NB_CLKDID_ALL | NB_CLKDID | LNK_PLL_LOCK; /* per BKDG */ + dword |= power_up_down(node); + + pci_write_config32(dev, 0xd4, dword); + } static void config_power_ctrl_misc_reg(device_t dev) {

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[commit] r6391 - trunk/src/cpu/amd/model_10xxx
by repository service Feb. 28, 2011

Feb. 28, 2011

Author: mjones Date: Mon Feb 28 00:53:11 2011 New Revision: 6391 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6391 Log: Prepare for next patches (Improving BKDG implementation of P-states, CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode). No change of behaviour intended. Refactor FAM10 fidvid . prep_fid_change was already long and it'd get longer with forthcoming patches. We now take apart F3x[84:80], ACPI Power State Control Registers, to its own function. Signed-off-by: Xavi Drudis Ferran <xdrudis(a)tinet.cat> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 00:50:30 2011 (r6390) +++ trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 00:53:11 2011 (r6391) @@ -257,7 +257,6 @@ pci_write_config32(dev, 0xD8, dword); } } - static void config_nb_syn_ptr_adj(device_t dev) { /* Note the following settings are additional from the ported @@ -269,6 +268,14 @@ } +static void config_acpi_pwr_state_ctrl_regs(device_t dev) { + /* Rev B settings - FIXME: support other revs. */ + u32 dword = 0xA0E641E6; + pci_write_config32(dev, 0x84, dword); + dword = 0xE600A681; + pci_write_config32(dev, 0x80, dword); +} + static void prep_fid_change(void) { u32 dword; @@ -295,12 +302,7 @@ config_nb_syn_ptr_adj(dev); - /* Rev B settings - FIXME: support other revs. */ - dword = 0xA0E641E6; - pci_write_config32(dev, 0x84, dword); - - dword = 0xE600A681; - pci_write_config32(dev, 0x80, dword); + config_acpi_pwr_state_ctrl_regs(dev); dword = pci_read_config32(dev, 0x80); printk(BIOS_DEBUG, " F3x80: %08x \n", dword);

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[commit] r6390 - trunk/src/cpu/amd/model_10xxx
by repository service Feb. 28, 2011

Feb. 28, 2011

Author: mjones Date: Mon Feb 28 00:50:30 2011 New Revision: 6390 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6390 Log: Prepare for next patches (Improving BKDG implementation of P-states, CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode). No change of behaviour intended. Refactor FAM10 fidvid . prep_fid_change was already long and it'd get longer with forthcoming patches. We now take apart F3xDC[NbsynPtrAdj], Northbridge/core synchronization FIFO pointer adjust, to its own function. Signed-off-by: Xavi Drudis Ferran <xdrudis(a)tinet.cat> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 00:47:57 2011 (r6389) +++ trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 00:50:30 2011 (r6390) @@ -258,6 +258,17 @@ } } + +static void config_nb_syn_ptr_adj(device_t dev) { + /* Note the following settings are additional from the ported + * function setFidVidRegs() + */ + u32 dword = pci_read_config32(dev, 0xDc); + dword |= 0x5 << 12; /* NbsynPtrAdj set to 0x5 per BKDG (needs reset) */ + pci_write_config32(dev, 0xdc, dword); + +} + static void prep_fid_change(void) { u32 dword; @@ -281,13 +292,8 @@ config_clk_power_ctrl_reg0(i); config_power_ctrl_misc_reg(dev); - - /* Note the following settings are additional from the ported - * function setFidVidRegs() - */ - dword = pci_read_config32(dev, 0xDc); - dword |= 0x5 << 12; /* NbsynPtrAdj set to 0x5 per BKDG (needs reset) */ - pci_write_config32(dev, 0xdc, dword); + + config_nb_syn_ptr_adj(dev); /* Rev B settings - FIXME: support other revs. */ dword = 0xA0E641E6;

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[commit] r6389 - trunk/src/cpu/amd/model_10xxx
by repository service Feb. 28, 2011

Feb. 28, 2011

Author: mjones Date: Mon Feb 28 00:47:57 2011 New Revision: 6389 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6389 Log: Prepare for next patches (Improving BKDG implementation of P-states, CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode). No change of behaviour intended. Refactor FAM10 fidvid . prep_fid_change was already long and it'd get longer with forthcoming patches. We now take apart F3xA0, Power Control Misc Register to its own function. Signed-off-by: Xavi Drudis Ferran <xdrudis(a)tinet.cat> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 00:45:34 2011 (r6388) +++ trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 00:47:57 2011 (r6389) @@ -231,9 +231,36 @@ } } +static void config_power_ctrl_misc_reg(device_t dev) { + /* check PVI/SVI */ + u32 dword = pci_read_config32(dev, 0xA0); + if (dword & PVI_MODE) { /* PVI */ + /* set slamVidMode to 0 for PVI */ + dword &= VID_SLAM_OFF | PLLLOCK_OFF; + dword |= PLLLOCK_DFT_L; + pci_write_config32(dev, 0xA0, dword); + } else { /* SVI */ + /* set slamVidMode to 1 for SVI */ + dword &= PLLLOCK_OFF; + dword |= PLLLOCK_DFT_L | VID_SLAM_ON; + pci_write_config32(dev, 0xA0, dword); + + u32 dtemp = dword; + + /* Program F3xD8[PwrPlanes] according F3xA0[DulaVdd] */ + dword = pci_read_config32(dev, 0xD8); + + if (dtemp & DUAL_VDD_BIT) + dword |= PWR_PLN_ON; + else + dword &= PWR_PLN_OFF; + pci_write_config32(dev, 0xD8, dword); + } +} + static void prep_fid_change(void) { - u32 dword, dtemp; + u32 dword; u32 nodes; device_t dev; int i; @@ -253,31 +280,8 @@ config_clk_power_ctrl_reg0(i); - /* check PVI/SVI */ - dword = pci_read_config32(dev, 0xA0); - if (dword & PVI_MODE) { /* PVI */ - /* set slamVidMode to 0 for PVI */ - dword &= VID_SLAM_OFF | PLLLOCK_OFF; - dword |= PLLLOCK_DFT_L; - pci_write_config32(dev, 0xA0, dword); - } else { /* SVI */ - /* set slamVidMode to 1 for SVI */ - dword &= PLLLOCK_OFF; - dword |= PLLLOCK_DFT_L | VID_SLAM_ON; - pci_write_config32(dev, 0xA0, dword); - - dtemp = dword; - - /* Program F3xD8[PwrPlanes] according F3xA0[DulaVdd] */ - dword = pci_read_config32(dev, 0xD8); - - if (dtemp & DUAL_VDD_BIT) - dword |= PWR_PLN_ON; - else - dword &= PWR_PLN_OFF; - pci_write_config32(dev, 0xD8, dword); - } - + config_power_ctrl_misc_reg(dev); + /* Note the following settings are additional from the ported * function setFidVidRegs() */

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[commit] r6388 - trunk/src/cpu/amd/model_10xxx
by repository service Feb. 28, 2011

Feb. 28, 2011

Author: mjones Date: Mon Feb 28 00:45:34 2011 New Revision: 6388 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6388 Log: Prepare for next patches (Improving BKDG implementation of P-states, CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode). No change of behaviour intended. Refactor FAM10 fidvid . prep_fid_change was already long and it'd get longer with forthcoming patches. We now take apart F3xD4, Clock Power/Timing Control 0 to its own function. Signed-off-by: Xavi Drudis Ferran <xdrudis(a)tinet.cat> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 00:42:58 2011 (r6387) +++ trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 00:45:34 2011 (r6388) @@ -179,6 +179,58 @@ pci_write_config32(dev, 0xd8, dtemp); } +static void config_clk_power_ctrl_reg0(int node) { + u32 dword; + device_t dev = NODE_PCI(node, 3); + /* Program fields in Clock Power/Control register0 (F3xD4) */ + + /* set F3xD4 Clock Power/Timing Control 0 Register + * NbClkDidApplyAll=1b + * NbClkDid=100b + * PowerStepUp= "platform dependent" + * PowerStepDown= "platform dependent" + * LinkPllLink=01b + * ClkRampHystSel=HW default + */ + /* check platform type */ + if (!(get_platform_type() & AMD_PTYPE_SVR)) { + /* For non-server platform + * PowerStepUp=01000b - 50nS + * PowerStepDown=01000b - 50ns + */ + dword = pci_read_config32(dev, 0xd4); + dword &= CPTC0_MASK; + dword |= NB_CLKDID_ALL | NB_CLKDID | PW_STP_UP50 | PW_STP_DN50 | LNK_PLL_LOCK; /* per BKDG */ + pci_write_config32(dev, 0xd4, dword); + } else { + dword = pci_read_config32(dev, 0xd4); + dword &= CPTC0_MASK; + /* get number of cores for PowerStepUp & PowerStepDown in server + 1 core - 400nS - 0000b + 2 cores - 200nS - 0010b + 3 cores - 133nS -> 100nS - 0011b + 4 cores - 100nS - 0011b + */ + switch (get_core_num_in_bsp(node)) { + case 0: + dword |= PW_STP_UP400 | PW_STP_DN400; + break; + case 1: + case 2: + dword |= PW_STP_UP200 | PW_STP_DN200; + break; + case 3: + dword |= PW_STP_UP100 | PW_STP_DN100; + break; + default: + dword |= PW_STP_UP100 | PW_STP_DN100; + break; + } + dword |= NB_CLKDID_ALL | NB_CLKDID | LNK_PLL_LOCK; + pci_write_config32(dev, 0xd4, dword); + } +} + static void prep_fid_change(void) { u32 dword, dtemp; @@ -199,52 +251,7 @@ /* Figure out the value for VsSlamTime and program it */ recalculateVsSlamTimeSettingOnCorePre(dev); - /* Program fields in Clock Power/Control register0 (F3xD4) */ - /* set F3xD4 Clock Power/Timing Control 0 Register - * NbClkDidApplyAll=1b - * NbClkDid=100b - * PowerStepUp= "platform dependent" - * PowerStepDown= "platform dependent" - * LinkPllLink=01b - * ClkRampHystSel=HW default - */ - /* check platform type */ - if (!(get_platform_type() & AMD_PTYPE_SVR)) { - /* For non-server platform - * PowerStepUp=01000b - 50nS - * PowerStepDown=01000b - 50ns - */ - dword = pci_read_config32(dev, 0xd4); - dword &= CPTC0_MASK; - dword |= NB_CLKDID_ALL | NB_CLKDID | PW_STP_UP50 | PW_STP_DN50 | LNK_PLL_LOCK; /* per BKDG */ - pci_write_config32(dev, 0xd4, dword); - } else { - dword = pci_read_config32(dev, 0xd4); - dword &= CPTC0_MASK; - /* get number of cores for PowerStepUp & PowerStepDown in server - 1 core - 400nS - 0000b - 2 cores - 200nS - 0010b - 3 cores - 133nS -> 100nS - 0011b - 4 cores - 100nS - 0011b - */ - switch (get_core_num_in_bsp(i)) { - case 0: - dword |= PW_STP_UP400 | PW_STP_DN400; - break; - case 1: - case 2: - dword |= PW_STP_UP200 | PW_STP_DN200; - break; - case 3: - dword |= PW_STP_UP100 | PW_STP_DN100; - break; - default: - dword |= PW_STP_UP100 | PW_STP_DN100; - break; - } - dword |= NB_CLKDID_ALL | NB_CLKDID | LNK_PLL_LOCK; - pci_write_config32(dev, 0xd4, dword); - } + config_clk_power_ctrl_reg0(i); /* check PVI/SVI */ dword = pci_read_config32(dev, 0xA0);

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[commit] r6387 - trunk/src/cpu/amd/model_10xxx
by repository service Feb. 28, 2011

Feb. 28, 2011

Author: mjones Date: Mon Feb 28 00:42:58 2011 New Revision: 6387 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6387 Log: Prepare for next patches (Improving BKDG implementation of P-states, CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode). No change of behaviour intended. Refactor FAM10 fidvid . prep_fid_change was already long and it'd get longer with forthcoming patches. We now take apart VSRamp in step b of 2.4.1.7 BKDG to its own function. Signed-off-by: Xavi Drudis Ferran <xdrudis(a)tinet.cat> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/fidvid.c Sun Feb 27 03:48:41 2011 (r6386) +++ trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 00:42:58 2011 (r6387) @@ -66,6 +66,21 @@ } } +static void setVSRamp(device_t dev) { + /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSRampTime] + * If this field accepts 8 values between 10 and 500 us why + * does page 324 say "BIOS should set this field to 001b." + * (20 us) ? + * Shouldn't it depend on the voltage regulators, mainboard + * or something ? + */ + u32 dword; + dword = pci_read_config32(dev, 0xd8); + dword &= VSRAMP_MASK; + dword |= VSRAMP_VALUE; + pci_write_config32(dev, 0xd8, dword); +} + static void recalculateVsSlamTimeSettingOnCorePre(device_t dev) { u8 pviModeFlag; @@ -179,11 +194,8 @@ printk(BIOS_DEBUG, "Prep FID/VID Node:%02x \n", i); dev = NODE_PCI(i, 3); - dword = pci_read_config32(dev, 0xd8); - dword &= VSRAMP_MASK; - dword |= VSRAMP_VALUE; - pci_write_config32(dev, 0xd8, dword); - + setVSRamp(dev); + /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSSlamTime] */ /* Figure out the value for VsSlamTime and program it */ recalculateVsSlamTimeSettingOnCorePre(dev);

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Via Epia-LN is in "supported list" ...but not in menuconfig
by mutt Feb. 28, 2011

Feb. 28, 2011

Hi, i would build coreboot for my motherboard VIA EPIA LN, listed in the supported board (http://www.coreboot.org/Supported_Motherboards) with a dedicated page: http://www.coreboot.org/VIA_EPIA-LN I'm following the HOWTO, always in wiki, but in menuconfig there is not my motherboard. This is very similar for SB a NB to EPIA-CN, listed in menuconfig...can i select this one? thanks for help!

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[commit] r6375 - trunk
by repository service Feb. 27, 2011

Feb. 27, 2011

Author: oxygene Date: Tue Feb 22 15:35:05 2011 New Revision: 6375 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6375 Log: Move coreboot specific rules and setup to toplevel Makefile.inc KERNELVERSION issue found by Stefan is fixed. Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Added: trunk/Makefile.inc Modified: trunk/Makefile Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Mon Feb 21 10:39:17 2011 (r6374) +++ trunk/Makefile Tue Feb 22 15:35:05 2011 (r6375) @@ -4,6 +4,7 @@ ## Copyright (C) 2008 Advanced Micro Devices, Inc. ## Copyright (C) 2008 Uwe Hermann <uwe(a)hermann-uwe.de> ## Copyright (C) 2009-2010 coresystems GmbH +## Copyright (C) 2011 secunet Security Networks AG ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -40,7 +41,6 @@ export objk := $(objutil)/kconfig -export KERNELVERSION := 4.0 export KCONFIG_AUTOHEADER := $(obj)/config.h export KCONFIG_AUTOCONFIG := $(obj)/auto.conf @@ -62,7 +62,6 @@ endif CPP:= $(CC) -x assembler-with-cpp -DASSEMBLY -E -ROMCC:= $(objutil)/romcc/romcc HOSTCC = gcc HOSTCXX = g++ HOSTCFLAGS := -I$(srck) -I$(objk) -g @@ -72,6 +71,13 @@ DOXYGEN := doxygen DOXYGEN_OUTPUT_DIR := doxygen +all: real-all + +# This include must come _before_ he pattern rules below! +# Order _does_ matter for pattern rules. +include Makefile.inc +include util/kconfig/Makefile + # Three cases where we don't need fully populated $(obj) lists: # 1. when no .config exists # 2. when make config (in any flavour) is run @@ -87,7 +93,7 @@ endif ifeq ($(NOCOMPILE),1) -all: config +real-all: config else @@ -114,23 +120,6 @@ strip_quotes = $(subst ",,$(subst \",,$(1))) -ARCHDIR-$(CONFIG_ARCH_X86) := x86 -ARCHDIR-$(CONFIG_ARCH_POWERPC) := ppc - -MAINBOARDDIR=$(call strip_quotes,$(CONFIG_MAINBOARD_DIR)) -export MAINBOARDDIR - -PLATFORM-y += src/arch/$(ARCHDIR-y) src/cpu src/mainboard/$(MAINBOARDDIR) -TARGETS-y := - -BUILD-y := src/lib src/boot src/console src/devices src/ec src/southbridge src/northbridge src/superio src/drivers -BUILD-y += util/cbfstool util/sconfig -BUILD-$(CONFIG_ARCH_X86) += src/pc80 - -ifneq ($(CONFIG_LOCALVERSION),"") -COREBOOT_EXTRA_VERSION := -$(call strip_quotes,$(CONFIG_LOCALVERSION)) -endif - # The primary target needs to be here before we include the # other files @@ -142,7 +131,7 @@ ifneq ($(CONFIG_SCANBUILD_REPORT_LOCATION),) CONFIG_SCANBUILD_REPORT_LOCATION:=-o $(CONFIG_SCANBUILD_REPORT_LOCATION) endif -all: +real-all: echo '#!/bin/sh' > .ccwrap echo 'CC="$(CC)"' >> .ccwrap echo 'if [ "$$1" = "--hostcc" ]; then shift; CC="$(HOSTCC)"; fi' >> .ccwrap @@ -151,7 +140,7 @@ chmod +x .ccwrap scan-build $(CONFIG_SCANBUILD_REPORT_LOCATION) -analyze-headers --use-cc=$(top)/.ccwrap --use-c++=$(top)/.ccwrap $(MAKE) INNER_SCANBUILD=y else -all: $(obj)/config.h coreboot +real-all: real-target endif # must come rather early @@ -160,29 +149,6 @@ $(obj)/config.h: $(MAKE) oldconfig -####################################################################### -# Build the tools - -CBFSTOOL:=$(obj)/cbfstool - -$(CBFSTOOL): $(objutil)/cbfstool/cbfstool - cp $< $@ - -# needed objects that every mainboard uses -# Creation of these is architecture and mainboard independent -$(obj)/mainboard/$(MAINBOARDDIR)/static.c: $(src)/mainboard/$(MAINBOARDDIR)/devicetree.cb $(objutil)/sconfig/sconfig - @printf " SCONFIG $(subst $(src)/,,$(<))\n" - mkdir -p $(obj)/mainboard/$(MAINBOARDDIR) - $(objutil)/sconfig/sconfig $(MAINBOARDDIR) $(obj)/mainboard/$(MAINBOARDDIR) - -$(objutil)/%.o: $(objutil)/%.c - @printf " HOSTCC $(subst $(objutil)/,,$(@))\n" - $(HOSTCC) -MMD -I$(subst $(objutil)/,util/,$(dir $<)) -I$(dir $<) $(HOSTCFLAGS) -c -o $@ $< - -$(obj)/%.ramstage.o: $(obj)/%.c $(obj)/config.h - @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD $(CFLAGS) -c -o $@ $< - # Add a new class of source/object files to the build system add-class= \ $(eval $(1)-srcs:=) \ @@ -198,28 +164,6 @@ $(eval $(1):=) \ $(eval special-classes+=$(1)) -$(call add-class,ramstage) -$(call add-class,romstage) -$(call add-class,driver) -$(call add-class,smm) -ramstage-S-ccopts:=-DASSEMBLY -romstage-c-ccopts:=-D__PRE_RAM__ -romstage-S-ccopts:=-DASSEMBLY -D__PRE_RAM__ -driver-S-ccopts:=-DASSEMBLY - - -$(call add-special-class,cbfs-files) -cbfs-files-handler= \ - $(if $(wildcard $(1)$($(2)-file)), \ - $(eval tmp-cbfs-file:= $(wildcard $(1)$($(2)-file))), \ - $(eval tmp-cbfs-file:= $($(2)-file))) \ - $(eval cbfs-files += $(tmp-cbfs-file)|$(2)|$($(2)-type)|$($(2)-position)) \ - $(eval $(2)-name:=) \ - $(eval $(2)-type:=) \ - $(eval $(2)-position:=) - -ramstage-srcs+=$(obj)/mainboard/$(MAINBOARDDIR)/static.c - # Clean -y variables, include Makefile.inc # Add paths to files in X-y to X-srcs # Add subdirs-y to subdirs @@ -245,7 +189,7 @@ $(if $(subdirs),$(eval $(call evaluate_subdirs))) # collect all object files eligible for building -subdirs:=$(PLATFORM-y) $(BUILD-y) +subdirs:=. $(eval $(call evaluate_subdirs)) src-to-obj=$(addsuffix .$(1).o, $(basename $(patsubst src/%, $(obj)/%, $($(1)-srcs)))) @@ -255,20 +199,9 @@ allobjs:=$(foreach var, $(addsuffix -objs,$(classes)), $($(var))) alldirs:=$(sort $(abspath $(dir $(allobjs)))) -define ramstage-objs_asl_template -$(obj)/$(1).ramstage.o: src/$(1).asl - @printf " IASL $$(subst $(top)/,,$$(@))\n" - $(CPP) -D__ACPI__ -P -include $(abspath $(obj)/config.h) -I$(src) -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $$(basename $$(a)).asl - iasl -p $$(obj)/$(1) -tc $$(basename $$(a)).asl - mv $$(obj)/$(1).hex $$(basename $$(a)).c - $(CC) $$(CFLAGS) $$(if $$(subst dsdt,,$$(basename $$(notdir $(1)))), -DAmlCode=AmlCode_$$(basename $$(notdir $(1)))) -c -o $$@ $$(basename $$(a)).c - # keep %.o: %.c rule from catching the temporary .c file after a make clean - mv $$(basename $$(a)).c $$(basename $$(a)).hex -endef - # macro to define template macros that are used by use_template macro define create_cc_template -# $1 obj class (ramstage, romstage, driver, smm) +# $1 obj class # $2 source suffix (c, S) # $3 additional compiler flags ifn$(EMPTY)def $(1)-objs_$(2)_template @@ -288,75 +221,20 @@ foreach-src=$(foreach file,$($(1)-srcs),$(eval $(call $(1)-objs_$(subst .,,$(suffix $(file)))_template,$(subst src/,,$(basename $(file)))))) $(eval $(foreach class,$(classes),$(call foreach-src,$(class)))) -DEPENDENCIES = $(ramstage-objs:.o=.d) $(romstage-objs:.o=.d) $(driver-objs:.o=.d) $(smm-objs:.o=.d) +DEPENDENCIES = $(allobjs:.o=.d) -include $(DEPENDENCIES) printall: - @echo ramstage-objs:=$(ramstage-objs) - @echo romstage-objs:=$(romstage-objs) - @echo driver-objs:=$(driver-objs) - @echo smm-objs:=$(smm-objs) + @$(foreach class,$(classes),echo $(class)-objs:=$($(class)-objs); ) @echo alldirs:=$(alldirs) @echo allsrcs=$(allsrcs) @echo DEPENDENCIES=$(DEPENDENCIES) @echo LIBGCC_FILE_NAME=$(LIBGCC_FILE_NAME) - @echo cbfs-files:='$(cbfs-files)' - -printcrt0s: - @echo crt0s=$(crt0s) - @echo ldscripts=$(ldscripts) - -OBJS := $(patsubst %,$(obj)/%,$(TARGETS-y)) -INCLUDES := -Isrc -Isrc/include -I$(obj) -Isrc/arch/$(ARCHDIR-y)/include -INCLUDES += -Isrc/devices/oprom/include -# abspath is a workaround for romcc -INCLUDES += -include $(abspath $(obj)/config.h) - -CFLAGS = $(INCLUDES) -Os -pipe -g -CFLAGS += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -CFLAGS += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -CFLAGS += -Wstrict-aliasing -Wshadow -ifeq ($(CONFIG_WARNINGS_ARE_ERRORS),y) -CFLAGS += -Werror -endif -ifneq ($(CONFIG_AMD_AGESA),y) -CFLAGS += -nostdinc -endif -CFLAGS += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer - -CBFS_COMPRESS_FLAG:=l -CBFS_PAYLOAD_COMPRESS_FLAG:= -CBFS_PAYLOAD_COMPRESS_NAME:=none -ifeq ($(CONFIG_COMPRESSED_PAYLOAD_LZMA),y) -CBFS_PAYLOAD_COMPRESS_FLAG:=l -CBFS_PAYLOAD_COMPRESS_NAME:=LZMA -endif - -coreboot: $(obj)/coreboot.rom + @$(foreach class,$(special-classes),echo $(class):='$($(class))'; ) endif -$(shell mkdir -p $(obj) $(objutil)/kconfig/lxdialog $(objutil)/cbfstool $(objutil)/romcc $(objutil)/options $(alldirs)) - -$(obj)/build.h: .xcompile - @printf " GEN build.h\n" - rm -f $(obj)/build.h - printf "/* build system definitions (autogenerated) */\n" > $(obj)/build.ht - printf "#ifndef __BUILD_H\n" >> $(obj)/build.ht - printf "#define __BUILD_H\n\n" >> $(obj)/build.ht - printf "#define COREBOOT_VERSION \"$(KERNELVERSION)-r$(shell if [ -d $(top)/.svn -a -f "`which svnversion`" ]; then svnversion $(top); else if [ -d $(top)/.git -a -f "`which git`" ]; then git --git-dir=/$(top)/.git log|grep git-svn-id|cut -f 2 -d@|cut -f 1 -d' '|sort -g|tail -1; fi; fi)\"\n" >> $(obj)/build.ht - printf "#define COREBOOT_EXTRA_VERSION \"$(COREBOOT_EXTRA_VERSION)\"\n" >> $(obj)/build.ht - printf "#define COREBOOT_BUILD \"`LANG= date`\"\n" >> $(obj)/build.ht - printf "\n" >> $(obj)/build.ht - printf "#define COREBOOT_COMPILER \"$(shell LANG= $(CC) --version | head -n1)\"\n" >> $(obj)/build.ht - printf "#define COREBOOT_ASSEMBLER \"$(shell LANG= $(AS) --version | head -n1)\"\n" >> $(obj)/build.ht - printf "#define COREBOOT_LINKER \"$(shell LANG= $(LD) --version | head -n1)\"\n" >> $(obj)/build.ht - printf "#define COREBOOT_COMPILE_TIME \"`LANG= date +%T`\"\n" >> $(obj)/build.ht - printf "#define COREBOOT_COMPILE_BY \"$(subst \,@,$(shell PATH=$$PATH:/usr/ucb whoami))\"\n" >> $(obj)/build.ht - printf "#define COREBOOT_COMPILE_HOST \"$(shell hostname -s 2>/dev/null)\"\n" >> $(obj)/build.ht - printf "#define COREBOOT_COMPILE_DOMAIN \"$(shell test `uname -s` = "Linux" && dnsdomainname || domainname 2>/dev/null)\"\n" >> $(obj)/build.ht - printf "#endif\n" >> $(obj)/build.ht - mv $(obj)/build.ht $(obj)/build.h +$(shell mkdir -p $(obj) $(objutil)/kconfig/lxdialog $(additional-dirs) $(alldirs)) cscope: cscope -bR @@ -369,25 +247,13 @@ doxygen-clean: rm -rf $(DOXYGEN_OUTPUT_DIR) -clean-for-update: doxygen-clean - rm -f $(ramstage-objs) $(romstage-objs) $(driver-objs) $(smm-objs) .xcompile +clean-for-update: doxygen-clean clean-for-update-target + rm -f $(allobjs) .xcompile rm -f $(DEPENDENCIES) - rm -f $(obj)/coreboot_ram* $(obj)/coreboot.romstage $(obj)/coreboot.pre* $(obj)/coreboot.bootblock $(obj)/coreboot.a - rm -rf $(obj)/bootblock* $(obj)/romstage* $(obj)/location.* - rm -f $(obj)/option_table.* $(obj)/crt0.S $(obj)/ldscript - rm -f $(obj)/mainboard/$(MAINBOARDDIR)/static.c $(obj)/mainboard/$(MAINBOARDDIR)/config.py $(obj)/mainboard/$(MAINBOARDDIR)/static.dot - rm -f $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s $(obj)/mainboard/$(MAINBOARDDIR)/crt0.disasm - rm -f $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc - rm -f $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.* $(obj)/mainboard/$(MAINBOARDDIR)/dsdt.* - rm -f $(obj)/cpu/x86/smm/smm_bin.c $(obj)/cpu/x86/smm/smm.* $(obj)/cpu/x86/smm/smm rmdir -p $(alldirs) 2>/dev/null >/dev/null || true - $(MAKE) -C payloads/external/SeaBIOS -f Makefile.inc clean - -clean: clean-for-update - rm -f $(obj)/coreboot* .ccwrap -clean-abuild: - rm -rf coreboot-builds +clean: clean-for-update clean-target + rm -f .ccwrap clean-cscope: rm -f cscope.out @@ -396,50 +262,4 @@ rm -rf $(obj) rm -f .config .config.old ..config.tmp .kconfig.d .tmpconfig* .ccwrap .xcompile -update: - dongle.py -c /dev/term/1 $(obj)/coreboot.rom EOF - -lint: - FAILED=0; LINTLOG=`mktemp`; \ - for script in util/lint/lint-*; do \ - echo; echo `basename $$script`; \ - grep "^# DESCR:" $$script | sed "s,.*DESCR: *,," ; \ - echo ========; \ - $$script > $$LINTLOG; \ - if [ `wc -l $$LINTLOG | cut -d' ' -f1` -eq 0 ]; then \ - printf "success\n\n"; \ - else \ - echo test failed: ; \ - cat $$LINTLOG; \ - rm -f $$LINTLOG; \ - FAILED=$$(( $$FAILED + 1 )); \ - fi; \ - echo ========; \ - done; \ - test $$FAILED -eq 0 || { echo "ERROR: $$FAILED test(s) failed." && exit 1; }; \ - rm -f $$LINTLOG - -# This include must come _before_ the pattern rules below! -# Order _does_ matter for pattern rules. -include util/kconfig/Makefile - -$(obj)/ldoptions: $(obj)/config.h - awk '/^#define ([^"])* ([^"])*$$/ {gsub("\\r","",$$3); print $$2 " = " $$3 ";";}' $< > $@ - -_WINCHECK=$(shell uname -o 2> /dev/null) -STACK= -ifeq ($(_WINCHECK),Msys) - STACK=-Wl,--stack,16384000 -endif -ifeq ($(_WINCHECK),Cygwin) - STACK=-Wl,--stack,16384000 -endif - -$(objutil)/romcc/romcc: $(top)/util/romcc/romcc.c - @printf " HOSTCC $(subst $(obj)/,,$(@)) (this may take a while)\n" - @# Note: Adding -O2 here might cause problems. For details see: - @# http://www.coreboot.org/pipermail/coreboot/2010-February/055825.html - $(HOSTCC) -g $(STACK) -Wall -o $@ $< - -.PHONY: $(PHONY) clean clean-abuild clean-cscope cscope distclean doxygen doxy coreboot .xcompile - +.PHONY: $(PHONY) clean clean-cscope cscope distclean doxygen doxy .xcompile Added: trunk/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/Makefile.inc Tue Feb 22 15:35:05 2011 (r6375) @@ -0,0 +1,227 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 secunet Security Networks AG +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +####################################################################### +# misleadingly named, this is the coreboot version +export KERNELVERSION := 4.0 + +####################################################################### +# Basic component discovery +ARCHDIR-$(CONFIG_ARCH_X86) := x86 +MAINBOARDDIR=$(call strip_quotes,$(CONFIG_MAINBOARD_DIR)) +export MAINBOARDDIR + +####################################################################### +# root rule to resolve if in build mode (ie. configuration exists) +real-target: $(obj)/config.h coreboot +coreboot: $(obj)/coreboot.rom + +####################################################################### +# our phony targets +PHONY+= clean-abuild coreboot + +####################################################################### +# root source directories of coreboot +subdirs-y := src/lib src/boot src/console src/devices src/ec src/southbridge src/northbridge src/superio src/drivers src/cpu +subdirs-y += util/cbfstool util/sconfig +subdirs-y += src/arch/$(ARCHDIR-y) +subdirs-y += src/mainboard/$(MAINBOARDDIR) + +subdirs-$(CONFIG_ARCH_X86) += src/pc80 + +####################################################################### +# Add source classes and their build options +classes-y := ramstage romstage driver smm + +ramstage-S-ccopts:=-DASSEMBLY +romstage-c-ccopts:=-D__PRE_RAM__ +romstage-S-ccopts:=-DASSEMBLY -D__PRE_RAM__ +driver-S-ccopts:=-DASSEMBLY + +####################################################################### +# Add handler to compile ACPI's ASL +define ramstage-objs_asl_template +$(obj)/$(1).ramstage.o: src/$(1).asl + @printf " IASL $$(subst $(top)/,,$$(@))\n" + $(CPP) -D__ACPI__ -P -include $(abspath $(obj)/config.h) -I$(src) -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $$(basename $$(a)).asl + iasl -p $$(obj)/$(1) -tc $$(basename $$(a)).asl + mv $$(obj)/$(1).hex $$(basename $$(a)).c + $(CC) $$(CFLAGS) $$(if $$(subst dsdt,,$$(basename $$(notdir $(1)))), -DAmlCode=AmlCode_$$(basename $$(notdir $(1)))) -c -o $$@ $$(basename $$(a)).c + # keep %.o: %.c rule from catching the temporary .c file after a make clean + mv $$(basename $$(a)).c $$(basename $$(a)).hex +endef + +####################################################################### +# Add handler for arbitrary files in CBFS +$(call add-special-class,cbfs-files) +cbfs-files-handler= \ + $(if $(wildcard $(1)$($(2)-file)), \ + $(eval tmp-cbfs-file:= $(wildcard $(1)$($(2)-file))), \ + $(eval tmp-cbfs-file:= $($(2)-file))) \ + $(eval cbfs-files += $(tmp-cbfs-file)|$(2)|$($(2)-type)|$($(2)-position)) \ + $(eval $(2)-name:=) \ + $(eval $(2)-type:=) \ + $(eval $(2)-position:=) + +####################################################################### +# a variety of flags for our build +CBFS_COMPRESS_FLAG:=l +CBFS_PAYLOAD_COMPRESS_FLAG:= +CBFS_PAYLOAD_COMPRESS_NAME:=none +ifeq ($(CONFIG_COMPRESSED_PAYLOAD_LZMA),y) +CBFS_PAYLOAD_COMPRESS_FLAG:=l +CBFS_PAYLOAD_COMPRESS_NAME:=LZMA +endif + +ifneq ($(CONFIG_LOCALVERSION),"") +COREBOOT_EXTRA_VERSION := -$(call strip_quotes,$(CONFIG_LOCALVERSION)) +endif + +INCLUDES := -Isrc -Isrc/include -I$(obj) -Isrc/arch/$(ARCHDIR-y)/include +INCLUDES += -Isrc/devices/oprom/include +# abspath is a workaround for romcc +INCLUDES += -include $(abspath $(obj)/config.h) + +CFLAGS = $(INCLUDES) -Os -pipe -g +CFLAGS += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes +CFLAGS += -Wwrite-strings -Wredundant-decls -Wno-trigraphs +CFLAGS += -Wstrict-aliasing -Wshadow +ifeq ($(CONFIG_WARNINGS_ARE_ERRORS),y) +CFLAGS += -Werror +endif +ifneq ($(CONFIG_AMD_AGESA),y) +CFLAGS += -nostdinc +endif +CFLAGS += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer + +additional-dirs := $(objutil)/cbfstool $(objutil)/romcc $(objutil)/options + +####################################################################### +# generate build support files +$(obj)/build.h: .xcompile + @printf " GEN build.h\n" + rm -f $(obj)/build.h + printf "/* build system definitions (autogenerated) */\n" > $(obj)/build.ht + printf "#ifndef __BUILD_H\n" >> $(obj)/build.ht + printf "#define __BUILD_H\n\n" >> $(obj)/build.ht + printf "#define COREBOOT_VERSION \"$(KERNELVERSION)-r$(shell if [ -d $(top)/.svn -a -f "`which svnversion`" ]; then svnversion $(top); else if [ -d $(top)/.git -a -f "`which git`" ]; then git --git-dir=/$(top)/.git log|grep git-svn-id|cut -f 2 -d@|cut -f 1 -d' '|sort -g|tail -1; fi; fi)\"\n" >> $(obj)/build.ht + printf "#define COREBOOT_EXTRA_VERSION \"$(COREBOOT_EXTRA_VERSION)\"\n" >> $(obj)/build.ht + printf "#define COREBOOT_BUILD \"`LANG= date`\"\n" >> $(obj)/build.ht + printf "\n" >> $(obj)/build.ht + printf "#define COREBOOT_COMPILER \"$(shell LANG= $(CC) --version | head -n1)\"\n" >> $(obj)/build.ht + printf "#define COREBOOT_ASSEMBLER \"$(shell LANG= $(AS) --version | head -n1)\"\n" >> $(obj)/build.ht + printf "#define COREBOOT_LINKER \"$(shell LANG= $(LD) --version | head -n1)\"\n" >> $(obj)/build.ht + printf "#define COREBOOT_COMPILE_TIME \"`LANG= date +%T`\"\n" >> $(obj)/build.ht + printf "#define COREBOOT_COMPILE_BY \"$(subst \,@,$(shell PATH=$$PATH:/usr/ucb whoami))\"\n" >> $(obj)/build.ht + printf "#define COREBOOT_COMPILE_HOST \"$(shell hostname -s 2>/dev/null)\"\n" >> $(obj)/build.ht + printf "#define COREBOOT_COMPILE_DOMAIN \"$(shell test `uname -s` = "Linux" && dnsdomainname || domainname 2>/dev/null)\"\n" >> $(obj)/build.ht + printf "#endif\n" >> $(obj)/build.ht + mv $(obj)/build.ht $(obj)/build.h + +$(obj)/ldoptions: $(obj)/config.h + awk '/^#define ([^"])* ([^"])*$$/ {gsub("\\r","",$$3); print $$2 " = " $$3 ";";}' $< > $@ + +####################################################################### +# Build the tools +CBFSTOOL:=$(obj)/cbfstool + +$(CBFSTOOL): $(objutil)/cbfstool/cbfstool + cp $< $@ + +_WINCHECK=$(shell uname -o 2> /dev/null) +STACK= +ifeq ($(_WINCHECK),Msys) + STACK=-Wl,--stack,16384000 +endif +ifeq ($(_WINCHECK),Cygwin) + STACK=-Wl,--stack,16384000 +endif + +ROMCC:= $(objutil)/romcc/romcc +$(ROMCC): $(top)/util/romcc/romcc.c + @printf " HOSTCC $(subst $(obj)/,,$(@)) (this may take a while)\n" + @# Note: Adding -O2 here might cause problems. For details see: + @# http://www.coreboot.org/pipermail/coreboot/2010-February/055825.html + $(HOSTCC) -g $(STACK) -Wall -o $@ $< + +####################################################################### +# needed objects that every mainboard uses +# Creation of these is architecture and mainboard independent +$(obj)/mainboard/$(MAINBOARDDIR)/static.c: $(src)/mainboard/$(MAINBOARDDIR)/devicetree.cb $(objutil)/sconfig/sconfig + @printf " SCONFIG $(subst $(src)/,,$(<))\n" + mkdir -p $(obj)/mainboard/$(MAINBOARDDIR) + $(objutil)/sconfig/sconfig $(MAINBOARDDIR) $(obj)/mainboard/$(MAINBOARDDIR) + +ramstage-y+=$(obj)/mainboard/$(MAINBOARDDIR)/static.c + +$(objutil)/%.o: $(objutil)/%.c + @printf " HOSTCC $(subst $(objutil)/,,$(@))\n" + $(HOSTCC) -MMD -I$(subst $(objutil)/,util/,$(dir $<)) -I$(dir $<) $(HOSTCFLAGS) -c -o $@ $< + +$(obj)/%.ramstage.o: $(obj)/%.c $(obj)/config.h + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC) -MMD $(CFLAGS) -c -o $@ $< + +####################################################################### +# Clean up rules +clean-abuild: + rm -rf coreboot-builds + +clean-for-update-target: + rm -f $(obj)/coreboot_ram* $(obj)/coreboot.romstage $(obj)/coreboot.pre* $(obj)/coreboot.bootblock $(obj)/coreboot.a + rm -rf $(obj)/bootblock* $(obj)/romstage* $(obj)/location.* + rm -f $(obj)/option_table.* $(obj)/crt0.S $(obj)/ldscript + rm -f $(obj)/mainboard/$(MAINBOARDDIR)/static.c $(obj)/mainboard/$(MAINBOARDDIR)/config.py $(obj)/mainboard/$(MAINBOARDDIR)/static.dot + rm -f $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s $(obj)/mainboard/$(MAINBOARDDIR)/crt0.disasm + rm -f $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc + rm -f $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.* $(obj)/mainboard/$(MAINBOARDDIR)/dsdt.* + rm -f $(obj)/cpu/x86/smm/smm_bin.c $(obj)/cpu/x86/smm/smm.* $(obj)/cpu/x86/smm/smm + $(MAKE) -C payloads/external/SeaBIOS -f Makefile.inc clean + +clean-target: + rm -f $(obj)/coreboot* + +####################################################################### +# Development utilities +printcrt0s: + @echo crt0s=$(crt0s) + @echo ldscripts=$(ldscripts) + +update: + dongle.py -c /dev/term/1 $(obj)/coreboot.rom EOF + +lint: + FAILED=0; LINTLOG=`mktemp`; \ + for script in util/lint/lint-*; do \ + echo; echo `basename $$script`; \ + grep "^# DESCR:" $$script | sed "s,.*DESCR: *,," ; \ + echo ========; \ + $$script > $$LINTLOG; \ + if [ `wc -l $$LINTLOG | cut -d' ' -f1` -eq 0 ]; then \ + printf "success\n\n"; \ + else \ + echo test failed: ; \ + cat $$LINTLOG; \ + rm -f $$LINTLOG; \ + FAILED=$$(( $$FAILED + 1 )); \ + fi; \ + echo ========; \ + done; \ + test $$FAILED -eq 0 || { echo "ERROR: $$FAILED test(s) failed." && exit 1; }; \ + rm -f $$LINTLOG

3 2

[PROPOSAL] Obsoleting support for non-CAR boards
by Alex G. Feb. 27, 2011

Feb. 27, 2011

We've all been thinking about it, though never said it much. It's obvious that non-CAR boards have become a drag recently: we have to find workarounds the romstage linking system in order to move forward with some ideas. Let's take for example removing .c includes from the source tree. We have an elegant way to specify which files should be compiled and link into romstage by romstage-y: your_favorite_file.c This works fine if we put it in the board's Makefile.inc, yet is ugly, and will break non-CAR boards if we happen to put it in the Makefile.inc of a device that is used by a non-CAR board. I can see non-CAR being a problem for any sub-point that deals with avoiding code duplication, including, but not limited to, removing .c includes, refactoring smbus code, and many of the refactoring ideas having to do with romstage I assume that CPUs and boards which do not support cache-as-ram in the hardware are already old enough to be considered obsolete. Maintaining those is an extra effort that nobody here really seems to be willing too put up with. As a result, I propose we continue with the code refactoring described here http://www.coreboot.org/Infrastructure_Projects without regard to non CAR-capable hardware. If we happen to break the build for such a board, we let it broken, and if it can not be fixed without going back on the new design philosophy, remove it from the tree entirely. Interested individuals, if any, can still checkout older revisions, and we can move forward with a cleaner, more efficient build system Alex Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Acked-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>

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