coreboot February 2011

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[commit] r6383 - trunk/src/mainboard/asrock
by repository service 26 Feb '11

26 Feb '11

Author: sduplichan Date: Sat Feb 26 19:42:04 2011 New Revision: 6383 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6383 Log: Correct error in ASRock E350M1 commit that breaks build for ASRock 939a785gmh. Signed-off-by: Scott Duplichan <scott(a)notabs.org> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/mainboard/asrock/Kconfig Modified: trunk/src/mainboard/asrock/Kconfig ============================================================================== --- trunk/src/mainboard/asrock/Kconfig Sat Feb 26 18:49:49 2011 (r6382) +++ trunk/src/mainboard/asrock/Kconfig Sat Feb 26 19:42:04 2011 (r6383) @@ -28,6 +28,7 @@ endchoice +source "src/mainboard/asrock/939a785gmh/Kconfig" source "src/mainboard/asrock/e350m1/Kconfig" config MAINBOARD_VENDOR

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build service results for r6382
by repository service 26 Feb '11

26 Feb '11

Dear coreboot readers! This is the automatic build system of coreboot. The developer "sduplichan" checked in revision 6382 to the coreboot repository. This caused the following changes: Change Log: Add support for the ASRock E350M1, an AMD family 14h Fusion board. A video option rom must be added for UMA graphics support. It can be extracted from the supplied UEFI BIOS. ASRock E350M1 support is based on the AMD persimmon project. The major differences are SIO model and DIMM SDP addressing. With this coreboot and seabios, the board can boot DOS from a SATA drive and can boot WinPE from a USB flash drive. I was unable to get Windows setup to run. The board has a socketed SPI flash BIOS chip and a serial port header. The SIO is Nuvoton NCT5572D. Using coreboot's existing Winbond w83627hf is a good enough match to get the serial port and keyboard working. Signed-off-by: Scott Duplichan <scott(a)notabs.org> Acked-by: Peter Stuge <peter(a)stuge.se> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build Log: Compilation of asrock:939a785gmh has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6382&device=939a785gmh&ven… If something broke during this checkin please be a pain in sduplichan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r6382 - in trunk/src/mainboard/asrock: . e350m1 e350m1/acpi
by repository service 26 Feb '11

26 Feb '11

Author: sduplichan Date: Sat Feb 26 18:49:49 2011 New Revision: 6382 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6382 Log: Add support for the ASRock E350M1, an AMD family 14h Fusion board. A video option rom must be added for UMA graphics support. It can be extracted from the supplied UEFI BIOS. ASRock E350M1 support is based on the AMD persimmon project. The major differences are SIO model and DIMM SDP addressing. With this coreboot and seabios, the board can boot DOS from a SATA drive and can boot WinPE from a USB flash drive. I was unable to get Windows setup to run. The board has a socketed SPI flash BIOS chip and a serial port header. The SIO is Nuvoton NCT5572D. Using coreboot's existing Winbond w83627hf is a good enough match to get the serial port and keyboard working. Signed-off-by: Scott Duplichan <scott(a)notabs.org> Acked-by: Peter Stuge <peter(a)stuge.se> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Deleted: trunk/src/mainboard/asrock/e350m1/acpi/ssdt2.asl trunk/src/mainboard/asrock/e350m1/acpi/ssdt3.asl trunk/src/mainboard/asrock/e350m1/acpi/ssdt4.asl trunk/src/mainboard/asrock/e350m1/acpi/ssdt5.asl Modified: trunk/src/mainboard/asrock/Kconfig trunk/src/mainboard/asrock/e350m1/Kconfig trunk/src/mainboard/asrock/e350m1/devicetree.cb trunk/src/mainboard/asrock/e350m1/dimmSpd.c trunk/src/mainboard/asrock/e350m1/dsdt.asl trunk/src/mainboard/asrock/e350m1/mainboard.c trunk/src/mainboard/asrock/e350m1/mptable.c trunk/src/mainboard/asrock/e350m1/romstage.c Modified: trunk/src/mainboard/asrock/Kconfig ============================================================================== --- trunk/src/mainboard/asrock/Kconfig Sat Feb 26 14:34:01 2011 (r6381) +++ trunk/src/mainboard/asrock/Kconfig Sat Feb 26 18:49:49 2011 (r6382) @@ -23,10 +23,12 @@ config BOARD_ASROCK_939A785GMH bool "939A785GMH/128M" +config BOARD_ASROCK_E350M1 + bool "E350M1" endchoice -source "src/mainboard/asrock/939a785gmh/Kconfig" +source "src/mainboard/asrock/e350m1/Kconfig" config MAINBOARD_VENDOR string Modified: trunk/src/mainboard/asrock/e350m1/Kconfig ============================================================================== --- trunk/src/mainboard/asrock/e350m1/Kconfig Sat Feb 26 14:34:01 2011 (r6381) +++ trunk/src/mainboard/asrock/e350m1/Kconfig Sat Feb 26 18:49:49 2011 (r6382) @@ -17,7 +17,7 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -if BOARD_AMD_PERSIMMON +if BOARD_ASROCK_E350M1 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -28,7 +28,7 @@ select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14_ROOT_COMPLEX select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800 - select SUPERIO_FINTEK_F81865F + select SUPERIO_WINBOND_W83627HF select BOARD_HAS_FADT select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE @@ -56,7 +56,7 @@ config MAINBOARD_DIR string - default amd/persimmon + default asrock/e350m1 config APIC_ID_OFFSET hex @@ -64,7 +64,7 @@ config MAINBOARD_PART_NUMBER string - default "Persimmon" + default "E350M1" config HW_MEM_HOLE_SIZEK hex @@ -132,16 +132,15 @@ config SIO_PORT hex - default 0x4e + default 0x2e config ONBOARD_VGA_IS_PRIMARY bool default y -#define CONFIG_VGA_BIOS_ID "1002,9804" config VGA_BIOS_ID string - default "1002,9804" + default "1002,9802" config DRIVERS_PS2_KEYBOARD bool @@ -151,5 +150,5 @@ bool default n -endif # BOARD_AMD_PERSIMMON +endif # BOARD_ASROCK_E350M1 Modified: trunk/src/mainboard/asrock/e350m1/devicetree.cb ============================================================================== --- trunk/src/mainboard/asrock/e350m1/devicetree.cb Sat Feb 26 14:34:01 2011 (r6381) +++ trunk/src/mainboard/asrock/e350m1/devicetree.cb Sat Feb 26 18:49:49 2011 (r6382) @@ -55,30 +55,46 @@ device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x439d - chip superio/fintek/f81865f - device pnp 4e.0 off # Floppy + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 4e.3 off end # Parallel Port - device pnp 4e.4 off end # Hardware Monitor - device pnp 4e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 end - device pnp 4e.6 off end # GPIO - device pnp 4e.a off end # PME - device pnp 4e.10 on # COM1 + device pnp 2e.2 on # Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 4e.11 off # COM2 + device pnp 2e.3 off # Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - end # f81865f + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end end #LPC device pci 14.4 on end # PCI 0x4384 device pci 14.5 on end # USB 2 Modified: trunk/src/mainboard/asrock/e350m1/dimmSpd.c ============================================================================== --- trunk/src/mainboard/asrock/e350m1/dimmSpd.c Sat Feb 26 14:34:01 2011 (r6381) +++ trunk/src/mainboard/asrock/e350m1/dimmSpd.c Sat Feb 26 18:49:49 2011 (r6382) @@ -34,8 +34,8 @@ { // socket 0 { - {0xA0, 0xA2}, // channel 0 dimms - {0xA4, 0xA8}, // channel 1 dimms + {0xA0, 0xA4}, // channel 0 dimms + {0x00, 0x00}, // channel 1 dimms }, // socket 1 { Modified: trunk/src/mainboard/asrock/e350m1/dsdt.asl ============================================================================== --- trunk/src/mainboard/asrock/e350m1/dsdt.asl Sat Feb 26 14:34:01 2011 (r6381) +++ trunk/src/mainboard/asrock/e350m1/dsdt.asl Sat Feb 26 18:49:49 2011 (r6382) @@ -22,8 +22,8 @@ "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "AMD ", /* OEMID */ - "PERSIMMO", /* TABLE ID */ + "ASROCK", /* OEMID */ + "E350M1 ", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ Modified: trunk/src/mainboard/asrock/e350m1/mainboard.c ============================================================================== --- trunk/src/mainboard/asrock/e350m1/mainboard.c Sat Feb 26 14:34:01 2011 (r6381) +++ trunk/src/mainboard/asrock/e350m1/mainboard.c Sat Feb 26 18:49:49 2011 (r6382) @@ -49,11 +49,11 @@ uint64_t uma_memory_base, uma_memory_size; /************************************************* -* enable the dedicated function in persimmon board. +* enable the dedicated function in e350m1 board. *************************************************/ -static void persimmon_enable(device_t dev) +static void e350m1_enable(device_t dev) { - printk(BIOS_INFO, "Mainboard Persimmon Enable. dev=0x%p\n", dev); + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); #if (CONFIG_GFXUMA == 1) msr_t msr, msr2; uint32_t sys_mem; @@ -110,6 +110,6 @@ return 0; } struct chip_operations mainboard_ops = { - CHIP_NAME("AMD PERSIMMON Mainboard") - .enable_dev = persimmon_enable, + CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") + .enable_dev = e350m1_enable, }; Modified: trunk/src/mainboard/asrock/e350m1/mptable.c ============================================================================== --- trunk/src/mainboard/asrock/e350m1/mptable.c Sat Feb 26 14:34:01 2011 (r6381) +++ trunk/src/mainboard/asrock/e350m1/mptable.c Sat Feb 26 18:49:49 2011 (r6382) @@ -50,7 +50,7 @@ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LAPIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); + memcpy(mc->mpc_oem, "ASROCK ", 8); smp_write_processors(mc); Modified: trunk/src/mainboard/asrock/e350m1/romstage.c ============================================================================== --- trunk/src/mainboard/asrock/e350m1/romstage.c Sat Feb 26 14:34:01 2011 (r6381) +++ trunk/src/mainboard/asrock/e350m1/romstage.c Sat Feb 26 18:49:49 2011 (r6382) @@ -31,7 +31,7 @@ #include <console/loglevel.h> #include "agesawrapper.h" #include "cpu/x86/bist.h" -#include "superio/fintek/f81865f/f81865f_early_serial.c" +#include "superio/winbond/w83627hf/early_serial.c" #include "cpu/x86/lapic/boot_cpu.c" #include "pc80/i8254.c" #include "pc80/i8259.c" @@ -40,7 +40,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) +#define SERIAL_DEV PNP_DEV(CONFIG_SIO_PORT, W83627HF_SP1) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -52,7 +52,7 @@ sb_poweron_init(); post_code(0x31); - f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); }

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[RFC] [PATCH] Overclocking support for 939a785gmh
by Rudolf Marek 26 Feb '11

26 Feb '11

Hi all, Attached patch adds support for CMOS options which can alter DDR Memory, HT GPU, and Sideport Voltages. Also as a quick hack it can change CPU base frequency from 200MHz to something else. I think this would be nice to show on FOSDEM.It could be extended so not only CPU PLL is programmed but also PCIe etc, also one could adjust the DDR divisors so the memory runs still like on 200MHz (same for HT). Also FID could be changed, but this is not implemented yet. The CPU voltage changes are possible too. It is just a question of writing to SIO... boot_option = Fallback last_boot = Fallback ECC_memory = Disable baud_rate = 115200 debug_level = Info power_on_after_fail = Disable hw_scrubber = Disable nmi = Disable iommu = Enable interleave_chip_selects = Enable multi_core = Enable slow_cpu = off max_mem_clock = DDR400 cmos_defaults_loaded = Disable ht_voltage = 1.30V sideport_voltage = 1.82V gpu_voltage = 1.10V memory_voltage = 2.60V cpu_freq = 210MHz Although it is bit hackish I do Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> If someone has similar/same board and has more time to work on this it would be very nice! Not sure If I will be able to prepare it to comittable state before FOSDEM. Thanks, Rudolf

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build service results for r6381
by repository service 26 Feb '11

26 Feb '11

Dear coreboot readers! This is the automatic build system of coreboot. The developer "ruik" checked in revision 6381 to the coreboot repository. This caused the following changes: Change Log: It adds support for automatic PSS object generation for AMD pre fam Fh CPU. Those CPUs require a hardcoded table, which I managed to rewrite during one particularly boring flight. Too pity it is only for Opteron CPUs. Someone needs to finish the second PDF for All others Athlons and Semprons. Also it enables the FID/VID changes in SB. Jakllsch had some troubles with that too but on am2 CPU. Those bits are only documented in SB600. They arent in RRG RPR and BDG. Signed-off-by: Rudolf Marek <r.marek(a)asssembler.cz> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build Log: Compilation of asi:mb_5blgp has been fixed If something broke during this checkin please be a pain in ruik's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r6381 - in trunk/src: cpu/amd/model_fxx southbridge/amd/sb700
by repository service 26 Feb '11

26 Feb '11

Author: ruik Date: Sat Feb 26 14:34:01 2011 New Revision: 6381 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6381 Log: It adds support for automatic PSS object generation for AMD pre fam Fh CPU. Those CPUs require a hardcoded table, which I managed to rewrite during one particularly boring flight. Too pity it is only for Opteron CPUs. Someone needs to finish the second PDF for All others Athlons and Semprons. Also it enables the FID/VID changes in SB. Jakllsch had some troubles with that too but on am2 CPU. Those bits are only documented in SB600. They arent in RRG RPR and BDG. Signed-off-by: Rudolf Marek <r.marek(a)asssembler.cz> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Modified: trunk/src/cpu/amd/model_fxx/powernow_acpi.c trunk/src/southbridge/amd/sb700/early_setup.c Modified: trunk/src/cpu/amd/model_fxx/powernow_acpi.c ============================================================================== --- trunk/src/cpu/amd/model_fxx/powernow_acpi.c Thu Feb 24 15:35:42 2011 (r6380) +++ trunk/src/cpu/amd/model_fxx/powernow_acpi.c Sat Feb 26 14:34:01 2011 (r6381) @@ -30,10 +30,9 @@ #include <cpu/amd/amdk8_sysconf.h> #include <arch/cpu.h> -#if CONFIG_K8_REV_F_SUPPORT static int write_pstates_for_core(u8 pstate_num, u16 *pstate_feq, u8 *pstate_vid, u8 *pstate_fid, u32 *pstate_power, int coreID, - u32 pcontrol_blk, u8 plen, u8 onlyBSP) + u32 pcontrol_blk, u8 plen, u8 onlyBSP, u32 control) { int lenp, lenpr, i; @@ -50,16 +49,8 @@ lenp = acpigen_write_package(pstate_num); for (i = 0;i < pstate_num;i++) { - u32 control, status; - - control = - (0x3 << 30) | /* IRT */ - (0x2 << 28) | /* RVO */ - (0x1 << 27) | /* ExtType */ - (0x2 << 20) | /* PLL_LOCK_TIME */ - (0x0 << 18) | /* MVS */ - (0x5 << 11) | /* VST */ - (pstate_vid[i] << 6) | + u32 status, c2; + c2 = control | (pstate_vid[i] << 6) | pstate_fid[i]; status = (pstate_vid[i] << 6) | @@ -69,7 +60,7 @@ pstate_power[i], 0x64, 0x7, - control, + c2, status); } /* update the package size */ @@ -81,6 +72,8 @@ acpigen_patch_len(lenpr - 2); return lenpr; } + +#if CONFIG_K8_REV_F_SUPPORT /* * Details about this algorithm , refert to BDKG 10.5.1 * Two parts are included, the another is the DSDT reconstruction process @@ -90,7 +83,7 @@ { int len; u8 processor_brand[49]; - u32 *v; + u32 *v, control; struct cpuid_result cpuid1; struct power_limit_encoding { @@ -367,15 +360,288 @@ len = 0; + control = (0x3 << 30) | /* IRT */ + (0x2 << 28) | /* RVO */ + (0x1 << 27) | /* ExtType */ + (0x2 << 20) | /* PLL_LOCK_TIME */ + (0x0 << 18) | /* MVS */ + (0x5 << 11); /* VST */ + + for (index = 0; index < (cmp_cap + 1); index++) { + len += write_pstates_for_core(Pstate_num, Pstate_feq, Pstate_vid, + Pstate_fid, Pstate_power, index, + pcontrol_blk, plen, onlyBSP, control); + } + + return len; +} + +#else + + +static uint8_t vid_to_reg(uint32_t vid) +{ + return (1550 - vid) / 25; +} + +static uint32_t vid_from_reg(uint8_t val) +{ + return (val == 0x1f ? 0 : 1550 - val * 25); +} + +static uint8_t freq_to_fid(uint32_t freq) +{ + return (freq - 800) / 100; +} +/* Return a frequency in MHz, given an input fid */ +static uint32_t fid_to_freq(uint32_t fid) +{ + return 800 + (fid * 100); +} + +#define MAXP 7 + +struct pstate { + uint16_t freqMhz; /* in MHz */ + uint16_t voltage; /* in mV */ + uint16_t tdp; /* in W * 10 */ +}; + +struct cpuentry { + uint16_t modelnr; /* numeric model value, unused in code */ + uint8_t brandID; /* CPUID 8000_0001h EBX [11:6] (BrandID) */ + uint32_t cpuid; /* CPUID 8000_0001h EAX [31:0] (CPUID) */ + uint8_t maxFID; /* FID/VID Status MaxFID Field */ + uint8_t startFID; /* FID/VID Status StartFID Field */ + uint16_t pwr:12; /* Thermal Design Power of Max P-State *10 (fixed point) */ + /* Other MAX P state are read from CPU, other P states in following table */ + struct pstate pstates[MAXP]; +}; + +struct cpuentry entr[] = { + /* rev E single core, check OSA152FAA5BK */ + {152, 0xc, 0x20f51, 0x12, 0x12, 926, + {{2400, 1350, 900}, {2200, 1300, 766}, + {2000, 1250, 651}, {1800, 1200, 522}, + {1000, 1100, 320}}}, + {252, 0x10, 0x20f51, 0x12, 0x12, 926, + {{2400, 1350, 900}, {2200, 1300, 766}, + {2000, 1250, 651}, {1800, 1200, 522}, + {1000, 1100, 320}}}, + {852, 0x14, 0x20f51, 0x12, 0x12, 926, + {{2400, 1350, 900}, {2200, 1300, 766}, + {2000, 1250, 651}, {1800, 1200, 522}, + {1000, 1100, 320}}}, + {254, 0x10, 0x20f51, 0x14, 0x14, 926, + {{2600, 1350, 902}, {2400, 1300, 770}, + {2200, 1250, 657}, {2000, 1200, 559}, + {1800, 1150, 476}, {1000, 1100, 361}}}, + {854, 0x14, 0x20f51, 0x14, 0x14, 926, + {{2600, 1350, 902}, {2400, 1300, 770}, + {2200, 1250, 657}, {2000, 1200, 559}, + {1800, 1150, 476}, {1000, 1100, 361}}}, + {242, 0x10, 0x20f51, 0x8, 0x8, 853, + {}}, + {842, 0x10, 0x20f51, 0x8, 0x8, 853, + {}}, + {244, 0x10, 0x20f51, 0xa, 0xa, 853, + {{1000, 1100, 378}}}, + {844, 0x14, 0x20f51, 0xa, 0xa, 853, + {{1000, 1100, 378}}}, + {246, 0x10, 0x20f51, 0xc, 0xc, 853, + {{1800, 1350, 853}, + {1000, 1100, 378}}}, + {846, 0x14, 0x20f51, 0xc, 0xc, 853, + {{1800, 1350, 853}, + {1000, 1100, 378}}}, + {242, 0x10, 0x20f51, 0x8, 0x8, 853, + {}}, + {842, 0x14, 0x20f51, 0x8, 0x8, 853, + {}}, + {244, 0x10, 0x20f51, 0xa, 0xa, 853, + {{1000, 1100, 378}}}, + {844, 0x14, 0x20f51, 0xa, 0xa, 853, + {{1000, 1100, 378}}}, + {246, 0x10, 0x20f51, 0xc, 0xc, 853, + {{1800, 1350, 827}, {1000, 1100, 366}}}, + {846, 0x14, 0x20f51, 0xc, 0xc, 853, + {{1800, 1350, 827}, {1000, 1100, 366}}}, + {248, 0x10, 0x20f51, 0xe, 0xe, 853, + {{2000, 1350, 827}, {1800, 1300, 700}, + {1000, 1100, 366}}}, + {848, 0x14, 0x20f51, 0xe, 0xe, 853, + {{2000, 1350, 827}, {1800, 1300, 700}, + {1000, 1100, 366}}}, + {250, 0x10, 0x20f51, 0x10, 0x10, 853, + {{2200, 1350, 853}, {2000, 1300, 827}, + {1800, 1250, 702}, {1000, 1100, 301}}}, + {850, 0x14, 0x20f51, 0x10, 0x10, 853, + {{2200, 1350, 853}, {2000, 1300, 827}, + {1800, 1250, 702}, {1000, 1100, 301}}}, +/* begin OSK246FAA5BL */ + {246, 0x12, 0x20f51, 0xc, 0xc, 547, + {{1800, 1350, 461}, {1000, 1100, 223}}}, + {846, 0x16, 0x20f51, 0xc, 0xc, 547, + {{1800, 1350, 461}, {1000, 1100, 223}}}, + {148, 0xe, 0x20f51, 0xe, 0xe, 547, + {{2000, 1350, 521}, {1800, 1300, 459}, + {1000, 1100, 211}}}, + {248, 0x12, 0x20f51, 0xe, 0xe, 547, + {{2000, 1350, 521}, {1800, 1300, 459}, + {1000, 1100, 211}}}, + {848, 0x16, 0x20f51, 0xe, 0xe, 547, + {{2000, 1350, 521}, {1800, 1300, 459}, + {1000, 1100, 211}}}, + {250, 0x12, 0x20f51, 0x10, 0x10, 547, + {{2200, 1350, 521}, {2000, 1300, 440}, + {1800, 1250, 379}, {1000, 1100, 199}}}, + {850, 0x16, 0x20f51, 0x10, 0x10, 547, + {{2200, 1350, 521}, {2000, 1300, 440}, + {1800, 1250, 379}, {1000, 1100, 199}}}, + {144, 0xc, 0x20f71, 0xa, 0xa, 670, + {{1000, 1100, 296}}}, + {148, 0xc, 0x20f71, 0xe, 0xe, 853, + {{2000, 1350, 830}, {1800, 1300, 704}, + {1000, 1100, 296}}}, + {152, 0xc, 0x20f71, 0x12, 0x12, 104, + {{2400, 1350, 1016}, {2200, 1300, 863}, + {2000, 1250, 732}, {1800, 1200, 621}, + {1000, 1100, 419}}}, + {146, 0xc, 0x20f71, 0xc, 0xc, 670, + {{1800, 1350, 647}, {1000, 1100, 286}}}, + {150, 0xc, 0x20f71, 0x10, 0x10, 853, + {{2200, 1350, 830}, {2000, 1300, 706}, + {1800, 1250, 596}, {1000, 1100, 350}}}, + {154, 0xc, 0x20f71, 0x14, 0x14, 1040, + {{2600, 1350, 1017}, {2400, 1300, 868}, + {2200, 1250, 740}, {2000, 1200, 630}, + {1800, 1150, 537}, {1000, 1100, 416}}}, + /* rev E dualcore */ + {165, 0x2c, 0x20f12, 0xa, 0xa, 950, + {{1000, 1100, 406}}}, + {265, 0x30, 0x20f12, 0xa, 0xa, 950, + {{1000, 1100, 406}}}, + {865, 0x34, 0x20f12, 0xa, 0xa, 950, + {{1000, 1100, 406}}}, + {270, 0x30, 0x20f12, 0xc, 0xc, 950, + {{1800, 1300, 903}, {1000, 1100, 383}}}, + {870, 0x34, 0x20f12, 0xc, 0xc, 950, + {{1800, 1300, 903}, {1000, 1100, 383}}}, + {275, 0x30, 0x20f12, 0xe, 0xe, 950, + {{2000, 1300, 903}, {1800, 1250, 759}, + {1000, 1100, 361}}}, + {875, 0x34, 0x20f12, 0xe, 0xe, 950, + {{2000, 1300, 903}, {1800, 1250, 759}, + {1000, 1100, 361}}}, + {280, 0x30, 0x20f12, 0x10, 0x10, 926, + {{2400, 1350, 900}, {2200, 1300, 766}, + {1800, 1200, 552}, {1000, 1100, 320}}}, + {880, 0x34, 0x20f12, 0x10, 0x10, 926, + {{2400, 1350, 900}, {2200, 1300, 766}, + {1800, 1200, 552}, {1000, 1100, 320}}}, + {170, 0x2c, 0x20f32, 0xc, 0xc, 1100, + {{1800, 1300, 1056}, {1000, 1100, 514}}}, + {175, 0x2c, 0x20f32, 0xe, 0xe, 1100, + {{2000, 1300, 1056}, {1800, 1250, 891}, + {1000, 1100, 490}}}, + {260, 0x32, 0x20f32, 0x8, 0x8, 550, + {}}, + {860, 0x36, 0x20f32, 0x8, 0x8, 550, + {}}, + {165, 0x2e, 0x20f32, 0xa, 0xa, 550, + {{1000, 1100, 365}}}, + {265, 0x32, 0x20f32, 0xa, 0xa, 550, + {{1000, 1100, 365}}}, + {865, 0x36, 0x20f32, 0xa, 0xa, 550, + {{1000, 1100, 365}}}, + {270, 0x32, 0x20f12, 0xc, 0xc, 550, + {{1800, 1150, 520}, {1000, 1100, 335}}}, + {870, 0x36, 0x20f12, 0xc, 0xc, 550, + {{1800, 1150, 520}, {1000, 1100, 335}}}, + {180, 0x2c, 0x20f32, 0x10, 0x10, 1100, + {{2200, 1300, 1056}, {2000, 1250, 891}, + {1800, 1200, 748}, {1000, 1100, 466}}}, + {3000, 0x4, 0x10ff0, 0xa, 0xa, 670, + {{1000, 1100, 210}}}, +}; + +static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) +{ + + u8 cmp_cap; + struct cpuentry *data = NULL; + uint32_t control; + int i = 0, index, len = 0, Pstate_num = 0; + msr_t msr; + u8 Pstate_fid[10]; + u16 Pstate_feq[10]; + u8 Pstate_vid[10]; + u32 Pstate_power[10]; + u8 Max_fid, Start_fid, Start_vid, Max_vid; + struct cpuid_result cpuid1 = cpuid(0x80000001); + + msr = rdmsr(0xc0010042); + Max_fid = (msr.lo & 0x3F0000) >> 16; + Max_vid = (msr.hi & 0x3F0000) >> 16; + Start_fid = (msr.lo & 0x3F00) >> 8; + Start_vid = (msr.hi & 0x3F00) >> 8; + + cmp_cap = + (pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xE8) & + 0x3000) >> 12; + + for (i = 0; i < ARRAY_SIZE(entr); i++) { + if ((entr[i].cpuid == cpuid1.eax) + && (entr[i].startFID == Start_fid) + && (entr[i].maxFID == Max_fid) + && (entr[i].brandID == ((u8 )((cpuid1.ebx >> 6) & 0xff)))) { + data = &entr[i]; + break; + } + } + + if (data == NULL) { + printk(BIOS_WARNING, "Unknown CPU, please update the powernow_acpi.c\n"); + return 0; + } + + /* IRT 80us, PLL_LOCK_TIME 2us, MVS 25mv, VST 100us */ + control = (3 << 30) | (2 << 20) | (0 << 18) | (5 << 11) | (1 << 29); + len = 0; + Pstate_num = 0; + + Pstate_fid[Pstate_num] = Max_fid; + Pstate_feq[Pstate_num] = fid_to_freq(Max_fid); + Pstate_vid[Pstate_num] = Max_vid; + Pstate_power[Pstate_num] = data->pwr * 100; + Pstate_num++; + + do { + Pstate_fid[Pstate_num] = freq_to_fid(data->pstates[Pstate_num - 1].freqMhz) & 0x3f; + Pstate_feq[Pstate_num] = data->pstates[Pstate_num - 1].freqMhz; + Pstate_vid[Pstate_num] = vid_to_reg(data->pstates[Pstate_num - 1].voltage); + Pstate_power[Pstate_num] = data->pstates[Pstate_num - 1].tdp * 100; + Pstate_num++; + } while ((Pstate_num < MAXP) && (data->pstates[Pstate_num].freqMhz != 0)); + + for (i=0;i<Pstate_num;i++) + printk(BIOS_DEBUG, "P#%d freq %d [MHz] voltage %d [mV] TDP %d [mW]\n", i, + Pstate_feq[i], + vid_from_reg(Pstate_vid[i]), + Pstate_power[i]); + for (index = 0; index < (cmp_cap + 1); index++) { len += write_pstates_for_core(Pstate_num, Pstate_feq, Pstate_vid, Pstate_fid, Pstate_power, index, - pcontrol_blk, plen, onlyBSP); + pcontrol_blk, plen, onlyBSP, control); } return len; } +#endif + + int amd_model_fxx_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP) { int lens; @@ -388,11 +654,3 @@ return lens; } -#else - -int amd_model_fxx_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP) -{ - return 0; -} - -#endif Modified: trunk/src/southbridge/amd/sb700/early_setup.c ============================================================================== --- trunk/src/southbridge/amd/sb700/early_setup.c Thu Feb 24 15:35:42 2011 (r6380) +++ trunk/src/southbridge/amd/sb700/early_setup.c Sat Feb 26 14:34:01 2011 (r6381) @@ -232,6 +232,12 @@ pmio_write(0x42, byte); pmio_write(0x89, 0x10); + + /* Toggle the LDT_STOP# during FID/VID Change, this bit is documented + only in SB600! + While here, enable C states too + */ + pmio_write(0x67, 0x6); } void hard_reset(void)

1 0

Re: [coreboot] [PATCH] outb(* 0x80) to post_code()
by Keith Hui 25 Feb '11

25 Feb '11

> Message: 2 > Date: Fri, 25 Feb 2011 19:48:24 +0200 > From: "Alex G." <mr.nuke.me(a)gmail.com> > To: "coreboot(a)coreboot.org" <coreboot(a)coreboot.org> > Subject: Re: [coreboot] [PATCH] outb(* 0x80) to post_code() > Message-ID: <4D67EB68.2090609(a)gmail.com> > Content-Type: text/plain; charset="iso-8859-1" > > Find attached the version with the colloquial verbiage abridged. > > Alex IMO POST_DIE should not be 0xff to reduce confusion. That code, in most other BIOS vendors, is emitted when all is well and OS has begun booting. I am proposing reserving the range 0xE0-0xEF for unrecoverable errors. We already have POST_DEAD_CODE being 0xEE. Going along this line we should make POST_DIE 0xEF, possibly alternating with another code if more detail is to be provided. What do you think?

1 0

[PATCH 5/5] libpayload: Add more libpci-compatibility (#defines)
by Patrick Georgi 25 Feb '11

25 Feb '11

Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- payloads/libpayload/include/pci.h | 2 ++ payloads/libpayload/include/pci/pci.h | 26 ++++++++++++++++++++++++++ 2 files changed, 28 insertions(+), 0 deletions(-) diff --git a/payloads/libpayload/include/pci.h b/payloads/libpayload/include/pci.h index 2490f6c..005634a 100644 --- a/payloads/libpayload/include/pci.h +++ b/payloads/libpayload/include/pci.h @@ -42,6 +42,8 @@ typedef u32 pcidev_t; #define REG_SUBSYS_VENDOR_ID 0x2C #define REG_SUBSYS_ID 0x2E +#define REG_COMMAND_IO (1 << 0) +#define REG_COMMAND_MEM (1 << 1) #define REG_COMMAND_BM (1 << 2) #define HEADER_TYPE_NORMAL 0 diff --git a/payloads/libpayload/include/pci/pci.h b/payloads/libpayload/include/pci/pci.h index 9c7ced8..53da0e1 100644 --- a/payloads/libpayload/include/pci/pci.h +++ b/payloads/libpayload/include/pci/pci.h @@ -39,6 +39,32 @@ #define PCI_SUBSYSTEM_VENDOR_ID REG_SUBSYS_VENDOR_ID #define PCI_SUBSYSTEM_ID REG_SUBSYS_ID +#define PCI_COMMAND REG_COMMAND +#define PCI_COMMAND_IO REG_COMMAND_IO +#define PCI_COMMAND_MEMORY REG_COMMAND_MEM +#define PCI_COMMAND_MASTER REG_COMMAND_BM + +#define PCI_HEADER_TYPE REG_HEADER_TYPE +#define PCI_HEADER_TYPE_NORMAL HEADER_TYPE_NORMAL +#define PCI_HEADER_TYPE_BRIDGE HEADER_TYPE_BRIDGE +#define PCI_HEADER_TYPE_CARDBUS HEADER_TYPE_CARDBUS + +#define PCI_BASE_ADDRESS_0 0x10 +#define PCI_BASE_ADDRESS_1 0x14 +#define PCI_BASE_ADDRESS_2 0x18 +#define PCI_BASE_ADDRESS_3 0x1c +#define PCI_BASE_ADDRESS_4 0x20 +#define PCI_BASE_ADDRESS_5 0x24 +#define PCI_BASE_ADDRESS_SPACE 1 // mask +#define PCI_BASE_ADDRESS_SPACE_IO 1 +#define PCI_BASE_ADDRESS_SPACE_MEM 0 +#define PCI_BASE_ADDRESS_IO_MASK ~0xf +#define PCI_BASE_ADDRESS_MEM_MASK ~0x3 + +#define PCI_ROM_ADDRESS 0x30 +#define PCI_ROM_ADDRESS1 0x38 // on bridges +#define PCI_ROM_ADDRESS_MASK ~0x7ff + struct pci_dev { u16 domain; u8 bus, dev, func; -- 1.7.1

3 2

[PATCH 3/5] libpayload: Implement ffs()
by Patrick Georgi 25 Feb '11

25 Feb '11

Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- payloads/libpayload/include/strings.h | 35 ++++++++++++++++++++++++++++ payloads/libpayload/libc/Makefile.inc | 2 +- payloads/libpayload/libc/strings.c | 40 +++++++++++++++++++++++++++++++++ 3 files changed, 76 insertions(+), 1 deletions(-) create mode 100644 payloads/libpayload/include/strings.h create mode 100644 payloads/libpayload/libc/strings.c diff --git a/payloads/libpayload/include/strings.h b/payloads/libpayload/include/strings.h new file mode 100644 index 0000000..ce7fe93 --- /dev/null +++ b/payloads/libpayload/include/strings.h @@ -0,0 +1,35 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2011 secunet Security Networks AG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _STRING_H +#define _STRING_H + +int ffs(int i); + +#endif diff --git a/payloads/libpayload/libc/Makefile.inc b/payloads/libpayload/libc/Makefile.inc index 3cd98c9..d629ccc 100644 --- a/payloads/libpayload/libc/Makefile.inc +++ b/payloads/libpayload/libc/Makefile.inc @@ -32,7 +32,7 @@ TARGETS-$(CONFIG_LIBC) += libc/malloc.o libc/printf.o libc/console.o libc/string TARGETS-$(CONFIG_LIBC) += libc/memory.o libc/ctype.o libc/ipchecksum.o libc/lib.o TARGETS-$(CONFIG_LIBC) += libc/rand.o libc/time.o libc/exec.o TARGETS-$(CONFIG_LIBC) += libc/readline.o libc/getopt_long.o libc/sysinfo.o -TARGETS-$(CONFIG_LIBC) += libc/args.o +TARGETS-$(CONFIG_LIBC) += libc/args.o libc/strings.o # should be moved to coreboot directory TARGETS-$(CONFIG_LAR) += libc/lar.o diff --git a/payloads/libpayload/libc/strings.c b/payloads/libpayload/libc/strings.c new file mode 100644 index 0000000..9a56ba1 --- /dev/null +++ b/payloads/libpayload/libc/strings.c @@ -0,0 +1,40 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2011 secunet Security Networks AG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +int ffs(int i) +{ + int count = 1; + if (i == 0) return 0; + + while ((i & 1) != 1) { + i>>=1; + count++; + } + return count; +} -- 1.7.1

3 3

[PATCH 2/5] libpayload: Some more standard types and defines
by Patrick Georgi 25 Feb '11

25 Feb '11

Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- payloads/libpayload/include/limits.h | 2 ++ payloads/libpayload/include/stdint.h | 5 +++++ 2 files changed, 7 insertions(+), 0 deletions(-) diff --git a/payloads/libpayload/include/limits.h b/payloads/libpayload/include/limits.h index ae71dfd..be7dde0 100644 --- a/payloads/libpayload/include/limits.h +++ b/payloads/libpayload/include/limits.h @@ -40,4 +40,6 @@ # endif #endif +#define UINT_MAX (unsigned int)0xffffffff + #endif diff --git a/payloads/libpayload/include/stdint.h b/payloads/libpayload/include/stdint.h index ae143d7..8e5083e 100644 --- a/payloads/libpayload/include/stdint.h +++ b/payloads/libpayload/include/stdint.h @@ -27,4 +27,9 @@ * SUCH DAMAGE. */ +#ifndef __STDINT_H +#define __STDINT_H #include <arch/types.h> + +typedef unsigned long uintptr_t; +#endif -- 1.7.1

3 3

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coreboot February 2011