coreboot February 2011

coreboot@coreboot.org

52 participants
283 discussions

Re: [coreboot] Help with RX serial interrupts?
by Rudolf Marek 08 Feb '11

08 Feb '11

Looks like a RX pin multiplexing is wrong, therefore no IRQ is generated? Rudolf PS: I go for a holiday so don't expect much answers from me.

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Re: [coreboot] Help with RX serial interrupts?
by Alex G. 08 Feb '11

08 Feb '11

On 02/08/2011 11:32 PM, Votier, Sean (DS-1) wrote: > Designation: Non-SSA/Finmeccanica > > > Thanks for the reply Alex. I'll do my best to help as much as I can. Though make sure next time you hit the "reply all" or "reply list" button, as your message didn't make it to the list. > No, I'm not totally sure. I've looked through the docs and picked the > values for the registers that seem appropriate. There's the problem right there. There is a big difference between "seems" and "are". I'm working on a K8T800 board, the southbridge containing the IOAPIC is already supported, and yet it still doesn't work. Try to rip off as much data as you can from the mfg BIOS. That's all I can tell you, I'm not an expert in the field. > I looked though the core > boot code to see what was in there but their IRQ scheme it's much more > complicated than I need and it didn't lend itself well to my particular > situation. The problem with IRQ's is that they are a bitch to > troubleshoot, particularly when the signals are all on the silicon so > you can't put a scope on them :( > Coreboot's scheme is fairly straightforward. To my understanding, it sets up the IOAPICs as virtual-wire, compliant with the Intel MP spec (which I read last night :P ). To software, this looks (should look) just like PIC mode. Alex > > Sean > > > -----Original Message----- > From: coreboot-bounces+svotier=drs-ds.com(a)coreboot.org > [mailto:coreboot-bounces+svotier=drs-ds.com@coreboot.org] On Behalf Of > Alex G. > Sent: Tuesday, February 08, 2011 4:15 PM > To: coreboot(a)coreboot.org > Subject: Re: [coreboot] Help with RX serial interrupts? > > Are you sure it's not just a bad PIC/APIC config? > > Alex > > On 02/08/2011 10:15 PM, Votier, Sean (DS-1) wrote: >> Designation: Non-SSA/Finmeccanica >> >> Hi all. >> >> I would like to apologise for being a lurker on this list and only >> popping up when I need help. But I need help........... >> >> I've run into an issue that has been stumping my for the last couple >> of weeks. >> >> I'm developing bios code for a GE CR-11 Compact PCI board. >> >> The chips I'm working with are: >> >> 1.06 Mhz Pentium M >> >> E7520 Northbridge >> >> 6300ESB Southbridge >> >> I'm initialising the SIU in the Southbridge. I have the port > configured. >> I can see data transmitted and received from and to the serial port >> using a scope on the serial cable and also on my emulator but I can't >> seem to get the receive side to generate an interrupt. Does anyone >> have experience with serial interrupts on this hardware? Can you run >> through the steps involved for a very simple rx interrupt config just >> in case I missed something in the Intel docs. Know of an pitfalls? > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > > 3.1.1001

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[PATCH] Fix some errata for AMD Family F processors
by Alex G. 08 Feb '11

08 Feb '11

See patch for detailed description. Alex

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Re: [coreboot] Help with RX serial interrupts?
by Alex G. 08 Feb '11

08 Feb '11

Are you sure it's not just a bad PIC/APIC config? Alex On 02/08/2011 10:15 PM, Votier, Sean (DS-1) wrote: > Designation: Non-SSA/Finmeccanica > > Hi all. > > I would like to apologise for being a lurker on this list and only > popping up when I need help. But I need help……….. > > I’ve run into an issue that has been stumping my for the last couple of > weeks. > > I’m developing bios code for a GE CR-11 Compact PCI board. > > The chips I’m working with are: > > 1.06 Mhz Pentium M > > E7520 Northbridge > > 6300ESB Southbridge > > I’m initialising the SIU in the Southbridge. I have the port configured. > I can see data transmitted and received from and to the serial port > using a scope on the serial cable and also on my emulator but I can’t > seem to get the receive side to generate an interrupt. Does anyone have > experience with serial interrupts on this hardware? Can you run through > the steps involved for a very simple rx interrupt config just in case I > missed something in the Intel docs. Know of an pitfalls?

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Help with RX serial interrupts?
by Votier, Sean (DS-1) 08 Feb '11

08 Feb '11

Designation: Non-SSA/Finmeccanica Hi all. I would like to apologise for being a lurker on this list and only popping up when I need help. But I need help........... I've run into an issue that has been stumping my for the last couple of weeks. I'm developing bios code for a GE CR-11 Compact PCI board. The chips I'm working with are: 1.06 Mhz Pentium M E7520 Northbridge 6300ESB Southbridge I'm initialising the SIU in the Southbridge. I have the port configured. I can see data transmitted and received from and to the serial port using a scope on the serial cable and also on my emulator but I can't seem to get the receive side to generate an interrupt. Does anyone have experience with serial interrupts on this hardware? Can you run through the steps involved for a very simple rx interrupt config just in case I missed something in the Intel docs. Know of an pitfalls? Thanks in advance for the help. Sean 3.1.1001

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[commit] r6338 - in trunk/util/nvramtool: . accessors
by repository service 08 Feb '11

08 Feb '11

Author: jakllsch Date: Tue Feb 8 17:07:49 2011 New Revision: 6338 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6338 Log: Add NetBSD support to nvramtool. Signed-off-by: <jakllsch(a)kollasch.net> Acked-by: Patrick Georgi <patrick.georgi(a)secunet.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/nvramtool/Makefile trunk/util/nvramtool/accessors/cmos-hw-unix.c Modified: trunk/util/nvramtool/Makefile ============================================================================== --- trunk/util/nvramtool/Makefile Tue Feb 8 09:37:47 2011 (r6337) +++ trunk/util/nvramtool/Makefile Tue Feb 8 17:07:49 2011 (r6338) @@ -39,6 +39,9 @@ ifeq ($(OS_ARCH), Darwin) LDFLAGS = -framework DirectIO endif +ifeq ($(OS_ARCH), NetBSD) +LDFLAGS = -l$(shell uname -p) +endif all: dep $(PROGRAM) Modified: trunk/util/nvramtool/accessors/cmos-hw-unix.c ============================================================================== --- trunk/util/nvramtool/accessors/cmos-hw-unix.c Tue Feb 8 09:37:47 2011 (r6337) +++ trunk/util/nvramtool/accessors/cmos-hw-unix.c Tue Feb 8 17:07:49 2011 (r6338) @@ -17,6 +17,53 @@ #if (defined(__MACH__) && defined(__APPLE__)) #include <DirectIO/darwinio.h> #endif +#if defined(__NetBSD__) +#if defined(__i386__) || defined(__x86_64__) +#include <machine/sysarch.h> + +static inline void outb(uint8_t value, uint16_t port) +{ + asm volatile ("outb %b0,%w1": :"a" (value), "Nd" (port)); +} + +static inline uint8_t inb(uint16_t port) +{ + uint8_t value; + asm volatile ("inb %w1,%0":"=a" (value):"Nd" (port)); + return value; +} + +static inline void outw(uint16_t value, uint16_t port) +{ + asm volatile ("outw %w0,%w1": :"a" (value), "Nd" (port)); +} + +static inline uint16_t inw(uint16_t port) +{ + uint16_t value; + asm volatile ("inw %w1,%0":"=a" (value):"Nd" (port)); + return value; +} + +static inline void outl(uint32_t value, uint16_t port) +{ + asm volatile ("outl %0,%w1": :"a" (value), "Nd" (port)); +} + +static inline uint32_t inl(uint16_t port) +{ + uint32_t value; + asm volatile ("inl %1,%0":"=a" (value):"Nd" (port)); + return value; +} +#endif +#ifdef __x86_64__ +#define iopl x86_64_iopl +#endif +#ifdef __i386__ +#define iopl i386_iopl +#endif +#endif #define OUTB outb #define OUTW outw #define OUTL outl

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cmos recovery feature
by Josef Kellermann 08 Feb '11

08 Feb '11

Patrick, having made a 'svn up' I'm getting a build error: make: *** Keine Regel vorhanden, um das Target »cmos.default«, benötigt von »build/coreboot.pre1«, zu erstellen. Schluss. I've added this to my mainboards Makefile.inc: cbfs-files-y += cmos.default cmos.default-name = cmos.default cmos.default-type = 0xaa cmos.default also exists in mainboard dir. I've also tried with: cmos.default-file = cmos.default Any idea ? Regards, Joseph

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[commit] r6337 - trunk
by repository service 08 Feb '11

08 Feb '11

Author: oxygene Date: Tue Feb 8 09:37:47 2011 New Revision: 6337 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6337 Log: Fix cmos-files-y for relative paths Thanks to Josef Kellermann <seppk(a)arcor.de> for reporting the issue. Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Acked-by: Patrick Georgi <patrick.georgi(a)secunet.com> Modified: trunk/Makefile Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Tue Feb 8 03:36:39 2011 (r6336) +++ trunk/Makefile Tue Feb 8 09:37:47 2011 (r6337) @@ -208,10 +208,10 @@ $$(subst $(top)/,, \ $$(abspath $$(addprefix $(dir $(1)),$$($(type)-y)))))) \ $(foreach file,$(cbfs-files-y), \ - $(if $(wildcard $(dir $(1))$$($(file)-file)), \ - $(eval tmp-cbfs-file:= $(wildcard $(dir $(1))$$($(file)-file))), \ - $(eval tmp-cbfs-file:= $$($(file)-file))) \ - $(eval cbfs-files += $(tmp-cbfs-file)|$(file)|$$($(file)-type)|$$($(file)-position)) \ + $(if $(wildcard $(dir $(1))$($(file)-file)), \ + $(eval tmp-cbfs-file:= $(wildcard $(dir $(1))$($(file)-file))), \ + $(eval tmp-cbfs-file:= $($(file)-file))) \ + $(eval cbfs-files += $(tmp-cbfs-file)|$(file)|$($(file)-type)|$($(file)-position)) \ $(eval $(file)-name:=) \ $(eval $(file)-type:=) \ $(eval $(file)-position:=)) \

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[PATCH] Fix issue with Winbond W83627EHG MIDI driver
by Alex G. 07 Feb '11

07 Feb '11

(See Patch) This fixes the "ERROR: device PNP: 002e.207 index 98 has no mask." that I have been getting on the W83627EHG. Alex

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[commit] r6336 - trunk/src/superio/winbond/w83627ehg
by repository service 07 Feb '11

07 Feb '11

Author: jakllsch Date: Tue Feb 8 03:36:39 2011 New Revision: 6336 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6336 Log: Place the W83627EHG MIDI base address mask in the correct position. Corrects "index 98 has no mask" error at runtime. Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Acked-by: Jonathan Kollasch <jakllsch(a)kollasch.net> Modified: trunk/src/superio/winbond/w83627ehg/superio.c Modified: trunk/src/superio/winbond/w83627ehg/superio.c ============================================================================== --- trunk/src/superio/winbond/w83627ehg/superio.c Mon Feb 7 21:16:40 2011 (r6335) +++ trunk/src/superio/winbond/w83627ehg/superio.c Tue Feb 8 03:36:39 2011 (r6336) @@ -189,7 +189,7 @@ { &ops, W83627EHG_HWM, PNP_IO0 | PNP_IRQ0, {0x07fe, 0}, }, { &ops, W83627EHG_GAME, PNP_IO0, {0x07ff, 0}, }, - { &ops, W83627EHG_MIDI, PNP_IO1 | PNP_IRQ0, {0x07fe, 4}, }, + { &ops, W83627EHG_MIDI, PNP_IO1 | PNP_IRQ0, {0, 0}, {0x07fe, 4}, }, { &ops, W83627EHG_GPIO1, }, { &ops, W83627EHG_GPIO2, }, { &ops, W83627EHG_GPIO3, },

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coreboot February 2011