coreboot February 2011

coreboot@coreboot.org

52 participants
283 discussions

[PATCH 2/4] libpayload: Less noisy lpgcc
by Patrick Georgi 11 Feb '11

11 Feb '11

lpgcc was too noisy in some cases Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- payloads/libpayload/bin/lpgcc | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/payloads/libpayload/bin/lpgcc b/payloads/libpayload/bin/lpgcc index 826e498..57015d5 100755 --- a/payloads/libpayload/bin/lpgcc +++ b/payloads/libpayload/bin/lpgcc @@ -30,12 +30,14 @@ # let's not recurse. # This is a hack, I know, but it makes sure that really simple user errors # don't fork-bomb your machine. -echo "CC = $CC" +# echo "CC = $CC" +if [ -n "$CC" ]; then b=`basename $CC` if [ "$b" = "lpgcc" ]; then CC="" fi +fi -- 1.7.1

2 1

inteltool: first preview for machine-readable output
by Антон Кочков 11 Feb '11

11 Feb '11

inteltool: first preview for machine-readable output Signed-off-by: Anton Kochkov <anton.kochkov(a)gmail.com> --- This is only for preview and discussion, it's still ugly and dont safe/clear.

2 2

inteltool: first preview for machine-readable output, fixes
by Антон Кочков 10 Feb '11

10 Feb '11

inteltool: first preview for machine-readable output, fixes Signed-off-by: Anton Kochkov <anton.kochkov(a)gmail.com> --- This is only for preview and discussion, it's still ugly and dont safe/clear.

1 0

what was 'set' in struct io_info for?
by Jonathan A. Kollasch 10 Feb '11

10 Feb '11

Hi, I noticed that, other than initialization in almost every superio, the 'set' member of struct io_info doesn't seem to be referenced by the pnp code. Worth the removing? Jonathan Kollasch

4 3

[commit] r6342 - trunk/src/cpu/amd/car
by repository service 10 Feb '11

10 Feb '11

Author: sduplichan Date: Thu Feb 10 21:49:56 2011 New Revision: 6342 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6342 Log: According to AMD documentation, cache type WP should be used for execution from flash memory. Coreboot uses WB. While there is no noticeable performance difference between the two settings, use of WB can cause a problem for a jtag debugger. The attached patch changes AMD cache as ram setting for flash execution from WB to WP. Signed-off-by: Scott Duplichan <scott(a)notabs.org> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/cpu/amd/car/cache_as_ram.inc Modified: trunk/src/cpu/amd/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/amd/car/cache_as_ram.inc Thu Feb 10 09:49:57 2011 (r6341) +++ trunk/src/cpu/amd/car/cache_as_ram.inc Thu Feb 10 21:49:56 2011 (r6342) @@ -294,11 +294,11 @@ xorl %edx, %edx /* * IMPORTANT: The two lines below can _not_ be written like this: - * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRPROT), %eax * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html */ movl $REAL_XIP_ROM_BASE, %eax - orl $MTRR_TYPE_WRBACK, %eax + orl $MTRR_TYPE_WRPROT, %eax wrmsr movl $MTRRphysMask_MSR(1), %ecx

1 0

[PATCH] cache type for BIOS flash memory should be WP-MMIO, not WB-MMIO
by Scott Duplichan 10 Feb '11

10 Feb '11

According to AMD documentation, cache type WP should be used for execution from flash memory. Coreboot uses WB. While there is no noticeable performance difference between the two settings, use of WB can cause a problem for a jtag debugger. The attached patch changes AMD cache as ram setting for flash execution from WB to WP. Signed-off-by: Scott Duplichan <scott(a)notabs.org> Index: src/cpu/amd/car/cache_as_ram.inc =================================================================== --- src/cpu/amd/car/cache_as_ram.inc (revision 6341) +++ src/cpu/amd/car/cache_as_ram.inc (working copy) @@ -294,11 +294,11 @@ xorl %edx, %edx /* * IMPORTANT: The two lines below can _not_ be written like this: - * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRPROT), %eax * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html */ movl $REAL_XIP_ROM_BASE, %eax - orl $MTRR_TYPE_WRBACK, %eax + orl $MTRR_TYPE_WRPROT, %eax wrmsr movl $MTRRphysMask_MSR(1), %ecx

2 1

[commit] r6341 - trunk/src/southbridge/amd/rs690
by repository service 10 Feb '11

10 Feb '11

Author: oxygene Date: Thu Feb 10 09:49:57 2011 New Revision: 6341 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6341 Log: RS690: Provide support for MMCONF. If enabled, set up 0xe0000000..0xf0000000 as MMCONF area. Must still be configured in per-board ACPI for the OS to pick it up, so it's disabled by default. Signed-off-by: Josef Kellermann<seppk(a)arcor.de> Acked-by: Patrick Georgi <patrick.georgi(a)secunet.com> Modified: trunk/src/southbridge/amd/rs690/Kconfig trunk/src/southbridge/amd/rs690/ht.c Modified: trunk/src/southbridge/amd/rs690/Kconfig ============================================================================== --- trunk/src/southbridge/amd/rs690/Kconfig Thu Feb 10 08:51:51 2011 (r6340) +++ trunk/src/southbridge/amd/rs690/Kconfig Thu Feb 10 09:49:57 2011 (r6341) @@ -20,3 +20,10 @@ config SOUTHBRIDGE_AMD_RS690 bool +if SOUTHBRIDGE_AMD_RS690 +config EXT_CONF_SUPPORT + def_bool n + help + Select if RS690 should be setup to support MMCONF. + +endif Modified: trunk/src/southbridge/amd/rs690/ht.c ============================================================================== --- trunk/src/southbridge/amd/rs690/ht.c Thu Feb 10 08:51:51 2011 (r6340) +++ trunk/src/southbridge/amd/rs690/ht.c Thu Feb 10 09:49:57 2011 (r6341) @@ -22,8 +22,93 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <lib.h> #include "rs690.h" +static void ht_dev_set_resources(device_t dev) +{ +#if CONFIG_EXT_CONF_SUPPORT == 1 + unsigned reg; + device_t k8_f1; + resource_t rbase, rend; + u32 base, limit; + struct resource *resource; + + printk(BIOS_DEBUG,"%s %s\n", dev_path(dev), __func__); + + resource = probe_resource(dev, 0x1C); + if (resource) { + set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 0 << 3); // make bar3 visible + set_nbcfg_enable_bits(dev, 0x7C, 1 << 30, 1 << 30); /* Enables writes to the BAR3 register. */ + set_nbcfg_enable_bits(dev, 0x84, 7 << 16, 0 << 16); // program bus range: 255 busses + pci_write_config32(dev, 0x1C, resource->base); + /* Enable MMCONFIG decoding. */ + set_htiu_enable_bits(dev, 0x32, 1 << 28, 1 << 28); /* PCIEMiscInit */ + set_nbcfg_enable_bits(dev, 0x7C, 1 << 30, 0 << 30); /* Disable writes to the BAR3 register. */ + set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 1 << 3); // hide bar 3 + + // setup resource nonposted in k8 mmio + /* Get the base address */ + rbase = resource->base; + /* Get the limit (rounded up) */ + rend = resource_end(resource); + printk(BIOS_DEBUG,"%s: %s[0x1C] base = %0llx limit = %0llx\n", __func__, dev_path(dev), rbase, rend); + k8_f1 = dev_find_slot(0,PCI_DEVFN(0x18,1)); + // find a not assigned resource + for( reg = 0xb8; reg >= 0x80; reg -= 8 ) { + base = pci_read_config32(k8_f1,reg); + limit = pci_read_config32(k8_f1,reg+4); + if( !(base & 3) ) break; // found a not assigned resource + } + if( !(base & 3) ) { + u32 sblk; + device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + /* Remember this resource has been stored. */ + resource->flags |= IORESOURCE_STORED; + report_resource_stored(dev, resource, " <mmconfig>"); + /* Get SBLink value (HyperTransport I/O Hub Link ID). */ + sblk = (pci_read_config32(k8_f0, 0x64) >> 8) & 0x3; + base &= 0x000000f0; + base |= ((rbase >> 8) & 0xffffff00); + base |= 3; + limit &= 0x00000048; + limit |= ((rend >> 8) & 0xffffff00); + limit |= (sblk << 4); + limit |= (1 << 7); + printk(BIOS_INFO, "%s <- index %x base %04x limit %04x\n", dev_path(k8_f1), reg, base, limit); + pci_write_config32(k8_f1, reg+4, limit); + pci_write_config32(k8_f1, reg, base); + } + } +#endif + pci_dev_set_resources(dev); +} + +static void ht_dev_read_resources(device_t dev) +{ +#if CONFIG_EXT_CONF_SUPPORT == 1 + struct resource *res; + + printk(BIOS_DEBUG,"%s %s\n", dev_path(dev), __func__); + set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 1 << 3); // hide bar 3 +#endif + + pci_dev_read_resources(dev); + +#if CONFIG_EXT_CONF_SUPPORT == 1 + /* Add an MMCONFIG resource. */ + res = new_resource(dev, 0x1C); + res->base = EXT_CONF_BASE_ADDRESS; + res->size = 256 * 1024 * 1024; // 256 busses, 1MB memory space each + res->align = log2(res->size); + res->gran = log2(res->size); + res->limit = 0xffffffffffffffffULL; /* 64bit */ + res->flags = IORESOURCE_FIXED | IORESOURCE_MEM | IORESOURCE_PCI64 | IORESOURCE_ASSIGNED; + + compact_resources(dev); +#endif +} + /* for UMA internal graphics */ void avoid_lpc_dma_deadlock(device_t nb_dev, device_t sb_dev) { @@ -80,8 +165,8 @@ }; static struct device_operations ht_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .read_resources = ht_dev_read_resources, + .set_resources = ht_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = pcie_init, .scan_bus = 0,

1 0

[commit] r6340 - in trunk/src: cpu/amd/model_fxx northbridge/amd/amdk8
by repository service 09 Feb '11

09 Feb '11

Author: oxygene Date: Thu Feb 10 08:51:51 2011 New Revision: 6340 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6340 Log: Implemented workaround for erratum 169, obsoleting erratum 131. Workaround for 131 removed. Changed workaround for erratum 110 to only include pre-revision-F processors. For details, check AMD publications: #25759 (Errata for Fam F pre-revision F processors) #33610 (Errata for Fam F revision F and later processor) Based on work and previous patches by: Rudolf Marek <r.marek(a)assembler.cz> Josef Kellermann <seppk(a)arcor.de> Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Acked-by: Patrick Georgi <patrick.georgi(a)secunet.com> Modified: trunk/src/cpu/amd/model_fxx/model_fxx_init.c trunk/src/northbridge/amd/amdk8/coherent_ht.c Modified: trunk/src/cpu/amd/model_fxx/model_fxx_init.c ============================================================================== --- trunk/src/cpu/amd/model_fxx/model_fxx_init.c Thu Feb 10 08:48:07 2011 (r6339) +++ trunk/src/cpu/amd/model_fxx/model_fxx_init.c Thu Feb 10 08:51:51 2011 (r6340) @@ -411,33 +411,35 @@ msr.hi |= 1 << (43 - 32); wrmsr_amd(BU_CFG_MSR, msr); + /* Erratum 110 */ + /* This erratum applies to D0 thru E6 revisions + * Revision F and later are unaffected. There are two fixes + * depending on processor revision. + */ if (is_cpu_d0()) { /* Erratum 110 ... */ msr = rdmsr_amd(CPU_ID_HYPER_EXT_FEATURES); msr.hi |= 1; wrmsr_amd(CPU_ID_HYPER_EXT_FEATURES, msr); } -#endif -#if CONFIG_K8_REV_F_SUPPORT == 0 if (!is_cpu_pre_e0()) -#endif { /* Erratum 110 ... */ msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); msr.hi |= 1; wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); } - +#endif + + #if CONFIG_K8_REV_F_SUPPORT == 0 - /* I can't touch this msr on early buggy cpus */ + /* I can't touch this msr on early buggy cpus */ if (!is_cpu_pre_b3()) #endif { - - /* Erratum 89 ... */ msr = rdmsr(NB_CFG_MSR); - msr.lo |= 1 << 3; + #if CONFIG_K8_REV_F_SUPPORT == 0 if (!is_cpu_pre_c0() && is_cpu_pre_d0()) { /* D0 later don't need it */ @@ -448,6 +450,18 @@ msr.hi |= 1 << (36 - 32); } #endif + /* Erratum 89 ... */ + /* Erratum 89 is mistakenly labeled as 88 in AMD pub #25759 + * It is correctly labeled as 89 on page 49 of the document + * and in AMD pub#33610 + */ + msr.lo |= 1 << 3; + /* Erratum 169 */ + /* This supersedes erratum 131; 131 should not be applied with 169 + * We also need to set some bits in the northbridge, handled in src/northbridge/amdk8/ + */ + msr.hi |= 1; + wrmsr(NB_CFG_MSR, msr); } /* Erratum 122 */ @@ -455,12 +469,6 @@ msr.lo |= 1 << 6; wrmsr(HWCR_MSR, msr); -#if CONFIG_K8_REV_F_SUPPORT == 1 - /* Erratum 131... */ - msr = rdmsr(NB_CFG_MSR); - msr.lo |= 1 << 20; - wrmsr(NB_CFG_MSR, msr); -#endif } Modified: trunk/src/northbridge/amd/amdk8/coherent_ht.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/coherent_ht.c Thu Feb 10 08:48:07 2011 (r6339) +++ trunk/src/northbridge/amd/amdk8/coherent_ht.c Thu Feb 10 08:51:51 2011 (r6340) @@ -1662,10 +1662,10 @@ unsigned node; int needs_reset = 0; for(node = 0; node < nodes; node++) { -#if CONFIG_K8_REV_F_SUPPORT == 0 device_t dev; uint32_t cmd; dev = NODE_MC(node); +#if CONFIG_K8_REV_F_SUPPORT == 0 if (is_cpu_pre_c0()) { /* Errata 66 @@ -1708,6 +1708,20 @@ } } #endif + + +#if CONFIG_K8_REV_F_SUPPORT == 0 + /* I can't touch this msr on early buggy cpus, and cannot apply either 169 or 131 */ + if (!is_cpu_pre_b3()) +#endif + { + /* Errata 169 */ + /* We also need to set some bits in NB_CFG_MSR, which is handled in src/cpu/amd/model_fxx/ */ + cmd = pci_read_config32(dev, 0x68); + cmd &= ~(1 << 22); + cmd |= (1 << 21); + pci_write_config32(dev, 0x68, cmd); + } } return needs_reset; }

1 0

[commit] r6339 - trunk/src/cpu/amd/model_fxx
by repository service 09 Feb '11

09 Feb '11

Author: oxygene Date: Thu Feb 10 08:48:07 2011 New Revision: 6339 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6339 Log: Fix a potential system hang by handling AMD Model F Erratum 89 a bit later. Signed-off-by: Josef Kellermann <seppk(a)arcor.de> Acked-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Modified: trunk/src/cpu/amd/model_fxx/model_fxx_init.c Modified: trunk/src/cpu/amd/model_fxx/model_fxx_init.c ============================================================================== --- trunk/src/cpu/amd/model_fxx/model_fxx_init.c Tue Feb 8 17:07:49 2011 (r6338) +++ trunk/src/cpu/amd/model_fxx/model_fxx_init.c Thu Feb 10 08:48:07 2011 (r6339) @@ -384,23 +384,6 @@ wrmsr_amd(DC_CFG_MSR, msr); } - /* I can't touch this msr on early buggy cpus */ - if (!is_cpu_pre_b3()) { - - /* Erratum 89 ... */ - msr = rdmsr(NB_CFG_MSR); - msr.lo |= 1 << 3; - - if (!is_cpu_pre_c0() && is_cpu_pre_d0()) { - /* D0 later don't need it */ - /* Erratum 86 Disable data masking on C0 and - * later processor revs. - * FIXME this is only needed if ECC is enabled. - */ - msr.hi |= 1 << (36 - 32); - } - wrmsr(NB_CFG_MSR, msr); - } /* Erratum 97 ... */ if (!is_cpu_pre_c0() && is_cpu_pre_d0()) { @@ -445,7 +428,28 @@ msr.hi |= 1; wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); } + +#if CONFIG_K8_REV_F_SUPPORT == 0 + /* I can't touch this msr on early buggy cpus */ + if (!is_cpu_pre_b3()) +#endif + { + /* Erratum 89 ... */ + msr = rdmsr(NB_CFG_MSR); + msr.lo |= 1 << 3; +#if CONFIG_K8_REV_F_SUPPORT == 0 + if (!is_cpu_pre_c0() && is_cpu_pre_d0()) { + /* D0 later don't need it */ + /* Erratum 86 Disable data masking on C0 and + * later processor revs. + * FIXME this is only needed if ECC is enabled. + */ + msr.hi |= 1 << (36 - 32); + } +#endif + wrmsr(NB_CFG_MSR, msr); + } /* Erratum 122 */ msr = rdmsr(HWCR_MSR); msr.lo |= 1 << 6;

1 0

[patch] nvramtool hardware access on NetBSD
by Jonathan A. Kollasch 08 Feb '11

08 Feb '11

Add NetBSD support to nvramtool. Signed-off-by: <jakllsch(a)kollasch.net>

4 4

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coreboot February 2011