coreboot February 2011

coreboot@coreboot.org

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283 discussions

[PATCH] Fix superio enable calls
by Rudolf Marek 12 Feb '11

12 Feb '11

Hello, While hunting yet another bug, I noticed that part of my serial log is missing. Especially I missed the Allocating & Setting resources. It turns out that the code which enables specific LDN is somewhat buggy: static void w83627dhg_pnp_enable(device_t dev) { - if (!dev->enabled) - return; - pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); pnp_exit_ext_func_mode(dev); } So instead of enable the device the device gets disabled. However after some time the serial line gets back, most likely some "enable resources" might fix it. I'm attaching patch which somewhat fixes the problem and changes the function to look same in all superio code. Some boards even did not convert the dev->enabled to 0,1 values. Also makes me wonder some sio call pnp_enable directly, which has yet another semantics, it wont enable already enabled devices just disable those which declared not enabled. And no PnP enter conf magic is called (maybe this is the reason). Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Not abuild tested, works on dhg. I need to know if this fix is OK this way. Thanks, Rudolf

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Re: [coreboot] searching volunteer to install coreboot on asus m4a78 pro
by xdrudis 12 Feb '11

12 Feb '11

On Sat, Feb 12, 2011 at 05:33:44PM +0100, xdrudis wrote: > http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail&name=W25Q80BVDA… > Forgot to say: this is the one I bought (thanks to Rudolf Marek for the advice) and it's working here with flashrom. The original chip in my board was not yours, it was by Macronix, but yours seems even more similar, to my limited knowledge.

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[commit] r6343 - in trunk/src/southbridge/amd: sb600 sb800
by repository service 12 Feb '11

12 Feb '11

Author: ruik Date: Sat Feb 12 17:24:48 2011 New Revision: 6343 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6343 Log: Attached patch fixes the LPC decode ranges of SB600/SB800. We enable early only Serial/SIO/RTC. Everything else needs to be done by lpc.c Problem was that early settings survived, because the lpc.c is doing ORs only... Hence we decode quite a lot and even strange ranges like IO port 0x4600 etc... Also, if some port which does not fit to predefined set is requested, like 0x290 for Hardware monitor, the wide port is done, but in our case it has range 512 bytes which means we decode in fact 0x290 - 0x490. And if we hit GPU in the 0x3bx range I receive MCE exception if I do isadump -f 0x300 which is bad. Therefore If I detect that the requested range is small (16 bytes) I additionally set the small wide io region so only 16 bytes is decoded. While at it, I fix spelling typos and I init the regs so we don't write random garbage to regs even if we don't enable them later. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/southbridge/amd/sb600/early_setup.c trunk/src/southbridge/amd/sb600/lpc.c trunk/src/southbridge/amd/sb800/early_setup.c trunk/src/southbridge/amd/sb800/lpc.c Modified: trunk/src/southbridge/amd/sb600/early_setup.c ============================================================================== --- trunk/src/southbridge/amd/sb600/early_setup.c Thu Feb 10 21:49:56 2011 (r6342) +++ trunk/src/southbridge/amd/sb600/early_setup.c Sat Feb 12 17:24:48 2011 (r6343) @@ -364,26 +364,8 @@ dev = pci_locate_device(PCI_ID(0x1002, 0x438D), 0); /* DMA enable */ pci_write_config8(dev, 0x40, 0x04); - - /* IO Port Decode Enable */ - pci_write_config8(dev, 0x44, 0xFF); - pci_write_config8(dev, 0x45, 0xFF); - pci_write_config8(dev, 0x46, 0xC3); - pci_write_config8(dev, 0x47, 0xFF); - - // TODO: This has already been done(?) - /* IO/Mem Port Decode Enable, I don't know why CIM disable some ports. - * Disable LPC TimeOut counter, enable SuperIO Configuration Port (2e/2f), - * Alternate SuperIO Configuration Port (4e/4f), Wide Generic IO Port (64/65). */ - byte = pci_read_config8(dev, 0x48); - byte |= (1 << 1) | (1 << 0); /* enable Super IO config port 2e-2h, 4e-4f */ - byte |= 1 << 6; /* enable for RTC I/O range */ - pci_write_config8(dev, 0x48, byte); + /* LPC Sync Timeout */ pci_write_config8(dev, 0x49, 0xFF); - /* Enable 0x480-0x4bf, 0x4700-0x470B */ - byte = pci_read_config8(dev, 0x4A); - byte |= ((1 << 1) + (1 << 6)); /*0x42, save the configuraion for port 0x80. */ - pci_write_config8(dev, 0x4A, byte); /* Enable Tpm12_en and Tpm_legacy. I don't know what is its usage and copied from CIM. */ pci_write_config8(dev, 0x7C, 0x05); Modified: trunk/src/southbridge/amd/sb600/lpc.c ============================================================================== --- trunk/src/southbridge/amd/sb600/lpc.c Thu Feb 10 21:49:56 2011 (r6342) +++ trunk/src/southbridge/amd/sb600/lpc.c Sat Feb 12 17:24:48 2011 (r6343) @@ -103,7 +103,8 @@ struct bus *link; u32 reg, reg_x; int var_num = 0; - u16 reg_var[3]; + u16 reg_var[3] = {0x0, 0x0, 0x0}; + u8 wiosize = pci_read_config8(dev, 0x74); reg = pci_read_config32(dev, 0x44); reg_x = pci_read_config32(dev, 0x48); @@ -134,13 +135,14 @@ case 0x2f8: /* COM2 */ reg |= (1 << 7); break; - case 0x378: /* Parallal 1 */ + case 0x378: /* Parallel 1 */ reg |= (1 << 0); + reg |= (1 << 1); /* + 0x778 for ECP */ break; case 0x3f0: /* FD0 */ reg |= (1 << 26); break; - case 0x220: /* Aduio 0 */ + case 0x220: /* Audio 0 */ reg |= (1 << 8); break; case 0x300: /* Midi 0 */ @@ -170,12 +172,19 @@ switch (var_num) { case 0: reg_x |= (1 << 2); + if ((end - base) < 16) + wiosize |= (1 << 0); break; case 1: reg_x |= (1 << 24); + if ((end - base) < 16) + wiosize |= (1 << 2); break; case 2: reg_x |= (1 << 25); + reg_x |= (1 << 24); + if ((end - base) < 16) + wiosize |= (1 << 3); break; } reg_var[var_num++] = @@ -197,6 +206,7 @@ pci_write_config16(dev, 0x64, reg_var[0]); break; } + pci_write_config8(dev, 0x74, wiosize); } static void sb600_lpc_enable_resources(device_t dev) Modified: trunk/src/southbridge/amd/sb800/early_setup.c ============================================================================== --- trunk/src/southbridge/amd/sb800/early_setup.c Thu Feb 10 21:49:56 2011 (r6342) +++ trunk/src/southbridge/amd/sb800/early_setup.c Sat Feb 12 17:24:48 2011 (r6343) @@ -450,26 +450,8 @@ /* DMA enable */ pci_write_config8(dev, 0x40, 0x04); - /* IO Port Decode Enable */ - pci_write_config8(dev, 0x44, 0xFF); - pci_write_config8(dev, 0x45, 0xFF); - pci_write_config8(dev, 0x46, 0xC3); - pci_write_config8(dev, 0x47, 0xFF); - - /* IO/Mem Port Decode Enable, I don't know why CIM disable some ports. - * Disable LPC TimeOut counter, enable SuperIO Configuration Port (2e/2f), - * Alternate SuperIO Configuration Port (4e/4f), Wide Generic IO Port (64/65). - * Enable bits for LPC ROM memory address range 1&2 for 1M ROM setting.*/ - byte = pci_read_config8(dev, 0x48); - byte |= (1 << 1) | (1 << 0); /* enable Super IO config port 2e-2h, 4e-4f */ - byte |= (1 << 3) | (1 << 4); /* enable for LPC ROM address range1&2, Enable 512KB rom access at 0xFFF80000 - 0xFFFFFFFF */ - byte |= 1 << 6; /* enable for RTC I/O range */ - pci_write_config8(dev, 0x48, byte); + /* LPC Sync Timeout */ pci_write_config8(dev, 0x49, 0xFF); - /* Enable 0x480-0x4bf, 0x4700-0x470B */ - byte = pci_read_config8(dev, 0x4A); - byte |= ((1 << 1) + (1 << 6)); /*0x42, save the configuraion for port 0x80. */ - pci_write_config8(dev, 0x4A, byte); /* Set LPC ROM size, it has been done in sb800_lpc_init(). * enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB; Modified: trunk/src/southbridge/amd/sb800/lpc.c ============================================================================== --- trunk/src/southbridge/amd/sb800/lpc.c Thu Feb 10 21:49:56 2011 (r6342) +++ trunk/src/southbridge/amd/sb800/lpc.c Sat Feb 12 17:24:48 2011 (r6343) @@ -122,7 +122,8 @@ struct bus *link; u32 reg, reg_x; int var_num = 0; - u16 reg_var[3]; + u16 reg_var[3] = {0x0, 0x0, 0x0}; + u8 wiosize = pci_read_config8(dev, 0x74); reg = pci_read_config32(dev, 0x44); reg_x = pci_read_config32(dev, 0x48); @@ -153,13 +154,14 @@ case 0x2f8: /* COM2 */ reg |= (1 << 7); break; - case 0x378: /* Parallal 1 */ + case 0x378: /* Parallel 1 */ reg |= (1 << 0); + reg |= (1 << 1); /* + 0x778 for ECP */ break; case 0x3f0: /* FD0 */ reg |= (1 << 26); break; - case 0x220: /* Aduio 0 */ + case 0x220: /* Audio 0 */ reg |= (1 << 8); break; case 0x300: /* Midi 0 */ @@ -189,12 +191,19 @@ switch (var_num) { case 0: reg_x |= (1 << 2); + if ((end - base) < 16) + wiosize |= (1 << 0); break; case 1: reg_x |= (1 << 24); + if ((end - base) < 16) + wiosize |= (1 << 2); break; case 2: reg_x |= (1 << 25); + reg_x |= (1 << 24); + if ((end - base) < 16) + wiosize |= (1 << 3); break; } reg_var[var_num++] = @@ -216,6 +225,7 @@ pci_write_config16(dev, 0x64, reg_var[0]); break; } + pci_write_config8(dev, 0x74, wiosize); } static void sb800_lpc_enable_resources(device_t dev)

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msrtool code-generation from xml definitions file. Preliminary release.
by Антон Кочков 12 Feb '11

12 Feb '11

See example. Write bugs and suggestions -- Best regards, Anton Kochkov

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SVN service down?
by Gregg Levine 12 Feb '11

12 Feb '11

Hello! I've been trying to update my checked out coreboot code drop since just ten minutes ago. In fact I would bring up a console and enter at the appropriate directory, "svn update" (without quotes) and wait. It would seem to be hanging. Network monitors would only indicate that my SSH shell is the only thing running on the host. ----- Gregg C Levine gregg.drwho8(a)gmail.com "This signature fought the Time Wars, time and again."

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coreboot.rom
by ali hagigat 12 Feb '11

12 Feb '11

How the file coreboot.rom is written on BIOS chip logically? Suppose our BIOS chip is 1 mega bytes. We should read first byte from the beginning of the file and write it to the address zero of BIOS chip and continue this way? I checked the content of build/coreboot.rom and the last byte was 0x0a!! Which is written probably on the top of our EEPROM. Right? but src/arch/i386/init/ldscript.ld specifies the last byte as 0x00!! SECTIONS { _ROMTOP = 0xfffffff0; . = _ROMTOP; .resetvector . : { *(.reset) . = 15 ; BYTE(0x00); } } Please help me with this puzzle. Thank you.

4 3

msrtool: add support for Intel
by Антон Кочков 12 Feb '11

12 Feb '11

msrtool: add support for Intel Signed-off-by: Anton Kochkov <anton.kochkov(a)gmail.com> ---

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[PATCH 4/4] libpayload: Use fprintf(stderr, ...) in library
by Patrick Georgi 11 Feb '11

11 Feb '11

If we have it, why not use it? Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- payloads/libpayload/include/assert.h | 3 ++- payloads/libpayload/libc/lib.c | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/include/assert.h b/payloads/libpayload/include/assert.h index fda4bc0..9968504 100644 --- a/payloads/libpayload/include/assert.h +++ b/payloads/libpayload/include/assert.h @@ -28,6 +28,7 @@ */ #include <stdlib.h> +#include <stdio.h> // assert's existence depends on NDEBUG state on _last_ inclusion of assert.h, // so don't guard this against double-includes. @@ -35,5 +36,5 @@ // Heisenbugs appear if statement has side-effects. This could be worked around but does the standard allow for that? #define assert(statement) #else -#define assert(statement) if ((statement) == 0) { printf("assertion failed in file %s, function %s(), line %s\n", __FILE__, __FUNCTION__, __LINE__); abort(); } +#define assert(statement) if ((statement) == 0) { fprintf(stderr, "assertion failed in file %s, function %s(), line %s\n", __FILE__, __FUNCTION__, __LINE__); abort(); } #endif diff --git a/payloads/libpayload/libc/lib.c b/payloads/libpayload/libc/lib.c index baccc07..c8539cb 100644 --- a/payloads/libpayload/libc/lib.c +++ b/payloads/libpayload/libc/lib.c @@ -109,7 +109,7 @@ u8 hex2bin(u8 h) */ void fatal(const char *msg) { - printf("%s",msg); + fprintf(stderr, "%s",msg); halt(); } -- 1.7.1

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[PATCH 3/4] libpayload: Stub out FILE*, stdout/stdin/stderr and implement fprintf on these
by Patrick Georgi 11 Feb '11

11 Feb '11

- Add FILE* - Add stdout, stdin, stderr stubs - Add fprintf that redirects to printf for stdout and stderr and fails otherwise Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- payloads/libpayload/include/stdio.h | 11 ++++++++++- payloads/libpayload/libc/printf.c | 14 ++++++++++++++ 2 files changed, 24 insertions(+), 1 deletions(-) diff --git a/payloads/libpayload/include/stdio.h b/payloads/libpayload/include/stdio.h index 73af2d1..fb40a0d 100644 --- a/payloads/libpayload/include/stdio.h +++ b/payloads/libpayload/include/stdio.h @@ -32,6 +32,15 @@ #include <stddef.h> +struct _FILE { +} _stdout, _stdin, _stderr; + +typedef struct _FILE FILE; + +FILE *stdout = &_stdout; +FILE *stdin = &_stdin; +FILE *stderr = &_stderr; + /** * @defgroup printf Print functions * @{ @@ -39,6 +48,7 @@ int snprintf(char *str, size_t size, const char *fmt, ...); int sprintf(char *str, const char *fmt, ...); int printf(const char *fmt, ...); +int fprintf(FILE *file, const char *fmt, ...); /** @} */ void perror(const char *s); @@ -47,5 +57,4 @@ void perror(const char *s); #define SEEK_CUR 1 /**< The seek offset is against the current position. */ #define SEEK_END 2 /**< The seek offset is against the end of the file. */ - #endif diff --git a/payloads/libpayload/libc/printf.c b/payloads/libpayload/libc/printf.c index 04d3931..a1ebb14 100644 --- a/payloads/libpayload/libc/printf.c +++ b/payloads/libpayload/libc/printf.c @@ -723,6 +723,20 @@ int sprintf(char *str, const char *fmt, ...) return ret; } +int fprintf(FILE *file, const char *fmt, ...) +{ + int ret; + if ((file == stdout) || (file == stderr)) { + va_list args; + va_start(args, fmt); + ret = vprintf(fmt, args); + va_end(args); + + return ret; + } + return -1; +} + struct vsnprintf_data { size_t size; /* Total space for string */ size_t len; /* Count of currently used characters */ -- 1.7.1

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[PATCH 1/4] libpayload: Some more POSIX compatibility
by Patrick Georgi 11 Feb '11

11 Feb '11

- Add assert.h - Add arpa/inet.h - Add assert-macro Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- payloads/libpayload/include/arpa/inet.h | 36 ++++++++++++++++++++++++++++ payloads/libpayload/include/assert.h | 39 +++++++++++++++++++++++++++++++ 2 files changed, 75 insertions(+), 0 deletions(-) create mode 100644 payloads/libpayload/include/arpa/inet.h create mode 100644 payloads/libpayload/include/assert.h diff --git a/payloads/libpayload/include/arpa/inet.h b/payloads/libpayload/include/arpa/inet.h new file mode 100644 index 0000000..4fc8a89 --- /dev/null +++ b/payloads/libpayload/include/arpa/inet.h @@ -0,0 +1,36 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2011 secunet Security Networks AG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _ARPA_INET_H +#define _ARPA_INET_H + +// arch/endian.h already provides ?to?[lwb] +#include <arch/endian.h> + +#endif diff --git a/payloads/libpayload/include/assert.h b/payloads/libpayload/include/assert.h new file mode 100644 index 0000000..fda4bc0 --- /dev/null +++ b/payloads/libpayload/include/assert.h @@ -0,0 +1,39 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2011 secunet Security Networks AG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <stdlib.h> + +// assert's existence depends on NDEBUG state on _last_ inclusion of assert.h, +// so don't guard this against double-includes. +#ifdef NDEBUG +// Heisenbugs appear if statement has side-effects. This could be worked around but does the standard allow for that? +#define assert(statement) +#else +#define assert(statement) if ((statement) == 0) { printf("assertion failed in file %s, function %s(), line %s\n", __FILE__, __FUNCTION__, __LINE__); abort(); } +#endif -- 1.7.1

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coreboot February 2011