coreboot February 2011

coreboot@coreboot.org

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283 discussions

Re: [coreboot] AMD Agesa and AMD CIMx SB800 code. Patch 8 of 8.
by Stefan Reinauer 14 Feb '11

14 Feb '11

* Vibrans, Frank <Frank.Vibrans(a)amd.com> [110213 22:55]: > Add IBASE DB-FT1 and AMD Inagua motherboards. Patch 8 of 8. > > This code provides support for IBASE Technology DB-FT1 (AMD code > name Persimmon) and AMD Inagua platforms. It is dependent on all > other patches in this set. > > Signed-off-by Frank Vibrans <frank.vibrans(a)amd.com> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>

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Re: [coreboot] AMD Agesa and AMD CIMx SB800 code. Patch 7 of 8.
by Stefan Reinauer 14 Feb '11

14 Feb '11

* Vibrans, Frank <Frank.Vibrans(a)amd.com> [110213 22:55]: > Add SMSC KBC 1100 superio code. Patch 7 of 8. > > This code provides support for the superio chip on the AMD Inagua > platform (not commercially available). It is independent of the AMD > code. > > Signed-off-by Frank Vibrans <frank.vibrans(a)amd.com> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>

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[commit] r6351 - in trunk/src/superio/smsc: . kbc1100
by repository service 14 Feb '11

14 Feb '11

Author: mjones Date: Mon Feb 14 20:00:13 2011 New Revision: 6351 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6351 Log: This code provides support for the superio chip on the AMD Inagua platform (not commercially available). It is independent of the AMD>code. Signed-off-by: Frank Vibrans <frank.vibrans(a)amd.com> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Acked-by: Marc Jones <marcj303(a)gmail.com> Added: trunk/src/superio/smsc/kbc1100/ trunk/src/superio/smsc/kbc1100/Makefile.inc trunk/src/superio/smsc/kbc1100/chip.h trunk/src/superio/smsc/kbc1100/kbc1100.h trunk/src/superio/smsc/kbc1100/kbc1100_early_init.c trunk/src/superio/smsc/kbc1100/superio.c Modified: trunk/src/superio/smsc/Kconfig trunk/src/superio/smsc/Makefile.inc Modified: trunk/src/superio/smsc/Kconfig ============================================================================== --- trunk/src/superio/smsc/Kconfig Mon Feb 14 19:56:10 2011 (r6350) +++ trunk/src/superio/smsc/Kconfig Mon Feb 14 20:00:13 2011 (r6351) @@ -35,5 +35,7 @@ bool config SUPERIO_SMSC_SIO10N268 bool +config SUPERIO_SMSC_KBC1100 + bool config SUPERIO_SMSC_SMSCSUPERIO bool Modified: trunk/src/superio/smsc/Makefile.inc ============================================================================== --- trunk/src/superio/smsc/Makefile.inc Mon Feb 14 19:56:10 2011 (r6350) +++ trunk/src/superio/smsc/Makefile.inc Mon Feb 14 20:00:13 2011 (r6351) @@ -26,4 +26,5 @@ subdirs-y += lpc47n217 subdirs-y += lpc47n227 subdirs-y += sio10n268 +subdirs-y += kbc1100 subdirs-y += smscsuperio Added: trunk/src/superio/smsc/kbc1100/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/superio/smsc/kbc1100/Makefile.inc Mon Feb 14 20:00:13 2011 (r6351) @@ -0,0 +1,20 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +ramstage-$(CONFIG_SUPERIO_SMSC_KBC1100) += superio.c Added: trunk/src/superio/smsc/kbc1100/chip.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/superio/smsc/kbc1100/chip.h Mon Feb 14 20:00:13 2011 (r6351) @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_SMSC_KBC1100_CHIP_H +#define SUPERIO_SMSC_KBC1100_CHIP_H + +#include <pc80/keyboard.h> +#include <uart8250.h> + +struct chip_operations; +extern struct chip_operations superio_smsc_kbc1100_ops; + +struct superio_smsc_kbc1100_config { + struct uart8250 com1, com2; + struct pc_keyboard keyboard; +}; + +#endif \ No newline at end of file Added: trunk/src/superio/smsc/kbc1100/kbc1100.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/superio/smsc/kbc1100/kbc1100.h Mon Feb 14 20:00:13 2011 (r6351) @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define KBC1100_PM1 1 /* PM1 */ +#define SMSCSUPERIO_SP1 4 /* Com1 */ +#define SMSCSUPERIO_SP2 5 /* Com2 */ +#define KBC1100_KBC 7 /* Keyboard */ +#define KBC1100_EC0 8 /* EC Channel 0 */ +#define KBC1100_MAILBOX 9 /* Mail Box */ +#define KBC1100_GPIO 0x0A /* GPIO */ +#define KBC1100_SPI 0x0B /* Share flash interface */ + +#define KBC1100_EC1 0x0D /* EC Channel 1 */ +#define KBC1100_EC2 0x0E /* EC Channel 2 */ + + Added: trunk/src/superio/smsc/kbc1100/kbc1100_early_init.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/superio/smsc/kbc1100/kbc1100_early_init.c Mon Feb 14 20:00:13 2011 (r6351) @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */ + +#include <arch/romcc_io.h> +#include "kbc1100.h" + +static inline void pnp_enter_conf_state(device_t dev) +{ + unsigned port = dev>>8; + outb(0x55, port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + unsigned port = dev>>8; + outb(0xaa, port); +} + +static inline void kbc1100_early_init(unsigned port) +{ + device_t dev; + dev = PNP_DEV (port, KBC1100_KBC); + + pnp_enter_conf_state(dev); + + /* Serial IRQ enabled */ + outb(0x25, port); + outb(0x04, port + 1); + + /* Enable SMSC UART 0 */ + dev = PNP_DEV (port, SMSCSUPERIO_SP1); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, CONFIG_TTYS0_BASE); + pnp_set_enable(dev, 1); + + /* Enable keyboard */ + dev = PNP_DEV (port, KBC1100_KBC); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); + pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); + pnp_set_irq(dev, 0x70, 1); /* IRQ 1 */ + pnp_set_irq(dev, 0x72, 12); /* IRQ 12 */ + pnp_set_enable(dev, 1); + + /* Enable EC Channel 0 */ + dev = PNP_DEV (port, KBC1100_EC0); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 1); + + pnp_exit_conf_state(dev); + + /* disable the 1s timer */ + outb(0xE7, 0x64); +} + Added: trunk/src/superio/smsc/kbc1100/superio.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/superio/smsc/kbc1100/superio.c Mon Feb 14 20:00:13 2011 (r6351) @@ -0,0 +1,124 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* RAM driver for the SMSC KBC1100 Super I/O chip */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <console/console.h> +#include <device/smbus.h> +#include <string.h> +#include <bitops.h> +#include <uart8250.h> +#include <pc80/keyboard.h> +#include <stdlib.h> +#include "chip.h" +#include "kbc1100.h" + +/* Forward declarations */ +static void enable_dev(device_t dev); +static void kbc1100_pnp_set_resources(device_t dev); +static void kbc1100_pnp_enable_resources(device_t dev); +static void kbc1100_pnp_enable(device_t dev); +static void kbc1100_init(device_t dev); + +static void pnp_enter_conf_state(device_t dev); +static void pnp_exit_conf_state(device_t dev); + +struct chip_operations superio_smsc_kbc1100_ops = { + CHIP_NAME("SMSC KBC1100 Super I/O") + .enable_dev = enable_dev +}; + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = kbc1100_pnp_set_resources, + .enable_resources = kbc1100_pnp_enable_resources, + .enable = kbc1100_pnp_enable, + .init = kbc1100_init, +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, KBC1100_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, +}; + +static void enable_dev(device_t dev) +{ + pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +static void kbc1100_pnp_set_resources(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_resources(dev); + pnp_exit_conf_state(dev); +} + +static void kbc1100_pnp_enable_resources(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_enable_resources(dev); + pnp_exit_conf_state(dev); +} + +static void kbc1100_pnp_enable(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + + if(dev->enabled) { + pnp_set_enable(dev, 1); + } + else { + pnp_set_enable(dev, 0); + } + pnp_exit_conf_state(dev); +} + +static void kbc1100_init(device_t dev) +{ + struct superio_smsc_kbc1100_config *conf = dev->chip_info; + struct resource *res0, *res1; + + + + if (!dev->enabled) { + return; + } + + switch(dev->path.pnp.device) { + + case KBC1100_KBC: + res0 = find_resource(dev, PNP_IDX_IO0); + res1 = find_resource(dev, PNP_IDX_IO1); + pc_keyboard_init(&conf->keyboard); + break; + } +} + +static void pnp_enter_conf_state(device_t dev) +{ + outb(0x55, dev->path.pnp.port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + outb(0xaa, dev->path.pnp.port); +}

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Re: [coreboot] AMD Agesa and AMD CIMx SB800 code. Patch 6 of 8.
by Stefan Reinauer 14 Feb '11

14 Feb '11

* Vibrans, Frank <Frank.Vibrans(a)amd.com> [110213 22:53]: > Add Fintek f81865f superio code. Patch 6 of 8. > > This code provides support for the superio chip on the IBASE Technology > DB-FT1 (AMD code name Persimmon) platform. It is independent of the AMD > code. > > Signed-off-by Frank Vibrans <frank.vibrans(a)amd.com> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>

2 2

Re: [coreboot] AMD Agesa and AMD CIMx SB800 code. Patch 4 of 8.
by Stefan Reinauer 14 Feb '11

14 Feb '11

* Vibrans, Frank <Frank.Vibrans(a)amd.com> [110213 22:50]: > Add AMD cpu wrapper code. Patch 4 of 8. > > This code provides cpu early initialization for Family 14h cpus. It is > dependent on the AMD Agesa code. > > Signed-off-by Frank Vibrans <frank.vibrans(a)amd.com> > > Add AMD cpu wrapper code. Patch 4 of 8. > > This code provides cpu early initialization for Family 14h cpus. It is > dependent on the AMD Agesa code. > > Signed-off-by Frank Vibrans <frank.vibrans(a)amd.com> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>

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[commit] r6350 - trunk/src/include/cpu/amd
by repository service 14 Feb '11

14 Feb '11

Author: mjones Date: Mon Feb 14 19:56:10 2011 New Revision: 6350 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6350 Log: I missed a file that was part of the AMD AGESA CPU wrapper checkin, r6347. Signed-off-by: Frank Vibrans <frank.vibrans(a)amd.com> Acked-by: Marc Jones <marcj303(a)gmail.com Added: trunk/src/include/cpu/amd/amdfam14.h Added: trunk/src/include/cpu/amd/amdfam14.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/include/cpu/amd/amdfam14.h Mon Feb 14 19:56:10 2011 (r6350) @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef CPU_AMD_FAM14_H +#define CPU_AMD_FAM14_H + +#include <cpu/x86/msr.h> + +#define HWCR_MSR 0xC0010015 +#define NB_CFG_MSR 0xC001001f +#define LS_CFG_MSR 0xC0011020 +#define IC_CFG_MSR 0xC0011021 +#define DC_CFG_MSR 0xC0011022 +#define BU_CFG_MSR 0xC0011023 +#define BU_CFG2_MSR 0xC001102A + +#define CPU_ID_FEATURES_MSR 0xC0011004 +#define CPU_ID_EXT_FEATURES_MSR 0xC0011005 + +msr_t rdmsr_amd(u32 index); +void wrmsr_amd(u32 index, msr_t msr); + +//#if defined(__GNUC__) +//// it can be used to get unitid and coreid it running only +//struct node_core_id get_node_core_id(u32 nb_cfg_54); +//struct node_core_id get_node_core_id_x(void); +//#endif + +#if defined(__PRE_RAM__) +void wait_all_core0_started(void); +void wait_all_other_cores_started(u32 bsp_apicid); +void wait_all_aps_started(u32 bsp_apicid); +void allow_all_aps_stop(u32 bsp_apicid); +#endif +u32 get_initial_apicid(void); + +#endif /* CPU_AMD_FAM14_H */

1 0

[commit] r6349 - in trunk/src/superio/fintek: . f81865f
by repository service 14 Feb '11

14 Feb '11

Author: mjones Date: Mon Feb 14 19:52:15 2011 New Revision: 6349 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6349 Log: This code provides support for the superio chip on the IBASE Technology DB-FT1 (AMD code name Persimmon) platform. It is independent of the AMD code. Signed-off-by: Frank Vibrans <frank.vibrans(a)amd.com> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Acked-by: Marc Jones <marcj303(a)gmail.com> Added: trunk/src/superio/fintek/f81865f/ trunk/src/superio/fintek/f81865f/Makefile.inc trunk/src/superio/fintek/f81865f/chip.h trunk/src/superio/fintek/f81865f/f81865f.h trunk/src/superio/fintek/f81865f/f81865f_early_serial.c trunk/src/superio/fintek/f81865f/superio.c Modified: trunk/src/superio/fintek/Kconfig trunk/src/superio/fintek/Makefile.inc Modified: trunk/src/superio/fintek/Kconfig ============================================================================== --- trunk/src/superio/fintek/Kconfig Mon Feb 14 19:47:37 2011 (r6348) +++ trunk/src/superio/fintek/Kconfig Mon Feb 14 19:52:15 2011 (r6349) @@ -27,3 +27,5 @@ bool config SUPERIO_FINTEK_F71889 bool +config SUPERIO_FINTEK_F81865F + bool Modified: trunk/src/superio/fintek/Makefile.inc ============================================================================== --- trunk/src/superio/fintek/Makefile.inc Mon Feb 14 19:47:37 2011 (r6348) +++ trunk/src/superio/fintek/Makefile.inc Mon Feb 14 19:52:15 2011 (r6349) @@ -22,3 +22,4 @@ subdirs-y += f71863fg subdirs-y += f71872 subdirs-y += f71889 +subdirs-y += f81865f Added: trunk/src/superio/fintek/f81865f/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/superio/fintek/f81865f/Makefile.inc Mon Feb 14 19:52:15 2011 (r6349) @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Advanced Micro Devices, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ramstage-$(CONFIG_SUPERIO_FINTEK_F81865F) += superio.c Added: trunk/src/superio/fintek/f81865f/chip.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/superio/fintek/f81865f/chip.h Mon Feb 14 19:52:15 2011 (r6349) @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_FINTEK_F81865_CHIP_H +#define SUPERIO_FINTEK_F81865_CHIP_H + +#include <pc80/keyboard.h> +#include <uart8250.h> + +/* This chip doesn't have keyboard and mouse support. */ + +extern struct chip_operations superio_fintek_f81865f_ops; + +struct superio_fintek_f81865f_config { + struct uart8250 com1, com2; + struct pc_keyboard keyboard; +}; + +#endif Added: trunk/src/superio/fintek/f81865f/f81865f.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/superio/fintek/f81865f/f81865f.h Mon Feb 14 19:52:15 2011 (r6349) @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Datasheet: + * - Name: F81865F/F-I + */ +#ifndef SUPERIO_FINTEK_F81865_F81865_H +#define SUPERIO_FINTEK_F81865_F81865_H + +/* Logical Device Numbers (LDN). */ +#define F81865F_FDC 0x00 /* Floppy */ +#define F81865F_SP1 0x10 /* UART1 */ +#define F81865F_SP2 0x11 /* UART2 */ +#define F81865F_PP 0x03 /* Parallel Port */ +#define F81865F_HWM 0x04 /* Hardware Monitor */ +#define F81865F_KBC 0x05 /* Keyboard/Mouse */ +#define F81865F_GPIO 0x06 /* General Purpose I/O (GPIO) */ +#define F81865F_PME 0x0a /* Power Management Events (PME) */ + +#endif Added: trunk/src/superio/fintek/f81865f/f81865f_early_serial.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/superio/fintek/f81865f/f81865f_early_serial.c Mon Feb 14 19:52:15 2011 (r6349) @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Pre-RAM driver for the Fintek F81865F/FG Super I/O chip. */ + +#include <arch/romcc_io.h> +#include "f81865f.h" + +static void pnp_enter_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0x87, port); + outb(0x87, port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + +static void f81865f_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} Added: trunk/src/superio/fintek/f81865f/superio.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/superio/fintek/f81865f/superio.c Mon Feb 14 19:52:15 2011 (r6349) @@ -0,0 +1,114 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <console/console.h> +#include <stdlib.h> +#include "chip.h" +#include "f81865f.h" + +static void pnp_enter_conf_state(device_t dev) +{ + outb(0x87, dev->path.pnp.port); + outb(0x87, dev->path.pnp.port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + outb(0xaa, dev->path.pnp.port); +} + +static void f81865f_init(device_t dev) +{ + struct superio_fintek_f81865f_config *conf = dev->chip_info; + struct resource *res0; + + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + /* TODO: Might potentially need code for HWM or FDC etc. */ + case F81865F_SP1: + res0 = find_resource(dev, PNP_IDX_IO0); + init_uart8250(res0->base, &conf->com1); + break; + case F81865F_SP2: + res0 = find_resource(dev, PNP_IDX_IO0); + init_uart8250(res0->base, &conf->com2); + break; + case F81865F_KBC: + pc_keyboard_init(&conf->keyboard); + break; + } +} + +static void f81865f_pnp_set_resources(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_resources(dev); + pnp_exit_conf_state(dev); +} + +static void f81865f_pnp_enable_resources(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_enable_resources(dev); + pnp_exit_conf_state(dev); +} + +static void f81865f_pnp_enable(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + (dev->enabled) ? pnp_set_enable(dev, 1) : pnp_set_enable(dev, 0); + pnp_exit_conf_state(dev); +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = f81865f_pnp_set_resources, + .enable_resources = f81865f_pnp_enable_resources, + .enable = f81865f_pnp_enable, + .init = f81865f_init, +}; + +static struct pnp_info pnp_dev_info[] = { + /* TODO: Some of the 0x7f8 etc. values may not be correct. */ + { &ops, F81865F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &ops, F81865F_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, F81865F_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, F81865F_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, { 0x07ff, 0}, }, + { &ops, F81865F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &ops, F81865F_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0}, }, + { &ops, F81865F_GPIO, PNP_IRQ0, }, + { &ops, F81865F_PME, }, +}; + +static void enable_dev(device_t dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_fintek_f81865f_ops = { + CHIP_NAME("Fintek F81865F Super I/O") + .enable_dev = enable_dev +};

1 0

Re: [coreboot] (no subject)
by Stefan Reinauer 14 Feb '11

14 Feb '11

* Vibrans, Frank <Frank.Vibrans(a)amd.com> [110213 22:52]: > Add support for AMD Agesa wrapper code. Patch 5 of 8. > > This code fixes a number of build issues related to the AMD Agesa code. > The particular issues are global variables existing in romstage and the > use of GCC intrinsics in the build. The former issue will be addressed > shortly, and the latter issue requires community assistance. This code > is dependent on the AMD Family 14h mainboard code. > > Signed-off-by Frank Vibrans <frank.vibrans(a)amd.com> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>

2 1

[commit] r6348 - in trunk: . src/arch/x86/init
by repository service 14 Feb '11

14 Feb '11

Author: mjones Date: Mon Feb 14 19:47:37 2011 New Revision: 6348 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6348 Log: This code fixes a number of build issues related to the AMD Agesa code. The particular issues are global variables existing in romstage and the use of GCC intrinsics in the build. The former issue will be addressed shortly, and the latter issue requires community assistance. This code is dependent on the AMD Family 14h mainboard code. Signed-off-by: Frank Vibrans <frank.vibrans(a)amd.com> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/Makefile trunk/src/arch/x86/init/ldscript_fallback_cbfs.lb Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Mon Feb 14 19:42:12 2011 (r6347) +++ trunk/Makefile Mon Feb 14 19:47:37 2011 (r6348) @@ -300,13 +300,16 @@ # abspath is a workaround for romcc INCLUDES += -include $(abspath $(obj)/config.h) -CFLAGS = $(INCLUDES) -Os -nostdinc -pipe -g +CFLAGS = $(INCLUDES) -Os -pipe -g CFLAGS += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes CFLAGS += -Wwrite-strings -Wredundant-decls -Wno-trigraphs CFLAGS += -Wstrict-aliasing -Wshadow ifeq ($(CONFIG_WARNINGS_ARE_ERRORS),y) CFLAGS += -Werror endif +ifneq ($(CONFIG_AMD_AGESA),y) +CFLAGS += -nostdinc +endif CFLAGS += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer CBFS_COMPRESS_FLAG:=l Modified: trunk/src/arch/x86/init/ldscript_fallback_cbfs.lb ============================================================================== --- trunk/src/arch/x86/init/ldscript_fallback_cbfs.lb Mon Feb 14 19:42:12 2011 (r6347) +++ trunk/src/arch/x86/init/ldscript_fallback_cbfs.lb Mon Feb 14 19:47:37 2011 (r6348) @@ -49,5 +49,6 @@ *(.comment.*) *(.note.*) } - _bogus = ASSERT((SIZEOF(.bss) + SIZEOF(.data)) == 0, "Do not use global variables in romstage"); +/* _bogus = ASSERT((SIZEOF(.bss) + SIZEOF(.data)) == 0, "Do not use global variables in romstage"); */ + _bogus = ASSERT((SIZEOF(.bss)) == 0, "Do not use global variables in romstage"); }

1 0

[commit] r6347 - in trunk/src/cpu/amd: . agesa_wrapper agesa_wrapper/family14
by repository service 14 Feb '11

14 Feb '11

Author: mjones Date: Mon Feb 14 19:42:12 2011 New Revision: 6347 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6347 Log: Add AMD cpu wrapper code. Patch 4 of 8. This code provides cpu early initialization for Family 14h cpus. It is dependent on the AMD Agesa code. Signed-off-by: Frank Vibrans <frank.vibrans(a)amd.com> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Acked-by: Marc Jones <marcj303(a)gmail.com> Added: trunk/src/cpu/amd/agesa_wrapper/ trunk/src/cpu/amd/agesa_wrapper/Kconfig trunk/src/cpu/amd/agesa_wrapper/Makefile.inc trunk/src/cpu/amd/agesa_wrapper/family14/ trunk/src/cpu/amd/agesa_wrapper/family14/Kconfig trunk/src/cpu/amd/agesa_wrapper/family14/Makefile.inc trunk/src/cpu/amd/agesa_wrapper/family14/apic_timer.c trunk/src/cpu/amd/agesa_wrapper/family14/cache_as_ram.inc trunk/src/cpu/amd/agesa_wrapper/family14/chip.h trunk/src/cpu/amd/agesa_wrapper/family14/chip_name.c trunk/src/cpu/amd/agesa_wrapper/family14/model_14_init.c Modified: trunk/src/cpu/amd/Kconfig trunk/src/cpu/amd/Makefile.inc Modified: trunk/src/cpu/amd/Kconfig ============================================================================== --- trunk/src/cpu/amd/Kconfig Mon Feb 14 19:38:14 2011 (r6346) +++ trunk/src/cpu/amd/Kconfig Mon Feb 14 19:42:12 2011 (r6347) @@ -20,3 +20,5 @@ source src/cpu/amd/model_lx/Kconfig source src/cpu/amd/sc520/Kconfig + +source src/cpu/amd/agesa_wrapper/Kconfig Modified: trunk/src/cpu/amd/Makefile.inc ============================================================================== --- trunk/src/cpu/amd/Makefile.inc Mon Feb 14 19:38:14 2011 (r6346) +++ trunk/src/cpu/amd/Makefile.inc Mon Feb 14 19:42:12 2011 (r6347) @@ -12,3 +12,6 @@ subdirs-$(CONFIG_CPU_AMD_LX) += model_lx subdirs-$(CONFIG_CPU_AMD_SC520) += sc520 subdirs-$(CONFIG_CPU_AMD_SOCKET_S1G1) += socket_S1G1 + +subdirs-$(CONFIG_AMD_AGESA) += agesa_wrapper +subdirs-$(CONFIG_AMD_AGESA) += ../../vendorcode/amd/agesa Added: trunk/src/cpu/amd/agesa_wrapper/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/cpu/amd/agesa_wrapper/Kconfig Mon Feb 14 19:42:12 2011 (r6347) @@ -0,0 +1,20 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +source src/cpu/amd/agesa_wrapper/family14/Kconfig Added: trunk/src/cpu/amd/agesa_wrapper/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/cpu/amd/agesa_wrapper/Makefile.inc Mon Feb 14 19:42:12 2011 (r6347) @@ -0,0 +1,19 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +subdirs-$(CONFIG_CPU_AMD_AGESA_WRAPPER_FAMILY14) += family14 Added: trunk/src/cpu/amd/agesa_wrapper/family14/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/cpu/amd/agesa_wrapper/family14/Kconfig Mon Feb 14 19:42:12 2011 (r6347) @@ -0,0 +1,74 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +config CPU_AMD_AGESA_WRAPPER_FAMILY14 + bool + select PCI_IO_CFG_EXT + +config CPU_ADDR_BITS + int + default 36 + depends on CPU_AMD_AGESA_WRAPPER_FAMILY14 + +config CPU_SOCKET_TYPE + hex + default 0x10 + depends on CPU_AMD_AGESA_WRAPPER_FAMILY14 + +# DDR2 and REG +config DIMM_SUPPORT + hex + default 0x0104 + depends on CPU_AMD_AGESA_WRAPPER_FAMILY14 + +config EXT_RT_TBL_SUPPORT + bool + default n + depends on CPU_AMD_AGESA_WRAPPER_FAMILY14 + +config EXT_CONF_SUPPORT + bool + default n + depends on CPU_AMD_AGESA_WRAPPER_FAMILY14 + +config CBB + hex + default 0x0 + depends on CPU_AMD_AGESA_WRAPPER_FAMILY14 + +config CDB + hex + default 0x18 + depends on CPU_AMD_AGESA_WRAPPER_FAMILY14 + +config XIP_ROM_BASE + hex + default 0xfff80000 + depends on CPU_AMD_AGESA_WRAPPER_FAMILY14 + +config XIP_ROM_SIZE + hex + default 0x80000 + depends on CPU_AMD_AGESA_WRAPPER_FAMILY14 + +config HAVE_INIT_TIMER + bool + default y + depends on CPU_AMD_AGESA_WRAPPER_FAMILY14 + Added: trunk/src/cpu/amd/agesa_wrapper/family14/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/cpu/amd/agesa_wrapper/family14/Makefile.inc Mon Feb 14 19:42:12 2011 (r6347) @@ -0,0 +1,285 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +ramstage-y += chip_name.c +driver-y += model_14_init.c + +AGESA_ROOT = ../../../../vendorcode/amd/agesa + +agesa_lib_src = $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/Family/0x14/F14NbLclkDpm.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSbLink.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLib.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14PerCorePciTables.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14BrandIdFt1.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbInitAtPost.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14IoCstate.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuIoCstate.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnprotoon.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch05000025.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B_Unenc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A_Unenc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch05000025_Unenc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14/F14PciePifServices.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuInitEarlyTable.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/Family/0x14/F14NbLclkNclkRatio.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/Family/0x14/F14NbSmu.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PcieInitAtEnv.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PcieInitAtPost.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/Feature/NbLclkDpm.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/Feature/NbFuseTable.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/Family/0x14/F14NbPowerGate.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Common/GnbLibFeatures.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14Pstate.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuC6State.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14C6State.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmMemRestore.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mm.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuCommonF14Utilities.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnEquivalenceTable.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttml.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtrci3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtReset.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnmcton.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCacheInit.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttdimbt.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtsdi3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mthdi.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtEarly.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14PowerMgmtSystemTables.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnfeat.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmStandardTraining.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Fam14/htNbUtilitiesFam14.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuBist.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmParallelTraining.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/LVDDR3/mflvddr3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14/F14PcieComplexConfig.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14PowerPlane.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnreg.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnflowon.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/CHINTLV/mfchi.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PcieInit.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxInitAtMidPost.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/ON/mpuon3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahalt.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mt.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PciePortInit.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnflow.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuFeatureLeveling.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttoptsrc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/PARTRN/mfParallelTraining.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxInitAtPost.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmEcc.c +agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/Dispatcher.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/MEMCLR/mfmemclr.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14WheaInitDataTables.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuDmi.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttsrc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnmct.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterfaceNonCoherent.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnidendimmon.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuSrat.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdS3LateRestore.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Table.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14/F14PcieComplexServices.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14Utilities.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterface.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxStrapsInit.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbInitAtEarly.c +agesa_lib_src += $(AGESA_ROOT)/Lib/amdlib.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCacheFlushOnHalt.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/minit.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14/F14PciePhyServices.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtLate.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnoton.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/INTLVRN/mfintlvrn.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbInit.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/IDENDIMM/mfidendimm.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmflow.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ardk/ma.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/CommonInits.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPstateLeveling.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mndcton.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitPost.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxGmcInit.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuBrandId.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnphy.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitEnv.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmConditionalPso.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtPost.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/CommonReturns.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPowerMgmt.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitResume.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14PowerCheck.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14Dmi.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnregon.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitEarly.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuFamilyTranslation.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPostInit.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mn.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxInitAtEnvPost.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuHwC1e.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuLateInit.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/CreateStruct.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuWhea.c +agesa_lib_src += $(AGESA_ROOT)/Lib/helper.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/CSINTLV/mfcsi.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/ECC/mfecc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/DMI/mfDMI.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/ON/mpson3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdLateRunApTask.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPowerMgmtMultiSocket.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmUmaAlloc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPstateTables.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14PciTables.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPowerMgmtSingleSocket.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtMid.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mt3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmExcludeDimm.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PcieInitAtEarlyPost.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterfaceGeneral.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/S3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuFeatures.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mp.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mdef.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mtthrc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuGeneralServices.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htNb.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuSlit.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/ECC/mfemp.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbInitAtLatePost.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmNodeInterleave.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Fam14/htNbFam14.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxConfigData.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/ON/mmflowon.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitReset.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14MsrTables.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PcieInitAtLatePost.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttEdgeDetect.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxRegisterAcc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitLate.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htFeat.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbInitAtReset.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnLogicalIdTables.c +agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/hobTransfer.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuApicUtilities.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtEnv.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuEventLog.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterfaceCoherent.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/muc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmLvDdr3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuMicrocodePatch.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttecc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14SoftwareThermal.c +agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/agesaCallouts.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnon.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/PARTRN/mfStandardTraining.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mndct.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmOnlineSpare.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuEarlyInit.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnphyon.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/merrhdl.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdS3Save.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtspd3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14BrandId.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htMain.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuWarmReset.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbConfigData.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mttwl3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPstateGather.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtot3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmMemClr.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ardk/ON/mauon3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/TABLE/mftds.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ardk/ON/mason3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/S3/mfs3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htNotify.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnS3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/heapManager.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mttecc3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnS3on.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitMid.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mntrain3.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/Family/0x14/F14GfxServices.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/S3SaveState.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Common/S3RestoreState.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PcieLateInit.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PciePortLateInit.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PcieMiscLib.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbSmuLib.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbInitAtEnv.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/Family/0x14/F14NbServices.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxLib.c +agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbPowerMgmt.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/HT/htInitReset.c +agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mu.c + +romstage-y += $(agesa_lib_src) +ramstage-y += $(agesa_lib_src) + +subdirs-y += ../../mtrr +subdirs-y += ../../../x86/tsc +subdirs-y += ../../../x86/lapic +subdirs-y += ../../../x86/cache +subdirs-y += ../../../x86/mtrr +subdirs-y += ../../../x86/pae +subdirs-y += ../../../x86/smm + +ramstage-y += apic_timer.c +cpu_incs += $(src)/cpu/amd/agesa_wrapper/family14/cache_as_ram.inc Added: trunk/src/cpu/amd/agesa_wrapper/family14/apic_timer.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/cpu/amd/agesa_wrapper/family14/apic_timer.c Mon Feb 14 19:42:12 2011 (r6347) @@ -0,0 +1,58 @@ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#include <stdint.h> +#include <delay.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/lapic.h> + +/* NOTE: We use the APIC TIMER register is to hold flags for AP init during + * pre-memory init (__PRE_RAM__). Don't use init_timer() and udelay is + * redirected to udelay_tsc(). + */ + + +void init_timer(void) +{ + /* Set the apic timer to no interrupts and periodic mode */ + lapic_write(LAPIC_LVTT, (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0)); + + /* Set the divider to 1, no divider */ + lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1); + + /* Set the initial counter to 0xffffffff */ + lapic_write(LAPIC_TMICT, 0xffffffff); +} + + +void udelay(u32 usecs) +{ + u32 start, value, ticks; + /* Calculate the number of ticks to run, our FSB runs a 200Mhz */ + ticks = usecs * 200; + start = lapic_read(LAPIC_TMCCT); + do { + value = lapic_read(LAPIC_TMCCT); + } while((start - value) < ticks); + +} Added: trunk/src/cpu/amd/agesa_wrapper/family14/cache_as_ram.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/cpu/amd/agesa_wrapper/family14/cache_as_ram.inc Mon Feb 14 19:42:12 2011 (r6347) @@ -0,0 +1,98 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/****************************************************************************** + * AMD Generic Encapsulated Software Architecture + * + * $Workfile:: cache_as_ram.inc + * + * Description: cache_as_ram.inc - AGESA Module Entry Point for GCC complier + * + ****************************************************************************** + */ + +#include "gcccar.inc" + +/* + * XMM map: + * xmm0: BIST + * xmm1: backup ebx -- cpu_init_detected + */ + +.code32 +.globl cache_as_ram_setup, disable_cache_as_ram, cache_as_ram_setup_out + +cache_as_ram_setup: + + post_code(0xa0) + + /* enable SSE2 128bit instructions */ + /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */ + + movl %cr4, %eax + orl $(3<<9), %eax + movl %eax, %cr4 + + /* Get the cpu_init_detected */ + mov $1, %eax + cpuid + shr $24, %ebx + + /* Save the BIST result */ + cvtsi2sd %ebp, %xmm0 + + /* for normal part %ebx already contain cpu_init_detected from fallback call */ + + /* Save the cpu_init_detected */ + cvtsi2sd %ebx, %xmm1 + + post_code(0xa1) + AMD_ENABLE_STACK + + post_code(0xa1) + + /* Restore the BIST result */ + cvtsd2si %xmm0, %edx + + /* Restore the cpu_init_detected */ + cvtsd2si %xmm1, %ebx + + pushl %ebx /* init detected */ + pushl %edx /* bist */ + call cache_as_ram_main + + /* Should never see this postcode */ + post_code(0xaf) +stop: + jmp stop + +disable_cache_as_ram: + /* Save return stack */ + cvtsi2sd %esp, %xmm0 + + AMD_DISABLE_STACK + + /* Restore the return stack */ + cvtsd2si %xmm0, %esp + + ret + +cache_as_ram_setup_out: + + Added: trunk/src/cpu/amd/agesa_wrapper/family14/chip.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/cpu/amd/agesa_wrapper/family14/chip.h Mon Feb 14 19:42:12 2011 (r6347) @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations cpu_amd_agesa_wrapper_family14_ops; + +struct cpu_amd_agesa_wrapper_family14_config { +}; Added: trunk/src/cpu/amd/agesa_wrapper/family14/chip_name.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/cpu/amd/agesa_wrapper/family14/chip_name.c Mon Feb 14 19:42:12 2011 (r6347) @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "chip.h" + +struct chip_operations cpu_amd_agesa_wrapper_family14_ops = { + CHIP_NAME("AMD CPU Family 14h") +}; Added: trunk/src/cpu/amd/agesa_wrapper/family14/model_14_init.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/cpu/amd/agesa_wrapper/family14/model_14_init.c Mon Feb 14 19:42:12 2011 (r6347) @@ -0,0 +1,137 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/pae.h> +#include <pc80/mc146818rtc.h> +#include <cpu/x86/lapic.h> + +#include <cpu/cpu.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/mtrr.h> +#include <cpu/amd/multicore.h> +#include <cpu/amd/amdfam14.h> + +#define MCI_STATUS 0x401 + +msr_t rdmsr_amd(u32 index) +{ + msr_t result; + __asm__ __volatile__( + "rdmsr" + :"=a"(result.lo), "=d"(result.hi) + :"c"(index), "D"(0x9c5a203a) + ); + return result; +} + +void wrmsr_amd(u32 index, msr_t msr) +{ + __asm__ __volatile__( + "wrmsr" + : /* No outputs */ + :"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a) + ); +} + +static void model_14_init(device_t dev) +{ + printk(BIOS_DEBUG, "Model 14 Init - a no-op.\n"); + + u8 i; + msr_t msr; + struct node_core_id id; +#if CONFIG_LOGICAL_CPUS == 1 + u32 siblings; +#endif + +// id = get_node_core_id(read_nb_cfg_54()); /* nb_cfg_54 can not be set */ +// printk(BIOS_DEBUG, "nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid); + + /* Turn on caching if we haven't already */ + x86_enable_cache(); + amd_setup_mtrrs(); + x86_mtrr_check(); + + disable_cache(); + + /* zero the machine check error status registers */ + msr.lo = 0; + msr.hi = 0; + for (i = 0; i < 5; i++) { + wrmsr(MCI_STATUS + (i * 4), msr); + } + + enable_cache(); + + /* Enable the local cpu apics */ + setup_lapic(); + + /* Set the processor name string */ +// init_processor_name(); + + +#if CONFIG_LOGICAL_CPUS == 1 + siblings = cpuid_ecx(0x80000008) & 0xff; + + if (siblings > 0) { + msr = rdmsr_amd(CPU_ID_FEATURES_MSR); + msr.lo |= 1 << 28; + wrmsr_amd(CPU_ID_FEATURES_MSR, msr); + + msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); + msr.hi |= 1 << (33 - 32); + wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); + } + printk(BIOS_DEBUG, "siblings = %02d, ", siblings); +#endif + + /* DisableCf8ExtCfg */ + msr = rdmsr(NB_CFG_MSR); + msr.hi &= ~(1 << (46 - 32)); + wrmsr(NB_CFG_MSR, msr); + + + /* Write protect SMM space with SMMLOCK. */ + msr = rdmsr(HWCR_MSR); + msr.lo |= (1 << 0); + wrmsr(HWCR_MSR, msr); +} + +static struct device_operations cpu_dev_ops = { + .init = model_14_init, +}; + +static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_AMD, 0x500f00 }, /* ON-A0 */ + { X86_VENDOR_AMD, 0x500f01 }, /* ON-A1 */ + { X86_VENDOR_AMD, 0x500f10 }, /* ON-B0 */ + { 0, 0 }, +}; + +static const struct cpu_driver model_14 __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +};

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coreboot February 2011