coreboot December 2011

coreboot@coreboot.org

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174 discussions

New patch to review for coreboot: 76ee7c3 Use convenience function to checksum
by Philip Prindeville 24 Dec '11

24 Dec '11

Philip Prindeville (pprindeville(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/497 -gerrit commit 76ee7c3f8e68eae1df5fcb43bcfb54dcdf489cad Author: Philip Prindeville <philipp(a)redfish-solutions.com> Date: Fri Dec 23 17:22:05 2011 -0700 Use convenience function to checksum That coreboot uses the IP checksum is an artifact, not a deliberate requirement to be compatible with the Internet Protocole suite. Use a wrapper to abstract the computation of coreboot's checksum. Change-Id: I6491b9ba5efb9ffe5cb12a6172653a6ac80a1370 Signed-off-by: Philip Prindeville <philipp(a)redfish-solutions.com> --- payloads/coreinfo/coreboot_module.c | 6 +++--- payloads/libpayload/include/coreboot_tables.h | 5 +++++ 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/payloads/coreinfo/coreboot_module.c b/payloads/coreinfo/coreboot_module.c index 5d13128..7289366 100644 --- a/payloads/coreinfo/coreboot_module.c +++ b/payloads/coreinfo/coreboot_module.c @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <coreboot_tables.h> #include "coreinfo.h" +#include <coreboot_tables.h> #ifdef CONFIG_MODULE_COREBOOT @@ -189,10 +189,10 @@ static int parse_header(void *addr, int len) /* FIXME: Check the checksum. */ - if (ipchksum((uint16_t *) header, sizeof(*header))) + if (cb_checksum(header, sizeof(*header))) return -1; - if (ipchksum((uint16_t *) (ptr + sizeof(*header)), header->table_bytes) + if (cb_checksum((ptr + sizeof(*header)), header->table_bytes) != header->table_checksum) return -1; diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 3b3b7d2..574469a 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -223,6 +223,11 @@ static inline u64 cb_unpack64(struct cbuint64 val) return (((u64) val.hi) << 32) | val.lo; } +static inline u16 cb_checksum(const void *ptr, unsigned len) +{ + return ipchksum(ptr, len); +} + /* Helpful macros */ #define MEM_RANGE_COUNT(_rec) \

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Patch set updated for coreboot: db8120b Replace UNPACK_CB64 macro with inline
by Philip Prindeville 24 Dec '11

24 Dec '11

Philip Prindeville (pprindeville(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/495 -gerrit commit db8120b11aa3b9610f31ace9bbba61b6e5fa4046 Author: Philip Prindeville <philipp(a)redfish-solutions.com> Date: Fri Dec 23 17:09:02 2011 -0700 Replace UNPACK_CB64 macro with inline Having submitted a module based on coreboot to LKML for acceptance, it was requested that fewer macros and more inlines be used (because of their superior type-checking when performing pointer casts, etc). This is the first of several changes to make the relevant parts of coreboot comply to linux code standards. Change-Id: Iffe7061fa62fa639e0cb6ccb9125eb3403d06b1a Signed-off-by: Philip Prindeville <philipp(a)redfish-solutions.com> --- payloads/coreinfo/coreboot_module.c | 6 +++--- payloads/libpayload/arch/i386/coreboot.c | 4 ++-- payloads/libpayload/include/coreboot_tables.h | 10 +++++++--- 3 files changed, 12 insertions(+), 8 deletions(-) diff --git a/payloads/coreinfo/coreboot_module.c b/payloads/coreinfo/coreboot_module.c index dd589ac..5d13128 100644 --- a/payloads/coreinfo/coreboot_module.c +++ b/payloads/coreinfo/coreboot_module.c @@ -112,9 +112,9 @@ int coreboot_module_redraw(WINDOW *win) } wprintw(win, "%16.16llx - %16.16llx", - UNPACK_CB64(cb_info.range[i].start), - UNPACK_CB64(cb_info.range[i].start) + - UNPACK_CB64(cb_info.range[i].size) - 1); + cb_unpack64(cb_info.range[i].start), + cb_unpack64(cb_info.range[i].start) + + cb_unpack64(cb_info.range[i].size) - 1); } return 0; diff --git a/payloads/libpayload/arch/i386/coreboot.c b/payloads/libpayload/arch/i386/coreboot.c index 365445e..a77144b 100644 --- a/payloads/libpayload/arch/i386/coreboot.c +++ b/payloads/libpayload/arch/i386/coreboot.c @@ -63,10 +63,10 @@ static void cb_parse_memory(unsigned char *ptr, struct sysinfo_t *info) #endif info->memrange[info->n_memranges].base = - UNPACK_CB64(range->start); + cb_unpack64(range->start); info->memrange[info->n_memranges].size = - UNPACK_CB64(range->size); + cb_unpack64(range->size); info->memrange[info->n_memranges].type = range->type; diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index d342c99..3b3b7d2 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -216,6 +216,13 @@ struct cb_cmos_checksum { u32 type; }; +/* Helpful inlines */ + +static inline u64 cb_unpack64(struct cbuint64 val) +{ + return (((u64) val.hi) << 32) | val.lo; +} + /* Helpful macros */ #define MEM_RANGE_COUNT(_rec) \ @@ -231,7 +238,4 @@ struct cb_cmos_checksum { #define MB_PART_STRING(_mb) \ (((unsigned char *) ((_mb)->strings)) + (_mb)->part_number_idx) -#define UNPACK_CB64(_in) \ - ( (((u64) _in.hi) << 32) | _in.lo ) - #endif

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New patch to review for coreboot: 3ff84d3 ACPI: remove empty get_cst_entries()
by Sven Schnelle 23 Dec '11

23 Dec '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/496 -gerrit commit 3ff84d326ee881a4ec2f3995744363d75710cf14 Author: Sven Schnelle <svens(a)stackframe.org> Date: Fri Dec 23 10:29:09 2011 +0100 ACPI: remove empty get_cst_entries() This function prevents the linker from choosing the right get_cst_entries(), preventing writing the _CST tables. Change-Id: I4bc0168aee110171faeaa081f217dfd1536bb821 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/cpu/intel/speedstep/acpi.c | 7 +------ 1 files changed, 1 insertions(+), 6 deletions(-) diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index 8f32e4f..c7ad4f6 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -62,11 +62,6 @@ static int get_fsb(void) return 200; } -int get_cst_entries(struct cst_entry **entries __attribute__((unused))) -{ - return 0; -} - void generate_cpu_entries(void) { int len_pr, len_ps; @@ -89,7 +84,7 @@ void generate_cpu_entries(void) len_pr = acpigen_write_processor((cpuID-1)*cores_per_package+coreID-1, pcontrol_blk, plen); len_pr += acpigen_write_empty_PCT(); len_pr += acpigen_write_PSD_package(cpuID-1,cores_per_package,SW_ANY); - if ((count = get_cst_entries(&cst_entries)) > 0) + if (get_cst_entries && (count = get_cst_entries(&cst_entries)) > 0) len_pr += acpigen_write_CST_package(cst_entries, count); len_pr += acpigen_write_name("_PSS");

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Will coreboot work on my machine?
by jacob scott 23 Dec '11

23 Dec '11

As I understand, this is where to send my motherboard specs, my apologies if it isn't. ASUS M4A88T-V EVO/USB3 AMD 880G/SB710 AMD Athlon II x4 640 More specs: http://usa.asus.com/Motherboards/AMD_AM3/M4A88TV_EVOUSB3/#specifications *lspci -tvnn *output: ~$ lspci -tvnn -[0000:00]-+-00.0 Advanced Micro Devices [AMD] RS880 Host Bridge [1022:9601] +-02.0-[01]--+-00.0 ATI Technologies Inc Redwood [Radeon HD 5670] [1002:68d8] | \-00.1 ATI Technologies Inc Redwood HDMI Audio [Radeon HD 5600 Series] [1002:aa60] +-09.0-[02]----00.0 Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller [10ec:8168] +-0a.0-[03]----00.0 NEC Corporation uPD720200 USB 3.0 Host Controller [1033:0194] +-11.0 ATI Technologies Inc SB7x0/SB8x0/SB9x0 SATA Controller [IDE mode] [1002:4390] +-12.0 ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB OHCI0 Controller [1002:4397] +-12.1 ATI Technologies Inc SB7x0 USB OHCI1 Controller [1002:4398] +-12.2 ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB EHCI Controller [1002:4396] +-13.0 ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB OHCI0 Controller [1002:4397] +-13.1 ATI Technologies Inc SB7x0 USB OHCI1 Controller [1002:4398] +-13.2 ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB EHCI Controller [1002:4396] +-14.0 ATI Technologies Inc SBx00 SMBus Controller [1002:4385] +-14.1 ATI Technologies Inc SB7x0/SB8x0/SB9x0 IDE Controller [1002:439c] +-14.2 ATI Technologies Inc SBx00 Azalia (Intel HDA) [1002:4383] +-14.3 ATI Technologies Inc SB7x0/SB8x0/SB9x0 LPC host controller [1002:439d] +-14.4-[04]--+-05.0 Ralink corp. RT2760 Wireless 802.11n 1T/2R Cardbus [1814:0701] | \-08.0 VIA Technologies, Inc. VT6306/7/8 [Fire II(M)] IEEE 1394 OHCI Controller [1106:3044] +-14.5 ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB OHCI2 Controller [1002:4399] +-18.0 Advanced Micro Devices [AMD] Family 10h Processor HyperTransport Configuration [1022:1200] +-18.1 Advanced Micro Devices [AMD] Family 10h Processor Address Map [1022:1201] +-18.2 Advanced Micro Devices [AMD] Family 10h Processor DRAM Controller [1022:1202] +-18.3 Advanced Micro Devices [AMD] Family 10h Processor Miscellaneous Control [1022:1203] \-18.4 Advanced Micro Devices [AMD] Family 10h Processor Link Control [1022:1204] ~$ *superistool -dV *output: ~# superiotool -dV superiotool r6637 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=standard) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x2e... Found ITE IT8721F (id=0x8721, rev=0x3) at 0x2e No dump available for this Super I/O Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x164e... Failed. Returned data: port=0xff, port+1=0xff Probing for Nuvoton Super I/O at 0x164e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x164e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for Nuvoton Super I/O at 0x2e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x2e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for Nuvoton Super I/O at 0x4e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x4e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for VIA Super I/O at 0x3f0... PCI device 1106:0686 not found. Probing for Server Engines Super I/O at 0x2e... Failed. Returned data: id=0xffff, rev=0xff ~# *flashrom -V *output: ~# flashrom -V flashrom v0.9.4-r1394 on Linux 3.0.0-14-generic (x86_64), built with libpci 3.1.7, GCC 4.6.1, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1907M loops per second, 10 myus = 10 us, 100 myus = 99 us, 1000 myus = 997 us, 10000 myus = 9984 us, 4 myus = 14 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "System manufacturer" DMI string system-product-name: "System Product Name" DMI string system-version: "System Version" DMI string baseboard-manufacturer: "ASUSTeK Computer INC." DMI string baseboard-product-name: "M4A88T-V EVO/USB3" DMI string baseboard-version: "Rev X.0x" DMI string chassis-type: "Desktop" Found ITE Super I/O, ID 0x8721 on port 0x2e Found chipset "AMD SB700/SB710/SB750/SB850" with PCI ID 1002:439d. Enabling flash write... SPI base address is at 0xfec10000 AltSpiCSEnable=0, SpiRomEnable=1, AbortEnable=0 PrefetchEnSPIFromIMC=0, PrefetchEnSPIFromHost=1, SpiOpEnInLpcMode=1 SpiArbEnable=1, SpiAccessMacRomEn=1, SpiHostAccessRomEn=1, ArbWaitCount=4, SpiBridgeDisable=1, DropOneClkOnRd=0 NormSpeed is 33 MHz GPIO11 used for SPI_DO GPIO12 used for SPI_DI GPIO31 used for SPI_HOLD GPIO32 used for SPI_CS GPIO47 used for SPI_CLK SB700 IMC is not active. ROM strap override is not active OK. This chipset supports the following protocols: LPC, FWH, SPI. Super I/O ID 0x8721 is not on the list of flash capable controllers. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0x03, id2 0x99, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Atmel AT25DF641, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Chip status register is 00 Found Eon flash chip "EN25F16" (2048 kB, SPI) at physical address 0xffe00000. Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x03, id2 0x99, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xd8, id2 0xb1, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x03, id2 0x99, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for SST SST25VF010.REMS, 128 kB: probe_spi_rems: id1 0x1c, id2 0x14 Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for SST SST25VF040.REMS, 512 kB: probe_spi_rems: id1 0x1c, id2 0x14 Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for SST SST25LF040A.RES, 512 kB: probe_spi_res2: id1 0x14, id2 0x14 Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0x1c, id2 0x14 Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xd8, id2 0xb1, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x74, id2 0xd9, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x03, id2 0x99, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x03, id2 0x99, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0xd8, id2 0xb1, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0xd8, id2 0xb1, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0x03, id2 0x99, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0x03, id2 0x99, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for ST M25P05.RES, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for ST M25P10.RES, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x03, id2 0x99, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x03, id2 0x99, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xd8, id2 0xb1, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x03, id2 0x99, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0x03, id2 0x99, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0x03, id2 0x99, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0x03, id2 0x99, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x03, id2 0x99, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x03, id2 0x99, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x03, id2 0x99, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0xd8, id2 0xb1, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xd8, id2 0xb1, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x03, id2 0x99, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0x1c, id2 0x3115 Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0x1c, id2 0x14 === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! No operations were specified. ~#

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Patch set updated for coreboot: 1ba80c2 F14 mainboard: mptable update
by Kerry Sheh 22 Dec '11

22 Dec '11

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/451 -gerrit commit 1ba80c2a084e3403fc7ce06c487e0a97316b668e Author: Kerry Sheh <shekairui(a)gmail.com> Date: Thu Dec 22 12:18:26 2011 +0800 F14 mainboard: mptable update Add GNB internal graphic interrupt, correct southbridge hd audio device interrupt. and remove the dead code already commented out. south_station, union_station, inagua, persimmon and e350m1 mainboard are included herein. Change-Id: Ic7618d80e0432ed0e22d1c16e1adb8ba6cea2e59 Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> --- src/mainboard/amd/inagua/mptable.c | 10 +++++++--- src/mainboard/amd/persimmon/mptable.c | 8 +++++--- src/mainboard/amd/south_station/mptable.c | 8 +++++--- src/mainboard/amd/union_station/mptable.c | 8 +++++--- src/mainboard/asrock/e350m1/mptable.c | 8 +++++--- 5 files changed, 27 insertions(+), 15 deletions(-) diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c index 7278936..73d946c 100644 --- a/src/mainboard/amd/inagua/mptable.c +++ b/src/mainboard/amd/inagua/mptable.c @@ -166,11 +166,15 @@ static void *smp_write_config_table(void *v) #define PCI_INT(bus, dev, int_sign, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb800, (pin)) + /* APU Internal Graphic Device*/ + PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + /* SMBUS */ PCI_INT(0x0, 0x14, 0x0, 0x10); - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); + /* Southbridge HD Audio */ + PCI_INT(0x0, 0x14, 0x2, intr_data[0x13]); /* USB */ PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); @@ -179,7 +183,7 @@ static void *smp_write_config_table(void *v) PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); + PCI_INT(0x0, 0x14, 0x5, intr_data[0x36]); /* sata */ PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c index 92c842f..18a7707 100644 --- a/src/mainboard/amd/persimmon/mptable.c +++ b/src/mainboard/amd/persimmon/mptable.c @@ -90,9 +90,13 @@ static void *smp_write_config_table(void *v) #define PCI_INT(bus, dev, fn, pin) #endif + /* APU Internal Graphic Device*/ + PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ PCI_INT(0x0, 0x14, 0x0, 0x10); - /* HD Audio: */ + /* Southbridge HD Audio: */ PCI_INT(0x0, 0x14, 0x2, 0x12); PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */ @@ -105,8 +109,6 @@ static void *smp_write_config_table(void *v) /* sata */ PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); - /* PCI_INT(0x0, 0x14, 0x2, 0x12); */ - /* on board NIC & Slot PCIE. */ /* PCI slots */ diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c index a3b4b5c..5c8ae5a 100644 --- a/src/mainboard/amd/south_station/mptable.c +++ b/src/mainboard/amd/south_station/mptable.c @@ -90,9 +90,13 @@ static void *smp_write_config_table(void *v) #define PCI_INT(bus, dev, fn, pin) #endif + /* APU Internal Graphic Device*/ + PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ PCI_INT(0x0, 0x14, 0x0, 0x10); - /* HD Audio: */ + /* Southbridge HD Audio: */ PCI_INT(0x0, 0x14, 0x2, 0x12); PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */ @@ -105,8 +109,6 @@ static void *smp_write_config_table(void *v) /* sata */ PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); - /* PCI_INT(0x0, 0x14, 0x2, 0x12); */ - /* on board NIC & Slot PCIE. */ /* PCI slots */ diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c index a3b4b5c..5c8ae5a 100644 --- a/src/mainboard/amd/union_station/mptable.c +++ b/src/mainboard/amd/union_station/mptable.c @@ -90,9 +90,13 @@ static void *smp_write_config_table(void *v) #define PCI_INT(bus, dev, fn, pin) #endif + /* APU Internal Graphic Device*/ + PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ PCI_INT(0x0, 0x14, 0x0, 0x10); - /* HD Audio: */ + /* Southbridge HD Audio: */ PCI_INT(0x0, 0x14, 0x2, 0x12); PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */ @@ -105,8 +109,6 @@ static void *smp_write_config_table(void *v) /* sata */ PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); - /* PCI_INT(0x0, 0x14, 0x2, 0x12); */ - /* on board NIC & Slot PCIE. */ /* PCI slots */ diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c index 960c2c8..de9d7f4 100644 --- a/src/mainboard/asrock/e350m1/mptable.c +++ b/src/mainboard/asrock/e350m1/mptable.c @@ -90,9 +90,13 @@ static void *smp_write_config_table(void *v) #define PCI_INT(bus, dev, fn, pin) #endif + /* APU Internal Graphic Device*/ + PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ PCI_INT(0x0, 0x14, 0x0, 0x10); - /* HD Audio: */ + /* Southbridge HD Audio: */ PCI_INT(0x0, 0x14, 0x2, 0x12); PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */ @@ -105,8 +109,6 @@ static void *smp_write_config_table(void *v) /* sata */ PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); - /* PCI_INT(0x0, 0x14, 0x2, 0x12); */ - /* on board NIC & Slot PCIE. */ /* PCI slots */

1 0

Patch set updated for coreboot: 42bde27 F14 mainboard: update acpi interrupt routing in pic and apic mode
by Kerry Sheh 22 Dec '11

22 Dec '11

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/452 -gerrit commit 42bde27e1474bd45ef0d727ef7a874f1eebfd3ab Author: Kerry Sheh <shekairui(a)gmail.com> Date: Thu Dec 22 12:18:37 2011 +0800 F14 mainboard: update acpi interrupt routing in pic and apic mode Add interrupt routing for APU GNB internal Graphic and HD audio device, and other pcie bridge device in GNB. south_station, union_station, inagua, persimmon and e350m1 mainboard are included herein. Change-Id: I4b6e0fce8d34637c03de8ebfdadea008c98e193b Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> --- src/mainboard/amd/inagua/acpi/routing.asl | 59 ++++++++++++--------- src/mainboard/amd/persimmon/acpi/routing.asl | 59 ++++++++++++--------- src/mainboard/amd/south_station/acpi/routing.asl | 59 ++++++++++++--------- src/mainboard/amd/union_station/acpi/routing.asl | 59 ++++++++++++--------- src/mainboard/asrock/e350m1/acpi/routing.asl | 59 ++++++++++++--------- 5 files changed, 170 insertions(+), 125 deletions(-) diff --git a/src/mainboard/amd/inagua/acpi/routing.asl b/src/mainboard/amd/inagua/acpi/routing.asl index cb50394..d7e4687 100644 --- a/src/mainboard/amd/inagua/acpi/routing.asl +++ b/src/mainboard/amd/inagua/acpi/routing.asl @@ -31,22 +31,28 @@ Scope(\_SB) { /* NB devices */ /* Bus 0, Dev 0 - RS780 Host Controller */ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + Package(){0x0001FFFF, 0, INTC, 0 }, + Package(){0x0001FFFF, 1, INTD, 0 }, /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ Package(){0x0002FFFF, 0, INTC, 0 }, Package(){0x0002FFFF, 1, INTD, 0 }, Package(){0x0002FFFF, 2, INTA, 0 }, Package(){0x0002FFFF, 3, INTB, 0 }, /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + Package(){0x0003FFFF, 0, INTD, 0 }, + Package(){0x0003FFFF, 1, INTA, 0 }, + Package(){0x0003FFFF, 2, INTB, 0 }, + Package(){0x0003FFFF, 3, INTC, 0 }, /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ Package(){0x0004FFFF, 0, INTA, 0 }, Package(){0x0004FFFF, 1, INTB, 0 }, Package(){0x0004FFFF, 2, INTC, 0 }, Package(){0x0004FFFF, 3, INTD, 0 }, /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, INTB, 0 }, */ - /* Package(){0x0005FFFF, 1, INTC, 0 }, */ - /* Package(){0x0005FFFF, 2, INTD, 0 }, */ - /* Package(){0x0005FFFF, 3, INTA, 0 }, */ + Package(){0x0005FFFF, 0, INTB, 0 }, + Package(){0x0005FFFF, 1, INTC, 0 }, + Package(){0x0005FFFF, 2, INTD, 0 }, + Package(){0x0005FFFF, 3, INTA, 0 }, /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ Package(){0x0006FFFF, 0, INTC, 0 }, Package(){0x0006FFFF, 1, INTD, 0 }, @@ -126,41 +132,44 @@ Scope(\_SB) { /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ Package(){0x0003FFFF, 0, 0, 19 }, + Package(){0x0003FFFF, 1, 0, 16 }, + Package(){0x0003FFFF, 2, 0, 17 }, + Package(){0x0003FFFF, 3, 0, 18 }, /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ Package(){0x0004FFFF, 0, 0, 16 }, - /* Package(){0x0004FFFF, 1, 0, 17 }, */ - /* Package(){0x0004FFFF, 2, 0, 18 }, */ - /* Package(){0x0004FFFF, 3, 0, 19 }, */ + Package(){0x0004FFFF, 1, 0, 17 }, + Package(){0x0004FFFF, 2, 0, 18 }, + Package(){0x0004FFFF, 3, 0, 19 }, /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, 0, 17 }, */ - /* Package(){0x0005FFFF, 1, 0, 18 }, */ - /* Package(){0x0005FFFF, 2, 0, 19 }, */ - /* Package(){0x0005FFFF, 3, 0, 16 }, */ + Package(){0x0005FFFF, 0, 0, 17 }, + Package(){0x0005FFFF, 1, 0, 18 }, + Package(){0x0005FFFF, 2, 0, 19 }, + Package(){0x0005FFFF, 3, 0, 16 }, /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - /* Package(){0x0006FFFF, 0, 0, 18 }, */ - /* Package(){0x0006FFFF, 1, 0, 19 }, */ - /* Package(){0x0006FFFF, 2, 0, 16 }, */ - /* Package(){0x0006FFFF, 3, 0, 17 }, */ + Package(){0x0006FFFF, 0, 0, 18 }, + Package(){0x0006FFFF, 1, 0, 19 }, + Package(){0x0006FFFF, 2, 0, 16 }, + Package(){0x0006FFFF, 3, 0, 17 }, /* Bus 0, Dev 7 - PCIe Bridge for network card */ - /* Package(){0x0007FFFF, 0, 0, 19 }, */ - /* Package(){0x0007FFFF, 1, 0, 16 }, */ - /* Package(){0x0007FFFF, 2, 0, 17 }, */ - /* Package(){0x0007FFFF, 3, 0, 18 }, */ + Package(){0x0007FFFF, 0, 0, 19 }, + Package(){0x0007FFFF, 1, 0, 16 }, + Package(){0x0007FFFF, 2, 0, 17 }, + Package(){0x0007FFFF, 3, 0, 18 }, /* Bus 0, Dev 9 - PCIe Bridge for network card */ Package(){0x0009FFFF, 0, 0, 17 }, - /* Package(){0x0009FFFF, 1, 0, 16 }, */ - /* Package(){0x0009FFFF, 2, 0, 17 }, */ - /* Package(){0x0009FFFF, 3, 0, 18 }, */ + Package(){0x0009FFFF, 1, 0, 16 }, + Package(){0x0009FFFF, 2, 0, 17 }, + Package(){0x0009FFFF, 3, 0, 18 }, /* Bus 0, Dev A - PCIe Bridge for network card */ Package(){0x000AFFFF, 0, 0, 18 }, - /* Package(){0x000AFFFF, 1, 0, 16 }, */ - /* Package(){0x000AFFFF, 2, 0, 17 }, */ - /* Package(){0x000AFFFF, 3, 0, 18 }, */ + Package(){0x000AFFFF, 1, 0, 16 }, + Package(){0x000AFFFF, 2, 0, 17 }, + Package(){0x000AFFFF, 3, 0, 18 }, /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ /* SB devices in APIC mode */ diff --git a/src/mainboard/amd/persimmon/acpi/routing.asl b/src/mainboard/amd/persimmon/acpi/routing.asl index cb50394..d7e4687 100644 --- a/src/mainboard/amd/persimmon/acpi/routing.asl +++ b/src/mainboard/amd/persimmon/acpi/routing.asl @@ -31,22 +31,28 @@ Scope(\_SB) { /* NB devices */ /* Bus 0, Dev 0 - RS780 Host Controller */ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + Package(){0x0001FFFF, 0, INTC, 0 }, + Package(){0x0001FFFF, 1, INTD, 0 }, /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ Package(){0x0002FFFF, 0, INTC, 0 }, Package(){0x0002FFFF, 1, INTD, 0 }, Package(){0x0002FFFF, 2, INTA, 0 }, Package(){0x0002FFFF, 3, INTB, 0 }, /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + Package(){0x0003FFFF, 0, INTD, 0 }, + Package(){0x0003FFFF, 1, INTA, 0 }, + Package(){0x0003FFFF, 2, INTB, 0 }, + Package(){0x0003FFFF, 3, INTC, 0 }, /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ Package(){0x0004FFFF, 0, INTA, 0 }, Package(){0x0004FFFF, 1, INTB, 0 }, Package(){0x0004FFFF, 2, INTC, 0 }, Package(){0x0004FFFF, 3, INTD, 0 }, /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, INTB, 0 }, */ - /* Package(){0x0005FFFF, 1, INTC, 0 }, */ - /* Package(){0x0005FFFF, 2, INTD, 0 }, */ - /* Package(){0x0005FFFF, 3, INTA, 0 }, */ + Package(){0x0005FFFF, 0, INTB, 0 }, + Package(){0x0005FFFF, 1, INTC, 0 }, + Package(){0x0005FFFF, 2, INTD, 0 }, + Package(){0x0005FFFF, 3, INTA, 0 }, /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ Package(){0x0006FFFF, 0, INTC, 0 }, Package(){0x0006FFFF, 1, INTD, 0 }, @@ -126,41 +132,44 @@ Scope(\_SB) { /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ Package(){0x0003FFFF, 0, 0, 19 }, + Package(){0x0003FFFF, 1, 0, 16 }, + Package(){0x0003FFFF, 2, 0, 17 }, + Package(){0x0003FFFF, 3, 0, 18 }, /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ Package(){0x0004FFFF, 0, 0, 16 }, - /* Package(){0x0004FFFF, 1, 0, 17 }, */ - /* Package(){0x0004FFFF, 2, 0, 18 }, */ - /* Package(){0x0004FFFF, 3, 0, 19 }, */ + Package(){0x0004FFFF, 1, 0, 17 }, + Package(){0x0004FFFF, 2, 0, 18 }, + Package(){0x0004FFFF, 3, 0, 19 }, /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, 0, 17 }, */ - /* Package(){0x0005FFFF, 1, 0, 18 }, */ - /* Package(){0x0005FFFF, 2, 0, 19 }, */ - /* Package(){0x0005FFFF, 3, 0, 16 }, */ + Package(){0x0005FFFF, 0, 0, 17 }, + Package(){0x0005FFFF, 1, 0, 18 }, + Package(){0x0005FFFF, 2, 0, 19 }, + Package(){0x0005FFFF, 3, 0, 16 }, /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - /* Package(){0x0006FFFF, 0, 0, 18 }, */ - /* Package(){0x0006FFFF, 1, 0, 19 }, */ - /* Package(){0x0006FFFF, 2, 0, 16 }, */ - /* Package(){0x0006FFFF, 3, 0, 17 }, */ + Package(){0x0006FFFF, 0, 0, 18 }, + Package(){0x0006FFFF, 1, 0, 19 }, + Package(){0x0006FFFF, 2, 0, 16 }, + Package(){0x0006FFFF, 3, 0, 17 }, /* Bus 0, Dev 7 - PCIe Bridge for network card */ - /* Package(){0x0007FFFF, 0, 0, 19 }, */ - /* Package(){0x0007FFFF, 1, 0, 16 }, */ - /* Package(){0x0007FFFF, 2, 0, 17 }, */ - /* Package(){0x0007FFFF, 3, 0, 18 }, */ + Package(){0x0007FFFF, 0, 0, 19 }, + Package(){0x0007FFFF, 1, 0, 16 }, + Package(){0x0007FFFF, 2, 0, 17 }, + Package(){0x0007FFFF, 3, 0, 18 }, /* Bus 0, Dev 9 - PCIe Bridge for network card */ Package(){0x0009FFFF, 0, 0, 17 }, - /* Package(){0x0009FFFF, 1, 0, 16 }, */ - /* Package(){0x0009FFFF, 2, 0, 17 }, */ - /* Package(){0x0009FFFF, 3, 0, 18 }, */ + Package(){0x0009FFFF, 1, 0, 16 }, + Package(){0x0009FFFF, 2, 0, 17 }, + Package(){0x0009FFFF, 3, 0, 18 }, /* Bus 0, Dev A - PCIe Bridge for network card */ Package(){0x000AFFFF, 0, 0, 18 }, - /* Package(){0x000AFFFF, 1, 0, 16 }, */ - /* Package(){0x000AFFFF, 2, 0, 17 }, */ - /* Package(){0x000AFFFF, 3, 0, 18 }, */ + Package(){0x000AFFFF, 1, 0, 16 }, + Package(){0x000AFFFF, 2, 0, 17 }, + Package(){0x000AFFFF, 3, 0, 18 }, /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ /* SB devices in APIC mode */ diff --git a/src/mainboard/amd/south_station/acpi/routing.asl b/src/mainboard/amd/south_station/acpi/routing.asl index cb50394..d7e4687 100644 --- a/src/mainboard/amd/south_station/acpi/routing.asl +++ b/src/mainboard/amd/south_station/acpi/routing.asl @@ -31,22 +31,28 @@ Scope(\_SB) { /* NB devices */ /* Bus 0, Dev 0 - RS780 Host Controller */ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + Package(){0x0001FFFF, 0, INTC, 0 }, + Package(){0x0001FFFF, 1, INTD, 0 }, /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ Package(){0x0002FFFF, 0, INTC, 0 }, Package(){0x0002FFFF, 1, INTD, 0 }, Package(){0x0002FFFF, 2, INTA, 0 }, Package(){0x0002FFFF, 3, INTB, 0 }, /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + Package(){0x0003FFFF, 0, INTD, 0 }, + Package(){0x0003FFFF, 1, INTA, 0 }, + Package(){0x0003FFFF, 2, INTB, 0 }, + Package(){0x0003FFFF, 3, INTC, 0 }, /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ Package(){0x0004FFFF, 0, INTA, 0 }, Package(){0x0004FFFF, 1, INTB, 0 }, Package(){0x0004FFFF, 2, INTC, 0 }, Package(){0x0004FFFF, 3, INTD, 0 }, /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, INTB, 0 }, */ - /* Package(){0x0005FFFF, 1, INTC, 0 }, */ - /* Package(){0x0005FFFF, 2, INTD, 0 }, */ - /* Package(){0x0005FFFF, 3, INTA, 0 }, */ + Package(){0x0005FFFF, 0, INTB, 0 }, + Package(){0x0005FFFF, 1, INTC, 0 }, + Package(){0x0005FFFF, 2, INTD, 0 }, + Package(){0x0005FFFF, 3, INTA, 0 }, /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ Package(){0x0006FFFF, 0, INTC, 0 }, Package(){0x0006FFFF, 1, INTD, 0 }, @@ -126,41 +132,44 @@ Scope(\_SB) { /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ Package(){0x0003FFFF, 0, 0, 19 }, + Package(){0x0003FFFF, 1, 0, 16 }, + Package(){0x0003FFFF, 2, 0, 17 }, + Package(){0x0003FFFF, 3, 0, 18 }, /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ Package(){0x0004FFFF, 0, 0, 16 }, - /* Package(){0x0004FFFF, 1, 0, 17 }, */ - /* Package(){0x0004FFFF, 2, 0, 18 }, */ - /* Package(){0x0004FFFF, 3, 0, 19 }, */ + Package(){0x0004FFFF, 1, 0, 17 }, + Package(){0x0004FFFF, 2, 0, 18 }, + Package(){0x0004FFFF, 3, 0, 19 }, /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, 0, 17 }, */ - /* Package(){0x0005FFFF, 1, 0, 18 }, */ - /* Package(){0x0005FFFF, 2, 0, 19 }, */ - /* Package(){0x0005FFFF, 3, 0, 16 }, */ + Package(){0x0005FFFF, 0, 0, 17 }, + Package(){0x0005FFFF, 1, 0, 18 }, + Package(){0x0005FFFF, 2, 0, 19 }, + Package(){0x0005FFFF, 3, 0, 16 }, /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - /* Package(){0x0006FFFF, 0, 0, 18 }, */ - /* Package(){0x0006FFFF, 1, 0, 19 }, */ - /* Package(){0x0006FFFF, 2, 0, 16 }, */ - /* Package(){0x0006FFFF, 3, 0, 17 }, */ + Package(){0x0006FFFF, 0, 0, 18 }, + Package(){0x0006FFFF, 1, 0, 19 }, + Package(){0x0006FFFF, 2, 0, 16 }, + Package(){0x0006FFFF, 3, 0, 17 }, /* Bus 0, Dev 7 - PCIe Bridge for network card */ - /* Package(){0x0007FFFF, 0, 0, 19 }, */ - /* Package(){0x0007FFFF, 1, 0, 16 }, */ - /* Package(){0x0007FFFF, 2, 0, 17 }, */ - /* Package(){0x0007FFFF, 3, 0, 18 }, */ + Package(){0x0007FFFF, 0, 0, 19 }, + Package(){0x0007FFFF, 1, 0, 16 }, + Package(){0x0007FFFF, 2, 0, 17 }, + Package(){0x0007FFFF, 3, 0, 18 }, /* Bus 0, Dev 9 - PCIe Bridge for network card */ Package(){0x0009FFFF, 0, 0, 17 }, - /* Package(){0x0009FFFF, 1, 0, 16 }, */ - /* Package(){0x0009FFFF, 2, 0, 17 }, */ - /* Package(){0x0009FFFF, 3, 0, 18 }, */ + Package(){0x0009FFFF, 1, 0, 16 }, + Package(){0x0009FFFF, 2, 0, 17 }, + Package(){0x0009FFFF, 3, 0, 18 }, /* Bus 0, Dev A - PCIe Bridge for network card */ Package(){0x000AFFFF, 0, 0, 18 }, - /* Package(){0x000AFFFF, 1, 0, 16 }, */ - /* Package(){0x000AFFFF, 2, 0, 17 }, */ - /* Package(){0x000AFFFF, 3, 0, 18 }, */ + Package(){0x000AFFFF, 1, 0, 16 }, + Package(){0x000AFFFF, 2, 0, 17 }, + Package(){0x000AFFFF, 3, 0, 18 }, /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ /* SB devices in APIC mode */ diff --git a/src/mainboard/amd/union_station/acpi/routing.asl b/src/mainboard/amd/union_station/acpi/routing.asl index cb50394..d7e4687 100644 --- a/src/mainboard/amd/union_station/acpi/routing.asl +++ b/src/mainboard/amd/union_station/acpi/routing.asl @@ -31,22 +31,28 @@ Scope(\_SB) { /* NB devices */ /* Bus 0, Dev 0 - RS780 Host Controller */ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + Package(){0x0001FFFF, 0, INTC, 0 }, + Package(){0x0001FFFF, 1, INTD, 0 }, /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ Package(){0x0002FFFF, 0, INTC, 0 }, Package(){0x0002FFFF, 1, INTD, 0 }, Package(){0x0002FFFF, 2, INTA, 0 }, Package(){0x0002FFFF, 3, INTB, 0 }, /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + Package(){0x0003FFFF, 0, INTD, 0 }, + Package(){0x0003FFFF, 1, INTA, 0 }, + Package(){0x0003FFFF, 2, INTB, 0 }, + Package(){0x0003FFFF, 3, INTC, 0 }, /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ Package(){0x0004FFFF, 0, INTA, 0 }, Package(){0x0004FFFF, 1, INTB, 0 }, Package(){0x0004FFFF, 2, INTC, 0 }, Package(){0x0004FFFF, 3, INTD, 0 }, /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, INTB, 0 }, */ - /* Package(){0x0005FFFF, 1, INTC, 0 }, */ - /* Package(){0x0005FFFF, 2, INTD, 0 }, */ - /* Package(){0x0005FFFF, 3, INTA, 0 }, */ + Package(){0x0005FFFF, 0, INTB, 0 }, + Package(){0x0005FFFF, 1, INTC, 0 }, + Package(){0x0005FFFF, 2, INTD, 0 }, + Package(){0x0005FFFF, 3, INTA, 0 }, /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ Package(){0x0006FFFF, 0, INTC, 0 }, Package(){0x0006FFFF, 1, INTD, 0 }, @@ -126,41 +132,44 @@ Scope(\_SB) { /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ Package(){0x0003FFFF, 0, 0, 19 }, + Package(){0x0003FFFF, 1, 0, 16 }, + Package(){0x0003FFFF, 2, 0, 17 }, + Package(){0x0003FFFF, 3, 0, 18 }, /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ Package(){0x0004FFFF, 0, 0, 16 }, - /* Package(){0x0004FFFF, 1, 0, 17 }, */ - /* Package(){0x0004FFFF, 2, 0, 18 }, */ - /* Package(){0x0004FFFF, 3, 0, 19 }, */ + Package(){0x0004FFFF, 1, 0, 17 }, + Package(){0x0004FFFF, 2, 0, 18 }, + Package(){0x0004FFFF, 3, 0, 19 }, /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, 0, 17 }, */ - /* Package(){0x0005FFFF, 1, 0, 18 }, */ - /* Package(){0x0005FFFF, 2, 0, 19 }, */ - /* Package(){0x0005FFFF, 3, 0, 16 }, */ + Package(){0x0005FFFF, 0, 0, 17 }, + Package(){0x0005FFFF, 1, 0, 18 }, + Package(){0x0005FFFF, 2, 0, 19 }, + Package(){0x0005FFFF, 3, 0, 16 }, /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - /* Package(){0x0006FFFF, 0, 0, 18 }, */ - /* Package(){0x0006FFFF, 1, 0, 19 }, */ - /* Package(){0x0006FFFF, 2, 0, 16 }, */ - /* Package(){0x0006FFFF, 3, 0, 17 }, */ + Package(){0x0006FFFF, 0, 0, 18 }, + Package(){0x0006FFFF, 1, 0, 19 }, + Package(){0x0006FFFF, 2, 0, 16 }, + Package(){0x0006FFFF, 3, 0, 17 }, /* Bus 0, Dev 7 - PCIe Bridge for network card */ - /* Package(){0x0007FFFF, 0, 0, 19 }, */ - /* Package(){0x0007FFFF, 1, 0, 16 }, */ - /* Package(){0x0007FFFF, 2, 0, 17 }, */ - /* Package(){0x0007FFFF, 3, 0, 18 }, */ + Package(){0x0007FFFF, 0, 0, 19 }, + Package(){0x0007FFFF, 1, 0, 16 }, + Package(){0x0007FFFF, 2, 0, 17 }, + Package(){0x0007FFFF, 3, 0, 18 }, /* Bus 0, Dev 9 - PCIe Bridge for network card */ Package(){0x0009FFFF, 0, 0, 17 }, - /* Package(){0x0009FFFF, 1, 0, 16 }, */ - /* Package(){0x0009FFFF, 2, 0, 17 }, */ - /* Package(){0x0009FFFF, 3, 0, 18 }, */ + Package(){0x0009FFFF, 1, 0, 16 }, + Package(){0x0009FFFF, 2, 0, 17 }, + Package(){0x0009FFFF, 3, 0, 18 }, /* Bus 0, Dev A - PCIe Bridge for network card */ Package(){0x000AFFFF, 0, 0, 18 }, - /* Package(){0x000AFFFF, 1, 0, 16 }, */ - /* Package(){0x000AFFFF, 2, 0, 17 }, */ - /* Package(){0x000AFFFF, 3, 0, 18 }, */ + Package(){0x000AFFFF, 1, 0, 16 }, + Package(){0x000AFFFF, 2, 0, 17 }, + Package(){0x000AFFFF, 3, 0, 18 }, /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ /* SB devices in APIC mode */ diff --git a/src/mainboard/asrock/e350m1/acpi/routing.asl b/src/mainboard/asrock/e350m1/acpi/routing.asl index cb50394..d7e4687 100644 --- a/src/mainboard/asrock/e350m1/acpi/routing.asl +++ b/src/mainboard/asrock/e350m1/acpi/routing.asl @@ -31,22 +31,28 @@ Scope(\_SB) { /* NB devices */ /* Bus 0, Dev 0 - RS780 Host Controller */ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + Package(){0x0001FFFF, 0, INTC, 0 }, + Package(){0x0001FFFF, 1, INTD, 0 }, /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ Package(){0x0002FFFF, 0, INTC, 0 }, Package(){0x0002FFFF, 1, INTD, 0 }, Package(){0x0002FFFF, 2, INTA, 0 }, Package(){0x0002FFFF, 3, INTB, 0 }, /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + Package(){0x0003FFFF, 0, INTD, 0 }, + Package(){0x0003FFFF, 1, INTA, 0 }, + Package(){0x0003FFFF, 2, INTB, 0 }, + Package(){0x0003FFFF, 3, INTC, 0 }, /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ Package(){0x0004FFFF, 0, INTA, 0 }, Package(){0x0004FFFF, 1, INTB, 0 }, Package(){0x0004FFFF, 2, INTC, 0 }, Package(){0x0004FFFF, 3, INTD, 0 }, /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, INTB, 0 }, */ - /* Package(){0x0005FFFF, 1, INTC, 0 }, */ - /* Package(){0x0005FFFF, 2, INTD, 0 }, */ - /* Package(){0x0005FFFF, 3, INTA, 0 }, */ + Package(){0x0005FFFF, 0, INTB, 0 }, + Package(){0x0005FFFF, 1, INTC, 0 }, + Package(){0x0005FFFF, 2, INTD, 0 }, + Package(){0x0005FFFF, 3, INTA, 0 }, /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ Package(){0x0006FFFF, 0, INTC, 0 }, Package(){0x0006FFFF, 1, INTD, 0 }, @@ -126,41 +132,44 @@ Scope(\_SB) { /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ Package(){0x0003FFFF, 0, 0, 19 }, + Package(){0x0003FFFF, 1, 0, 16 }, + Package(){0x0003FFFF, 2, 0, 17 }, + Package(){0x0003FFFF, 3, 0, 18 }, /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ Package(){0x0004FFFF, 0, 0, 16 }, - /* Package(){0x0004FFFF, 1, 0, 17 }, */ - /* Package(){0x0004FFFF, 2, 0, 18 }, */ - /* Package(){0x0004FFFF, 3, 0, 19 }, */ + Package(){0x0004FFFF, 1, 0, 17 }, + Package(){0x0004FFFF, 2, 0, 18 }, + Package(){0x0004FFFF, 3, 0, 19 }, /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, 0, 17 }, */ - /* Package(){0x0005FFFF, 1, 0, 18 }, */ - /* Package(){0x0005FFFF, 2, 0, 19 }, */ - /* Package(){0x0005FFFF, 3, 0, 16 }, */ + Package(){0x0005FFFF, 0, 0, 17 }, + Package(){0x0005FFFF, 1, 0, 18 }, + Package(){0x0005FFFF, 2, 0, 19 }, + Package(){0x0005FFFF, 3, 0, 16 }, /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - /* Package(){0x0006FFFF, 0, 0, 18 }, */ - /* Package(){0x0006FFFF, 1, 0, 19 }, */ - /* Package(){0x0006FFFF, 2, 0, 16 }, */ - /* Package(){0x0006FFFF, 3, 0, 17 }, */ + Package(){0x0006FFFF, 0, 0, 18 }, + Package(){0x0006FFFF, 1, 0, 19 }, + Package(){0x0006FFFF, 2, 0, 16 }, + Package(){0x0006FFFF, 3, 0, 17 }, /* Bus 0, Dev 7 - PCIe Bridge for network card */ - /* Package(){0x0007FFFF, 0, 0, 19 }, */ - /* Package(){0x0007FFFF, 1, 0, 16 }, */ - /* Package(){0x0007FFFF, 2, 0, 17 }, */ - /* Package(){0x0007FFFF, 3, 0, 18 }, */ + Package(){0x0007FFFF, 0, 0, 19 }, + Package(){0x0007FFFF, 1, 0, 16 }, + Package(){0x0007FFFF, 2, 0, 17 }, + Package(){0x0007FFFF, 3, 0, 18 }, /* Bus 0, Dev 9 - PCIe Bridge for network card */ Package(){0x0009FFFF, 0, 0, 17 }, - /* Package(){0x0009FFFF, 1, 0, 16 }, */ - /* Package(){0x0009FFFF, 2, 0, 17 }, */ - /* Package(){0x0009FFFF, 3, 0, 18 }, */ + Package(){0x0009FFFF, 1, 0, 16 }, + Package(){0x0009FFFF, 2, 0, 17 }, + Package(){0x0009FFFF, 3, 0, 18 }, /* Bus 0, Dev A - PCIe Bridge for network card */ Package(){0x000AFFFF, 0, 0, 18 }, - /* Package(){0x000AFFFF, 1, 0, 16 }, */ - /* Package(){0x000AFFFF, 2, 0, 17 }, */ - /* Package(){0x000AFFFF, 3, 0, 18 }, */ + Package(){0x000AFFFF, 1, 0, 16 }, + Package(){0x000AFFFF, 2, 0, 17 }, + Package(){0x000AFFFF, 3, 0, 18 }, /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ /* SB devices in APIC mode */

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Patch merged into coreboot/master: 7b5f093 south_station: Enable GNB hd audio
by gerrit＠coreboot.org 22 Dec '11

22 Dec '11

the following patch was just integrated into master: commit 7b5f093920dc0918eb620bac184588333e7ef7cc Author: Kerry Sheh <shekairui(a)gmail.com> Date: Wed Nov 23 15:04:13 2011 +0800 south_station: Enable GNB hd audio Enable HD audio over HDMI. Tested in Ubuntu-11.10 with ATI Catalyst Proprietary Driver installed. Change-Id: I013c2c15ee56a7b134d980da1aa1856778a1eb4c Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Build-Tested: build bot (Jenkins) at Wed Nov 23 07:43:19 2011, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Tue Dec 20 07:28:39 2011, giving +2 See http://review.coreboot.org/450 for details. -gerrit

1 0

Patch set updated for coreboot: ebfafa0 Cleanup needed to make coreboot converge with linux driver
by Philip Prindeville 21 Dec '11

21 Dec '11

Philip Prindeville (pprindeville(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/495 -gerrit commit ebfafa07bc5c92d4c14b890e245e57124d1b7edb Author: Philip Prindeville <philipp(a)redfish-solutions.com> Date: Wed Dec 21 13:29:53 2011 -0700 Cleanup needed to make coreboot converge with linux driver Having submitted changes upstream to add a linux kernel library for Coreboot, I was given a list of changes to make. While all good suggestions, they would have caused the linux version to diverge significantly with the original coreboot code from which it was cloned. Those changes are: * more use of inline functions rather than macros (they avoid typecasts); * convenience functions to access the motherboard vendor and part # from the parsed sysinfo. * use of void * for pointers to untyped memory; * eliminate unnecessary casts; * pass end-boundary of E820 memory region when parsing coreboot tables (in case of corruption); * add missing phys_to_virt() when handling FORWARD records; * save mainboard record pointer into sysinfo structure for later retrieval; * pass through return value from get_coreboot_info() in lib_get_sysinfo(); The fifth change merits some more detail: on some of the systems I develop on the CB table gets indirected to by a CB_FORWARD record. When the final table (and not the initial stub containing the CB_FORWARD) is found, it is tucked up in the last bytes of the E820 region. Passing 0x1000 as the length might not always be correct if the table begins at less than 0x1000 bytes from the end of that region. Explicitly passing in the region's end is a more accurate semantic. Change-Id: Iffe7061fa62fa639e0cb6ccb9125eb3403d06b1a Signed-off-by: Philip Prindeville <philipp(a)redfish-solutions.com> --- payloads/coreinfo/coreboot_module.c | 12 ++-- payloads/libpayload/arch/i386/coreboot.c | 66 +++++++++++++++---------- payloads/libpayload/arch/i386/sysinfo.c | 8 ++- payloads/libpayload/include/coreboot_tables.h | 33 ++++++++---- payloads/libpayload/include/libpayload.h | 2 +- payloads/libpayload/include/sysinfo.h | 3 + 6 files changed, 77 insertions(+), 47 deletions(-) diff --git a/payloads/coreinfo/coreboot_module.c b/payloads/coreinfo/coreboot_module.c index dd589ac..f298595 100644 --- a/payloads/coreinfo/coreboot_module.c +++ b/payloads/coreinfo/coreboot_module.c @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <coreboot_tables.h> #include "coreinfo.h" +#include <coreboot_tables.h> #ifdef CONFIG_MODULE_COREBOOT @@ -112,9 +112,9 @@ int coreboot_module_redraw(WINDOW *win) } wprintw(win, "%16.16llx - %16.16llx", - UNPACK_CB64(cb_info.range[i].start), - UNPACK_CB64(cb_info.range[i].start) + - UNPACK_CB64(cb_info.range[i].size) - 1); + cb_unpack64(cb_info.range[i].start), + cb_unpack64(cb_info.range[i].start) + + cb_unpack64(cb_info.range[i].size) - 1); } return 0; @@ -142,8 +142,8 @@ static void parse_mainboard(unsigned char *ptr) { struct cb_mainboard *mb = (struct cb_mainboard *)ptr; - strncpy(cb_info.vendor, (const char *)MB_VENDOR_STRING(mb), 31); - strncpy(cb_info.part, (const char *)MB_PART_STRING(mb), 31); + strncpy(cb_info.vendor, (const char *)cb_mb_vendor_string(mb), 31); + strncpy(cb_info.part, (const char *)cb_mb_part_string(mb), 31); } static void parse_strings(unsigned char *ptr) diff --git a/payloads/libpayload/arch/i386/coreboot.c b/payloads/libpayload/arch/i386/coreboot.c index 365445e..e49cba8 100644 --- a/payloads/libpayload/arch/i386/coreboot.c +++ b/payloads/libpayload/arch/i386/coreboot.c @@ -42,9 +42,9 @@ /* === Parsing code === */ /* This is the generic parsing code. */ -static void cb_parse_memory(unsigned char *ptr, struct sysinfo_t *info) +static void cb_parse_memory(void *ptr, struct sysinfo_t *info) { - struct cb_memory *mem = (struct cb_memory *)ptr; + struct cb_memory *mem = ptr; int count = MEM_RANGE_COUNT(mem); int i; @@ -54,8 +54,7 @@ static void cb_parse_memory(unsigned char *ptr, struct sysinfo_t *info) info->n_memranges = 0; for (i = 0; i < count; i++) { - struct cb_memory_range *range = - (struct cb_memory_range *)MEM_RANGE_PTR(mem, i); + struct cb_memory_range *range = MEM_RANGE_PTR(mem, i); #ifdef CONFIG_MEMMAP_RAM_ONLY if (range->type != CB_MEM_RAM) @@ -63,10 +62,10 @@ static void cb_parse_memory(unsigned char *ptr, struct sysinfo_t *info) #endif info->memrange[info->n_memranges].base = - UNPACK_CB64(range->start); + cb_unpack64(range->start); info->memrange[info->n_memranges].size = - UNPACK_CB64(range->size); + cb_unpack64(range->size); info->memrange[info->n_memranges].type = range->type; @@ -74,29 +73,29 @@ static void cb_parse_memory(unsigned char *ptr, struct sysinfo_t *info) } } -static void cb_parse_serial(unsigned char *ptr, struct sysinfo_t *info) +static void cb_parse_serial(void *ptr, struct sysinfo_t *info) { - struct cb_serial *ser = (struct cb_serial *)ptr; + struct cb_serial *ser = ptr; if (ser->type != CB_SERIAL_TYPE_IO_MAPPED) return; info->ser_ioport = ser->baseaddr; } -static void cb_parse_version(unsigned char *ptr, struct sysinfo_t *info) +static void cb_parse_version(void *ptr, struct sysinfo_t *info) { - struct cb_string *ver = (struct cb_string *)ptr; + struct cb_string *ver = ptr; info->cb_version = (char *)ver->string; } #ifdef CONFIG_NVRAM -static void cb_parse_optiontable(unsigned char *ptr, struct sysinfo_t *info) +static void cb_parse_optiontable(void *ptr, struct sysinfo_t *info) { - info->option_table = (struct cb_cmos_option_table *)ptr; + info->option_table = ptr; } -static void cb_parse_checksum(unsigned char *ptr, struct sysinfo_t *info) +static void cb_parse_checksum(void *ptr, struct sysinfo_t *info) { - struct cb_cmos_checksum *cmos_cksum = (struct cb_cmos_checksum *)ptr; + struct cb_cmos_checksum *cmos_cksum = ptr; info->cmos_range_start = cmos_cksum->range_start; info->cmos_range_end = cmos_cksum->range_end; info->cmos_checksum_location = cmos_cksum->location; @@ -104,39 +103,42 @@ static void cb_parse_checksum(unsigned char *ptr, struct sysinfo_t *info) #endif #ifdef CONFIG_COREBOOT_VIDEO_CONSOLE -static void cb_parse_framebuffer(unsigned char *ptr, struct sysinfo_t *info) +static void cb_parse_framebuffer(void *ptr, struct sysinfo_t *info) { - info->framebuffer = (struct cb_framebuffer *)ptr; + info->framebuffer = ptr; } #endif -static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) +static int cb_parse_header(void *addr, void *end, struct sysinfo_t *info) { struct cb_header *header; - unsigned char *ptr = (unsigned char *)addr; + unsigned char *ptr = addr; + void *forward; int i; - for (i = 0; i < len; i += 16, ptr += 16) { + for (i = 0; (void *)ptr < end; i += 16, ptr += 16) { header = (struct cb_header *)ptr; if (!strncmp((const char *)header->signature, "LBIO", 4)) break; } /* We walked the entire space and didn't find anything. */ - if (i >= len) + if ((void *)ptr >= end) return -1; if (!header->table_bytes) return 0; /* Make sure the checksums match. */ - if (ipchksum((u16 *) header, sizeof(*header)) != 0) + if (cb_checksum(header, sizeof(*header)) != 0) return -1; - if (ipchksum((u16 *) (ptr + sizeof(*header)), + if (cb_checksum((ptr + sizeof(*header)), header->table_bytes) != header->table_checksum) return -1; + info->header = header; + /* Now, walk the tables. */ ptr += header->header_bytes; @@ -146,8 +148,8 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) /* We only care about a few tags here (maybe more later). */ switch (rec->tag) { case CB_TAG_FORWARD: - return cb_parse_header((void *)(unsigned long)((struct cb_forward *)rec)->forward, len, info); - continue; + forward = phys_to_virt((void *)(unsigned long)((struct cb_forward *)rec)->forward); + return cb_parse_header(forward, forward + 0x1000, info); case CB_TAG_MEMORY: cb_parse_memory(ptr, info); break; @@ -172,9 +174,16 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) cb_parse_framebuffer(ptr, info); break; #endif + + case CB_TAG_MAINBOARD: + info->mainboard = (struct cb_mainboard *)ptr; + break; } ptr += rec->size; + + if ((void *)ptr >= end) + return -1; } return 1; @@ -185,10 +194,13 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) int get_coreboot_info(struct sysinfo_t *info) { - int ret = cb_parse_header(phys_to_virt(0x00000000), 0x1000, info); + void *base = phys_to_virt(0x00000000); + int ret = cb_parse_header(base, base + 0x1000, info); - if (ret != 1) - ret = cb_parse_header(phys_to_virt(0x000f0000), 0x1000, info); + if (ret != 1) { + base = phys_to_virt(0x000f0000); + ret = cb_parse_header(base, base + 0x1000, info); + } return (ret == 1) ? 0 : -1; } diff --git a/payloads/libpayload/arch/i386/sysinfo.c b/payloads/libpayload/arch/i386/sysinfo.c index 599a811..6c1ef3f 100644 --- a/payloads/libpayload/arch/i386/sysinfo.c +++ b/payloads/libpayload/arch/i386/sysinfo.c @@ -45,8 +45,10 @@ struct sysinfo_t lib_sysinfo = { #endif }; -void lib_get_sysinfo(void) +int lib_get_sysinfo(void) { + int ret; + /* Get the CPU speed (for delays). */ lib_sysinfo.cpu_khz = get_cpu_speed(); @@ -59,7 +61,7 @@ void lib_get_sysinfo(void) /* Get information from the coreboot tables, * if they exist */ - get_coreboot_info(&lib_sysinfo); + ret = get_coreboot_info(&lib_sysinfo); if (!lib_sysinfo.n_memranges) { /* If we can't get a good memory range, use the default. */ @@ -73,4 +75,6 @@ void lib_get_sysinfo(void) lib_sysinfo.memrange[1].size = 31 * 1024 * 1024; lib_sysinfo.memrange[1].type = CB_MEM_RAM; } + + return ret; } diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index d342c99..706e714 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -216,22 +216,33 @@ struct cb_cmos_checksum { u32 type; }; +static inline u16 cb_checksum(const void *ptr, unsigned len) +{ + return ipchksum(ptr, len); +} + +static inline const u8 *cb_mb_vendor_string(const struct cb_mainboard *cbm) +{ + return cbm->strings + cbm->vendor_idx; +} + +static inline const u8 *cb_mb_part_string(const struct cb_mainboard *cbm) +{ + return cbm->strings + cbm->part_number_idx; +} + +static inline u64 cb_unpack64(struct cbuint64 val) +{ + return (((u64) val.hi) << 32) | val.lo; +} + /* Helpful macros */ #define MEM_RANGE_COUNT(_rec) \ (((_rec)->size - sizeof(*(_rec))) / sizeof((_rec)->map[0])) #define MEM_RANGE_PTR(_rec, _idx) \ - (((u8 *) (_rec)) + sizeof(*(_rec)) \ - + (sizeof((_rec)->map[0]) * (_idx))) - -#define MB_VENDOR_STRING(_mb) \ - (((unsigned char *) ((_mb)->strings)) + (_mb)->vendor_idx) - -#define MB_PART_STRING(_mb) \ - (((unsigned char *) ((_mb)->strings)) + (_mb)->part_number_idx) - -#define UNPACK_CB64(_in) \ - ( (((u64) _in.hi) << 32) | _in.lo ) + (void *)(((u8 *) (_rec)) + sizeof(*(_rec)) \ + + (sizeof((_rec)->map[0]) * (_idx))) #endif diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 8c8abc4..d9f7d21 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -369,7 +369,7 @@ int sysinfo_have_multiboot(unsigned long *addr); int get_coreboot_info(struct sysinfo_t *info); int get_multiboot_info(struct sysinfo_t *info); -void lib_get_sysinfo(void); +int lib_get_sysinfo(void); /* Timer functions - defined by each architecture. */ unsigned int get_cpu_speed(void); diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index c1d2002..778dfe9 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -56,6 +56,9 @@ struct sysinfo_t { struct cb_framebuffer *framebuffer; unsigned long *mbtable; /** Pointer to the multiboot table */ + + struct cb_header *header; + struct cb_mainboard *mainboard; }; extern struct sysinfo_t lib_sysinfo;

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Patch merged into coreboot/master: b4145dc Add RS780 defaut graphics ID to AMD Mahogany mainboard.
by gerrit＠coreboot.org 21 Dec '11

21 Dec '11

the following patch was just integrated into master: commit b4145dcaed06d31ba8c85270e25b810448cd0ea1 Author: Marc Jones <marcj303(a)gmail.com> Date: Wed Dec 14 15:59:02 2011 -0700 Add RS780 defaut graphics ID to AMD Mahogany mainboard. Added the default ID to the mainboard Kconfig. Change-Id: Ie5d39ccdda9d4f5a86214b5bd9ca629070ff152a Signed-off-by: Marc Jones <marcj303(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Dec 21 08:51:51 2011, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Wed Dec 21 01:06:42 2011, giving +2 See http://review.coreboot.org/488 for details. -gerrit

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New patch to review for coreboot: 9451dd1 Cleanup needed to make coreboot converge with linux driver
by Philip Prindeville 21 Dec '11

21 Dec '11

Philip Prindeville (pprindeville(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/495 -gerrit commit 9451dd17a684e5a8e438fb541f52775ade0f5a40 Author: Philip Prindeville <philipp(a)redfish-solutions.com> Date: Wed Dec 21 13:29:53 2011 -0700 Cleanup needed to make coreboot converge with linux driver Having submitted changes upstream to add a linux kernel library for Coreboot, I was given a list of changes to make. While all good suggestions, they would have caused the linux version to diverge significantly with the original coreboot code from which it was cloned. Those changes are: * more use of inline functions rather than macros (they avoid typecasts); * convenience functions to access the motherboard vendor and part # from the parsed sysinfo. * use of void * for pointers to untyped memory; * eliminate unnecessary casts; * pass end-boundary of E820 memory region when parsing coreboot tables (in case of corruption); * add missing phys_to_virt() when handling FORWARD records; * save mainboard record pointer into sysinfo structure for later retrieval; * pass through return value from get_coreboot_info() in lib_get_sysinfo(); Change-Id: Iffe7061fa62fa639e0cb6ccb9125eb3403d06b1a Signed-off-by: Philip Prindeville <philipp(a)redfish-solutions.com> --- payloads/coreinfo/coreboot_module.c | 12 ++-- payloads/libpayload/arch/i386/coreboot.c | 66 +++++++++++++++---------- payloads/libpayload/arch/i386/sysinfo.c | 8 ++- payloads/libpayload/include/coreboot_tables.h | 33 ++++++++---- payloads/libpayload/include/libpayload.h | 2 +- payloads/libpayload/include/sysinfo.h | 3 + 6 files changed, 77 insertions(+), 47 deletions(-) diff --git a/payloads/coreinfo/coreboot_module.c b/payloads/coreinfo/coreboot_module.c index dd589ac..f298595 100644 --- a/payloads/coreinfo/coreboot_module.c +++ b/payloads/coreinfo/coreboot_module.c @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <coreboot_tables.h> #include "coreinfo.h" +#include <coreboot_tables.h> #ifdef CONFIG_MODULE_COREBOOT @@ -112,9 +112,9 @@ int coreboot_module_redraw(WINDOW *win) } wprintw(win, "%16.16llx - %16.16llx", - UNPACK_CB64(cb_info.range[i].start), - UNPACK_CB64(cb_info.range[i].start) + - UNPACK_CB64(cb_info.range[i].size) - 1); + cb_unpack64(cb_info.range[i].start), + cb_unpack64(cb_info.range[i].start) + + cb_unpack64(cb_info.range[i].size) - 1); } return 0; @@ -142,8 +142,8 @@ static void parse_mainboard(unsigned char *ptr) { struct cb_mainboard *mb = (struct cb_mainboard *)ptr; - strncpy(cb_info.vendor, (const char *)MB_VENDOR_STRING(mb), 31); - strncpy(cb_info.part, (const char *)MB_PART_STRING(mb), 31); + strncpy(cb_info.vendor, (const char *)cb_mb_vendor_string(mb), 31); + strncpy(cb_info.part, (const char *)cb_mb_part_string(mb), 31); } static void parse_strings(unsigned char *ptr) diff --git a/payloads/libpayload/arch/i386/coreboot.c b/payloads/libpayload/arch/i386/coreboot.c index 365445e..e49cba8 100644 --- a/payloads/libpayload/arch/i386/coreboot.c +++ b/payloads/libpayload/arch/i386/coreboot.c @@ -42,9 +42,9 @@ /* === Parsing code === */ /* This is the generic parsing code. */ -static void cb_parse_memory(unsigned char *ptr, struct sysinfo_t *info) +static void cb_parse_memory(void *ptr, struct sysinfo_t *info) { - struct cb_memory *mem = (struct cb_memory *)ptr; + struct cb_memory *mem = ptr; int count = MEM_RANGE_COUNT(mem); int i; @@ -54,8 +54,7 @@ static void cb_parse_memory(unsigned char *ptr, struct sysinfo_t *info) info->n_memranges = 0; for (i = 0; i < count; i++) { - struct cb_memory_range *range = - (struct cb_memory_range *)MEM_RANGE_PTR(mem, i); + struct cb_memory_range *range = MEM_RANGE_PTR(mem, i); #ifdef CONFIG_MEMMAP_RAM_ONLY if (range->type != CB_MEM_RAM) @@ -63,10 +62,10 @@ static void cb_parse_memory(unsigned char *ptr, struct sysinfo_t *info) #endif info->memrange[info->n_memranges].base = - UNPACK_CB64(range->start); + cb_unpack64(range->start); info->memrange[info->n_memranges].size = - UNPACK_CB64(range->size); + cb_unpack64(range->size); info->memrange[info->n_memranges].type = range->type; @@ -74,29 +73,29 @@ static void cb_parse_memory(unsigned char *ptr, struct sysinfo_t *info) } } -static void cb_parse_serial(unsigned char *ptr, struct sysinfo_t *info) +static void cb_parse_serial(void *ptr, struct sysinfo_t *info) { - struct cb_serial *ser = (struct cb_serial *)ptr; + struct cb_serial *ser = ptr; if (ser->type != CB_SERIAL_TYPE_IO_MAPPED) return; info->ser_ioport = ser->baseaddr; } -static void cb_parse_version(unsigned char *ptr, struct sysinfo_t *info) +static void cb_parse_version(void *ptr, struct sysinfo_t *info) { - struct cb_string *ver = (struct cb_string *)ptr; + struct cb_string *ver = ptr; info->cb_version = (char *)ver->string; } #ifdef CONFIG_NVRAM -static void cb_parse_optiontable(unsigned char *ptr, struct sysinfo_t *info) +static void cb_parse_optiontable(void *ptr, struct sysinfo_t *info) { - info->option_table = (struct cb_cmos_option_table *)ptr; + info->option_table = ptr; } -static void cb_parse_checksum(unsigned char *ptr, struct sysinfo_t *info) +static void cb_parse_checksum(void *ptr, struct sysinfo_t *info) { - struct cb_cmos_checksum *cmos_cksum = (struct cb_cmos_checksum *)ptr; + struct cb_cmos_checksum *cmos_cksum = ptr; info->cmos_range_start = cmos_cksum->range_start; info->cmos_range_end = cmos_cksum->range_end; info->cmos_checksum_location = cmos_cksum->location; @@ -104,39 +103,42 @@ static void cb_parse_checksum(unsigned char *ptr, struct sysinfo_t *info) #endif #ifdef CONFIG_COREBOOT_VIDEO_CONSOLE -static void cb_parse_framebuffer(unsigned char *ptr, struct sysinfo_t *info) +static void cb_parse_framebuffer(void *ptr, struct sysinfo_t *info) { - info->framebuffer = (struct cb_framebuffer *)ptr; + info->framebuffer = ptr; } #endif -static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) +static int cb_parse_header(void *addr, void *end, struct sysinfo_t *info) { struct cb_header *header; - unsigned char *ptr = (unsigned char *)addr; + unsigned char *ptr = addr; + void *forward; int i; - for (i = 0; i < len; i += 16, ptr += 16) { + for (i = 0; (void *)ptr < end; i += 16, ptr += 16) { header = (struct cb_header *)ptr; if (!strncmp((const char *)header->signature, "LBIO", 4)) break; } /* We walked the entire space and didn't find anything. */ - if (i >= len) + if ((void *)ptr >= end) return -1; if (!header->table_bytes) return 0; /* Make sure the checksums match. */ - if (ipchksum((u16 *) header, sizeof(*header)) != 0) + if (cb_checksum(header, sizeof(*header)) != 0) return -1; - if (ipchksum((u16 *) (ptr + sizeof(*header)), + if (cb_checksum((ptr + sizeof(*header)), header->table_bytes) != header->table_checksum) return -1; + info->header = header; + /* Now, walk the tables. */ ptr += header->header_bytes; @@ -146,8 +148,8 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) /* We only care about a few tags here (maybe more later). */ switch (rec->tag) { case CB_TAG_FORWARD: - return cb_parse_header((void *)(unsigned long)((struct cb_forward *)rec)->forward, len, info); - continue; + forward = phys_to_virt((void *)(unsigned long)((struct cb_forward *)rec)->forward); + return cb_parse_header(forward, forward + 0x1000, info); case CB_TAG_MEMORY: cb_parse_memory(ptr, info); break; @@ -172,9 +174,16 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) cb_parse_framebuffer(ptr, info); break; #endif + + case CB_TAG_MAINBOARD: + info->mainboard = (struct cb_mainboard *)ptr; + break; } ptr += rec->size; + + if ((void *)ptr >= end) + return -1; } return 1; @@ -185,10 +194,13 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) int get_coreboot_info(struct sysinfo_t *info) { - int ret = cb_parse_header(phys_to_virt(0x00000000), 0x1000, info); + void *base = phys_to_virt(0x00000000); + int ret = cb_parse_header(base, base + 0x1000, info); - if (ret != 1) - ret = cb_parse_header(phys_to_virt(0x000f0000), 0x1000, info); + if (ret != 1) { + base = phys_to_virt(0x000f0000); + ret = cb_parse_header(base, base + 0x1000, info); + } return (ret == 1) ? 0 : -1; } diff --git a/payloads/libpayload/arch/i386/sysinfo.c b/payloads/libpayload/arch/i386/sysinfo.c index 599a811..6c1ef3f 100644 --- a/payloads/libpayload/arch/i386/sysinfo.c +++ b/payloads/libpayload/arch/i386/sysinfo.c @@ -45,8 +45,10 @@ struct sysinfo_t lib_sysinfo = { #endif }; -void lib_get_sysinfo(void) +int lib_get_sysinfo(void) { + int ret; + /* Get the CPU speed (for delays). */ lib_sysinfo.cpu_khz = get_cpu_speed(); @@ -59,7 +61,7 @@ void lib_get_sysinfo(void) /* Get information from the coreboot tables, * if they exist */ - get_coreboot_info(&lib_sysinfo); + ret = get_coreboot_info(&lib_sysinfo); if (!lib_sysinfo.n_memranges) { /* If we can't get a good memory range, use the default. */ @@ -73,4 +75,6 @@ void lib_get_sysinfo(void) lib_sysinfo.memrange[1].size = 31 * 1024 * 1024; lib_sysinfo.memrange[1].type = CB_MEM_RAM; } + + return ret; } diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index d342c99..706e714 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -216,22 +216,33 @@ struct cb_cmos_checksum { u32 type; }; +static inline u16 cb_checksum(const void *ptr, unsigned len) +{ + return ipchksum(ptr, len); +} + +static inline const u8 *cb_mb_vendor_string(const struct cb_mainboard *cbm) +{ + return cbm->strings + cbm->vendor_idx; +} + +static inline const u8 *cb_mb_part_string(const struct cb_mainboard *cbm) +{ + return cbm->strings + cbm->part_number_idx; +} + +static inline u64 cb_unpack64(struct cbuint64 val) +{ + return (((u64) val.hi) << 32) | val.lo; +} + /* Helpful macros */ #define MEM_RANGE_COUNT(_rec) \ (((_rec)->size - sizeof(*(_rec))) / sizeof((_rec)->map[0])) #define MEM_RANGE_PTR(_rec, _idx) \ - (((u8 *) (_rec)) + sizeof(*(_rec)) \ - + (sizeof((_rec)->map[0]) * (_idx))) - -#define MB_VENDOR_STRING(_mb) \ - (((unsigned char *) ((_mb)->strings)) + (_mb)->vendor_idx) - -#define MB_PART_STRING(_mb) \ - (((unsigned char *) ((_mb)->strings)) + (_mb)->part_number_idx) - -#define UNPACK_CB64(_in) \ - ( (((u64) _in.hi) << 32) | _in.lo ) + (void *)(((u8 *) (_rec)) + sizeof(*(_rec)) \ + + (sizeof((_rec)->map[0]) * (_idx))) #endif diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 8c8abc4..d9f7d21 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -369,7 +369,7 @@ int sysinfo_have_multiboot(unsigned long *addr); int get_coreboot_info(struct sysinfo_t *info); int get_multiboot_info(struct sysinfo_t *info); -void lib_get_sysinfo(void); +int lib_get_sysinfo(void); /* Timer functions - defined by each architecture. */ unsigned int get_cpu_speed(void); diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index c1d2002..778dfe9 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -56,6 +56,9 @@ struct sysinfo_t { struct cb_framebuffer *framebuffer; unsigned long *mbtable; /** Pointer to the multiboot table */ + + struct cb_header *header; + struct cb_mainboard *mainboard; }; extern struct sysinfo_t lib_sysinfo;

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coreboot December 2011