coreboot August 2010

coreboot@coreboot.org

67 participants
267 discussions

flashrom patch: add support for Abit AB-BM6 board
by Tim ter Laak 14 Sep '10

14 Sep '10

Hello all, This patch adds support for the Abit AB-BM6 mainboard to flashrom. The biggest part is a generic function to lower a GPIO line on the PIIX4E southbridge, copied and adapted from its ich_gpio_raise() counterpart (mostly lower instead of raise, followed names from the PIIX4E datasheet). The board specific function then uses this to lower GPO 26. Signed-off-by: Tim ter Laak <timl(a)scintilla.utwente.nl> --- The patch was made from the flashrom subdir, because svn diff from the top-level coreboot dir (as per the directions in the Development Guidelines on the wiki) didn't seem to work for me. Probably because flashrom is fetched externally when checking out coreboot? Anyway, I hope this is okay. If you really prefer a diff from the top-level dir just let me know, and I'll regenerate it with gnu diff. Kind regards, Tim. Index: board_enable.c =================================================================== --- board_enable.c (revision 3559) +++ board_enable.c (working copy) @@ -349,6 +349,58 @@ } /** + * Set the specified GPIO on the specified PIIX4 southbridge to low. + * + * @param name The name of this board. + * @param piix_vendor PCI vendor ID of the specified PIIX4 southbridge. (0x8086) + * @param piix_device PCI device ID of the specified PIIX4 southbridge, function Power Management (0x7113 for PIIX4E) + * @param pmbase_reg PMBASE register offset in the bridge. (0x40 for PIIX4E) + * @param pmbase_mask PMBASE bitmask (0xFFC0) + * @param gporeg Offset of GPOREG register in I/O space, relative to GPIOBASE. (0x34) + * @param gpio_bit The bit (GPIO) which shall be set to low. + * @return If the write-enable was successful return 0, otherwise return -1. + */ +static int piix4_gpio_lower(const char *name, uint16_t piix_vendor, + uint16_t piix_device, uint8_t pmbase_reg, + uint8_t gporeg, uint32_t pmbase_mask, + unsigned int gpio_bit) +{ + struct pci_dev *dev; + uint16_t pmbar; + uint32_t reg32; + + dev = pci_dev_find(piix_vendor, piix_device); /* Intel PIIX4 ACPI function */ + if (!dev) { + fprintf(stderr, "\nERROR: PIIX4 dev %4x:%4x not found.\n", + piix_vendor, piix_device); + return -1; + } + + /* Use PMBASE register to find the I/O space for GPIO. */ + pmbar = pci_read_word(dev, pmbase_reg) & pmbase_mask; + + /* Set specified GPIO to high. */ + reg32 = INL(pmbar + gporeg); + OUTB(0x00, 0xEB); /* dummy write to unused port as delay */ + + reg32 &= ~(1 << gpio_bit); + OUTL(reg32, pmbar + gporeg); + OUTB(0x00, 0xEB); /* another delay */ + + return 0; +} + +/** + * Suited for Abit AB-BM6. + */ +static int piix4_gpio26_lower(const char *name) +{ + return piix4_gpio_lower(name, 0x8086, 0x7113, 0x40, 0x34, 0xffc0, 26); +} + + + +/** * Suited for Acorp 6A815EPD. */ static int board_acorp_6a815epd(const char *name) @@ -672,6 +724,8 @@ NULL, NULL, "GIGABYTE GA-7VT600", board_biostar_p4m80_m4}, {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, "MSI K8T Neo2", w83627thf_gpio4_4_raise_2e}, + {0x8086, 0x7190, 0x0000, 0x0000, 0x8086, 0x7110, 0x0000, 0x0000, + "abit", "ab-bm6", "Abit AB-BM6", piix4_gpio26_lower}, {0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL} /* Keep this */ };

5 13

[PATCH] Istanbul support
by Arne Georg Gleditsch 13 Sep '10

13 Sep '10

Hi, The following patch implements Opteron Fam 10 rev D (aka Istanbul) support for coreboot. I have not updated MAX_CPUS for all fam10 mainboards, but it might make sense to multiply those by 1.5. Signed-off-by: Arne Georg Gleditsch <arne.gleditsch(a)numascale.com> -- Arne.

9 43

workaround for mahogany_fam10. Not a signed-off-by
by Bao, Zheng 11 Sep '10

11 Sep '10

This is for the mahogany_fam10 I just sent. It is not a signed-off-by patch. We need to work it out about this problem. Index: src/northbridge/amd/amdht/h3finit.c =================================================================== --- src/northbridge/amd/amdht/h3finit.c (revision 4521) +++ src/northbridge/amd/amdht/h3finit.c (working copy) @@ -1104,6 +1104,7 @@ AmdPCIRead(currentPtr, &temp); } while (!IS_HT_SLAVE_CAPABILITY(temp)); +#if (CONFIG_HT_CHAIN_UNITID_BASE != 0) AmdPCIReadBits(currentPtr, 25, 21, &unitIDcnt); if ((unitIDcnt + currentBUID > 31) || ((secBus == 0) && (unitIDcnt + currentBUID > 24))) { @@ -1145,7 +1146,7 @@ STOP_HERE; break; } - +#endif AmdPCIReadBits(currentPtr, 26, 26, &temp); pDat->PortList[pDat->TotalLinks*2+1].Link = (u8)temp; pDat->PortList[pDat->TotalLinks*2+1].Pointer = currentPtr; @@ -1156,6 +1157,11 @@ depth++; pDat->TotalLinks++; currentBUID += unitIDcnt; +#if CONFIG_HT_CHAIN_UNITID_BASE == 0 + STOP_HERE; + break; +#endif + } if (pDat->HtBlock->AMD_CB_EventNotify) {

4 3

MS-6147, SeaBIOS, and OpenBSD.
by Mats Erik Andersson 08 Sep '10

08 Sep '10

Hello again, two years have passed since I developed the support for MS-6147. Now I return to slowly activate myself again. In a first run I would like to report the following: 1. Coreboot-v4.0, svn rev 5740, works well on MSI MS-6147. 2. In the overview of supported mainboards, there ought to be an entry "Y" for MSI MS-6147, stipulating that the DIL32-ROM is set in a socket. 3. SeaBIOS works on MS-6147, but I had to strip down most functionality in order to fit the combined image into the 64 kB available (120 byte to spare!) since the standard fallback duplication was left intact. No VGA BIOS was included. 4. From this minimal SeaBIOS payload, I did successfully boot into a fully functional OpenBSD 4.4, which I as always use with a serial console. The disk is a 1GB Compact Flash card. Best regards, Mats Erik Andersson, fil. dr <mats.andersson(a)gisladisker.se> Abonnerar på: debian-mentors, debian-devel-games, debian-perl, debian-ipv6, debian-qa

4 6

ABIT IP35-E flashrom read success, hardware info
by Антон Кочков 05 Sep '10

05 Sep '10

2 1

util directory
by ali hagigat 03 Sep '10

03 Sep '10

Inside util/abuild we have two files: abuild and abuild.1 What language do they have written with? What is their functions in short? Are they necessary for building a coreboot image?

3 2

[PATCH] use Kconfig for both options on Lippert boards
by Jens Rottmann 01 Sep '10

01 Sep '10

SMC_CONFIG is needed before the device tree is ready and some people would rather not have mainboard settings like sio_gp1x_config in the device tree anyway. So found a nice united home for both in Kconfig, where users can change them without having to mess around in the C code. Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTEmbedded.de> --- Patrick, BTW, what happened to your patch which made the struct mainboard_config work again? I don't remember it getting committed. I don't use it mainly because SMC_CONFIG is needed early and I perfer not scattering 2 options in different places, but I _do_ think the mainboard logic is a kind of device and might be part (root??) of the tree. So IMHO your patch which reenables this is a very good thing to have! Cheers, Jens --- src/mainboard/lippert/roadrunner-lx/Kconfig (rev 5758) +++ src/mainboard/lippert/roadrunner-lx/Kconfig (working copy) @@ -11,6 +11,8 @@ select PIRQ_ROUTE select UDELAY_TSC select CACHE_AS_RAM + # Standard chip is a 512 KB FWH. Replacing it with a 1 MB + # SST 49LF008A is possible. select BOARD_ROMSIZE_KB_512 config MAINBOARD_DIR @@ -29,4 +31,11 @@ hex default 0x4000 +config ONBOARD_UARTS_RS485 + bool "Switch on-board serial ports to RS485" + default n + help + If selected, both on-board serial ports will operate in RS485 mode + instead of RS232. + endif # BOARD_LIPPERT_ROADRUNNER_LX --- src/mainboard/lippert/roadrunner-lx/chip.h (rev 5758) +++ src/mainboard/lippert/roadrunner-lx/chip.h (working copy) @@ -18,13 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* Based on chip.h from AMD's DB800 mainboard. */ - -#include <stdint.h> - extern struct chip_operations mainboard_ops; -struct mainboard_config { - /* bit5 = Live LED, bit2 = RS485_EN2, bit1 = RS485_EN1 */ - u8 sio_gp1x_config; -}; +struct mainboard_config {}; --- src/mainboard/lippert/roadrunner-lx/mainboard.c (rev 5758) +++ src/mainboard/lippert/roadrunner-lx/mainboard.c (working copy) @@ -29,6 +29,13 @@ #include <device/pci_ids.h> #include "chip.h" +/* Bit1 switches Com1 to RS485, bit2 same for Com2, bit5 turns off the Live LED. */ +#if CONFIG_ONBOARD_UARTS_RS485 + #define SIO_GP1X_CONFIG 0x26 +#else + #define SIO_GP1X_CONFIG 0x20 +#endif + static const u16 ec_init_table[] = { /* hi=data, lo=index */ 0x1900, /* Enable monitoring */ 0x0351, /* TMPIN1,2 diode mode, TMPIN3 off */ @@ -40,7 +47,6 @@ static void init(struct device *dev) { - struct mainboard_config *mb = dev->chip_info; unsigned int gpio_base, i; printk(BIOS_DEBUG, "LiPPERT RoadRunner-LX ENTER %s\n", __func__); @@ -61,7 +67,8 @@ outb(val >> 8, 0x0296); } - outb(mb->sio_gp1x_config, 0x1220); /* Simple-I/O GP17-10 */ + /* bit5 = Live LED, bit2 = RS485_EN2, bit1 = RS485_EN1 */ + outb(SIO_GP1X_CONFIG, 0x1220); /* Simple-I/O GP17-10 */ printk(BIOS_DEBUG, "LiPPERT RoadRunner-LX EXIT %s\n", __func__); } --- src/mainboard/lippert/roadrunner-lx/romstage.c (rev 5758) +++ src/mainboard/lippert/roadrunner-lx/romstage.c (working copy) @@ -132,4 +132,3 @@ /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ return; } - --- src/mainboard/lippert/spacerunner-lx/Kconfig (rev 5758) +++ src/mainboard/lippert/spacerunner-lx/Kconfig (working copy) @@ -12,6 +12,8 @@ select PIRQ_ROUTE select UDELAY_TSC select CACHE_AS_RAM + # Board is equipped with a 1 MB SPI flash, however, due to limitations + # of the IT8712F Super I/O, only the top 512 KB are directly mapped. select BOARD_ROMSIZE_KB_512 config MAINBOARD_DIR @@ -30,4 +32,17 @@ hex default 0x4000 +config ONBOARD_UARTS_RS485 + bool "Switch on-board serial ports to RS485" + default n + help + If selected, both on-board serial ports will operate in RS485 mode + instead of RS232. + +config ONBOARD_IDE_SLAVE + bool "Make on-board SSD act as Slave" + default n + help + If selected, the on-board SSD will act as IDE Slave instead of Master. + endif # BOARD_LIPPERT_SPACERUNNER_LX --- src/mainboard/lippert/spacerunner-lx/chip.h (rev 5758) +++ src/mainboard/lippert/spacerunner-lx/chip.h (working copy) @@ -18,13 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* Based on chip.h from AMD's DB800 mainboard. */ - -#include <stdint.h> - extern struct chip_operations mainboard_ops; -struct mainboard_config { - /* bit2 = RS485_EN2, bit1 = RS485_EN1, bit0 = Live LED */ - u8 sio_gp1x_config; -}; +struct mainboard_config {}; --- src/mainboard/lippert/spacerunner-lx/mainboard.c (rev 5758) +++ src/mainboard/lippert/spacerunner-lx/mainboard.c (working copy) @@ -29,6 +29,13 @@ #include <device/pci_ids.h> #include "chip.h" +/* Bit0 turns off the Live LED, bit1 switches Com1 to RS485, bit2 same for Com2. */ +#if CONFIG_ONBOARD_UARTS_RS485 + #define SIO_GP1X_CONFIG 0x07 +#else + #define SIO_GP1X_CONFIG 0x01 +#endif + static const u16 ec_init_table[] = { /* hi=data, lo=index */ 0x1900, /* Enable monitoring */ 0x3050, /* VIN4,5 enabled */ @@ -41,7 +48,6 @@ static void init(struct device *dev) { - struct mainboard_config *mb = dev->chip_info; unsigned int gpio_base, i; printk(BIOS_DEBUG, "LiPPERT SpaceRunner-LX ENTER %s\n", __func__); @@ -65,7 +71,9 @@ outb(val >> 8, 0x0296); } - outb(mb->sio_gp1x_config, 0x1220); /* Simple-I/O GP17-10 */ + /* bit2 = RS485_EN2, bit1 = RS485_EN1, bit0 = Live LED */ + outb(SIO_GP1X_CONFIG, 0x1220); /* Simple-I/O GP17-10 */ + printk(BIOS_DEBUG, "LiPPERT SpaceRunner-LX EXIT %s\n", __func__); } --- src/mainboard/lippert/spacerunner-lx/romstage.c (rev 5758) +++ src/mainboard/lippert/spacerunner-lx/romstage.c (working copy) @@ -41,7 +41,11 @@ #include "superio/ite/it8712f/it8712f_early_serial.c" /* Bit0 enables Spread Spectrum, bit1 makes on-board SSD act as IDE slave. */ -#define SMC_CONFIG 0x01 +#if CONFIG_ONBOARD_IDE_SLAVE + #define SMC_CONFIG 0x03 +#else + #define SMC_CONFIG 0x01 +#endif #define ManualConf 1 /* No automatic strapped PLL config */ #define PLLMSRhi 0x0000059C /* Manual settings for the PLL */ @@ -201,4 +205,3 @@ /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ return; } - _

5 9

[PATCH] added ich10r gpio support to intel tool
by Warren Turkal 01 Sep '10

01 Sep '10

I have attached a patch for ich10r support for dumping gpio registers. I am looking for comments and a possible committer. Thanks, wt

4 7

via pc3500g
by illdred 01 Sep '10

01 Sep '10

Good day, I would like to use coreboot on my machine. I have a VIA PC3500G motherboard. VIA C7 cpu, VIA CN896 northbirdge, VIA 8237A southbridge Will it work? looks to me like the only unsupported piece is the northbridge. lspci -tvnn -+-[0000:80]---01.0 VIA Technologies, Inc. VT1708/A [Azalia HDAC] (VIA High Definition Audio Controller) [1106:3288] \-[0000:00]-+-00.0 VIA Technologies, Inc. CN896/VN896/P4M900 Host Bridge [1106:0364] +-00.1 VIA Technologies, Inc. CN896/VN896/P4M900 Host Bridge [1106:1364] +-00.2 VIA Technologies, Inc. CN896/VN896/P4M900 Host Bridge [1106:2364] +-00.3 VIA Technologies, Inc. CN896/VN896/P4M900 Host Bridge [1106:3364] +-00.4 VIA Technologies, Inc. CN896/VN896/P4M900 Host Bridge [1106:4364] +-00.5 VIA Technologies, Inc. CN896/VN896/P4M900 I/O APIC Interrupt Controller [1106:5364] +-00.6 VIA Technologies, Inc. CN896/VN896/P4M900 Security Device [1106:6364] +-00.7 VIA Technologies, Inc. CN896/VN896/P4M900 Host Bridge [1106:7364] +-01.0-[01]-- +-02.0-[02]--+-00.0 ATI Technologies Inc RV610 video device [Radeon HD 2400 PRO] [1002:94c3] | \-00.1 ATI Technologies Inc RV610 audio device [Radeon HD 2400 PRO] [1002:aa10] +-03.0-[03]-- +-0f.0 VIA Technologies, Inc. Device [1106:5337] +-0f.1 VIA Technologies, Inc. VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE [1106:0571] +-10.0 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] +-10.1 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] +-10.2 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] +-10.3 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] +-10.4 VIA Technologies, Inc. USB 2.0 [1106:3104] +-11.0 VIA Technologies, Inc. VT8237A PCI to ISA Bridge [1106:3337] +-11.7 VIA Technologies, Inc. VT8251 Ultra VLINK Controller [1106:287e] +-13.0 VIA Technologies, Inc. VT8237A Host Bridge [1106:337b] \-13.1-[04-05]--+-04.0-[05]--+-00.0 ATI Technologies Inc RV 610LE PCI [Radeon HD 2400] [1002:94cc] | \-00.1 ATI Technologies Inc RV610 audio device [Radeon HD 2400 PRO] [1002:aa10] \-0e.0 VIA Technologies, Inc. VT6102 [Rhine-II] [1106:3065] superiotool -dV superiotool r5728 Probing for ...<snip> Probing for ITE Super I/O (init=standard) at 0x2e... Found ITE IT8716F (id=0x8716, rev=0x1) at 0x2e Register dump: idx 20 21 22 23 24 2b val 87 16 01 10 1e 00 def 87 16 01 00 00 00 LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 val 00 00 00 00 04 00 80 def 00 03 f0 06 02 00 00 LDN 0x01 (COM1) idx 30 60 61 70 f0 f1 f2 f3 val 00 00 00 00 00 50 00 7f def 00 03 f8 04 00 50 00 7f LDN 0x02 (COM2) idx 30 60 61 70 f0 f1 f2 f3 val 00 00 00 00 00 50 00 7f def 00 02 f8 03 00 50 00 7f LDN 0x03 (Parallel port) idx 30 60 61 62 63 70 74 f0 val 00 00 00 00 00 00 04 08 def 00 03 78 07 78 07 03 03 LDN 0x04 (Environment controller) idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 val 01 02 90 00 00 00 00 00 0a 00 80 00 ff def 00 02 90 02 30 09 00 00 00 00 00 NA NA LDN 0x05 (Keyboard) idx 30 60 61 62 63 70 71 f0 val 00 00 60 00 64 00 02 48 def 01 00 60 00 64 01 02 00 LDN 0x06 (Mouse) idx 30 70 71 f0 val 00 0c 02 00 def 00 0c 02 00 LDN 0x07 (GPIO) idx 25 26 27 28 29 2a 2c 60 61 62 63 64 65 70 71 72 73 74 b0 b1 b2 b3 b4 b5 b8 b9 ba bb bc bd c0 c1 c2 c3 c4 c8 c9 ca cb cc e0 e1 e2 e3 e4 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd val 01 00 00 00 00 81 1f 00 00 08 00 08 20 00 01 00 38 00 00 00 00 00 00 00 60 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 08 03 00 00 3f 00 def 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 20 38 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 40 00 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA 00 LDN 0x08 (MIDI port) idx 30 60 61 70 f0 val 00 03 00 0a 00 def 00 03 00 0a 00 LDN 0x09 (Game port) idx 30 60 61 val 00 02 01 def 00 02 01 LDN 0x0a (Consumer IR) idx 30 60 61 70 f0 val 00 03 10 0b 06 def 00 03 10 0b 00 flashrom -V flashrom v0.9.2-r1001 on Linux 2.6.33-dirigible33 (i686), built with libpci 3.1.7, GCC 4.5.0 20100520 (prerelease) flashrom is free software, get the source code at http://www.flashrom.org Initializing internal programmer No coreboot table found. DMI string system-manufacturer: " " DMI string system-product-name: " " DMI string system-version: " " DMI string baseboard-manufacturer: "PC1" DMI string baseboard-product-name: "PC3500G" DMI string baseboard-version: "3.x" DMI string chassis-type: "Desktop" Found ITE Super I/O, id 8716 Found chipset "VIA VT8237A", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Serial flash segment 0xfffe0000-0xffffffff enabled Serial flash segment 0x000e0000-0x000fffff enabled Serial flash segment 0xffee0000-0xffefffff enabled Serial flash segment 0xfff80000-0xfffeffff enabled LPC write to serial flash enabled Serial flash pin 29 Serial flash port 0x0820 Calibrating delay loop... 387M loops per second, delay more than 10% too short, recalculating... 381M loops per second, delay more than 10% too short, recalculating... 434M loops per second, delay more than 10% too short, recalculating... 436M loops per second, delay more than 10% too short, recalculating... 436M loops per second, delay loop is unreliable, trying to continue 10 myus = 10 us, 100 myus = 89 us, 1000 myus = 873 us, 10000 myus = 31905 us, OK. <snip> Probing for Macronix MX25L4005, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Chip status register is 00 Chip status register: Status Register Write Disable (SRWD) is not set Chip status register: Bit 6 is not set Chip status register: Bit 5 / Block Protect 3 (BP3) is not set Chip status register: Bit 4 / Block Protect 2 (BP2) is not set Chip status register: Bit 3 / Block Protect 1 (BP1) is not set Chip status register: Bit 2 / Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Found chip "Macronix MX25L4005" (512 KB, SPI) at physical address 0xfff80000. <snip> === This flash part has status UNTESTED for operations: ERASE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Thanks for your help! ===

3 3

Real mode ebx corruption
by Myles Watson 01 Sep '10

01 Sep '10

Has anyone seen corruption of ebx when using real mode for option ROMs? I'm running the same ROM with SeaBIOS and real mode, and a series of writes (ax = 1ab1 bx = b10d) works fine with SeaBIOS, but several of the bx values are corrupted to b100 with real mode. The only hint I can find is: // Put registers back on the stack. The assembler code // will later pop them. // What happens here is that we force (volatile!) changing // the values of the parameters of this function. We do this // because we know that they stay alive on the stack after // we leave this function. Don't say this is bollocks. *(volatile u32 *)&eax = reg_info.eax; *(volatile u32 *)&ecx = reg_info.ecx; *(volatile u32 *)&edx = reg_info.edx; *(volatile u32 *)&ebx = reg_info.ebx; Since it's real mode, it seems like the only place for corruption is the call & return. Am I missing something? Thanks, Myles

1 0

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coreboot August 2010