coreboot August 2010

coreboot@coreboot.org

67 participants
267 discussions

Re: [coreboot] alix 2d2
by Jens Rottmann 01 Sep '10

01 Sep '10

> Since the change is so small, how about we just add a Kconfig option > to select the 2D2 variant of the board. Or handle this even simpler yet: put both table entries for devices 0A _and_ 0E in, increase IRQ_SLOT_COUNT to 7 and call the thing ALIX 2Dx. AFAIK an IRQ routing table entry gets ignored anyway if the appropriate device is not there, so the extra entry won't hurt either variant. Cheers, Jens

4 8

Re: [coreboot] Chipset VIA Apollo Pro+?
by Mats Erik Andersson 31 Aug '10

31 Aug '10

lördag den 28 augusti 2010 klockan 13:16 skrev anders(a)jenbo.dk detta: > I did some initial code for this chip set (debug is working) > but haven't played with it for a while. > > Mvh Anders > This is good news, that some knowledge indeed has been gathered. I will begin reading the more or less relevant background material there is, so I would welcome any collaboration that might be offered. Hälsningar, best regards, Mats E A > ----- Reply message ----- > Fra: "Darmawan Salihun" <darmawan.salihun(a)gmail.com> > Dato: lør., aug. 28, 2010 10:09 > Emne: [coreboot] Chipset VIA Apollo Pro+? > Til: "Mats Erik Andersson" <mats.andersson(a)gisladisker.se> > Cc: <coreboot(a)coreboot.org> > > > I have the datasheet of this chipset. I'll send it to you later. I was > one working with legacy BIOS on moatherboard with this chipset. > > -Darmawan > > On 8/27/10, Mats Erik Andersson <mats.andersson(a)gisladisker.se> wrote: > > Hello, > > > > is there now, or has there been, someone interested > > in the legacy chipset VIA Apollo Pro+? In the sense > > of investigating its use with Coreboot. > > > > The northbridge is VIA VT82C693, and the southbridge > > is VIA VT82C596A on a mainboard from ECS: > > > > PCI-bridge VT82C691, > > AGP-bridge VT82C598, > > ISA-bridge VT82C596A, > > IDE-interface VT82C571, > > USB-controller VT82C572, and > > Power-ctrl VT82C596. > > > > A search for datasheets has given nothing but trivial > > information.

2 1

[PATCH] Make last_dev match comments
by Myles Watson 31 Aug '10

31 Aug '10

This patch simplifies last_dev. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

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[FILO] r138 - trunk/filo/i386
by repository service 31 Aug '10

31 Aug '10

Author: oxygene Date: Tue Aug 31 22:26:34 2010 New Revision: 138 URL: http://tracker.coreboot.org/trac/filo/changeset/138 Log: Fix display of converted memory map entries Convert address of framebuffer info array to virtual before using it Modified: trunk/filo/i386/linux_load.c Modified: trunk/filo/i386/linux_load.c ============================================================================== --- trunk/filo/i386/linux_load.c Tue Aug 24 13:36:51 2010 (r137) +++ trunk/filo/i386/linux_load.c Tue Aug 31 22:26:34 2010 (r138) @@ -277,7 +277,7 @@ linux_map->addr = filo_map->base; linux_map->size = filo_map->size; linux_map->type = filo_map->type; - debug("%016Lx - %016Lx (%d)\n", linux_map->addr, + debug("%016llx - %016llx (%d)\n", linux_map->addr, linux_map->addr + linux_map->size, linux_map->type); params->e820_map_nr = i + 1; @@ -311,22 +311,25 @@ if (!lib_sysinfo.framebuffer) return; - params->lfb_width = lib_sysinfo.framebuffer->x_resolution; - params->lfb_height = lib_sysinfo.framebuffer->y_resolution; - params->lfb_depth = lib_sysinfo.framebuffer->bits_per_pixel; - params->lfb_linelength = lib_sysinfo.framebuffer->bytes_per_line; - params->lfb_base = lib_sysinfo.framebuffer->physical_address; + struct cb_framebuffer *fb = phys_to_virt(lib_sysinfo.framebuffer); + + params->lfb_width = fb->x_resolution; + params->lfb_height = fb->y_resolution; + params->lfb_depth = fb->bits_per_pixel; + params->lfb_linelength = fb->bytes_per_line; + params->lfb_base = fb->physical_address; + // prolly not enough for the boot splash?! params->lfb_size = (params->lfb_linelength * params->lfb_height + 65535) >> 16; - params->red_size = lib_sysinfo.framebuffer->red_mask_size; - params->red_pos = lib_sysinfo.framebuffer->red_mask_pos; - params->green_size = lib_sysinfo.framebuffer->green_mask_size; - params->green_pos = lib_sysinfo.framebuffer->green_mask_pos; - params->blue_size = lib_sysinfo.framebuffer->blue_mask_size; - params->blue_pos = lib_sysinfo.framebuffer->blue_mask_pos; - params->rsvd_size = lib_sysinfo.framebuffer->reserved_mask_size; - params->rsvd_pos = lib_sysinfo.framebuffer->reserved_mask_pos; + params->red_size = fb->red_mask_size; + params->red_pos = fb->red_mask_pos; + params->green_size = fb->green_mask_size; + params->green_pos = fb->green_mask_pos; + params->blue_size = fb->blue_mask_size; + params->blue_pos = fb->blue_mask_pos; + params->rsvd_size = fb->reserved_mask_size; + params->rsvd_pos = fb->reserved_mask_pos; #endif }

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build service results for r5760
by repository service 31 Aug '10

31 Aug '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "myles" checked in revision 5760 to the coreboot repository. This caused the following changes: Change Log: SMC_CONFIG is needed before the device tree is ready and some people would rather not have mainboard settings like sio_gp1x_config in the device tree anyway. So found a nice united home for both in Kconfig, where users can change them without having to mess around in the C code. Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTEmbedded.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Compilation of a-trend:atc-6220 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5760&device=atc-6220&vendo… If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r5760 - in trunk/src/mainboard/lippert: roadrunner-lx spacerunner-lx
by repository service 31 Aug '10

31 Aug '10

Author: myles Date: Tue Aug 31 21:19:16 2010 New Revision: 5760 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5760 Log: SMC_CONFIG is needed before the device tree is ready and some people would rather not have mainboard settings like sio_gp1x_config in the device tree anyway. So found a nice united home for both in Kconfig, where users can change them without having to mess around in the C code. Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTEmbedded.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/src/mainboard/lippert/roadrunner-lx/Kconfig trunk/src/mainboard/lippert/roadrunner-lx/chip.h trunk/src/mainboard/lippert/roadrunner-lx/mainboard.c trunk/src/mainboard/lippert/roadrunner-lx/romstage.c trunk/src/mainboard/lippert/spacerunner-lx/Kconfig trunk/src/mainboard/lippert/spacerunner-lx/chip.h trunk/src/mainboard/lippert/spacerunner-lx/mainboard.c trunk/src/mainboard/lippert/spacerunner-lx/romstage.c Modified: trunk/src/mainboard/lippert/roadrunner-lx/Kconfig ============================================================================== --- trunk/src/mainboard/lippert/roadrunner-lx/Kconfig Tue Aug 31 21:02:45 2010 (r5759) +++ trunk/src/mainboard/lippert/roadrunner-lx/Kconfig Tue Aug 31 21:19:16 2010 (r5760) @@ -11,6 +11,8 @@ select PIRQ_ROUTE select UDELAY_TSC select CACHE_AS_RAM + # Standard chip is a 512 KB FWH. Replacing it with a 1 MB + # SST 49LF008A is possible. select BOARD_ROMSIZE_KB_512 config MAINBOARD_DIR @@ -29,4 +31,11 @@ hex default 0x4000 +config ONBOARD_UARTS_RS485 + bool "Switch on-board serial ports to RS485" + default n + help + If selected, both on-board serial ports will operate in RS485 mode + instead of RS232. + endif # BOARD_LIPPERT_ROADRUNNER_LX Modified: trunk/src/mainboard/lippert/roadrunner-lx/chip.h ============================================================================== --- trunk/src/mainboard/lippert/roadrunner-lx/chip.h Tue Aug 31 21:02:45 2010 (r5759) +++ trunk/src/mainboard/lippert/roadrunner-lx/chip.h Tue Aug 31 21:19:16 2010 (r5760) @@ -18,13 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* Based on chip.h from AMD's DB800 mainboard. */ - -#include <stdint.h> - extern struct chip_operations mainboard_ops; -struct mainboard_config { - /* bit5 = Live LED, bit2 = RS485_EN2, bit1 = RS485_EN1 */ - u8 sio_gp1x_config; -}; +struct mainboard_config {}; Modified: trunk/src/mainboard/lippert/roadrunner-lx/mainboard.c ============================================================================== --- trunk/src/mainboard/lippert/roadrunner-lx/mainboard.c Tue Aug 31 21:02:45 2010 (r5759) +++ trunk/src/mainboard/lippert/roadrunner-lx/mainboard.c Tue Aug 31 21:19:16 2010 (r5760) @@ -29,6 +29,13 @@ #include <device/pci_ids.h> #include "chip.h" +/* Bit1 switches Com1 to RS485, bit2 same for Com2, bit5 turns off the Live LED. */ +#if CONFIG_ONBOARD_UARTS_RS485 + #define SIO_GP1X_CONFIG 0x26 +#else + #define SIO_GP1X_CONFIG 0x20 +#endif + static const u16 ec_init_table[] = { /* hi=data, lo=index */ 0x1900, /* Enable monitoring */ 0x0351, /* TMPIN1,2 diode mode, TMPIN3 off */ @@ -40,7 +47,6 @@ static void init(struct device *dev) { - struct mainboard_config *mb = dev->chip_info; unsigned int gpio_base, i; printk(BIOS_DEBUG, "LiPPERT RoadRunner-LX ENTER %s\n", __func__); @@ -61,7 +67,8 @@ outb(val >> 8, 0x0296); } - outb(mb->sio_gp1x_config, 0x1220); /* Simple-I/O GP17-10 */ + /* bit5 = Live LED, bit2 = RS485_EN2, bit1 = RS485_EN1 */ + outb(SIO_GP1X_CONFIG, 0x1220); /* Simple-I/O GP17-10 */ printk(BIOS_DEBUG, "LiPPERT RoadRunner-LX EXIT %s\n", __func__); } Modified: trunk/src/mainboard/lippert/roadrunner-lx/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/roadrunner-lx/romstage.c Tue Aug 31 21:02:45 2010 (r5759) +++ trunk/src/mainboard/lippert/roadrunner-lx/romstage.c Tue Aug 31 21:19:16 2010 (r5760) @@ -132,4 +132,3 @@ /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ return; } - Modified: trunk/src/mainboard/lippert/spacerunner-lx/Kconfig ============================================================================== --- trunk/src/mainboard/lippert/spacerunner-lx/Kconfig Tue Aug 31 21:02:45 2010 (r5759) +++ trunk/src/mainboard/lippert/spacerunner-lx/Kconfig Tue Aug 31 21:19:16 2010 (r5760) @@ -12,6 +12,8 @@ select PIRQ_ROUTE select UDELAY_TSC select CACHE_AS_RAM + # Board is equipped with a 1 MB SPI flash, however, due to limitations + # of the IT8712F Super I/O, only the top 512 KB are directly mapped. select BOARD_ROMSIZE_KB_512 config MAINBOARD_DIR @@ -30,4 +32,17 @@ hex default 0x4000 +config ONBOARD_UARTS_RS485 + bool "Switch on-board serial ports to RS485" + default n + help + If selected, both on-board serial ports will operate in RS485 mode + instead of RS232. + +config ONBOARD_IDE_SLAVE + bool "Make on-board SSD act as Slave" + default n + help + If selected, the on-board SSD will act as IDE Slave instead of Master. + endif # BOARD_LIPPERT_SPACERUNNER_LX Modified: trunk/src/mainboard/lippert/spacerunner-lx/chip.h ============================================================================== --- trunk/src/mainboard/lippert/spacerunner-lx/chip.h Tue Aug 31 21:02:45 2010 (r5759) +++ trunk/src/mainboard/lippert/spacerunner-lx/chip.h Tue Aug 31 21:19:16 2010 (r5760) @@ -18,13 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* Based on chip.h from AMD's DB800 mainboard. */ - -#include <stdint.h> - extern struct chip_operations mainboard_ops; -struct mainboard_config { - /* bit2 = RS485_EN2, bit1 = RS485_EN1, bit0 = Live LED */ - u8 sio_gp1x_config; -}; +struct mainboard_config {}; Modified: trunk/src/mainboard/lippert/spacerunner-lx/mainboard.c ============================================================================== --- trunk/src/mainboard/lippert/spacerunner-lx/mainboard.c Tue Aug 31 21:02:45 2010 (r5759) +++ trunk/src/mainboard/lippert/spacerunner-lx/mainboard.c Tue Aug 31 21:19:16 2010 (r5760) @@ -29,6 +29,13 @@ #include <device/pci_ids.h> #include "chip.h" +/* Bit0 turns off the Live LED, bit1 switches Com1 to RS485, bit2 same for Com2. */ +#if CONFIG_ONBOARD_UARTS_RS485 + #define SIO_GP1X_CONFIG 0x07 +#else + #define SIO_GP1X_CONFIG 0x01 +#endif + static const u16 ec_init_table[] = { /* hi=data, lo=index */ 0x1900, /* Enable monitoring */ 0x3050, /* VIN4,5 enabled */ @@ -41,7 +48,6 @@ static void init(struct device *dev) { - struct mainboard_config *mb = dev->chip_info; unsigned int gpio_base, i; printk(BIOS_DEBUG, "LiPPERT SpaceRunner-LX ENTER %s\n", __func__); @@ -65,7 +71,9 @@ outb(val >> 8, 0x0296); } - outb(mb->sio_gp1x_config, 0x1220); /* Simple-I/O GP17-10 */ + /* bit2 = RS485_EN2, bit1 = RS485_EN1, bit0 = Live LED */ + outb(SIO_GP1X_CONFIG, 0x1220); /* Simple-I/O GP17-10 */ + printk(BIOS_DEBUG, "LiPPERT SpaceRunner-LX EXIT %s\n", __func__); } Modified: trunk/src/mainboard/lippert/spacerunner-lx/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/spacerunner-lx/romstage.c Tue Aug 31 21:02:45 2010 (r5759) +++ trunk/src/mainboard/lippert/spacerunner-lx/romstage.c Tue Aug 31 21:19:16 2010 (r5760) @@ -41,7 +41,11 @@ #include "superio/ite/it8712f/it8712f_early_serial.c" /* Bit0 enables Spread Spectrum, bit1 makes on-board SSD act as IDE slave. */ -#define SMC_CONFIG 0x01 +#if CONFIG_ONBOARD_IDE_SLAVE + #define SMC_CONFIG 0x03 +#else + #define SMC_CONFIG 0x01 +#endif #define ManualConf 1 /* No automatic strapped PLL config */ #define PLLMSRhi 0x0000059C /* Manual settings for the PLL */ @@ -201,4 +205,3 @@ /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ return; } -

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build service results for r5759
by repository service 31 Aug '10

31 Aug '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "myles" checked in revision 5759 to the coreboot repository. This caused the following changes: Change Log: Make ALIX.2D3 support 2D2 as well. Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTEmbedded.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Compilation of a-trend:atc-6220 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5759&device=atc-6220&vendo… If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[commit] r5759 - in trunk/src/mainboard/pcengines: . alix2d alix2d3
by repository service 31 Aug '10

31 Aug '10

Author: myles Date: Tue Aug 31 21:02:45 2010 New Revision: 5759 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5759 Log: Make ALIX.2D3 support 2D2 as well. Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTEmbedded.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Added: trunk/src/mainboard/pcengines/alix2d/ - copied from r5756, trunk/src/mainboard/pcengines/alix2d3/ Deleted: trunk/src/mainboard/pcengines/alix2d3/ Modified: trunk/src/mainboard/pcengines/Kconfig trunk/src/mainboard/pcengines/alix2d/Kconfig trunk/src/mainboard/pcengines/alix2d/irq_tables.c trunk/src/mainboard/pcengines/alix2d/mainboard.c trunk/src/mainboard/pcengines/alix2d/romstage.c Modified: trunk/src/mainboard/pcengines/Kconfig ============================================================================== --- trunk/src/mainboard/pcengines/Kconfig Tue Aug 31 08:10:54 2010 (r5758) +++ trunk/src/mainboard/pcengines/Kconfig Tue Aug 31 21:02:45 2010 (r5759) @@ -5,13 +5,13 @@ config BOARD_PCENGINES_ALIX1C bool "ALIX.1C" -config BOARD_PCENGINES_ALIX2D3 - bool "ALIX.2D3" +config BOARD_PCENGINES_ALIX2D + bool "ALIX.2D2 or 2D3" endchoice source "src/mainboard/pcengines/alix1c/Kconfig" -source "src/mainboard/pcengines/alix2d3/Kconfig" +source "src/mainboard/pcengines/alix2d/Kconfig" config MAINBOARD_VENDOR string Modified: trunk/src/mainboard/pcengines/alix2d/Kconfig ============================================================================== --- trunk/src/mainboard/pcengines/alix2d3/Kconfig Mon Aug 30 19:53:13 2010 (r5756) +++ trunk/src/mainboard/pcengines/alix2d/Kconfig Tue Aug 31 21:02:45 2010 (r5759) @@ -1,4 +1,4 @@ -if BOARD_PCENGINES_ALIX2D3 +if BOARD_PCENGINES_ALIX2D config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -14,18 +14,18 @@ config MAINBOARD_DIR string - default pcengines/alix2d3 + default pcengines/alix2d config MAINBOARD_PART_NUMBER string - default "ALIX.2D3" + default "ALIX.2D" config IRQ_SLOT_COUNT int - default 6 + default 7 config RAMBASE hex default 0x4000 -endif # BOARD_PCENGINES_ALIX2D3 +endif # BOARD_PCENGINES_ALIX2D Modified: trunk/src/mainboard/pcengines/alix2d/irq_tables.c ============================================================================== --- trunk/src/mainboard/pcengines/alix2d3/irq_tables.c Mon Aug 30 19:53:13 2010 (r5756) +++ trunk/src/mainboard/pcengines/alix2d/irq_tables.c Tue Aug 31 21:02:45 2010 (r5759) @@ -94,7 +94,7 @@ /* On-board ethernet (Left) */ {0x00, (0x09 << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, - /* On-board ethernet (Middle) */ + /* On-board ethernet (Middle, ALIX.2D3 only) */ {0x00, (0x0A << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* On-board ethernet (Right) */ @@ -103,6 +103,9 @@ /* Mini PCI (slot 1) */ {0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, + /* Mini PCI (slot 2, ALIX.2D2 only) */ + {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, + /* Chipset slots -- f.3 wires to B, and f.4 and f.5 wires to D. */ {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, } Modified: trunk/src/mainboard/pcengines/alix2d/mainboard.c ============================================================================== --- trunk/src/mainboard/pcengines/alix2d3/mainboard.c Mon Aug 30 19:53:13 2010 (r5756) +++ trunk/src/mainboard/pcengines/alix2d/mainboard.c Tue Aug 31 21:02:45 2010 (r5759) @@ -23,8 +23,8 @@ static void init(struct device *dev) { - printk(BIOS_DEBUG, "ALIX.2D3 ENTER %s\n", __func__); - printk(BIOS_DEBUG, "ALIX.2D3 EXIT %s\n", __func__); + printk(BIOS_DEBUG, "ALIX.2D ENTER %s\n", __func__); + printk(BIOS_DEBUG, "ALIX.2D EXIT %s\n", __func__); } static void enable_dev(struct device *dev) @@ -33,7 +33,7 @@ } struct chip_operations mainboard_ops = { - CHIP_NAME("PC Engines ALIX.2D3 Mainboard") + CHIP_NAME("PC Engines ALIX.2D Mainboard") .enable_dev = enable_dev, }; Modified: trunk/src/mainboard/pcengines/alix2d/romstage.c ============================================================================== --- trunk/src/mainboard/pcengines/alix2d3/romstage.c Mon Aug 30 19:53:13 2010 (r5756) +++ trunk/src/mainboard/pcengines/alix2d/romstage.c Tue Aug 31 21:02:45 2010 (r5759) @@ -35,7 +35,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -/* The ALIX.2D3 has no SMBus; the setup is hard-wired. */ +/* The ALIX.2D has no SMBus; the setup is hard-wired. */ static void cs5536_enable_smbus(void) { }

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[PATCH] Generate multiboot tables after and from coreboot tables
by Juhana Helovuo 31 Aug '10

31 Aug '10

Hello, The attached patch adds all the memory memory ranges in the coreboot tables also to the multiboot tables. It is useful e.g. when booting Linux with Grub2 payload, since then Linux gets the Coreboot memory map via multiboot tables. This patch causes multiboot table to be located in memory before coreboot tables, but it seemed to cause no harm for me. Signed-off-by: Juhana Helovuo <juhe(a)iki.fi> Best regards, Juhana Helovuo

3 4

On versions of a mainboard
by Mats Erik Andersson 31 Aug '10

31 Aug '10

Hello, I have begun the porting of the mainboard FIC VB-601 to Coreboot. In itself this is fairly standard, since it uses Intel i440BX as chipset. However, I am in possession of two pieces, one of version 1.3, the other of version 1.4. The first uses SuperIO W83977TF-AW, the other W83977EF-AW, and also there are small differences in board layout and population of minor components. This is also reflected in the fact that the older BIOS is not functional in the newer board. My question is this: Is there a possibility to make the file 'devicetree.cb' conditional on the used version, or must I implement two mainboard settings? Like BOARD_FIC_VB_601_V1_3 and BOARD_FIC_VB_601_V1_4 would replace my present setting BOARD_FIC_VB_601. I have not yet tested the compiled Coreboot image in either of the boards, so no preliminary statement can be passed on the necessity to uphold this distinction for Coreboot. Best regards, Mats Erik Andersson

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coreboot August 2010