coreboot August 2010

coreboot@coreboot.org

67 participants
267 discussions

[commit] r5677 - in trunk/src: mainboard/jetway/j7f24 northbridge/via/cn700 southbridge/via/vt8237r
by repository service 01 Aug '10

01 Aug '10

Author: stepan Date: Sun Aug 1 19:20:20 2010 New Revision: 5677 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5677 Log: Clarify a comment on an old hack, remove the call to early_mtrr_init that causes CAR to hang, provide more debugging output wrt memory size, and correct the numbering on the ram init sequence. Signed-off-by: Corey Osgood <corey.osgood(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/mainboard/jetway/j7f24/romstage.c trunk/src/northbridge/via/cn700/northbridge.c trunk/src/northbridge/via/cn700/raminit.c trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c Modified: trunk/src/mainboard/jetway/j7f24/romstage.c ============================================================================== --- trunk/src/mainboard/jetway/j7f24/romstage.c Sun Aug 1 17:41:14 2010 (r5676) +++ trunk/src/mainboard/jetway/j7f24/romstage.c Sun Aug 1 19:20:20 2010 (r5677) @@ -99,11 +99,6 @@ enable_smbus(); smbus_fixup(&ctrl); - if (bist == 0) { - print_debug("doing early_mtrr\n"); - early_mtrr_init(); - } - /* Halt if there was a built-in self test failure. */ report_bist_failure(bist); Modified: trunk/src/northbridge/via/cn700/northbridge.c ============================================================================== --- trunk/src/northbridge/via/cn700/northbridge.c Sun Aug 1 17:41:14 2010 (r5676) +++ trunk/src/northbridge/via/cn700/northbridge.c Sun Aug 1 19:20:20 2010 (r5677) @@ -177,7 +177,7 @@ } tomk = rambits * 64 * 1024; - printk(BIOS_SPEW, "tomk is 0x%lx\n", tomk); + printk(BIOS_DEBUG, "tomk is 0x%lx\n", tomk); /* Compute the Top Of Low Memory (TOLM), in Kb. */ tolmk = pci_tolm >> 10; if (tolmk >= tomk) { Modified: trunk/src/northbridge/via/cn700/raminit.c ============================================================================== --- trunk/src/northbridge/via/cn700/raminit.c Sun Aug 1 17:41:14 2010 (r5676) +++ trunk/src/northbridge/via/cn700/raminit.c Sun Aug 1 19:20:20 2010 (r5677) @@ -183,6 +183,8 @@ if (result == 0xff) die("DRAM module size too big, not supported by CN700\n"); + else + printk(BIOS_DEBUG, "Found %iMB of ram\n", result * ranks * 64); pci_write_config8(ctrl->d0f3, 0x40, result); pci_write_config8(ctrl->d0f3, 0x48, 0x00); @@ -400,18 +402,18 @@ read32(rank_address + 0x10); /* 3. Mode register set. */ - PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\n"); + PRINT_DEBUG_MEM("RAM Enable 3: Mode register set\n"); do_ram_command(dev, RAM_COMMAND_MRS); read32(rank_address + 0x120000); /* EMRS DLL Enable */ read32(rank_address + 0x800); /* MRS DLL Reset */ /* 4. Precharge all again. */ - PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\n"); + PRINT_DEBUG_MEM("RAM Enable 4: Precharge all\n"); do_ram_command(dev, RAM_COMMAND_PRECHARGE); read32(rank_address + 0x0); /* 5. Perform 8 refresh cycles. Wait tRC each time. */ - PRINT_DEBUG_MEM("RAM Enable 3: CBR\n"); + PRINT_DEBUG_MEM("RAM Enable 5: CBR\n"); do_ram_command(dev, RAM_COMMAND_CBR); for (i = 0; i < 8; i++) { read32(rank_address + 0x20); @@ -419,7 +421,7 @@ } /* 6. Mode register set. */ - PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\n"); + PRINT_DEBUG_MEM("RAM Enable 6: Mode register set\n"); /* Safe value for now, BL=8, WR=5, CAS=4 */ /* * (E)MRS values are from the BPG. No direct explanation is given, but @@ -432,7 +434,7 @@ read32(rank_address + 0x120020); /* EMRS OCD Calibration Mode Exit */ /* 8. Normal operation */ - PRINT_DEBUG_MEM("RAM Enable 5: Normal operation\n"); + PRINT_DEBUG_MEM("RAM Enable 7: Normal operation\n"); do_ram_command(dev, RAM_COMMAND_NORMAL); read32(rank_address + 0x30); } Modified: trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c ============================================================================== --- trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c Sun Aug 1 17:41:14 2010 (r5676) +++ trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c Sun Aug 1 19:20:20 2010 (r5677) @@ -61,8 +61,10 @@ PRINT_DEBUG("Waiting until SMBus ready\n"); - /* Yes, this is a mess, but it's the easiest way to do it. */ - /* XXX not so messy, but an explanation of the hack would have been better */ + /* Loop up to SMBUS_TIMEOUT times, waiting for bit 0 of the + * SMBus Host Status register to go to 0, indicating the operation + * was completed successfully. I don't remember why I did it this way, + * but I think it was because ROMCC was running low on registers */ loops = 0; while ((inb(SMBHSTSTAT) & 1) == 1 && loops < SMBUS_TIMEOUT) ++loops;

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[commit] r5676 - in trunk/src: . cpu/x86/smm southbridge/intel/i82801dx southbridge/intel/i82801gx
by repository service 01 Aug '10

01 Aug '10

Author: stepan Date: Sun Aug 1 17:41:14 2010 New Revision: 5676 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5676 Log: - fix SMM code relocation race - make SMM relocation debugging Kconfig accessible Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/src/Kconfig trunk/src/cpu/x86/smm/smmrelocate.S trunk/src/southbridge/intel/i82801dx/i82801dx.h trunk/src/southbridge/intel/i82801dx/i82801dx_smi.c trunk/src/southbridge/intel/i82801gx/i82801gx_smi.c Modified: trunk/src/Kconfig ============================================================================== --- trunk/src/Kconfig Sun Aug 1 17:33:30 2010 (r5675) +++ trunk/src/Kconfig Sun Aug 1 17:41:14 2010 (r5676) @@ -560,6 +560,18 @@ If unsure, say N. +config DEBUG_SMM_RELOCATION + bool "Debug SMM relocation code" + default n + depends on HAVE_SMI_HANDLER + help + This option enables additional SMM handler relocation related + debug messages. + + Note: This option will increase the size of the coreboot image. + + If unsure, say N. + config X86EMU_DEBUG bool "Output verbose x86emu debug messages" default n Modified: trunk/src/cpu/x86/smm/smmrelocate.S ============================================================================== --- trunk/src/cpu/x86/smm/smmrelocate.S Sun Aug 1 17:33:30 2010 (r5675) +++ trunk/src/cpu/x86/smm/smmrelocate.S Sun Aug 1 17:41:14 2010 (r5676) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008 coresystems GmbH + * Copyright (C) 2008-2010 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -24,12 +24,15 @@ // FIXME: Is this piece of code southbridge specific, or // can it be cleaned up so this include is not required? -// It's needed right now because we get our PM_BASE from +// It's needed right now because we get our DEFAULT_PMBASE from // here. +#if defined(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) #include "../../../southbridge/intel/i82801gx/i82801gx.h" - -#undef DEBUG_SMM_RELOCATION -//#define DEBUG_SMM_RELOCATION +#elif defined(CONFIG_SOUTHBRIDGE_INTEL_I82801DX) +#include "../../../southbridge/intel/i82801dx/i82801dx.h" +#else +#error "Southbridge needs SMM handler support." +#endif #define LAPIC_ID 0xfee00020 @@ -125,7 +128,7 @@ addr32 movl %eax, (%ebx) - /* The next section of code is hardware specific */ + /* The next section of code is potentially southbridge specific */ /* Clear SMI status */ movw $(DEFAULT_PMBASE + 0x34), %dx @@ -143,8 +146,9 @@ orl $(1 << 1), %eax outl %eax, %dx - /* End of hardware specific section. */ -#ifdef DEBUG_SMM_RELOCATION + /* End of southbridge specific section. */ + +#if defined(CONFIG_DEBUG_SMM_RELOCATION) && CONFIG_DEBUG_SMM_RELOCATION /* print [SMM-x] so we can determine if CPUx went to SMM */ movw $CONFIG_TTYS0_BASE, %dx mov $'[', %al Modified: trunk/src/southbridge/intel/i82801dx/i82801dx.h ============================================================================== --- trunk/src/southbridge/intel/i82801dx/i82801dx.h Sun Aug 1 17:33:30 2010 (r5675) +++ trunk/src/southbridge/intel/i82801dx/i82801dx.h Sun Aug 1 17:41:14 2010 (r5676) @@ -86,6 +86,7 @@ #define PCICMD 0x04 #define PMBASE 0x40 #define PMBASE_ADDR 0x0400 +#define DEFAULT_PMBASE PMBASE_ADDR #define ACPI_CNTL 0x44 #define BIOS_CNTL 0x4E #define GPIO_BASE 0x58 Modified: trunk/src/southbridge/intel/i82801dx/i82801dx_smi.c ============================================================================== --- trunk/src/southbridge/intel/i82801dx/i82801dx_smi.c Sun Aug 1 17:33:30 2010 (r5675) +++ trunk/src/southbridge/intel/i82801dx/i82801dx_smi.c Sun Aug 1 17:41:14 2010 (r5676) @@ -335,11 +335,13 @@ void smm_init(void) { - // FIXME is this a race condition? - smm_relocate(); + /* Put SMM code to 0xa0000 */ smm_install(); - // We're done. Make sure SMIs can happen! + /* Put relocation code to 0x38000 and relocate SMBASE */ + smm_relocate(); + + /* We're done. Make sure SMIs can happen! */ smi_set_eos(); } Modified: trunk/src/southbridge/intel/i82801gx/i82801gx_smi.c ============================================================================== --- trunk/src/southbridge/intel/i82801gx/i82801gx_smi.c Sun Aug 1 17:33:30 2010 (r5675) +++ trunk/src/southbridge/intel/i82801gx/i82801gx_smi.c Sun Aug 1 17:41:14 2010 (r5676) @@ -335,11 +335,13 @@ void smm_init(void) { - // FIXME is this a race condition? - smm_relocate(); + /* Put SMM code to 0xa0000 */ smm_install(); - // We're done. Make sure SMIs can happen! + /* Put relocation code to 0x38000 and relocate SMBASE */ + smm_relocate(); + + /* We're done. Make sure SMIs can happen! */ smi_set_eos(); }

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Re: [coreboot] coreboot halts at "doing early_mtrr"
by Stefan Reinauer 01 Aug '10

01 Aug '10

-------- Original Message -------- Subject: Re: [coreboot] coreboot halts at "doing early_mtrr" Date: Sun, 01 Aug 2010 17:28:41 +0200 From: Stefan Reinauer <stefan.reinauer(a)coresystems.de> Organization: coresystems GmbH To: Corey Osgood <corey.osgood(a)gmail.com> On 8/1/10 5:10 AM, Corey Osgood wrote: > Clarify a comment on an old hack, remove the call to early_mtrr_init > that causes CAR to hang, provide more debugging output wrt memory size, > and correct the numbering on the ram init sequence. > > Signed-off-by: Corey Osgood <corey.osgood(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de>

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[commit] r5675 - trunk/util/inteltool
by repository service 01 Aug '10

01 Aug '10

Author: stepan Date: Sun Aug 1 17:33:30 2010 New Revision: 5675 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5675 Log: add i945GSE to inteltool Signed-off-by: Björn Busse <bj.rn(a)co-assembler.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Corey Osgood <corey.osgood(a)gmail.com> Modified: trunk/util/inteltool/inteltool.c trunk/util/inteltool/inteltool.h trunk/util/inteltool/memory.c trunk/util/inteltool/pcie.c Modified: trunk/util/inteltool/inteltool.c ============================================================================== --- trunk/util/inteltool/inteltool.c Sun Aug 1 04:33:42 2010 (r5674) +++ trunk/util/inteltool/inteltool.c Sun Aug 1 17:33:30 2010 (r5675) @@ -40,6 +40,7 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915, "82915G/P/GV/GL/PL/910GL" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945P, "i945P" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GSE, "i945GSE" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PM965, "PM965" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q965, "Q963/965" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82975X, "i975X" }, Modified: trunk/util/inteltool/inteltool.h ============================================================================== --- trunk/util/inteltool/inteltool.h Sun Aug 1 04:33:42 2010 (r5674) +++ trunk/util/inteltool/inteltool.h Sun Aug 1 17:33:30 2010 (r5675) @@ -61,6 +61,7 @@ #define PCI_DEVICE_ID_INTEL_82915 0x2580 #define PCI_DEVICE_ID_INTEL_82945P 0x2770 #define PCI_DEVICE_ID_INTEL_82945GM 0x27a0 +#define PCI_DEVICE_ID_INTEL_82945GSE 0x27ac #define PCI_DEVICE_ID_INTEL_PM965 0x2a00 #define PCI_DEVICE_ID_INTEL_Q965 0x2990 #define PCI_DEVICE_ID_INTEL_82975X 0x277c Modified: trunk/util/inteltool/memory.c ============================================================================== --- trunk/util/inteltool/memory.c Sun Aug 1 04:33:42 2010 (r5674) +++ trunk/util/inteltool/memory.c Sun Aug 1 17:33:30 2010 (r5675) @@ -36,6 +36,7 @@ switch (nb->device_id) { case PCI_DEVICE_ID_INTEL_82915: case PCI_DEVICE_ID_INTEL_82945GM: + case PCI_DEVICE_ID_INTEL_82945GSE: case PCI_DEVICE_ID_INTEL_82945P: case PCI_DEVICE_ID_INTEL_82975X: mchbar_phys = pci_read_long(nb, 0x44) & 0xfffffffe; Modified: trunk/util/inteltool/pcie.c ============================================================================== --- trunk/util/inteltool/pcie.c Sun Aug 1 04:33:42 2010 (r5674) +++ trunk/util/inteltool/pcie.c Sun Aug 1 17:33:30 2010 (r5675) @@ -35,6 +35,7 @@ switch (nb->device_id) { case PCI_DEVICE_ID_INTEL_82915: case PCI_DEVICE_ID_INTEL_82945GM: + case PCI_DEVICE_ID_INTEL_82945GSE: case PCI_DEVICE_ID_INTEL_82945P: case PCI_DEVICE_ID_INTEL_82975X: epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; @@ -92,6 +93,7 @@ switch (nb->device_id) { case PCI_DEVICE_ID_INTEL_82915: case PCI_DEVICE_ID_INTEL_82945GM: + case PCI_DEVICE_ID_INTEL_82945GSE: case PCI_DEVICE_ID_INTEL_82945P: case PCI_DEVICE_ID_INTEL_82975X: dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe; @@ -150,6 +152,7 @@ switch (nb->device_id) { case PCI_DEVICE_ID_INTEL_82915: case PCI_DEVICE_ID_INTEL_82945GM: + case PCI_DEVICE_ID_INTEL_82945GSE: case PCI_DEVICE_ID_INTEL_82945P: case PCI_DEVICE_ID_INTEL_82975X: pciexbar_reg = pci_read_long(nb, 0x48);

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coreboot halts at "doing early_mtrr"
by austinro＠msu.edu 01 Aug '10

01 Aug '10

Hi. I have a Jetway 7F4K1G5S-LF board I'm trying to get working. When I build coreboot using the J7f24 target, it doesn't get past "doing early_mtrr". I added a few print statements (and included console.h) to try to track it down, and in "include/cpu/x86/cache.h" in disable_cache it will print the statement before write_cr0(cr0); but not the one after it. I don't know what to try next. I'm doing this on a 32-bit sidux box, with gcc 4.4.4. Any ideas? Thanks, Rob Austin

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add i945GSE to inteltool
by Björn Busse 01 Aug '10

01 Aug '10

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[commit] r5674 - in trunk/src: mainboard/asus/mew-vm northbridge/intel/i82810 southbridge/via/vt8237r
by repository service 01 Aug '10

01 Aug '10

Author: cozzie Date: Sun Aug 1 04:33:42 2010 New Revision: 5674 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5674 Log: Update my old, no longer active email addresses Signed-off-by: Corey Osgood <corey.osgood(a)gmail.com> Acked-by: Corey Osgood <corey.osgood(a)gmail.com> Modified: trunk/src/mainboard/asus/mew-vm/romstage.c trunk/src/northbridge/intel/i82810/chip.h trunk/src/northbridge/intel/i82810/i82810.h trunk/src/northbridge/intel/i82810/northbridge.c trunk/src/northbridge/intel/i82810/northbridge.h trunk/src/northbridge/intel/i82810/raminit.c trunk/src/northbridge/intel/i82810/raminit.h trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c Modified: trunk/src/mainboard/asus/mew-vm/romstage.c ============================================================================== --- trunk/src/mainboard/asus/mew-vm/romstage.c Thu Jul 29 21:25:31 2010 (r5673) +++ trunk/src/mainboard/asus/mew-vm/romstage.c Sun Aug 1 04:33:42 2010 (r5674) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Corey Osgood <corey(a)slightlyhackish.com> + * Copyright (C) 2007 Corey Osgood <corey.osgood(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by Modified: trunk/src/northbridge/intel/i82810/chip.h ============================================================================== --- trunk/src/northbridge/intel/i82810/chip.h Thu Jul 29 21:25:31 2010 (r5673) +++ trunk/src/northbridge/intel/i82810/chip.h Sun Aug 1 04:33:42 2010 (r5674) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Corey Osgood <corey(a)slightlyhackish.com> + * Copyright (C) 2007 Corey Osgood <corey.osgood(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by Modified: trunk/src/northbridge/intel/i82810/i82810.h ============================================================================== --- trunk/src/northbridge/intel/i82810/i82810.h Thu Jul 29 21:25:31 2010 (r5673) +++ trunk/src/northbridge/intel/i82810/i82810.h Sun Aug 1 04:33:42 2010 (r5674) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Corey Osgood <corey(a)slightlyhackish.com> + * Copyright (C) 2007 Corey Osgood <corey.osgood(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by Modified: trunk/src/northbridge/intel/i82810/northbridge.c ============================================================================== --- trunk/src/northbridge/intel/i82810/northbridge.c Thu Jul 29 21:25:31 2010 (r5673) +++ trunk/src/northbridge/intel/i82810/northbridge.c Sun Aug 1 04:33:42 2010 (r5674) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Corey Osgood <corey(a)slightlyhackish.com> + * Copyright (C) 2007 Corey Osgood <corey.osgood(a)gmail.com> * Copyright (C) 2010 Joseph Smith <joe(a)settoplinux.org> * * This program is free software; you can redistribute it and/or modify Modified: trunk/src/northbridge/intel/i82810/northbridge.h ============================================================================== --- trunk/src/northbridge/intel/i82810/northbridge.h Thu Jul 29 21:25:31 2010 (r5673) +++ trunk/src/northbridge/intel/i82810/northbridge.h Sun Aug 1 04:33:42 2010 (r5674) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Corey Osgood <corey(a)slightlyhackish.com> + * Copyright (C) 2007 Corey Osgood <corey.osgood(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by Modified: trunk/src/northbridge/intel/i82810/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i82810/raminit.c Thu Jul 29 21:25:31 2010 (r5673) +++ trunk/src/northbridge/intel/i82810/raminit.c Sun Aug 1 04:33:42 2010 (r5674) @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2009 Uwe Hermann <uwe(a)hermann-uwe.de> - * Copyright (C) 2007 Corey Osgood <corey(a)slightlyhackish.com> + * Copyright (C) 2007 Corey Osgood <corey.osgood(a)gmail.com> * Copyright (C) 2008-2009 Elia Yehuda <z4ziggy(a)gmail.com> * * This program is free software; you can redistribute it and/or modify Modified: trunk/src/northbridge/intel/i82810/raminit.h ============================================================================== --- trunk/src/northbridge/intel/i82810/raminit.h Thu Jul 29 21:25:31 2010 (r5673) +++ trunk/src/northbridge/intel/i82810/raminit.h Sun Aug 1 04:33:42 2010 (r5674) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Corey Osgood <corey(a)slightlyhackish.com> + * Copyright (C) 2007 Corey Osgood <corey.osgood(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by Modified: trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c ============================================================================== --- trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c Thu Jul 29 21:25:31 2010 (r5673) +++ trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c Sun Aug 1 04:33:42 2010 (r5674) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Corey Osgood <corey_osgood(a)verizon.net> + * Copyright (C) 2007 Corey Osgood <corey.osgood(a)gmail.com> * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> * * This program is free software; you can redistribute it and/or modify

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coreboot August 2010