coreboot August 2010

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67 participants
267 discussions

Re: [coreboot] Jetway J7F4K1G5S-LF acting weird, any suggestions?
by austinro＠msu.edu 05 Aug '10

05 Aug '10

Quoting "anders(a)jenbo.dk" <anders(a)jenbo.dk>: > When a memory module Is larger the nb supports it can be run are the > max supported size. > The nb you have supports 512 MB per side, the 1 gb you have has 1 > side with 1gb so you nb can't handle the full size, the 2 gb has 2 > sides With 1gb, so the nb can use a total of 1 gb. > I committed a patch to handle this type of stuff for 440bx. > All you have to do is force the sides to the max supported, if any > thing larger is detected. Hmm, I did not know that about the different sides of RAM. Thank you. (And thanks Google for filling in the details about low/high density RAM...) Okay, I'm comparing the raminit.c files for the cn700 and 440bx, I think I see what to do. Rob Austin

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Re: [coreboot] Fintek f71882
by Myles Watson 05 Aug '10

05 Aug '10

On Thu, Aug 5, 2010 at 5:03 AM, Alec Wright <alecjw(a)member.fsf.org> wrote: > I have a spare flash chip, and I should be able to reflash using an > external programmer if everything goes wrong. If I configure flashrom > as a motherboard with the f71805f chip, should i at least get serial > debugging? The first step would be to test flashrom and your spare flash chip with the factory BIOS. Read the original, swap it out, and write the original to the spare. If it still boots, then there's no harm in trying other things. Your northbridge and southbridge may also need some configuration before you can get serial debugging. If you look at SerialICE, it has several examples of minimal configurations to get serial working. Thanks, Myles

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Re: [coreboot] Coreinfo build patch
by Myles Watson 05 Aug '10

05 Aug '10

> Acked-by: Cai Bai Yin <caibaiyin.pku(a)gmail.com> >Acked-by: Peter Stuge <peter(a)stuge.se> Rev 5685. Thanks, Myles

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[commit] r5685 - trunk/payloads/coreinfo
by repository service 05 Aug '10

05 Aug '10

Author: myles Date: Thu Aug 5 16:41:29 2010 New Revision: 5685 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5685 Log: Change default path and configuration for Coreinfo. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Cai Bai Yin <caibaiyin.pku(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/payloads/coreinfo/Kconfig trunk/payloads/coreinfo/Makefile Modified: trunk/payloads/coreinfo/Kconfig ============================================================================== --- trunk/payloads/coreinfo/Kconfig Thu Aug 5 08:12:16 2010 (r5684) +++ trunk/payloads/coreinfo/Kconfig Thu Aug 5 16:41:29 2010 (r5685) @@ -103,8 +103,10 @@ default y config MODULE_LAR - bool "Enable the coreboot LAR module" - default y + bool "Enable the coreboot v3 LAR module" + help + LAR support must also be enabled in libpayload. + default n config MODULE_CBFS bool "Enable the coreboot CBFS module" Modified: trunk/payloads/coreinfo/Makefile ============================================================================== --- trunk/payloads/coreinfo/Makefile Thu Aug 5 08:12:16 2010 (r5684) +++ trunk/payloads/coreinfo/Makefile Thu Aug 5 16:41:29 2010 (r5685) @@ -44,7 +44,7 @@ HOSTCFLAGS := -I$(srck) -I$(objk) HOSTCXXFLAGS := -I$(srck) -I$(objk) -LIBPAYLOAD_DIR := ../libpayload +LIBPAYLOAD_DIR := ../libpayload/install/libpayload XCC := CC=$(CC) $(LIBPAYLOAD_DIR)/bin/lpgcc AS = $(LIBPAYLOAD_DIR)/bin/lpas STRIP ?= strip

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Re: [coreboot] Jetway J7F4K1G5S-LF acting weird, any suggestions?
by anders＠jenbo.dk 05 Aug '10

05 Aug '10

When a memory module Is larger the nb supports it can be run are the max supported size. The nb you have supports 512 MB per side, the 1 gb you have has 1 side with 1gb so you nb can't handle the full size, the 2 gb has 2 sides With 1gb, so the nb can use a total of 1 gb. I committed a patch to handle this type of stuff for 440bx. All you have to do is force the sides to the max supported, if any thing larger is detected. Mvh Anders ----- Reply message ----- Fra: "ron minnich" <rminnich(a)gmail.com> Dato: tir., aug. 3, 2010 19:41 Emne: [coreboot] Jetway J7F4K1G5S-LF acting weird, any suggestions? Til: <austinro(a)msu.edu> Cc: <coreboot(a)coreboot.org> Well, in the worst-case scenario, as a test, you can modify the raminit and just force it to use only 512M. Just as a test. I do this sometimes when I have ram issues. ron -- coreboot mailing list: coreboot(a)coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

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[PATCH][inteltool] Add support for NM10 and ICH8
by Corey Osgood 05 Aug '10

05 Aug '10

Patch attached. -Corey

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[commit] r5684 - trunk/src/northbridge/amd/amdht
by repository service 05 Aug '10

05 Aug '10

Author: zbao Date: Thu Aug 5 08:12:16 2010 New Revision: 5684 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5684 Log: The number of cores is got by reading the bit 15,13,12 of [0,24,3,e8]. The bit 15 seems to be a new feature when CPU started to have more than 4 cores. Zheng Yes, this was add for revD. Marc Jones Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/northbridge/amd/amdht/h3ncmn.c Modified: trunk/src/northbridge/amd/amdht/h3ncmn.c ============================================================================== --- trunk/src/northbridge/amd/amdht/h3ncmn.c Wed Aug 4 21:29:11 2010 (r5683) +++ trunk/src/northbridge/amd/amdht/h3ncmn.c Thu Aug 5 08:12:16 2010 (r5684) @@ -555,16 +555,17 @@ u8 i; ASSERT((node < nb->maxNodes)); - /* Read CmpCap */ + /* Read CmpCap [2][1:0] */ AmdPCIReadBits(MAKE_SBDFO(makePCISegmentFromNode(node), makePCIBusFromNode(node), makePCIDeviceFromNode(node), CPU_NB_FUNC_03, REG_NB_CAPABILITY_3XE8), - 13, 12, &temp); + 15, 12, &temp); + /* bits[15,13,12] specify the cores */ /* Support Downcoring */ - cores = temp + 1; + cores = ((temp & 8) >> 1) + (temp & 3) + 1; AmdPCIReadBits (MAKE_SBDFO(makePCISegmentFromNode(node), makePCIBusFromNode(node), makePCIDeviceFromNode(node),

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Coreinfo build patch
by Myles Watson 05 Aug '10

05 Aug '10

Change the default path to libpayload since they are both in payloads/. Change LAR support to default to no, since that is the default in libpayload. With this change, the steps to build coreinfo are: 1. Build libpayload: cd payloads/libpayload make menuconfig make install 2. Build coreinfo cd ../coreinfo make menuconfig make Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

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Fintek f71882
by Alec Wright 05 Aug '10

05 Aug '10

I've been looking through the datasheets for my superio (f71882f, not officially supported in coreboot) and the .h and _early_serial.c files for the f71805f (supported in coreboot). It looks like my superio might be compatible. (same addresses/commands etc). Is it worth a try? My COM1 port's fried and my COM2 port doesnt seem to work, although I think the latter might be an issue with the BIOS disabling it. If that's the case, how easy would it be to get a basic coreboot image on my board with serial debugging? RAM etc can come later. It looks like EHCI debug is possible on my motherboard, but at $90 each, I can't really afford a debugger - my motherboard cost half that.

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Re: [coreboot] Enable USB Debug Device!
by Myles Watson 04 Aug '10

04 Aug '10

On Tue, Aug 3, 2010 at 4:39 PM, <silversurfer.2010(a)gmx.de> wrote: > Hello, > > I bought the “PLX NET20DC USB Debug Device”. > > Now I want to use this device for debug purpose. But I get with different > mainboards the same build error messages. > > Can anybody help? > cc1: warnings being treated as errors We've made warnings errors since this code has been used much. You can change the default value for WARNINGS_ARE_ERRORS in src/Kconfig to n, make oldconfig, and try building again. It's a bonus if you fix the warnings and submit a patch :) Thanks, Myles

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coreboot August 2010